1//===--- Targets.cpp - Implement -arch option and targets -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements construction of a TargetInfo object from a 11// target triple. 12// 13//===----------------------------------------------------------------------===// 14 15#include "clang/Basic/TargetInfo.h" 16#include "clang/Basic/Builtins.h" 17#include "clang/Basic/Diagnostic.h" 18#include "clang/Basic/LangOptions.h" 19#include "clang/Basic/MacroBuilder.h" 20#include "clang/Basic/TargetBuiltins.h" 21#include "clang/Basic/TargetOptions.h" 22#include "llvm/ADT/APFloat.h" 23#include "llvm/ADT/OwningPtr.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/ADT/StringRef.h" 26#include "llvm/ADT/StringSwitch.h" 27#include "llvm/ADT/Triple.h" 28#include "llvm/IR/Type.h" 29#include "llvm/MC/MCSectionMachO.h" 30#include "llvm/Support/ErrorHandling.h" 31#include <algorithm> 32using namespace clang; 33 34//===----------------------------------------------------------------------===// 35// Common code shared among targets. 36//===----------------------------------------------------------------------===// 37 38/// DefineStd - Define a macro name and standard variants. For example if 39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40/// when in GNU mode. 41static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55} 56 57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63} 64 65//===----------------------------------------------------------------------===// 66// Defines specific to certain operating systems. 67//===----------------------------------------------------------------------===// 68 69namespace { 70template<typename TgtInfo> 71class OSTargetInfo : public TgtInfo { 72protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75public: 76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83}; 84} // end anonymous namespace 85 86 87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "5621"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.getOS() == llvm::Triple::IOS) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 152 } else { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[5]; 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 166 } 167 168 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 169} 170 171namespace { 172template<typename Target> 173class DarwinTargetInfo : public OSTargetInfo<Target> { 174protected: 175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 176 MacroBuilder &Builder) const { 177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 178 this->PlatformMinVersion); 179 } 180 181public: 182 DarwinTargetInfo(const std::string& triple) : 183 OSTargetInfo<Target>(triple) { 184 llvm::Triple T = llvm::Triple(triple); 185 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7); 186 this->MCountName = "\01mcount"; 187 } 188 189 virtual std::string isValidSectionSpecifier(StringRef SR) const { 190 // Let MCSectionMachO validate this. 191 StringRef Segment, Section; 192 unsigned TAA, StubSize; 193 bool HasTAA; 194 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 195 TAA, HasTAA, StubSize); 196 } 197 198 virtual const char *getStaticInitSectionSpecifier() const { 199 // FIXME: We should return 0 when building kexts. 200 return "__TEXT,__StaticInit,regular,pure_instructions"; 201 } 202 203 /// Darwin does not support protected visibility. Darwin's "default" 204 /// is very similar to ELF's "protected"; Darwin requires a "weak" 205 /// attribute on declarations that can be dynamically replaced. 206 virtual bool hasProtectedVisibility() const { 207 return false; 208 } 209}; 210 211 212// DragonFlyBSD Target 213template<typename Target> 214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 215protected: 216 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const { 218 // DragonFly defines; list based off of gcc output 219 Builder.defineMacro("__DragonFly__"); 220 Builder.defineMacro("__DragonFly_cc_version", "100001"); 221 Builder.defineMacro("__ELF__"); 222 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 223 Builder.defineMacro("__tune_i386__"); 224 DefineStd(Builder, "unix", Opts); 225 } 226public: 227 DragonFlyBSDTargetInfo(const std::string &triple) 228 : OSTargetInfo<Target>(triple) { 229 this->UserLabelPrefix = ""; 230 231 llvm::Triple Triple(triple); 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240}; 241 242// FreeBSD Target 243template<typename Target> 244class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245protected: 246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 } 260public: 261 FreeBSDTargetInfo(const std::string &triple) 262 : OSTargetInfo<Target>(triple) { 263 this->UserLabelPrefix = ""; 264 265 llvm::Triple Triple(triple); 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 case llvm::Triple::mips: 273 case llvm::Triple::mipsel: 274 case llvm::Triple::ppc: 275 case llvm::Triple::ppc64: 276 this->MCountName = "_mcount"; 277 break; 278 case llvm::Triple::arm: 279 this->MCountName = "__mcount"; 280 break; 281 } 282 283 } 284}; 285 286// Minix Target 287template<typename Target> 288class MinixTargetInfo : public OSTargetInfo<Target> { 289protected: 290 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 291 MacroBuilder &Builder) const { 292 // Minix defines 293 294 Builder.defineMacro("__minix", "3"); 295 Builder.defineMacro("_EM_WSIZE", "4"); 296 Builder.defineMacro("_EM_PSIZE", "4"); 297 Builder.defineMacro("_EM_SSIZE", "2"); 298 Builder.defineMacro("_EM_LSIZE", "4"); 299 Builder.defineMacro("_EM_FSIZE", "4"); 300 Builder.defineMacro("_EM_DSIZE", "8"); 301 Builder.defineMacro("__ELF__"); 302 DefineStd(Builder, "unix", Opts); 303 } 304public: 305 MinixTargetInfo(const std::string &triple) 306 : OSTargetInfo<Target>(triple) { 307 this->UserLabelPrefix = ""; 308 } 309}; 310 311// Linux target 312template<typename Target> 313class LinuxTargetInfo : public OSTargetInfo<Target> { 314protected: 315 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 316 MacroBuilder &Builder) const { 317 // Linux defines; list based off of gcc output 318 DefineStd(Builder, "unix", Opts); 319 DefineStd(Builder, "linux", Opts); 320 Builder.defineMacro("__gnu_linux__"); 321 Builder.defineMacro("__ELF__"); 322 if (Triple.getEnvironment() == llvm::Triple::Android) 323 Builder.defineMacro("__ANDROID__", "1"); 324 if (Opts.POSIXThreads) 325 Builder.defineMacro("_REENTRANT"); 326 if (Opts.CPlusPlus) 327 Builder.defineMacro("_GNU_SOURCE"); 328 } 329public: 330 LinuxTargetInfo(const std::string& triple) 331 : OSTargetInfo<Target>(triple) { 332 this->UserLabelPrefix = ""; 333 this->WIntType = TargetInfo::UnsignedInt; 334 } 335 336 virtual const char *getStaticInitSectionSpecifier() const { 337 return ".text.startup"; 338 } 339}; 340 341// NetBSD Target 342template<typename Target> 343class NetBSDTargetInfo : public OSTargetInfo<Target> { 344protected: 345 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 346 MacroBuilder &Builder) const { 347 // NetBSD defines; list based off of gcc output 348 Builder.defineMacro("__NetBSD__"); 349 Builder.defineMacro("__unix__"); 350 Builder.defineMacro("__ELF__"); 351 if (Opts.POSIXThreads) 352 Builder.defineMacro("_POSIX_THREADS"); 353 } 354public: 355 NetBSDTargetInfo(const std::string &triple) 356 : OSTargetInfo<Target>(triple) { 357 this->UserLabelPrefix = ""; 358 } 359}; 360 361// OpenBSD Target 362template<typename Target> 363class OpenBSDTargetInfo : public OSTargetInfo<Target> { 364protected: 365 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 366 MacroBuilder &Builder) const { 367 // OpenBSD defines; list based off of gcc output 368 369 Builder.defineMacro("__OpenBSD__"); 370 DefineStd(Builder, "unix", Opts); 371 Builder.defineMacro("__ELF__"); 372 if (Opts.POSIXThreads) 373 Builder.defineMacro("_REENTRANT"); 374 } 375public: 376 OpenBSDTargetInfo(const std::string &triple) 377 : OSTargetInfo<Target>(triple) { 378 this->UserLabelPrefix = ""; 379 this->TLSSupported = false; 380 381 llvm::Triple Triple(triple); 382 switch (Triple.getArch()) { 383 default: 384 case llvm::Triple::x86: 385 case llvm::Triple::x86_64: 386 case llvm::Triple::arm: 387 case llvm::Triple::sparc: 388 this->MCountName = "__mcount"; 389 break; 390 case llvm::Triple::mips64: 391 case llvm::Triple::mips64el: 392 case llvm::Triple::ppc: 393 case llvm::Triple::sparcv9: 394 this->MCountName = "_mcount"; 395 break; 396 } 397 } 398}; 399 400// Bitrig Target 401template<typename Target> 402class BitrigTargetInfo : public OSTargetInfo<Target> { 403protected: 404 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 405 MacroBuilder &Builder) const { 406 // Bitrig defines; list based off of gcc output 407 408 Builder.defineMacro("__Bitrig__"); 409 DefineStd(Builder, "unix", Opts); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 } 414public: 415 BitrigTargetInfo(const std::string &triple) 416 : OSTargetInfo<Target>(triple) { 417 this->UserLabelPrefix = ""; 418 this->TLSSupported = false; 419 this->MCountName = "__mcount"; 420 } 421}; 422 423// PSP Target 424template<typename Target> 425class PSPTargetInfo : public OSTargetInfo<Target> { 426protected: 427 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 428 MacroBuilder &Builder) const { 429 // PSP defines; list based on the output of the pspdev gcc toolchain. 430 Builder.defineMacro("PSP"); 431 Builder.defineMacro("_PSP"); 432 Builder.defineMacro("__psp__"); 433 Builder.defineMacro("__ELF__"); 434 } 435public: 436 PSPTargetInfo(const std::string& triple) 437 : OSTargetInfo<Target>(triple) { 438 this->UserLabelPrefix = ""; 439 } 440}; 441 442// PS3 PPU Target 443template<typename Target> 444class PS3PPUTargetInfo : public OSTargetInfo<Target> { 445protected: 446 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 447 MacroBuilder &Builder) const { 448 // PS3 PPU defines. 449 Builder.defineMacro("__PPC__"); 450 Builder.defineMacro("__PPU__"); 451 Builder.defineMacro("__CELLOS_LV2__"); 452 Builder.defineMacro("__ELF__"); 453 Builder.defineMacro("__LP32__"); 454 Builder.defineMacro("_ARCH_PPC64"); 455 Builder.defineMacro("__powerpc64__"); 456 } 457public: 458 PS3PPUTargetInfo(const std::string& triple) 459 : OSTargetInfo<Target>(triple) { 460 this->UserLabelPrefix = ""; 461 this->LongWidth = this->LongAlign = 32; 462 this->PointerWidth = this->PointerAlign = 32; 463 this->IntMaxType = TargetInfo::SignedLongLong; 464 this->UIntMaxType = TargetInfo::UnsignedLongLong; 465 this->Int64Type = TargetInfo::SignedLongLong; 466 this->SizeType = TargetInfo::UnsignedInt; 467 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 468 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 469 } 470}; 471 472// FIXME: Need a real SPU target. 473// PS3 SPU Target 474template<typename Target> 475class PS3SPUTargetInfo : public OSTargetInfo<Target> { 476protected: 477 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 478 MacroBuilder &Builder) const { 479 // PS3 PPU defines. 480 Builder.defineMacro("__SPU__"); 481 Builder.defineMacro("__ELF__"); 482 } 483public: 484 PS3SPUTargetInfo(const std::string& triple) 485 : OSTargetInfo<Target>(triple) { 486 this->UserLabelPrefix = ""; 487 } 488}; 489 490// AuroraUX target 491template<typename Target> 492class AuroraUXTargetInfo : public OSTargetInfo<Target> { 493protected: 494 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const { 496 DefineStd(Builder, "sun", Opts); 497 DefineStd(Builder, "unix", Opts); 498 Builder.defineMacro("__ELF__"); 499 Builder.defineMacro("__svr4__"); 500 Builder.defineMacro("__SVR4"); 501 } 502public: 503 AuroraUXTargetInfo(const std::string& triple) 504 : OSTargetInfo<Target>(triple) { 505 this->UserLabelPrefix = ""; 506 this->WCharType = this->SignedLong; 507 // FIXME: WIntType should be SignedLong 508 } 509}; 510 511// Solaris target 512template<typename Target> 513class SolarisTargetInfo : public OSTargetInfo<Target> { 514protected: 515 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 516 MacroBuilder &Builder) const { 517 DefineStd(Builder, "sun", Opts); 518 DefineStd(Builder, "unix", Opts); 519 Builder.defineMacro("__ELF__"); 520 Builder.defineMacro("__svr4__"); 521 Builder.defineMacro("__SVR4"); 522 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 523 // newer, but to 500 for everything else. feature_test.h has a check to 524 // ensure that you are not using C99 with an old version of X/Open or C89 525 // with a new version. 526 if (Opts.C99 || Opts.C11) 527 Builder.defineMacro("_XOPEN_SOURCE", "600"); 528 else 529 Builder.defineMacro("_XOPEN_SOURCE", "500"); 530 if (Opts.CPlusPlus) 531 Builder.defineMacro("__C99FEATURES__"); 532 Builder.defineMacro("_LARGEFILE_SOURCE"); 533 Builder.defineMacro("_LARGEFILE64_SOURCE"); 534 Builder.defineMacro("__EXTENSIONS__"); 535 Builder.defineMacro("_REENTRANT"); 536 } 537public: 538 SolarisTargetInfo(const std::string& triple) 539 : OSTargetInfo<Target>(triple) { 540 this->UserLabelPrefix = ""; 541 this->WCharType = this->SignedInt; 542 // FIXME: WIntType should be SignedLong 543 } 544}; 545 546// Windows target 547template<typename Target> 548class WindowsTargetInfo : public OSTargetInfo<Target> { 549protected: 550 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 551 MacroBuilder &Builder) const { 552 Builder.defineMacro("_WIN32"); 553 } 554 void getVisualStudioDefines(const LangOptions &Opts, 555 MacroBuilder &Builder) const { 556 if (Opts.CPlusPlus) { 557 if (Opts.RTTI) 558 Builder.defineMacro("_CPPRTTI"); 559 560 if (Opts.Exceptions) 561 Builder.defineMacro("_CPPUNWIND"); 562 } 563 564 if (!Opts.CharIsSigned) 565 Builder.defineMacro("_CHAR_UNSIGNED"); 566 567 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 568 // but it works for now. 569 if (Opts.POSIXThreads) 570 Builder.defineMacro("_MT"); 571 572 if (Opts.MSCVersion != 0) 573 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 574 575 if (Opts.MicrosoftExt) { 576 Builder.defineMacro("_MSC_EXTENSIONS"); 577 578 if (Opts.CPlusPlus11) { 579 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 580 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 581 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 582 } 583 } 584 585 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 586 } 587 588public: 589 WindowsTargetInfo(const std::string &triple) 590 : OSTargetInfo<Target>(triple) {} 591}; 592 593template <typename Target> 594class NaClTargetInfo : public OSTargetInfo<Target> { 595 protected: 596 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 597 MacroBuilder &Builder) const { 598 if (Opts.POSIXThreads) 599 Builder.defineMacro("_REENTRANT"); 600 if (Opts.CPlusPlus) 601 Builder.defineMacro("_GNU_SOURCE"); 602 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__native_client__"); 606 } 607 public: 608 NaClTargetInfo(const std::string &triple) 609 : OSTargetInfo<Target>(triple) { 610 this->UserLabelPrefix = ""; 611 this->LongAlign = 32; 612 this->LongWidth = 32; 613 this->PointerAlign = 32; 614 this->PointerWidth = 32; 615 this->IntMaxType = TargetInfo::SignedLongLong; 616 this->UIntMaxType = TargetInfo::UnsignedLongLong; 617 this->Int64Type = TargetInfo::SignedLongLong; 618 this->DoubleAlign = 64; 619 this->LongDoubleWidth = 64; 620 this->LongDoubleAlign = 64; 621 this->SizeType = TargetInfo::UnsignedInt; 622 this->PtrDiffType = TargetInfo::SignedInt; 623 this->IntPtrType = TargetInfo::SignedInt; 624 // RegParmMax is inherited from the underlying architecture 625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 626 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 627 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 628 } 629 virtual typename Target::CallingConvCheckResult checkCallingConvention( 630 CallingConv CC) const { 631 return CC == CC_PnaclCall ? Target::CCCR_OK : 632 Target::checkCallingConvention(CC); 633 } 634}; 635} // end anonymous namespace. 636 637//===----------------------------------------------------------------------===// 638// Specific target implementations. 639//===----------------------------------------------------------------------===// 640 641namespace { 642// PPC abstract base class 643class PPCTargetInfo : public TargetInfo { 644 static const Builtin::Info BuiltinInfo[]; 645 static const char * const GCCRegNames[]; 646 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 647 std::string CPU; 648public: 649 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) { 650 LongDoubleWidth = LongDoubleAlign = 128; 651 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 652 } 653 654 /// \brief Flags for architecture specific defines. 655 typedef enum { 656 ArchDefineNone = 0, 657 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 658 ArchDefinePpcgr = 1 << 1, 659 ArchDefinePpcsq = 1 << 2, 660 ArchDefine440 = 1 << 3, 661 ArchDefine603 = 1 << 4, 662 ArchDefine604 = 1 << 5, 663 ArchDefinePwr4 = 1 << 6, 664 ArchDefinePwr5 = 1 << 7, 665 ArchDefinePwr5x = 1 << 8, 666 ArchDefinePwr6 = 1 << 9, 667 ArchDefinePwr6x = 1 << 10, 668 ArchDefinePwr7 = 1 << 11, 669 ArchDefineA2 = 1 << 12, 670 ArchDefineA2q = 1 << 13 671 } ArchDefineTypes; 672 673 // Note: GCC recognizes the following additional cpus: 674 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 675 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 676 // titan, rs64. 677 virtual bool setCPU(const std::string &Name) { 678 bool CPUKnown = llvm::StringSwitch<bool>(Name) 679 .Case("generic", true) 680 .Case("440", true) 681 .Case("450", true) 682 .Case("601", true) 683 .Case("602", true) 684 .Case("603", true) 685 .Case("603e", true) 686 .Case("603ev", true) 687 .Case("604", true) 688 .Case("604e", true) 689 .Case("620", true) 690 .Case("630", true) 691 .Case("g3", true) 692 .Case("7400", true) 693 .Case("g4", true) 694 .Case("7450", true) 695 .Case("g4+", true) 696 .Case("750", true) 697 .Case("970", true) 698 .Case("g5", true) 699 .Case("a2", true) 700 .Case("a2q", true) 701 .Case("e500mc", true) 702 .Case("e5500", true) 703 .Case("power3", true) 704 .Case("pwr3", true) 705 .Case("power4", true) 706 .Case("pwr4", true) 707 .Case("power5", true) 708 .Case("pwr5", true) 709 .Case("power5x", true) 710 .Case("pwr5x", true) 711 .Case("power6", true) 712 .Case("pwr6", true) 713 .Case("power6x", true) 714 .Case("pwr6x", true) 715 .Case("power7", true) 716 .Case("pwr7", true) 717 .Case("powerpc", true) 718 .Case("ppc", true) 719 .Case("powerpc64", true) 720 .Case("ppc64", true) 721 .Default(false); 722 723 if (CPUKnown) 724 CPU = Name; 725 726 return CPUKnown; 727 } 728 729 virtual void getTargetBuiltins(const Builtin::Info *&Records, 730 unsigned &NumRecords) const { 731 Records = BuiltinInfo; 732 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 733 } 734 735 virtual bool isCLZForZeroUndef() const { return false; } 736 737 virtual void getTargetDefines(const LangOptions &Opts, 738 MacroBuilder &Builder) const; 739 740 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 741 742 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 743 StringRef Name, 744 bool Enabled) const; 745 746 virtual bool hasFeature(StringRef Feature) const; 747 748 virtual void getGCCRegNames(const char * const *&Names, 749 unsigned &NumNames) const; 750 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 751 unsigned &NumAliases) const; 752 virtual bool validateAsmConstraint(const char *&Name, 753 TargetInfo::ConstraintInfo &Info) const { 754 switch (*Name) { 755 default: return false; 756 case 'O': // Zero 757 break; 758 case 'b': // Base register 759 case 'f': // Floating point register 760 Info.setAllowsRegister(); 761 break; 762 // FIXME: The following are added to allow parsing. 763 // I just took a guess at what the actions should be. 764 // Also, is more specific checking needed? I.e. specific registers? 765 case 'd': // Floating point register (containing 64-bit value) 766 case 'v': // Altivec vector register 767 Info.setAllowsRegister(); 768 break; 769 case 'w': 770 switch (Name[1]) { 771 case 'd':// VSX vector register to hold vector double data 772 case 'f':// VSX vector register to hold vector float data 773 case 's':// VSX vector register to hold scalar float data 774 case 'a':// Any VSX register 775 break; 776 default: 777 return false; 778 } 779 Info.setAllowsRegister(); 780 Name++; // Skip over 'w'. 781 break; 782 case 'h': // `MQ', `CTR', or `LINK' register 783 case 'q': // `MQ' register 784 case 'c': // `CTR' register 785 case 'l': // `LINK' register 786 case 'x': // `CR' register (condition register) number 0 787 case 'y': // `CR' register (condition register) 788 case 'z': // `XER[CA]' carry bit (part of the XER register) 789 Info.setAllowsRegister(); 790 break; 791 case 'I': // Signed 16-bit constant 792 case 'J': // Unsigned 16-bit constant shifted left 16 bits 793 // (use `L' instead for SImode constants) 794 case 'K': // Unsigned 16-bit constant 795 case 'L': // Signed 16-bit constant shifted left 16 bits 796 case 'M': // Constant larger than 31 797 case 'N': // Exact power of 2 798 case 'P': // Constant whose negation is a signed 16-bit constant 799 case 'G': // Floating point constant that can be loaded into a 800 // register with one instruction per word 801 case 'H': // Integer/Floating point constant that can be loaded 802 // into a register using three instructions 803 break; 804 case 'm': // Memory operand. Note that on PowerPC targets, m can 805 // include addresses that update the base register. It 806 // is therefore only safe to use `m' in an asm statement 807 // if that asm statement accesses the operand exactly once. 808 // The asm statement must also use `%U<opno>' as a 809 // placeholder for the "update" flag in the corresponding 810 // load or store instruction. For example: 811 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 812 // is correct but: 813 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 814 // is not. Use es rather than m if you don't want the base 815 // register to be updated. 816 case 'e': 817 if (Name[1] != 's') 818 return false; 819 // es: A "stable" memory operand; that is, one which does not 820 // include any automodification of the base register. Unlike 821 // `m', this constraint can be used in asm statements that 822 // might access the operand several times, or that might not 823 // access it at all. 824 Info.setAllowsMemory(); 825 Name++; // Skip over 'e'. 826 break; 827 case 'Q': // Memory operand that is an offset from a register (it is 828 // usually better to use `m' or `es' in asm statements) 829 case 'Z': // Memory operand that is an indexed or indirect from a 830 // register (it is usually better to use `m' or `es' in 831 // asm statements) 832 Info.setAllowsMemory(); 833 Info.setAllowsRegister(); 834 break; 835 case 'R': // AIX TOC entry 836 case 'a': // Address operand that is an indexed or indirect from a 837 // register (`p' is preferable for asm statements) 838 case 'S': // Constant suitable as a 64-bit mask operand 839 case 'T': // Constant suitable as a 32-bit mask operand 840 case 'U': // System V Release 4 small data area reference 841 case 't': // AND masks that can be performed by two rldic{l, r} 842 // instructions 843 case 'W': // Vector constant that does not require memory 844 case 'j': // Vector constant that is all zeros. 845 break; 846 // End FIXME. 847 } 848 return true; 849 } 850 virtual const char *getClobbers() const { 851 return ""; 852 } 853 int getEHDataRegisterNumber(unsigned RegNo) const { 854 if (RegNo == 0) return 3; 855 if (RegNo == 1) return 4; 856 return -1; 857 } 858}; 859 860const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 861#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 862#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 863 ALL_LANGUAGES }, 864#include "clang/Basic/BuiltinsPPC.def" 865}; 866 867 868/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 869/// #defines that are not tied to a specific subtarget. 870void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 871 MacroBuilder &Builder) const { 872 // Target identification. 873 Builder.defineMacro("__ppc__"); 874 Builder.defineMacro("_ARCH_PPC"); 875 Builder.defineMacro("__powerpc__"); 876 Builder.defineMacro("__POWERPC__"); 877 if (PointerWidth == 64) { 878 Builder.defineMacro("_ARCH_PPC64"); 879 Builder.defineMacro("__powerpc64__"); 880 Builder.defineMacro("__ppc64__"); 881 } else { 882 Builder.defineMacro("__ppc__"); 883 } 884 885 // Target properties. 886 if (getTriple().getOS() != llvm::Triple::NetBSD && 887 getTriple().getOS() != llvm::Triple::OpenBSD) 888 Builder.defineMacro("_BIG_ENDIAN"); 889 Builder.defineMacro("__BIG_ENDIAN__"); 890 891 // Subtarget options. 892 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 893 Builder.defineMacro("__REGISTER_PREFIX__", ""); 894 895 // FIXME: Should be controlled by command line option. 896 Builder.defineMacro("__LONG_DOUBLE_128__"); 897 898 if (Opts.AltiVec) { 899 Builder.defineMacro("__VEC__", "10206"); 900 Builder.defineMacro("__ALTIVEC__"); 901 } 902 903 // CPU identification. 904 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 905 .Case("440", ArchDefineName) 906 .Case("450", ArchDefineName | ArchDefine440) 907 .Case("601", ArchDefineName) 908 .Case("602", ArchDefineName | ArchDefinePpcgr) 909 .Case("603", ArchDefineName | ArchDefinePpcgr) 910 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 911 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 912 .Case("604", ArchDefineName | ArchDefinePpcgr) 913 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 914 .Case("620", ArchDefineName | ArchDefinePpcgr) 915 .Case("630", ArchDefineName | ArchDefinePpcgr) 916 .Case("7400", ArchDefineName | ArchDefinePpcgr) 917 .Case("7450", ArchDefineName | ArchDefinePpcgr) 918 .Case("750", ArchDefineName | ArchDefinePpcgr) 919 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 920 | ArchDefinePpcsq) 921 .Case("a2", ArchDefineA2) 922 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 923 .Case("pwr3", ArchDefinePpcgr) 924 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 925 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 926 | ArchDefinePpcsq) 927 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 928 | ArchDefinePpcgr | ArchDefinePpcsq) 929 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 930 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 931 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 932 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 933 | ArchDefinePpcsq) 934 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 935 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 936 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 937 .Case("power3", ArchDefinePpcgr) 938 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 939 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 940 | ArchDefinePpcsq) 941 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 942 | ArchDefinePpcgr | ArchDefinePpcsq) 943 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 944 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 945 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 946 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 947 | ArchDefinePpcsq) 948 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 949 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 950 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 951 .Default(ArchDefineNone); 952 953 if (defs & ArchDefineName) 954 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 955 if (defs & ArchDefinePpcgr) 956 Builder.defineMacro("_ARCH_PPCGR"); 957 if (defs & ArchDefinePpcsq) 958 Builder.defineMacro("_ARCH_PPCSQ"); 959 if (defs & ArchDefine440) 960 Builder.defineMacro("_ARCH_440"); 961 if (defs & ArchDefine603) 962 Builder.defineMacro("_ARCH_603"); 963 if (defs & ArchDefine604) 964 Builder.defineMacro("_ARCH_604"); 965 if (defs & ArchDefinePwr4) 966 Builder.defineMacro("_ARCH_PWR4"); 967 if (defs & ArchDefinePwr5) 968 Builder.defineMacro("_ARCH_PWR5"); 969 if (defs & ArchDefinePwr5x) 970 Builder.defineMacro("_ARCH_PWR5X"); 971 if (defs & ArchDefinePwr6) 972 Builder.defineMacro("_ARCH_PWR6"); 973 if (defs & ArchDefinePwr6x) 974 Builder.defineMacro("_ARCH_PWR6X"); 975 if (defs & ArchDefinePwr7) 976 Builder.defineMacro("_ARCH_PWR7"); 977 if (defs & ArchDefineA2) 978 Builder.defineMacro("_ARCH_A2"); 979 if (defs & ArchDefineA2q) { 980 Builder.defineMacro("_ARCH_A2Q"); 981 Builder.defineMacro("_ARCH_QP"); 982 } 983 984 if (getTriple().getVendor() == llvm::Triple::BGQ) { 985 Builder.defineMacro("__bg__"); 986 Builder.defineMacro("__THW_BLUEGENE__"); 987 Builder.defineMacro("__bgq__"); 988 Builder.defineMacro("__TOS_BGQ__"); 989 } 990 991 // FIXME: The following are not yet generated here by Clang, but are 992 // generated by GCC: 993 // 994 // _SOFT_FLOAT_ 995 // __RECIP_PRECISION__ 996 // __APPLE_ALTIVEC__ 997 // __VSX__ 998 // __RECIP__ 999 // __RECIPF__ 1000 // __RSQRTE__ 1001 // __RSQRTEF__ 1002 // _SOFT_DOUBLE_ 1003 // __NO_LWSYNC__ 1004 // __HAVE_BSWAP__ 1005 // __LONGDOUBLE128 1006 // __CMODEL_MEDIUM__ 1007 // __CMODEL_LARGE__ 1008 // _CALL_SYSV 1009 // _CALL_DARWIN 1010 // __NO_FPRS__ 1011} 1012 1013void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1014 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1015 .Case("7400", true) 1016 .Case("g4", true) 1017 .Case("7450", true) 1018 .Case("g4+", true) 1019 .Case("970", true) 1020 .Case("g5", true) 1021 .Case("pwr6", true) 1022 .Case("pwr7", true) 1023 .Case("ppc64", true) 1024 .Default(false); 1025 1026 Features["qpx"] = (CPU == "a2q"); 1027} 1028 1029bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1030 StringRef Name, 1031 bool Enabled) const { 1032 if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" || 1033 Name == "popcntd" || Name == "qpx") { 1034 Features[Name] = Enabled; 1035 return true; 1036 } 1037 1038 return false; 1039} 1040 1041bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1042 return Feature == "powerpc"; 1043} 1044 1045 1046const char * const PPCTargetInfo::GCCRegNames[] = { 1047 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1048 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1049 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1050 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1051 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1052 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1053 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1054 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1055 "mq", "lr", "ctr", "ap", 1056 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1057 "xer", 1058 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1059 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1060 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1061 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1062 "vrsave", "vscr", 1063 "spe_acc", "spefscr", 1064 "sfp" 1065}; 1066 1067void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1068 unsigned &NumNames) const { 1069 Names = GCCRegNames; 1070 NumNames = llvm::array_lengthof(GCCRegNames); 1071} 1072 1073const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1074 // While some of these aliases do map to different registers 1075 // they still share the same register name. 1076 { { "0" }, "r0" }, 1077 { { "1"}, "r1" }, 1078 { { "2" }, "r2" }, 1079 { { "3" }, "r3" }, 1080 { { "4" }, "r4" }, 1081 { { "5" }, "r5" }, 1082 { { "6" }, "r6" }, 1083 { { "7" }, "r7" }, 1084 { { "8" }, "r8" }, 1085 { { "9" }, "r9" }, 1086 { { "10" }, "r10" }, 1087 { { "11" }, "r11" }, 1088 { { "12" }, "r12" }, 1089 { { "13" }, "r13" }, 1090 { { "14" }, "r14" }, 1091 { { "15" }, "r15" }, 1092 { { "16" }, "r16" }, 1093 { { "17" }, "r17" }, 1094 { { "18" }, "r18" }, 1095 { { "19" }, "r19" }, 1096 { { "20" }, "r20" }, 1097 { { "21" }, "r21" }, 1098 { { "22" }, "r22" }, 1099 { { "23" }, "r23" }, 1100 { { "24" }, "r24" }, 1101 { { "25" }, "r25" }, 1102 { { "26" }, "r26" }, 1103 { { "27" }, "r27" }, 1104 { { "28" }, "r28" }, 1105 { { "29" }, "r29" }, 1106 { { "30" }, "r30" }, 1107 { { "31" }, "r31" }, 1108 { { "fr0" }, "f0" }, 1109 { { "fr1" }, "f1" }, 1110 { { "fr2" }, "f2" }, 1111 { { "fr3" }, "f3" }, 1112 { { "fr4" }, "f4" }, 1113 { { "fr5" }, "f5" }, 1114 { { "fr6" }, "f6" }, 1115 { { "fr7" }, "f7" }, 1116 { { "fr8" }, "f8" }, 1117 { { "fr9" }, "f9" }, 1118 { { "fr10" }, "f10" }, 1119 { { "fr11" }, "f11" }, 1120 { { "fr12" }, "f12" }, 1121 { { "fr13" }, "f13" }, 1122 { { "fr14" }, "f14" }, 1123 { { "fr15" }, "f15" }, 1124 { { "fr16" }, "f16" }, 1125 { { "fr17" }, "f17" }, 1126 { { "fr18" }, "f18" }, 1127 { { "fr19" }, "f19" }, 1128 { { "fr20" }, "f20" }, 1129 { { "fr21" }, "f21" }, 1130 { { "fr22" }, "f22" }, 1131 { { "fr23" }, "f23" }, 1132 { { "fr24" }, "f24" }, 1133 { { "fr25" }, "f25" }, 1134 { { "fr26" }, "f26" }, 1135 { { "fr27" }, "f27" }, 1136 { { "fr28" }, "f28" }, 1137 { { "fr29" }, "f29" }, 1138 { { "fr30" }, "f30" }, 1139 { { "fr31" }, "f31" }, 1140 { { "cc" }, "cr0" }, 1141}; 1142 1143void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1144 unsigned &NumAliases) const { 1145 Aliases = GCCRegAliases; 1146 NumAliases = llvm::array_lengthof(GCCRegAliases); 1147} 1148} // end anonymous namespace. 1149 1150namespace { 1151class PPC32TargetInfo : public PPCTargetInfo { 1152public: 1153 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) { 1154 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1155 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1156 1157 switch (getTriple().getOS()) { 1158 case llvm::Triple::Linux: 1159 case llvm::Triple::FreeBSD: 1160 case llvm::Triple::NetBSD: 1161 SizeType = UnsignedInt; 1162 PtrDiffType = SignedInt; 1163 IntPtrType = SignedInt; 1164 break; 1165 default: 1166 break; 1167 } 1168 1169 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1170 LongDoubleWidth = LongDoubleAlign = 64; 1171 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1172 } 1173 1174 // PPC32 supports atomics up to 4 bytes. 1175 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1176 } 1177 1178 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1179 // This is the ELF definition, and is overridden by the Darwin sub-target 1180 return TargetInfo::PowerABIBuiltinVaList; 1181 } 1182}; 1183} // end anonymous namespace. 1184 1185namespace { 1186class PPC64TargetInfo : public PPCTargetInfo { 1187public: 1188 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) { 1189 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1190 IntMaxType = SignedLong; 1191 UIntMaxType = UnsignedLong; 1192 Int64Type = SignedLong; 1193 1194 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1195 LongDoubleWidth = LongDoubleAlign = 64; 1196 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1197 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1198 "i64:64:64-f32:32:32-f64:64:64-f128:64:64-" 1199 "v128:128:128-n32:64"; 1200 } else 1201 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1202 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1203 "v128:128:128-n32:64"; 1204 1205 // PPC64 supports atomics up to 8 bytes. 1206 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1207 } 1208 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1209 return TargetInfo::CharPtrBuiltinVaList; 1210 } 1211}; 1212} // end anonymous namespace. 1213 1214 1215namespace { 1216class DarwinPPC32TargetInfo : 1217 public DarwinTargetInfo<PPC32TargetInfo> { 1218public: 1219 DarwinPPC32TargetInfo(const std::string& triple) 1220 : DarwinTargetInfo<PPC32TargetInfo>(triple) { 1221 HasAlignMac68kSupport = true; 1222 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1223 LongLongAlign = 32; 1224 SuitableAlign = 128; 1225 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1226 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1227 } 1228 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1229 return TargetInfo::CharPtrBuiltinVaList; 1230 } 1231}; 1232 1233class DarwinPPC64TargetInfo : 1234 public DarwinTargetInfo<PPC64TargetInfo> { 1235public: 1236 DarwinPPC64TargetInfo(const std::string& triple) 1237 : DarwinTargetInfo<PPC64TargetInfo>(triple) { 1238 HasAlignMac68kSupport = true; 1239 SuitableAlign = 128; 1240 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1241 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1242 } 1243}; 1244} // end anonymous namespace. 1245 1246namespace { 1247 static const unsigned NVPTXAddrSpaceMap[] = { 1248 1, // opencl_global 1249 3, // opencl_local 1250 4, // opencl_constant 1251 1, // cuda_device 1252 4, // cuda_constant 1253 3, // cuda_shared 1254 }; 1255 class NVPTXTargetInfo : public TargetInfo { 1256 static const char * const GCCRegNames[]; 1257 static const Builtin::Info BuiltinInfo[]; 1258 std::vector<StringRef> AvailableFeatures; 1259 public: 1260 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) { 1261 BigEndian = false; 1262 TLSSupported = false; 1263 LongWidth = LongAlign = 64; 1264 AddrSpaceMap = &NVPTXAddrSpaceMap; 1265 // Define available target features 1266 // These must be defined in sorted order! 1267 NoAsmVariants = true; 1268 } 1269 virtual void getTargetDefines(const LangOptions &Opts, 1270 MacroBuilder &Builder) const { 1271 Builder.defineMacro("__PTX__"); 1272 Builder.defineMacro("__NVPTX__"); 1273 } 1274 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1275 unsigned &NumRecords) const { 1276 Records = BuiltinInfo; 1277 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1278 } 1279 virtual bool hasFeature(StringRef Feature) const { 1280 return Feature == "ptx" || Feature == "nvptx"; 1281 } 1282 1283 virtual void getGCCRegNames(const char * const *&Names, 1284 unsigned &NumNames) const; 1285 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1286 unsigned &NumAliases) const { 1287 // No aliases. 1288 Aliases = 0; 1289 NumAliases = 0; 1290 } 1291 virtual bool validateAsmConstraint(const char *&Name, 1292 TargetInfo::ConstraintInfo &info) const { 1293 // FIXME: implement 1294 return true; 1295 } 1296 virtual const char *getClobbers() const { 1297 // FIXME: Is this really right? 1298 return ""; 1299 } 1300 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1301 // FIXME: implement 1302 return TargetInfo::CharPtrBuiltinVaList; 1303 } 1304 virtual bool setCPU(const std::string &Name) { 1305 bool Valid = llvm::StringSwitch<bool>(Name) 1306 .Case("sm_20", true) 1307 .Case("sm_21", true) 1308 .Case("sm_30", true) 1309 .Case("sm_35", true) 1310 .Default(false); 1311 1312 return Valid; 1313 } 1314 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1315 StringRef Name, 1316 bool Enabled) const; 1317 }; 1318 1319 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1320#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1321#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1322 ALL_LANGUAGES }, 1323#include "clang/Basic/BuiltinsNVPTX.def" 1324 }; 1325 1326 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1327 "r0" 1328 }; 1329 1330 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1331 unsigned &NumNames) const { 1332 Names = GCCRegNames; 1333 NumNames = llvm::array_lengthof(GCCRegNames); 1334 } 1335 1336 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1337 StringRef Name, 1338 bool Enabled) const { 1339 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(), 1340 Name)) { 1341 Features[Name] = Enabled; 1342 return true; 1343 } else { 1344 return false; 1345 } 1346 } 1347 1348 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1349 public: 1350 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1351 PointerWidth = PointerAlign = 32; 1352 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1353 DescriptionString 1354 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1355 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1356 "n16:32:64"; 1357 } 1358 }; 1359 1360 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1361 public: 1362 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1363 PointerWidth = PointerAlign = 64; 1364 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1365 DescriptionString 1366 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1367 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1368 "n16:32:64"; 1369 } 1370 }; 1371} 1372 1373namespace { 1374 1375static const unsigned R600AddrSpaceMap[] = { 1376 1, // opencl_global 1377 3, // opencl_local 1378 2, // opencl_constant 1379 1, // cuda_device 1380 2, // cuda_constant 1381 3 // cuda_shared 1382}; 1383 1384static const char *DescriptionStringR600 = 1385 "e" 1386 "-p:32:32:32" 1387 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 1388 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1389 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1390 "-n32:64"; 1391 1392static const char *DescriptionStringR600DoubleOps = 1393 "e" 1394 "-p:32:32:32" 1395 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1396 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1397 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1398 "-n32:64"; 1399 1400static const char *DescriptionStringSI = 1401 "e" 1402 "-p:64:64:64" 1403 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1404 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1405 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1406 "-n32:64"; 1407 1408class R600TargetInfo : public TargetInfo { 1409 /// \brief The GPU profiles supported by the R600 target. 1410 enum GPUKind { 1411 GK_NONE, 1412 GK_R600, 1413 GK_R600_DOUBLE_OPS, 1414 GK_R700, 1415 GK_R700_DOUBLE_OPS, 1416 GK_EVERGREEN, 1417 GK_EVERGREEN_DOUBLE_OPS, 1418 GK_NORTHERN_ISLANDS, 1419 GK_CAYMAN, 1420 GK_SOUTHERN_ISLANDS 1421 } GPU; 1422 1423public: 1424 R600TargetInfo(const std::string& triple) 1425 : TargetInfo(triple), 1426 GPU(GK_R600) { 1427 DescriptionString = DescriptionStringR600; 1428 AddrSpaceMap = &R600AddrSpaceMap; 1429 } 1430 1431 virtual const char * getClobbers() const { 1432 return ""; 1433 } 1434 1435 virtual void getGCCRegNames(const char * const *&Names, 1436 unsigned &numNames) const { 1437 Names = NULL; 1438 numNames = 0; 1439 } 1440 1441 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1442 unsigned &NumAliases) const { 1443 Aliases = NULL; 1444 NumAliases = 0; 1445 } 1446 1447 virtual bool validateAsmConstraint(const char *&Name, 1448 TargetInfo::ConstraintInfo &info) const { 1449 return true; 1450 } 1451 1452 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1453 unsigned &NumRecords) const { 1454 Records = NULL; 1455 NumRecords = 0; 1456 } 1457 1458 1459 virtual void getTargetDefines(const LangOptions &Opts, 1460 MacroBuilder &Builder) const { 1461 Builder.defineMacro("__R600__"); 1462 } 1463 1464 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1465 return TargetInfo::CharPtrBuiltinVaList; 1466 } 1467 1468 virtual bool setCPU(const std::string &Name) { 1469 GPU = llvm::StringSwitch<GPUKind>(Name) 1470 .Case("r600" , GK_R600) 1471 .Case("rv610", GK_R600) 1472 .Case("rv620", GK_R600) 1473 .Case("rv630", GK_R600) 1474 .Case("rv635", GK_R600) 1475 .Case("rs780", GK_R600) 1476 .Case("rs880", GK_R600) 1477 .Case("rv670", GK_R600_DOUBLE_OPS) 1478 .Case("rv710", GK_R700) 1479 .Case("rv730", GK_R700) 1480 .Case("rv740", GK_R700_DOUBLE_OPS) 1481 .Case("rv770", GK_R700_DOUBLE_OPS) 1482 .Case("palm", GK_EVERGREEN) 1483 .Case("cedar", GK_EVERGREEN) 1484 .Case("sumo", GK_EVERGREEN) 1485 .Case("sumo2", GK_EVERGREEN) 1486 .Case("redwood", GK_EVERGREEN) 1487 .Case("juniper", GK_EVERGREEN) 1488 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1489 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1490 .Case("barts", GK_NORTHERN_ISLANDS) 1491 .Case("turks", GK_NORTHERN_ISLANDS) 1492 .Case("caicos", GK_NORTHERN_ISLANDS) 1493 .Case("cayman", GK_CAYMAN) 1494 .Case("aruba", GK_CAYMAN) 1495 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1496 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1497 .Case("verde", GK_SOUTHERN_ISLANDS) 1498 .Case("oland", GK_SOUTHERN_ISLANDS) 1499 .Default(GK_NONE); 1500 1501 if (GPU == GK_NONE) { 1502 return false; 1503 } 1504 1505 // Set the correct data layout 1506 switch (GPU) { 1507 case GK_NONE: 1508 case GK_R600: 1509 case GK_R700: 1510 case GK_EVERGREEN: 1511 case GK_NORTHERN_ISLANDS: 1512 DescriptionString = DescriptionStringR600; 1513 break; 1514 case GK_R600_DOUBLE_OPS: 1515 case GK_R700_DOUBLE_OPS: 1516 case GK_EVERGREEN_DOUBLE_OPS: 1517 case GK_CAYMAN: 1518 DescriptionString = DescriptionStringR600DoubleOps; 1519 break; 1520 case GK_SOUTHERN_ISLANDS: 1521 DescriptionString = DescriptionStringSI; 1522 break; 1523 } 1524 1525 return true; 1526 } 1527}; 1528 1529} // end anonymous namespace 1530 1531namespace { 1532// MBlaze abstract base class 1533class MBlazeTargetInfo : public TargetInfo { 1534 static const char * const GCCRegNames[]; 1535 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 1536 1537public: 1538 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) { 1539 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16"; 1540 } 1541 1542 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1543 unsigned &NumRecords) const { 1544 // FIXME: Implement. 1545 Records = 0; 1546 NumRecords = 0; 1547 } 1548 1549 virtual void getTargetDefines(const LangOptions &Opts, 1550 MacroBuilder &Builder) const; 1551 1552 virtual bool hasFeature(StringRef Feature) const { 1553 return Feature == "mblaze"; 1554 } 1555 1556 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1557 return TargetInfo::CharPtrBuiltinVaList; 1558 } 1559 virtual const char *getTargetPrefix() const { 1560 return "mblaze"; 1561 } 1562 virtual void getGCCRegNames(const char * const *&Names, 1563 unsigned &NumNames) const; 1564 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1565 unsigned &NumAliases) const; 1566 virtual bool validateAsmConstraint(const char *&Name, 1567 TargetInfo::ConstraintInfo &Info) const { 1568 switch (*Name) { 1569 default: return false; 1570 case 'O': // Zero 1571 return true; 1572 case 'b': // Base register 1573 case 'f': // Floating point register 1574 Info.setAllowsRegister(); 1575 return true; 1576 } 1577 } 1578 virtual const char *getClobbers() const { 1579 return ""; 1580 } 1581}; 1582 1583/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific 1584/// #defines that are not tied to a specific subtarget. 1585void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts, 1586 MacroBuilder &Builder) const { 1587 // Target identification. 1588 Builder.defineMacro("__microblaze__"); 1589 Builder.defineMacro("_ARCH_MICROBLAZE"); 1590 Builder.defineMacro("__MICROBLAZE__"); 1591 1592 // Target properties. 1593 Builder.defineMacro("_BIG_ENDIAN"); 1594 Builder.defineMacro("__BIG_ENDIAN__"); 1595 1596 // Subtarget options. 1597 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1598} 1599 1600 1601const char * const MBlazeTargetInfo::GCCRegNames[] = { 1602 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1603 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1604 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1605 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1606 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 1607 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 1608 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 1609 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 1610 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4", 1611 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp" 1612}; 1613 1614void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names, 1615 unsigned &NumNames) const { 1616 Names = GCCRegNames; 1617 NumNames = llvm::array_lengthof(GCCRegNames); 1618} 1619 1620const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = { 1621 { {"f0"}, "r0" }, 1622 { {"f1"}, "r1" }, 1623 { {"f2"}, "r2" }, 1624 { {"f3"}, "r3" }, 1625 { {"f4"}, "r4" }, 1626 { {"f5"}, "r5" }, 1627 { {"f6"}, "r6" }, 1628 { {"f7"}, "r7" }, 1629 { {"f8"}, "r8" }, 1630 { {"f9"}, "r9" }, 1631 { {"f10"}, "r10" }, 1632 { {"f11"}, "r11" }, 1633 { {"f12"}, "r12" }, 1634 { {"f13"}, "r13" }, 1635 { {"f14"}, "r14" }, 1636 { {"f15"}, "r15" }, 1637 { {"f16"}, "r16" }, 1638 { {"f17"}, "r17" }, 1639 { {"f18"}, "r18" }, 1640 { {"f19"}, "r19" }, 1641 { {"f20"}, "r20" }, 1642 { {"f21"}, "r21" }, 1643 { {"f22"}, "r22" }, 1644 { {"f23"}, "r23" }, 1645 { {"f24"}, "r24" }, 1646 { {"f25"}, "r25" }, 1647 { {"f26"}, "r26" }, 1648 { {"f27"}, "r27" }, 1649 { {"f28"}, "r28" }, 1650 { {"f29"}, "r29" }, 1651 { {"f30"}, "r30" }, 1652 { {"f31"}, "r31" }, 1653}; 1654 1655void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1656 unsigned &NumAliases) const { 1657 Aliases = GCCRegAliases; 1658 NumAliases = llvm::array_lengthof(GCCRegAliases); 1659} 1660} // end anonymous namespace. 1661 1662namespace { 1663// Namespace for x86 abstract base class 1664const Builtin::Info BuiltinInfo[] = { 1665#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1666#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1667 ALL_LANGUAGES }, 1668#include "clang/Basic/BuiltinsX86.def" 1669}; 1670 1671static const char* const GCCRegNames[] = { 1672 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1673 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1674 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1675 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1676 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1677 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1678 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1679 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1680 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1681}; 1682 1683const TargetInfo::AddlRegName AddlRegNames[] = { 1684 { { "al", "ah", "eax", "rax" }, 0 }, 1685 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1686 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1687 { { "dl", "dh", "edx", "rdx" }, 1 }, 1688 { { "esi", "rsi" }, 4 }, 1689 { { "edi", "rdi" }, 5 }, 1690 { { "esp", "rsp" }, 7 }, 1691 { { "ebp", "rbp" }, 6 }, 1692}; 1693 1694// X86 target abstract base class; x86-32 and x86-64 are very close, so 1695// most of the implementation can be shared. 1696class X86TargetInfo : public TargetInfo { 1697 enum X86SSEEnum { 1698 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 1699 } SSELevel; 1700 enum MMX3DNowEnum { 1701 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1702 } MMX3DNowLevel; 1703 1704 bool HasAES; 1705 bool HasPCLMUL; 1706 bool HasLZCNT; 1707 bool HasRDRND; 1708 bool HasBMI; 1709 bool HasBMI2; 1710 bool HasPOPCNT; 1711 bool HasRTM; 1712 bool HasPRFCHW; 1713 bool HasRDSEED; 1714 bool HasSSE4a; 1715 bool HasFMA4; 1716 bool HasFMA; 1717 bool HasXOP; 1718 bool HasF16C; 1719 1720 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1721 /// 1722 /// Each enumeration represents a particular CPU supported by Clang. These 1723 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1724 enum CPUKind { 1725 CK_Generic, 1726 1727 /// \name i386 1728 /// i386-generation processors. 1729 //@{ 1730 CK_i386, 1731 //@} 1732 1733 /// \name i486 1734 /// i486-generation processors. 1735 //@{ 1736 CK_i486, 1737 CK_WinChipC6, 1738 CK_WinChip2, 1739 CK_C3, 1740 //@} 1741 1742 /// \name i586 1743 /// i586-generation processors, P5 microarchitecture based. 1744 //@{ 1745 CK_i586, 1746 CK_Pentium, 1747 CK_PentiumMMX, 1748 //@} 1749 1750 /// \name i686 1751 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1752 //@{ 1753 CK_i686, 1754 CK_PentiumPro, 1755 CK_Pentium2, 1756 CK_Pentium3, 1757 CK_Pentium3M, 1758 CK_PentiumM, 1759 CK_C3_2, 1760 1761 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1762 /// Clang however has some logic to suport this. 1763 // FIXME: Warn, deprecate, and potentially remove this. 1764 CK_Yonah, 1765 //@} 1766 1767 /// \name Netburst 1768 /// Netburst microarchitecture based processors. 1769 //@{ 1770 CK_Pentium4, 1771 CK_Pentium4M, 1772 CK_Prescott, 1773 CK_Nocona, 1774 //@} 1775 1776 /// \name Core 1777 /// Core microarchitecture based processors. 1778 //@{ 1779 CK_Core2, 1780 1781 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1782 /// codename which GCC no longer accepts as an option to -march, but Clang 1783 /// has some logic for recognizing it. 1784 // FIXME: Warn, deprecate, and potentially remove this. 1785 CK_Penryn, 1786 //@} 1787 1788 /// \name Atom 1789 /// Atom processors 1790 //@{ 1791 CK_Atom, 1792 //@} 1793 1794 /// \name Nehalem 1795 /// Nehalem microarchitecture based processors. 1796 //@{ 1797 CK_Corei7, 1798 CK_Corei7AVX, 1799 CK_CoreAVXi, 1800 CK_CoreAVX2, 1801 //@} 1802 1803 /// \name K6 1804 /// K6 architecture processors. 1805 //@{ 1806 CK_K6, 1807 CK_K6_2, 1808 CK_K6_3, 1809 //@} 1810 1811 /// \name K7 1812 /// K7 architecture processors. 1813 //@{ 1814 CK_Athlon, 1815 CK_AthlonThunderbird, 1816 CK_Athlon4, 1817 CK_AthlonXP, 1818 CK_AthlonMP, 1819 //@} 1820 1821 /// \name K8 1822 /// K8 architecture processors. 1823 //@{ 1824 CK_Athlon64, 1825 CK_Athlon64SSE3, 1826 CK_AthlonFX, 1827 CK_K8, 1828 CK_K8SSE3, 1829 CK_Opteron, 1830 CK_OpteronSSE3, 1831 CK_AMDFAM10, 1832 //@} 1833 1834 /// \name Bobcat 1835 /// Bobcat architecture processors. 1836 //@{ 1837 CK_BTVER1, 1838 CK_BTVER2, 1839 //@} 1840 1841 /// \name Bulldozer 1842 /// Bulldozer architecture processors. 1843 //@{ 1844 CK_BDVER1, 1845 CK_BDVER2, 1846 //@} 1847 1848 /// This specification is deprecated and will be removed in the future. 1849 /// Users should prefer \see CK_K8. 1850 // FIXME: Warn on this when the CPU is set to it. 1851 CK_x86_64, 1852 //@} 1853 1854 /// \name Geode 1855 /// Geode processors. 1856 //@{ 1857 CK_Geode 1858 //@} 1859 } CPU; 1860 1861public: 1862 X86TargetInfo(const std::string& triple) 1863 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1864 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false), 1865 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false), 1866 HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false), 1867 HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) { 1868 BigEndian = false; 1869 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1870 } 1871 virtual unsigned getFloatEvalMethod() const { 1872 // X87 evaluates with 80 bits "long double" precision. 1873 return SSELevel == NoSSE ? 2 : 0; 1874 } 1875 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1876 unsigned &NumRecords) const { 1877 Records = BuiltinInfo; 1878 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1879 } 1880 virtual void getGCCRegNames(const char * const *&Names, 1881 unsigned &NumNames) const { 1882 Names = GCCRegNames; 1883 NumNames = llvm::array_lengthof(GCCRegNames); 1884 } 1885 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1886 unsigned &NumAliases) const { 1887 Aliases = 0; 1888 NumAliases = 0; 1889 } 1890 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1891 unsigned &NumNames) const { 1892 Names = AddlRegNames; 1893 NumNames = llvm::array_lengthof(AddlRegNames); 1894 } 1895 virtual bool validateAsmConstraint(const char *&Name, 1896 TargetInfo::ConstraintInfo &info) const; 1897 virtual std::string convertConstraint(const char *&Constraint) const; 1898 virtual const char *getClobbers() const { 1899 return "~{dirflag},~{fpsr},~{flags}"; 1900 } 1901 virtual void getTargetDefines(const LangOptions &Opts, 1902 MacroBuilder &Builder) const; 1903 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1904 StringRef Name, 1905 bool Enabled) const; 1906 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1907 virtual bool hasFeature(StringRef Feature) const; 1908 virtual void HandleTargetFeatures(std::vector<std::string> &Features); 1909 virtual const char* getABI() const { 1910 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1911 return "avx"; 1912 else if (getTriple().getArch() == llvm::Triple::x86 && 1913 MMX3DNowLevel == NoMMX3DNow) 1914 return "no-mmx"; 1915 return ""; 1916 } 1917 virtual bool setCPU(const std::string &Name) { 1918 CPU = llvm::StringSwitch<CPUKind>(Name) 1919 .Case("i386", CK_i386) 1920 .Case("i486", CK_i486) 1921 .Case("winchip-c6", CK_WinChipC6) 1922 .Case("winchip2", CK_WinChip2) 1923 .Case("c3", CK_C3) 1924 .Case("i586", CK_i586) 1925 .Case("pentium", CK_Pentium) 1926 .Case("pentium-mmx", CK_PentiumMMX) 1927 .Case("i686", CK_i686) 1928 .Case("pentiumpro", CK_PentiumPro) 1929 .Case("pentium2", CK_Pentium2) 1930 .Case("pentium3", CK_Pentium3) 1931 .Case("pentium3m", CK_Pentium3M) 1932 .Case("pentium-m", CK_PentiumM) 1933 .Case("c3-2", CK_C3_2) 1934 .Case("yonah", CK_Yonah) 1935 .Case("pentium4", CK_Pentium4) 1936 .Case("pentium4m", CK_Pentium4M) 1937 .Case("prescott", CK_Prescott) 1938 .Case("nocona", CK_Nocona) 1939 .Case("core2", CK_Core2) 1940 .Case("penryn", CK_Penryn) 1941 .Case("atom", CK_Atom) 1942 .Case("corei7", CK_Corei7) 1943 .Case("corei7-avx", CK_Corei7AVX) 1944 .Case("core-avx-i", CK_CoreAVXi) 1945 .Case("core-avx2", CK_CoreAVX2) 1946 .Case("k6", CK_K6) 1947 .Case("k6-2", CK_K6_2) 1948 .Case("k6-3", CK_K6_3) 1949 .Case("athlon", CK_Athlon) 1950 .Case("athlon-tbird", CK_AthlonThunderbird) 1951 .Case("athlon-4", CK_Athlon4) 1952 .Case("athlon-xp", CK_AthlonXP) 1953 .Case("athlon-mp", CK_AthlonMP) 1954 .Case("athlon64", CK_Athlon64) 1955 .Case("athlon64-sse3", CK_Athlon64SSE3) 1956 .Case("athlon-fx", CK_AthlonFX) 1957 .Case("k8", CK_K8) 1958 .Case("k8-sse3", CK_K8SSE3) 1959 .Case("opteron", CK_Opteron) 1960 .Case("opteron-sse3", CK_OpteronSSE3) 1961 .Case("amdfam10", CK_AMDFAM10) 1962 .Case("btver1", CK_BTVER1) 1963 .Case("btver2", CK_BTVER2) 1964 .Case("bdver1", CK_BDVER1) 1965 .Case("bdver2", CK_BDVER2) 1966 .Case("x86-64", CK_x86_64) 1967 .Case("geode", CK_Geode) 1968 .Default(CK_Generic); 1969 1970 // Perform any per-CPU checks necessary to determine if this CPU is 1971 // acceptable. 1972 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1973 // invalid without explaining *why*. 1974 switch (CPU) { 1975 case CK_Generic: 1976 // No processor selected! 1977 return false; 1978 1979 case CK_i386: 1980 case CK_i486: 1981 case CK_WinChipC6: 1982 case CK_WinChip2: 1983 case CK_C3: 1984 case CK_i586: 1985 case CK_Pentium: 1986 case CK_PentiumMMX: 1987 case CK_i686: 1988 case CK_PentiumPro: 1989 case CK_Pentium2: 1990 case CK_Pentium3: 1991 case CK_Pentium3M: 1992 case CK_PentiumM: 1993 case CK_Yonah: 1994 case CK_C3_2: 1995 case CK_Pentium4: 1996 case CK_Pentium4M: 1997 case CK_Prescott: 1998 case CK_K6: 1999 case CK_K6_2: 2000 case CK_K6_3: 2001 case CK_Athlon: 2002 case CK_AthlonThunderbird: 2003 case CK_Athlon4: 2004 case CK_AthlonXP: 2005 case CK_AthlonMP: 2006 case CK_Geode: 2007 // Only accept certain architectures when compiling in 32-bit mode. 2008 if (getTriple().getArch() != llvm::Triple::x86) 2009 return false; 2010 2011 // Fallthrough 2012 case CK_Nocona: 2013 case CK_Core2: 2014 case CK_Penryn: 2015 case CK_Atom: 2016 case CK_Corei7: 2017 case CK_Corei7AVX: 2018 case CK_CoreAVXi: 2019 case CK_CoreAVX2: 2020 case CK_Athlon64: 2021 case CK_Athlon64SSE3: 2022 case CK_AthlonFX: 2023 case CK_K8: 2024 case CK_K8SSE3: 2025 case CK_Opteron: 2026 case CK_OpteronSSE3: 2027 case CK_AMDFAM10: 2028 case CK_BTVER1: 2029 case CK_BTVER2: 2030 case CK_BDVER1: 2031 case CK_BDVER2: 2032 case CK_x86_64: 2033 return true; 2034 } 2035 llvm_unreachable("Unhandled CPU kind"); 2036 } 2037 2038 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 2039 // We accept all non-ARM calling conventions 2040 return (CC == CC_X86ThisCall || 2041 CC == CC_X86FastCall || 2042 CC == CC_X86StdCall || 2043 CC == CC_C || 2044 CC == CC_X86Pascal || 2045 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2046 } 2047 2048 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 2049 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2050 } 2051}; 2052 2053void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2054 // FIXME: This should not be here. 2055 Features["3dnow"] = false; 2056 Features["3dnowa"] = false; 2057 Features["mmx"] = false; 2058 Features["sse"] = false; 2059 Features["sse2"] = false; 2060 Features["sse3"] = false; 2061 Features["ssse3"] = false; 2062 Features["sse41"] = false; 2063 Features["sse42"] = false; 2064 Features["sse4a"] = false; 2065 Features["aes"] = false; 2066 Features["pclmul"] = false; 2067 Features["avx"] = false; 2068 Features["avx2"] = false; 2069 Features["lzcnt"] = false; 2070 Features["rdrand"] = false; 2071 Features["bmi"] = false; 2072 Features["bmi2"] = false; 2073 Features["popcnt"] = false; 2074 Features["rtm"] = false; 2075 Features["prfchw"] = false; 2076 Features["rdseed"] = false; 2077 Features["fma4"] = false; 2078 Features["fma"] = false; 2079 Features["xop"] = false; 2080 Features["f16c"] = false; 2081 2082 // FIXME: This *really* should not be here. 2083 2084 // X86_64 always has SSE2. 2085 if (getTriple().getArch() == llvm::Triple::x86_64) 2086 setFeatureEnabled(Features, "sse2", true); 2087 2088 switch (CPU) { 2089 case CK_Generic: 2090 case CK_i386: 2091 case CK_i486: 2092 case CK_i586: 2093 case CK_Pentium: 2094 case CK_i686: 2095 case CK_PentiumPro: 2096 break; 2097 case CK_PentiumMMX: 2098 case CK_Pentium2: 2099 setFeatureEnabled(Features, "mmx", true); 2100 break; 2101 case CK_Pentium3: 2102 case CK_Pentium3M: 2103 setFeatureEnabled(Features, "sse", true); 2104 break; 2105 case CK_PentiumM: 2106 case CK_Pentium4: 2107 case CK_Pentium4M: 2108 case CK_x86_64: 2109 setFeatureEnabled(Features, "sse2", true); 2110 break; 2111 case CK_Yonah: 2112 case CK_Prescott: 2113 case CK_Nocona: 2114 setFeatureEnabled(Features, "sse3", true); 2115 break; 2116 case CK_Core2: 2117 setFeatureEnabled(Features, "ssse3", true); 2118 break; 2119 case CK_Penryn: 2120 setFeatureEnabled(Features, "sse4.1", true); 2121 break; 2122 case CK_Atom: 2123 setFeatureEnabled(Features, "ssse3", true); 2124 break; 2125 case CK_Corei7: 2126 setFeatureEnabled(Features, "sse4", true); 2127 break; 2128 case CK_Corei7AVX: 2129 setFeatureEnabled(Features, "avx", true); 2130 setFeatureEnabled(Features, "aes", true); 2131 setFeatureEnabled(Features, "pclmul", true); 2132 break; 2133 case CK_CoreAVXi: 2134 setFeatureEnabled(Features, "avx", true); 2135 setFeatureEnabled(Features, "aes", true); 2136 setFeatureEnabled(Features, "pclmul", true); 2137 setFeatureEnabled(Features, "rdrnd", true); 2138 setFeatureEnabled(Features, "f16c", true); 2139 break; 2140 case CK_CoreAVX2: 2141 setFeatureEnabled(Features, "avx2", true); 2142 setFeatureEnabled(Features, "aes", true); 2143 setFeatureEnabled(Features, "pclmul", true); 2144 setFeatureEnabled(Features, "lzcnt", true); 2145 setFeatureEnabled(Features, "rdrnd", true); 2146 setFeatureEnabled(Features, "f16c", true); 2147 setFeatureEnabled(Features, "bmi", true); 2148 setFeatureEnabled(Features, "bmi2", true); 2149 setFeatureEnabled(Features, "rtm", true); 2150 setFeatureEnabled(Features, "fma", true); 2151 break; 2152 case CK_K6: 2153 case CK_WinChipC6: 2154 setFeatureEnabled(Features, "mmx", true); 2155 break; 2156 case CK_K6_2: 2157 case CK_K6_3: 2158 case CK_WinChip2: 2159 case CK_C3: 2160 setFeatureEnabled(Features, "3dnow", true); 2161 break; 2162 case CK_Athlon: 2163 case CK_AthlonThunderbird: 2164 case CK_Geode: 2165 setFeatureEnabled(Features, "3dnowa", true); 2166 break; 2167 case CK_Athlon4: 2168 case CK_AthlonXP: 2169 case CK_AthlonMP: 2170 setFeatureEnabled(Features, "sse", true); 2171 setFeatureEnabled(Features, "3dnowa", true); 2172 break; 2173 case CK_K8: 2174 case CK_Opteron: 2175 case CK_Athlon64: 2176 case CK_AthlonFX: 2177 setFeatureEnabled(Features, "sse2", true); 2178 setFeatureEnabled(Features, "3dnowa", true); 2179 break; 2180 case CK_K8SSE3: 2181 case CK_OpteronSSE3: 2182 case CK_Athlon64SSE3: 2183 setFeatureEnabled(Features, "sse3", true); 2184 setFeatureEnabled(Features, "3dnowa", true); 2185 break; 2186 case CK_AMDFAM10: 2187 setFeatureEnabled(Features, "sse3", true); 2188 setFeatureEnabled(Features, "sse4a", true); 2189 setFeatureEnabled(Features, "3dnowa", true); 2190 setFeatureEnabled(Features, "lzcnt", true); 2191 setFeatureEnabled(Features, "popcnt", true); 2192 break; 2193 case CK_BTVER1: 2194 setFeatureEnabled(Features, "ssse3", true); 2195 setFeatureEnabled(Features, "sse4a", true); 2196 setFeatureEnabled(Features, "lzcnt", true); 2197 setFeatureEnabled(Features, "popcnt", true); 2198 break; 2199 case CK_BTVER2: 2200 setFeatureEnabled(Features, "avx", true); 2201 setFeatureEnabled(Features, "sse4a", true); 2202 setFeatureEnabled(Features, "lzcnt", true); 2203 setFeatureEnabled(Features, "aes", true); 2204 setFeatureEnabled(Features, "pclmul", true); 2205 setFeatureEnabled(Features, "bmi", true); 2206 setFeatureEnabled(Features, "f16c", true); 2207 break; 2208 case CK_BDVER1: 2209 setFeatureEnabled(Features, "xop", true); 2210 setFeatureEnabled(Features, "lzcnt", true); 2211 setFeatureEnabled(Features, "aes", true); 2212 setFeatureEnabled(Features, "pclmul", true); 2213 break; 2214 case CK_BDVER2: 2215 setFeatureEnabled(Features, "xop", true); 2216 setFeatureEnabled(Features, "lzcnt", true); 2217 setFeatureEnabled(Features, "aes", true); 2218 setFeatureEnabled(Features, "pclmul", true); 2219 setFeatureEnabled(Features, "bmi", true); 2220 setFeatureEnabled(Features, "fma", true); 2221 setFeatureEnabled(Features, "f16c", true); 2222 break; 2223 case CK_C3_2: 2224 setFeatureEnabled(Features, "sse", true); 2225 break; 2226 } 2227} 2228 2229bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 2230 StringRef Name, 2231 bool Enabled) const { 2232 // FIXME: This *really* should not be here. We need some way of translating 2233 // options into llvm subtarget features. 2234 if (!Features.count(Name) && 2235 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" && 2236 Name != "rdrnd")) 2237 return false; 2238 2239 // FIXME: this should probably use a switch with fall through. 2240 2241 if (Enabled) { 2242 if (Name == "mmx") 2243 Features["mmx"] = true; 2244 else if (Name == "sse") 2245 Features["mmx"] = Features["sse"] = true; 2246 else if (Name == "sse2") 2247 Features["mmx"] = Features["sse"] = Features["sse2"] = true; 2248 else if (Name == "sse3") 2249 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2250 true; 2251 else if (Name == "ssse3") 2252 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2253 Features["ssse3"] = true; 2254 else if (Name == "sse4" || Name == "sse4.2") 2255 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2256 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2257 Features["popcnt"] = true; 2258 else if (Name == "sse4.1") 2259 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2260 Features["ssse3"] = Features["sse41"] = true; 2261 else if (Name == "3dnow") 2262 Features["mmx"] = Features["3dnow"] = true; 2263 else if (Name == "3dnowa") 2264 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true; 2265 else if (Name == "aes") 2266 Features["sse"] = Features["sse2"] = Features["aes"] = true; 2267 else if (Name == "pclmul") 2268 Features["sse"] = Features["sse2"] = Features["pclmul"] = true; 2269 else if (Name == "avx") 2270 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2271 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2272 Features["popcnt"] = Features["avx"] = true; 2273 else if (Name == "avx2") 2274 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2275 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2276 Features["popcnt"] = Features["avx"] = Features["avx2"] = true; 2277 else if (Name == "fma") 2278 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2279 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2280 Features["popcnt"] = Features["avx"] = Features["fma"] = true; 2281 else if (Name == "fma4") 2282 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2283 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2284 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 2285 Features["fma4"] = true; 2286 else if (Name == "xop") 2287 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2288 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2289 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 2290 Features["fma4"] = Features["xop"] = true; 2291 else if (Name == "sse4a") 2292 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2293 Features["sse4a"] = true; 2294 else if (Name == "lzcnt") 2295 Features["lzcnt"] = true; 2296 else if (Name == "rdrnd") 2297 Features["rdrand"] = true; 2298 else if (Name == "bmi") 2299 Features["bmi"] = true; 2300 else if (Name == "bmi2") 2301 Features["bmi2"] = true; 2302 else if (Name == "popcnt") 2303 Features["popcnt"] = true; 2304 else if (Name == "f16c") 2305 Features["f16c"] = true; 2306 else if (Name == "rtm") 2307 Features["rtm"] = true; 2308 else if (Name == "prfchw") 2309 Features["prfchw"] = true; 2310 else if (Name == "rdseed") 2311 Features["rdseed"] = true; 2312 } else { 2313 if (Name == "mmx") 2314 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; 2315 else if (Name == "sse") 2316 Features["sse"] = Features["sse2"] = Features["sse3"] = 2317 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2318 Features["sse4a"] = Features["avx"] = Features["avx2"] = 2319 Features["fma"] = Features["fma4"] = Features["aes"] = 2320 Features["pclmul"] = Features["xop"] = false; 2321 else if (Name == "sse2") 2322 Features["sse2"] = Features["sse3"] = Features["ssse3"] = 2323 Features["sse41"] = Features["sse42"] = Features["sse4a"] = 2324 Features["avx"] = Features["avx2"] = Features["fma"] = 2325 Features["fma4"] = Features["aes"] = Features["pclmul"] = 2326 Features["xop"] = false; 2327 else if (Name == "sse3") 2328 Features["sse3"] = Features["ssse3"] = Features["sse41"] = 2329 Features["sse42"] = Features["sse4a"] = Features["avx"] = 2330 Features["avx2"] = Features["fma"] = Features["fma4"] = 2331 Features["xop"] = false; 2332 else if (Name == "ssse3") 2333 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2334 Features["avx"] = Features["avx2"] = Features["fma"] = false; 2335 else if (Name == "sse4" || Name == "sse4.1") 2336 Features["sse41"] = Features["sse42"] = Features["avx"] = 2337 Features["avx2"] = Features["fma"] = false; 2338 else if (Name == "sse4.2") 2339 Features["sse42"] = Features["avx"] = Features["avx2"] = 2340 Features["fma"] = false; 2341 else if (Name == "3dnow") 2342 Features["3dnow"] = Features["3dnowa"] = false; 2343 else if (Name == "3dnowa") 2344 Features["3dnowa"] = false; 2345 else if (Name == "aes") 2346 Features["aes"] = false; 2347 else if (Name == "pclmul") 2348 Features["pclmul"] = false; 2349 else if (Name == "avx") 2350 Features["avx"] = Features["avx2"] = Features["fma"] = 2351 Features["fma4"] = Features["xop"] = false; 2352 else if (Name == "avx2") 2353 Features["avx2"] = false; 2354 else if (Name == "fma") 2355 Features["fma"] = false; 2356 else if (Name == "sse4a") 2357 Features["sse4a"] = Features["fma4"] = Features["xop"] = false; 2358 else if (Name == "lzcnt") 2359 Features["lzcnt"] = false; 2360 else if (Name == "rdrnd") 2361 Features["rdrand"] = false; 2362 else if (Name == "bmi") 2363 Features["bmi"] = false; 2364 else if (Name == "bmi2") 2365 Features["bmi2"] = false; 2366 else if (Name == "popcnt") 2367 Features["popcnt"] = false; 2368 else if (Name == "fma4") 2369 Features["fma4"] = Features["xop"] = false; 2370 else if (Name == "xop") 2371 Features["xop"] = false; 2372 else if (Name == "f16c") 2373 Features["f16c"] = false; 2374 else if (Name == "rtm") 2375 Features["rtm"] = false; 2376 else if (Name == "prfchw") 2377 Features["prfchw"] = false; 2378 else if (Name == "rdseed") 2379 Features["rdseed"] = false; 2380 } 2381 2382 return true; 2383} 2384 2385/// HandleTargetOptions - Perform initialization based on the user 2386/// configured set of features. 2387void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) { 2388 // Remember the maximum enabled sselevel. 2389 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2390 // Ignore disabled features. 2391 if (Features[i][0] == '-') 2392 continue; 2393 2394 StringRef Feature = StringRef(Features[i]).substr(1); 2395 2396 if (Feature == "aes") { 2397 HasAES = true; 2398 continue; 2399 } 2400 2401 if (Feature == "pclmul") { 2402 HasPCLMUL = true; 2403 continue; 2404 } 2405 2406 if (Feature == "lzcnt") { 2407 HasLZCNT = true; 2408 continue; 2409 } 2410 2411 if (Feature == "rdrand") { 2412 HasRDRND = true; 2413 continue; 2414 } 2415 2416 if (Feature == "bmi") { 2417 HasBMI = true; 2418 continue; 2419 } 2420 2421 if (Feature == "bmi2") { 2422 HasBMI2 = true; 2423 continue; 2424 } 2425 2426 if (Feature == "popcnt") { 2427 HasPOPCNT = true; 2428 continue; 2429 } 2430 2431 if (Feature == "rtm") { 2432 HasRTM = true; 2433 continue; 2434 } 2435 2436 if (Feature == "prfchw") { 2437 HasPRFCHW = true; 2438 continue; 2439 } 2440 2441 if (Feature == "rdseed") { 2442 HasRDSEED = true; 2443 continue; 2444 } 2445 2446 if (Feature == "sse4a") { 2447 HasSSE4a = true; 2448 continue; 2449 } 2450 2451 if (Feature == "fma4") { 2452 HasFMA4 = true; 2453 continue; 2454 } 2455 2456 if (Feature == "fma") { 2457 HasFMA = true; 2458 continue; 2459 } 2460 2461 if (Feature == "xop") { 2462 HasXOP = true; 2463 continue; 2464 } 2465 2466 if (Feature == "f16c") { 2467 HasF16C = true; 2468 continue; 2469 } 2470 2471 assert(Features[i][0] == '+' && "Invalid target feature!"); 2472 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2473 .Case("avx2", AVX2) 2474 .Case("avx", AVX) 2475 .Case("sse42", SSE42) 2476 .Case("sse41", SSE41) 2477 .Case("ssse3", SSSE3) 2478 .Case("sse3", SSE3) 2479 .Case("sse2", SSE2) 2480 .Case("sse", SSE1) 2481 .Default(NoSSE); 2482 SSELevel = std::max(SSELevel, Level); 2483 2484 MMX3DNowEnum ThreeDNowLevel = 2485 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2486 .Case("3dnowa", AMD3DNowAthlon) 2487 .Case("3dnow", AMD3DNow) 2488 .Case("mmx", MMX) 2489 .Default(NoMMX3DNow); 2490 2491 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2492 } 2493 2494 // Don't tell the backend if we're turning off mmx; it will end up disabling 2495 // SSE, which we don't want. 2496 std::vector<std::string>::iterator it; 2497 it = std::find(Features.begin(), Features.end(), "-mmx"); 2498 if (it != Features.end()) 2499 Features.erase(it); 2500} 2501 2502/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2503/// definitions for this particular subtarget. 2504void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2505 MacroBuilder &Builder) const { 2506 // Target identification. 2507 if (getTriple().getArch() == llvm::Triple::x86_64) { 2508 Builder.defineMacro("__amd64__"); 2509 Builder.defineMacro("__amd64"); 2510 Builder.defineMacro("__x86_64"); 2511 Builder.defineMacro("__x86_64__"); 2512 } else { 2513 DefineStd(Builder, "i386", Opts); 2514 } 2515 2516 // Subtarget options. 2517 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2518 // truly should be based on -mtune options. 2519 switch (CPU) { 2520 case CK_Generic: 2521 break; 2522 case CK_i386: 2523 // The rest are coming from the i386 define above. 2524 Builder.defineMacro("__tune_i386__"); 2525 break; 2526 case CK_i486: 2527 case CK_WinChipC6: 2528 case CK_WinChip2: 2529 case CK_C3: 2530 defineCPUMacros(Builder, "i486"); 2531 break; 2532 case CK_PentiumMMX: 2533 Builder.defineMacro("__pentium_mmx__"); 2534 Builder.defineMacro("__tune_pentium_mmx__"); 2535 // Fallthrough 2536 case CK_i586: 2537 case CK_Pentium: 2538 defineCPUMacros(Builder, "i586"); 2539 defineCPUMacros(Builder, "pentium"); 2540 break; 2541 case CK_Pentium3: 2542 case CK_Pentium3M: 2543 case CK_PentiumM: 2544 Builder.defineMacro("__tune_pentium3__"); 2545 // Fallthrough 2546 case CK_Pentium2: 2547 case CK_C3_2: 2548 Builder.defineMacro("__tune_pentium2__"); 2549 // Fallthrough 2550 case CK_PentiumPro: 2551 Builder.defineMacro("__tune_i686__"); 2552 Builder.defineMacro("__tune_pentiumpro__"); 2553 // Fallthrough 2554 case CK_i686: 2555 Builder.defineMacro("__i686"); 2556 Builder.defineMacro("__i686__"); 2557 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2558 Builder.defineMacro("__pentiumpro"); 2559 Builder.defineMacro("__pentiumpro__"); 2560 break; 2561 case CK_Pentium4: 2562 case CK_Pentium4M: 2563 defineCPUMacros(Builder, "pentium4"); 2564 break; 2565 case CK_Yonah: 2566 case CK_Prescott: 2567 case CK_Nocona: 2568 defineCPUMacros(Builder, "nocona"); 2569 break; 2570 case CK_Core2: 2571 case CK_Penryn: 2572 defineCPUMacros(Builder, "core2"); 2573 break; 2574 case CK_Atom: 2575 defineCPUMacros(Builder, "atom"); 2576 break; 2577 case CK_Corei7: 2578 case CK_Corei7AVX: 2579 case CK_CoreAVXi: 2580 case CK_CoreAVX2: 2581 defineCPUMacros(Builder, "corei7"); 2582 break; 2583 case CK_K6_2: 2584 Builder.defineMacro("__k6_2__"); 2585 Builder.defineMacro("__tune_k6_2__"); 2586 // Fallthrough 2587 case CK_K6_3: 2588 if (CPU != CK_K6_2) { // In case of fallthrough 2589 // FIXME: GCC may be enabling these in cases where some other k6 2590 // architecture is specified but -m3dnow is explicitly provided. The 2591 // exact semantics need to be determined and emulated here. 2592 Builder.defineMacro("__k6_3__"); 2593 Builder.defineMacro("__tune_k6_3__"); 2594 } 2595 // Fallthrough 2596 case CK_K6: 2597 defineCPUMacros(Builder, "k6"); 2598 break; 2599 case CK_Athlon: 2600 case CK_AthlonThunderbird: 2601 case CK_Athlon4: 2602 case CK_AthlonXP: 2603 case CK_AthlonMP: 2604 defineCPUMacros(Builder, "athlon"); 2605 if (SSELevel != NoSSE) { 2606 Builder.defineMacro("__athlon_sse__"); 2607 Builder.defineMacro("__tune_athlon_sse__"); 2608 } 2609 break; 2610 case CK_K8: 2611 case CK_K8SSE3: 2612 case CK_x86_64: 2613 case CK_Opteron: 2614 case CK_OpteronSSE3: 2615 case CK_Athlon64: 2616 case CK_Athlon64SSE3: 2617 case CK_AthlonFX: 2618 defineCPUMacros(Builder, "k8"); 2619 break; 2620 case CK_AMDFAM10: 2621 defineCPUMacros(Builder, "amdfam10"); 2622 break; 2623 case CK_BTVER1: 2624 defineCPUMacros(Builder, "btver1"); 2625 break; 2626 case CK_BTVER2: 2627 defineCPUMacros(Builder, "btver2"); 2628 break; 2629 case CK_BDVER1: 2630 defineCPUMacros(Builder, "bdver1"); 2631 break; 2632 case CK_BDVER2: 2633 defineCPUMacros(Builder, "bdver2"); 2634 break; 2635 case CK_Geode: 2636 defineCPUMacros(Builder, "geode"); 2637 break; 2638 } 2639 2640 // Target properties. 2641 Builder.defineMacro("__LITTLE_ENDIAN__"); 2642 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2643 2644 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2645 // functions in glibc header files that use FP Stack inline asm which the 2646 // backend can't deal with (PR879). 2647 Builder.defineMacro("__NO_MATH_INLINES"); 2648 2649 if (HasAES) 2650 Builder.defineMacro("__AES__"); 2651 2652 if (HasPCLMUL) 2653 Builder.defineMacro("__PCLMUL__"); 2654 2655 if (HasLZCNT) 2656 Builder.defineMacro("__LZCNT__"); 2657 2658 if (HasRDRND) 2659 Builder.defineMacro("__RDRND__"); 2660 2661 if (HasBMI) 2662 Builder.defineMacro("__BMI__"); 2663 2664 if (HasBMI2) 2665 Builder.defineMacro("__BMI2__"); 2666 2667 if (HasPOPCNT) 2668 Builder.defineMacro("__POPCNT__"); 2669 2670 if (HasRTM) 2671 Builder.defineMacro("__RTM__"); 2672 2673 if (HasPRFCHW) 2674 Builder.defineMacro("__PRFCHW__"); 2675 2676 if (HasRDSEED) 2677 Builder.defineMacro("__RDSEED__"); 2678 2679 if (HasSSE4a) 2680 Builder.defineMacro("__SSE4A__"); 2681 2682 if (HasFMA4) 2683 Builder.defineMacro("__FMA4__"); 2684 2685 if (HasFMA) 2686 Builder.defineMacro("__FMA__"); 2687 2688 if (HasXOP) 2689 Builder.defineMacro("__XOP__"); 2690 2691 if (HasF16C) 2692 Builder.defineMacro("__F16C__"); 2693 2694 // Each case falls through to the previous one here. 2695 switch (SSELevel) { 2696 case AVX2: 2697 Builder.defineMacro("__AVX2__"); 2698 case AVX: 2699 Builder.defineMacro("__AVX__"); 2700 case SSE42: 2701 Builder.defineMacro("__SSE4_2__"); 2702 case SSE41: 2703 Builder.defineMacro("__SSE4_1__"); 2704 case SSSE3: 2705 Builder.defineMacro("__SSSE3__"); 2706 case SSE3: 2707 Builder.defineMacro("__SSE3__"); 2708 case SSE2: 2709 Builder.defineMacro("__SSE2__"); 2710 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2711 case SSE1: 2712 Builder.defineMacro("__SSE__"); 2713 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2714 case NoSSE: 2715 break; 2716 } 2717 2718 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2719 switch (SSELevel) { 2720 case AVX2: 2721 case AVX: 2722 case SSE42: 2723 case SSE41: 2724 case SSSE3: 2725 case SSE3: 2726 case SSE2: 2727 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2728 break; 2729 case SSE1: 2730 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2731 break; 2732 default: 2733 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2734 } 2735 } 2736 2737 // Each case falls through to the previous one here. 2738 switch (MMX3DNowLevel) { 2739 case AMD3DNowAthlon: 2740 Builder.defineMacro("__3dNOW_A__"); 2741 case AMD3DNow: 2742 Builder.defineMacro("__3dNOW__"); 2743 case MMX: 2744 Builder.defineMacro("__MMX__"); 2745 case NoMMX3DNow: 2746 break; 2747 } 2748 2749 if (CPU >= CK_i486) { 2750 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2751 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2752 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2753 } 2754 if (CPU >= CK_i586) 2755 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2756} 2757 2758bool X86TargetInfo::hasFeature(StringRef Feature) const { 2759 return llvm::StringSwitch<bool>(Feature) 2760 .Case("aes", HasAES) 2761 .Case("avx", SSELevel >= AVX) 2762 .Case("avx2", SSELevel >= AVX2) 2763 .Case("bmi", HasBMI) 2764 .Case("bmi2", HasBMI2) 2765 .Case("fma", HasFMA) 2766 .Case("fma4", HasFMA4) 2767 .Case("lzcnt", HasLZCNT) 2768 .Case("rdrnd", HasRDRND) 2769 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2770 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2771 .Case("mmx", MMX3DNowLevel >= MMX) 2772 .Case("pclmul", HasPCLMUL) 2773 .Case("popcnt", HasPOPCNT) 2774 .Case("rtm", HasRTM) 2775 .Case("prfchw", HasPRFCHW) 2776 .Case("rdseed", HasRDSEED) 2777 .Case("sse", SSELevel >= SSE1) 2778 .Case("sse2", SSELevel >= SSE2) 2779 .Case("sse3", SSELevel >= SSE3) 2780 .Case("ssse3", SSELevel >= SSSE3) 2781 .Case("sse41", SSELevel >= SSE41) 2782 .Case("sse42", SSELevel >= SSE42) 2783 .Case("sse4a", HasSSE4a) 2784 .Case("x86", true) 2785 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2786 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2787 .Case("xop", HasXOP) 2788 .Case("f16c", HasF16C) 2789 .Default(false); 2790} 2791 2792bool 2793X86TargetInfo::validateAsmConstraint(const char *&Name, 2794 TargetInfo::ConstraintInfo &Info) const { 2795 switch (*Name) { 2796 default: return false; 2797 case 'Y': // first letter of a pair: 2798 switch (*(Name+1)) { 2799 default: return false; 2800 case '0': // First SSE register. 2801 case 't': // Any SSE register, when SSE2 is enabled. 2802 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2803 case 'm': // any MMX register, when inter-unit moves enabled. 2804 break; // falls through to setAllowsRegister. 2805 } 2806 case 'a': // eax. 2807 case 'b': // ebx. 2808 case 'c': // ecx. 2809 case 'd': // edx. 2810 case 'S': // esi. 2811 case 'D': // edi. 2812 case 'A': // edx:eax. 2813 case 'f': // any x87 floating point stack register. 2814 case 't': // top of floating point stack. 2815 case 'u': // second from top of floating point stack. 2816 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2817 case 'y': // Any MMX register. 2818 case 'x': // Any SSE register. 2819 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2820 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2821 case 'l': // "Index" registers: any general register that can be used as an 2822 // index in a base+index memory access. 2823 Info.setAllowsRegister(); 2824 return true; 2825 case 'C': // SSE floating point constant. 2826 case 'G': // x87 floating point constant. 2827 case 'e': // 32-bit signed integer constant for use with zero-extending 2828 // x86_64 instructions. 2829 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2830 // x86_64 instructions. 2831 return true; 2832 } 2833} 2834 2835 2836std::string 2837X86TargetInfo::convertConstraint(const char *&Constraint) const { 2838 switch (*Constraint) { 2839 case 'a': return std::string("{ax}"); 2840 case 'b': return std::string("{bx}"); 2841 case 'c': return std::string("{cx}"); 2842 case 'd': return std::string("{dx}"); 2843 case 'S': return std::string("{si}"); 2844 case 'D': return std::string("{di}"); 2845 case 'p': // address 2846 return std::string("im"); 2847 case 't': // top of floating point stack. 2848 return std::string("{st}"); 2849 case 'u': // second from top of floating point stack. 2850 return std::string("{st(1)}"); // second from top of floating point stack. 2851 default: 2852 return std::string(1, *Constraint); 2853 } 2854} 2855} // end anonymous namespace 2856 2857namespace { 2858// X86-32 generic target 2859class X86_32TargetInfo : public X86TargetInfo { 2860public: 2861 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) { 2862 DoubleAlign = LongLongAlign = 32; 2863 LongDoubleWidth = 96; 2864 LongDoubleAlign = 32; 2865 SuitableAlign = 128; 2866 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2867 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2868 "a0:0:64-f80:32:32-n8:16:32-S128"; 2869 SizeType = UnsignedInt; 2870 PtrDiffType = SignedInt; 2871 IntPtrType = SignedInt; 2872 RegParmMax = 3; 2873 2874 // Use fpret for all types. 2875 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2876 (1 << TargetInfo::Double) | 2877 (1 << TargetInfo::LongDouble)); 2878 2879 // x86-32 has atomics up to 8 bytes 2880 // FIXME: Check that we actually have cmpxchg8b before setting 2881 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2882 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2883 } 2884 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2885 return TargetInfo::CharPtrBuiltinVaList; 2886 } 2887 2888 int getEHDataRegisterNumber(unsigned RegNo) const { 2889 if (RegNo == 0) return 0; 2890 if (RegNo == 1) return 2; 2891 return -1; 2892 } 2893 virtual bool validateInputSize(StringRef Constraint, 2894 unsigned Size) const { 2895 switch (Constraint[0]) { 2896 default: break; 2897 case 'a': 2898 case 'b': 2899 case 'c': 2900 case 'd': 2901 return Size <= 32; 2902 } 2903 2904 return true; 2905 } 2906}; 2907} // end anonymous namespace 2908 2909namespace { 2910class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2911public: 2912 NetBSDI386TargetInfo(const std::string &triple) : 2913 NetBSDTargetInfo<X86_32TargetInfo>(triple) { 2914 } 2915 2916 virtual unsigned getFloatEvalMethod() const { 2917 // NetBSD defaults to "double" rounding 2918 return 1; 2919 } 2920}; 2921} // end anonymous namespace 2922 2923namespace { 2924class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2925public: 2926 OpenBSDI386TargetInfo(const std::string& triple) : 2927 OpenBSDTargetInfo<X86_32TargetInfo>(triple) { 2928 SizeType = UnsignedLong; 2929 IntPtrType = SignedLong; 2930 PtrDiffType = SignedLong; 2931 } 2932}; 2933} // end anonymous namespace 2934 2935namespace { 2936class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2937public: 2938 BitrigI386TargetInfo(const std::string& triple) : 2939 BitrigTargetInfo<X86_32TargetInfo>(triple) { 2940 SizeType = UnsignedLong; 2941 IntPtrType = SignedLong; 2942 PtrDiffType = SignedLong; 2943 } 2944}; 2945} // end anonymous namespace 2946 2947namespace { 2948class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2949public: 2950 DarwinI386TargetInfo(const std::string& triple) : 2951 DarwinTargetInfo<X86_32TargetInfo>(triple) { 2952 LongDoubleWidth = 128; 2953 LongDoubleAlign = 128; 2954 SuitableAlign = 128; 2955 MaxVectorAlign = 256; 2956 SizeType = UnsignedLong; 2957 IntPtrType = SignedLong; 2958 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2959 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2960 "a0:0:64-f80:128:128-n8:16:32-S128"; 2961 HasAlignMac68kSupport = true; 2962 } 2963 2964}; 2965} // end anonymous namespace 2966 2967namespace { 2968// x86-32 Windows target 2969class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2970public: 2971 WindowsX86_32TargetInfo(const std::string& triple) 2972 : WindowsTargetInfo<X86_32TargetInfo>(triple) { 2973 TLSSupported = false; 2974 WCharType = UnsignedShort; 2975 DoubleAlign = LongLongAlign = 64; 2976 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2977 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2978 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2979 } 2980 virtual void getTargetDefines(const LangOptions &Opts, 2981 MacroBuilder &Builder) const { 2982 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2983 } 2984}; 2985} // end anonymous namespace 2986 2987namespace { 2988 2989// x86-32 Windows Visual Studio target 2990class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2991public: 2992 VisualStudioWindowsX86_32TargetInfo(const std::string& triple) 2993 : WindowsX86_32TargetInfo(triple) { 2994 LongDoubleWidth = LongDoubleAlign = 64; 2995 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2996 } 2997 virtual void getTargetDefines(const LangOptions &Opts, 2998 MacroBuilder &Builder) const { 2999 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3000 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3001 // The value of the following reflects processor type. 3002 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3003 // We lost the original triple, so we use the default. 3004 Builder.defineMacro("_M_IX86", "600"); 3005 } 3006}; 3007} // end anonymous namespace 3008 3009namespace { 3010// x86-32 MinGW target 3011class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3012public: 3013 MinGWX86_32TargetInfo(const std::string& triple) 3014 : WindowsX86_32TargetInfo(triple) { 3015 } 3016 virtual void getTargetDefines(const LangOptions &Opts, 3017 MacroBuilder &Builder) const { 3018 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3019 DefineStd(Builder, "WIN32", Opts); 3020 DefineStd(Builder, "WINNT", Opts); 3021 Builder.defineMacro("_X86_"); 3022 Builder.defineMacro("__MSVCRT__"); 3023 Builder.defineMacro("__MINGW32__"); 3024 3025 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3026 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3027 if (Opts.MicrosoftExt) 3028 // Provide "as-is" __declspec. 3029 Builder.defineMacro("__declspec", "__declspec"); 3030 else 3031 // Provide alias of __attribute__ like mingw32-gcc. 3032 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3033 } 3034}; 3035} // end anonymous namespace 3036 3037namespace { 3038// x86-32 Cygwin target 3039class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3040public: 3041 CygwinX86_32TargetInfo(const std::string& triple) 3042 : X86_32TargetInfo(triple) { 3043 TLSSupported = false; 3044 WCharType = UnsignedShort; 3045 DoubleAlign = LongLongAlign = 64; 3046 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3047 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3048 "a0:0:64-f80:32:32-n8:16:32-S32"; 3049 } 3050 virtual void getTargetDefines(const LangOptions &Opts, 3051 MacroBuilder &Builder) const { 3052 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3053 Builder.defineMacro("_X86_"); 3054 Builder.defineMacro("__CYGWIN__"); 3055 Builder.defineMacro("__CYGWIN32__"); 3056 DefineStd(Builder, "unix", Opts); 3057 if (Opts.CPlusPlus) 3058 Builder.defineMacro("_GNU_SOURCE"); 3059 } 3060}; 3061} // end anonymous namespace 3062 3063namespace { 3064// x86-32 Haiku target 3065class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3066public: 3067 HaikuX86_32TargetInfo(const std::string& triple) 3068 : X86_32TargetInfo(triple) { 3069 SizeType = UnsignedLong; 3070 IntPtrType = SignedLong; 3071 PtrDiffType = SignedLong; 3072 ProcessIDType = SignedLong; 3073 this->UserLabelPrefix = ""; 3074 this->TLSSupported = false; 3075 } 3076 virtual void getTargetDefines(const LangOptions &Opts, 3077 MacroBuilder &Builder) const { 3078 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3079 Builder.defineMacro("__INTEL__"); 3080 Builder.defineMacro("__HAIKU__"); 3081 } 3082}; 3083} // end anonymous namespace 3084 3085// RTEMS Target 3086template<typename Target> 3087class RTEMSTargetInfo : public OSTargetInfo<Target> { 3088protected: 3089 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3090 MacroBuilder &Builder) const { 3091 // RTEMS defines; list based off of gcc output 3092 3093 Builder.defineMacro("__rtems__"); 3094 Builder.defineMacro("__ELF__"); 3095 } 3096public: 3097 RTEMSTargetInfo(const std::string &triple) 3098 : OSTargetInfo<Target>(triple) { 3099 this->UserLabelPrefix = ""; 3100 3101 llvm::Triple Triple(triple); 3102 switch (Triple.getArch()) { 3103 default: 3104 case llvm::Triple::x86: 3105 // this->MCountName = ".mcount"; 3106 break; 3107 case llvm::Triple::mips: 3108 case llvm::Triple::mipsel: 3109 case llvm::Triple::ppc: 3110 case llvm::Triple::ppc64: 3111 // this->MCountName = "_mcount"; 3112 break; 3113 case llvm::Triple::arm: 3114 // this->MCountName = "__mcount"; 3115 break; 3116 } 3117 3118 } 3119}; 3120 3121namespace { 3122// x86-32 RTEMS target 3123class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3124public: 3125 RTEMSX86_32TargetInfo(const std::string& triple) 3126 : X86_32TargetInfo(triple) { 3127 SizeType = UnsignedLong; 3128 IntPtrType = SignedLong; 3129 PtrDiffType = SignedLong; 3130 this->UserLabelPrefix = ""; 3131 } 3132 virtual void getTargetDefines(const LangOptions &Opts, 3133 MacroBuilder &Builder) const { 3134 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3135 Builder.defineMacro("__INTEL__"); 3136 Builder.defineMacro("__rtems__"); 3137 } 3138}; 3139} // end anonymous namespace 3140 3141namespace { 3142// x86-64 generic target 3143class X86_64TargetInfo : public X86TargetInfo { 3144public: 3145 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) { 3146 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3147 LongDoubleWidth = 128; 3148 LongDoubleAlign = 128; 3149 LargeArrayMinWidth = 128; 3150 LargeArrayAlign = 128; 3151 SuitableAlign = 128; 3152 IntMaxType = SignedLong; 3153 UIntMaxType = UnsignedLong; 3154 Int64Type = SignedLong; 3155 RegParmMax = 6; 3156 3157 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3158 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3159 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 3160 3161 // Use fpret only for long double. 3162 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3163 3164 // Use fp2ret for _Complex long double. 3165 ComplexLongDoubleUsesFP2Ret = true; 3166 3167 // x86-64 has atomics up to 16 bytes. 3168 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3169 // on CPUs with cmpxchg16b 3170 MaxAtomicPromoteWidth = 128; 3171 MaxAtomicInlineWidth = 64; 3172 } 3173 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3174 return TargetInfo::X86_64ABIBuiltinVaList; 3175 } 3176 3177 int getEHDataRegisterNumber(unsigned RegNo) const { 3178 if (RegNo == 0) return 0; 3179 if (RegNo == 1) return 1; 3180 return -1; 3181 } 3182 3183 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3184 return (CC == CC_Default || 3185 CC == CC_C || 3186 CC == CC_IntelOclBicc || 3187 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3188 } 3189 3190 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3191 return CC_C; 3192 } 3193 3194}; 3195} // end anonymous namespace 3196 3197namespace { 3198// x86-64 Windows target 3199class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3200public: 3201 WindowsX86_64TargetInfo(const std::string& triple) 3202 : WindowsTargetInfo<X86_64TargetInfo>(triple) { 3203 TLSSupported = false; 3204 WCharType = UnsignedShort; 3205 LongWidth = LongAlign = 32; 3206 DoubleAlign = LongLongAlign = 64; 3207 IntMaxType = SignedLongLong; 3208 UIntMaxType = UnsignedLongLong; 3209 Int64Type = SignedLongLong; 3210 SizeType = UnsignedLongLong; 3211 PtrDiffType = SignedLongLong; 3212 IntPtrType = SignedLongLong; 3213 this->UserLabelPrefix = ""; 3214 } 3215 virtual void getTargetDefines(const LangOptions &Opts, 3216 MacroBuilder &Builder) const { 3217 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3218 Builder.defineMacro("_WIN64"); 3219 } 3220 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3221 return TargetInfo::CharPtrBuiltinVaList; 3222 } 3223 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3224 return (CC == CC_C || 3225 CC == CC_IntelOclBicc || 3226 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3227 } 3228}; 3229} // end anonymous namespace 3230 3231namespace { 3232// x86-64 Windows Visual Studio target 3233class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3234public: 3235 VisualStudioWindowsX86_64TargetInfo(const std::string& triple) 3236 : WindowsX86_64TargetInfo(triple) { 3237 LongDoubleWidth = LongDoubleAlign = 64; 3238 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3239 } 3240 virtual void getTargetDefines(const LangOptions &Opts, 3241 MacroBuilder &Builder) const { 3242 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3243 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3244 Builder.defineMacro("_M_X64"); 3245 Builder.defineMacro("_M_AMD64"); 3246 } 3247}; 3248} // end anonymous namespace 3249 3250namespace { 3251// x86-64 MinGW target 3252class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3253public: 3254 MinGWX86_64TargetInfo(const std::string& triple) 3255 : WindowsX86_64TargetInfo(triple) { 3256 } 3257 virtual void getTargetDefines(const LangOptions &Opts, 3258 MacroBuilder &Builder) const { 3259 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3260 DefineStd(Builder, "WIN64", Opts); 3261 Builder.defineMacro("__MSVCRT__"); 3262 Builder.defineMacro("__MINGW32__"); 3263 Builder.defineMacro("__MINGW64__"); 3264 3265 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3266 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3267 if (Opts.MicrosoftExt) 3268 // Provide "as-is" __declspec. 3269 Builder.defineMacro("__declspec", "__declspec"); 3270 else 3271 // Provide alias of __attribute__ like mingw32-gcc. 3272 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3273 } 3274}; 3275} // end anonymous namespace 3276 3277namespace { 3278class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3279public: 3280 DarwinX86_64TargetInfo(const std::string& triple) 3281 : DarwinTargetInfo<X86_64TargetInfo>(triple) { 3282 Int64Type = SignedLongLong; 3283 MaxVectorAlign = 256; 3284 } 3285}; 3286} // end anonymous namespace 3287 3288namespace { 3289class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3290public: 3291 OpenBSDX86_64TargetInfo(const std::string& triple) 3292 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) { 3293 IntMaxType = SignedLongLong; 3294 UIntMaxType = UnsignedLongLong; 3295 Int64Type = SignedLongLong; 3296 } 3297}; 3298} // end anonymous namespace 3299 3300namespace { 3301class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3302public: 3303 BitrigX86_64TargetInfo(const std::string& triple) 3304 : BitrigTargetInfo<X86_64TargetInfo>(triple) { 3305 IntMaxType = SignedLongLong; 3306 UIntMaxType = UnsignedLongLong; 3307 Int64Type = SignedLongLong; 3308 } 3309}; 3310} 3311 3312namespace { 3313class AArch64TargetInfo : public TargetInfo { 3314 static const char * const GCCRegNames[]; 3315 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3316 3317 static const Builtin::Info BuiltinInfo[]; 3318public: 3319 AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) { 3320 BigEndian = false; 3321 LongWidth = LongAlign = 64; 3322 LongDoubleWidth = LongDoubleAlign = 128; 3323 PointerWidth = PointerAlign = 64; 3324 SuitableAlign = 128; 3325 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3326 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-" 3327 "f128:128:128-n32:64-S128"; 3328 3329 WCharType = UnsignedInt; 3330 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3331 3332 // AArch64 backend supports 64-bit operations at the moment. In principle 3333 // 128-bit is possible if register-pairs are used. 3334 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3335 3336 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3337 } 3338 virtual void getTargetDefines(const LangOptions &Opts, 3339 MacroBuilder &Builder) const { 3340 // GCC defines theses currently 3341 Builder.defineMacro("__aarch64__"); 3342 Builder.defineMacro("__AARCH64EL__"); 3343 3344 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3345 3346 // FIXME: these were written based on an unreleased version of a 32-bit ACLE 3347 // which was intended to be compatible with a 64-bit implementation. They 3348 // will need updating when a real 64-bit ACLE exists. Particularly pressing 3349 // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS. 3350 Builder.defineMacro("__ARM_ACLE", "101"); 3351 Builder.defineMacro("__ARM_ARCH", "8"); 3352 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3353 3354 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3355 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3356 Builder.defineMacro("__ARM_FEATURE_FMA"); 3357 3358 // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean 3359 // 128-bit LDXP present, at which point this becomes 0x1f. 3360 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf"); 3361 3362 // 0xe implies support for half, single and double precision operations. 3363 Builder.defineMacro("__ARM_FP", "0xe"); 3364 3365 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3366 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3367 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3368 3369 if (Opts.FastMath || Opts.FiniteMathOnly) 3370 Builder.defineMacro("__ARM_FP_FAST"); 3371 3372 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3373 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3374 3375 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3376 Opts.ShortWChar ? "2" : "4"); 3377 3378 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3379 Opts.ShortEnums ? "1" : "4"); 3380 3381 if (BigEndian) 3382 Builder.defineMacro("__ARM_BIG_ENDIAN"); 3383 } 3384 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3385 unsigned &NumRecords) const { 3386 Records = BuiltinInfo; 3387 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3388 } 3389 virtual bool hasFeature(StringRef Feature) const { 3390 return Feature == "aarch64"; 3391 } 3392 virtual void getGCCRegNames(const char * const *&Names, 3393 unsigned &NumNames) const; 3394 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3395 unsigned &NumAliases) const; 3396 3397 virtual bool isCLZForZeroUndef() const { return false; } 3398 3399 virtual bool validateAsmConstraint(const char *&Name, 3400 TargetInfo::ConstraintInfo &Info) const { 3401 switch (*Name) { 3402 default: return false; 3403 case 'w': // An FP/SIMD vector register 3404 Info.setAllowsRegister(); 3405 return true; 3406 case 'I': // Constant that can be used with an ADD instruction 3407 case 'J': // Constant that can be used with a SUB instruction 3408 case 'K': // Constant that can be used with a 32-bit logical instruction 3409 case 'L': // Constant that can be used with a 64-bit logical instruction 3410 case 'M': // Constant that can be used as a 32-bit MOV immediate 3411 case 'N': // Constant that can be used as a 64-bit MOV immediate 3412 case 'Y': // Floating point constant zero 3413 case 'Z': // Integer constant zero 3414 return true; 3415 case 'Q': // A memory reference with base register and no offset 3416 Info.setAllowsMemory(); 3417 return true; 3418 case 'S': // A symbolic address 3419 Info.setAllowsRegister(); 3420 return true; 3421 case 'U': 3422 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3423 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3424 // Usa: An absolute symbolic address 3425 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3426 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3427 } 3428 } 3429 3430 virtual const char *getClobbers() const { 3431 // There are no AArch64 clobbers shared by all asm statements. 3432 return ""; 3433 } 3434 3435 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3436 return TargetInfo::AArch64ABIBuiltinVaList; 3437 } 3438}; 3439 3440const char * const AArch64TargetInfo::GCCRegNames[] = { 3441 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3442 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3443 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3444 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3445 3446 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3447 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3448 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3449 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3450 3451 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3452 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3453 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3454 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3455 3456 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3457 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3458 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3459 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3460 3461 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3462 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3463 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3464 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3465 3466 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3467 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3468 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3469 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3470 3471 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3472 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3473 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3474 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3475}; 3476 3477void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3478 unsigned &NumNames) const { 3479 Names = GCCRegNames; 3480 NumNames = llvm::array_lengthof(GCCRegNames); 3481} 3482 3483const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3484 { { "x16" }, "ip0"}, 3485 { { "x17" }, "ip1"}, 3486 { { "x29" }, "fp" }, 3487 { { "x30" }, "lr" } 3488}; 3489 3490void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3491 unsigned &NumAliases) const { 3492 Aliases = GCCRegAliases; 3493 NumAliases = llvm::array_lengthof(GCCRegAliases); 3494 3495} 3496 3497const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3498#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3499#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3500 ALL_LANGUAGES }, 3501#include "clang/Basic/BuiltinsAArch64.def" 3502}; 3503 3504} // end anonymous namespace 3505 3506namespace { 3507class ARMTargetInfo : public TargetInfo { 3508 // Possible FPU choices. 3509 enum FPUMode { 3510 VFP2FPU = (1 << 0), 3511 VFP3FPU = (1 << 1), 3512 VFP4FPU = (1 << 2), 3513 NeonFPU = (1 << 3) 3514 }; 3515 3516 static bool FPUModeIsVFP(FPUMode Mode) { 3517 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU); 3518 } 3519 3520 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3521 static const char * const GCCRegNames[]; 3522 3523 std::string ABI, CPU; 3524 3525 unsigned FPU : 4; 3526 3527 unsigned IsAAPCS : 1; 3528 unsigned IsThumb : 1; 3529 3530 // Initialized via features. 3531 unsigned SoftFloat : 1; 3532 unsigned SoftFloatABI : 1; 3533 3534 static const Builtin::Info BuiltinInfo[]; 3535 3536 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3537 // On linux, binaries targeting old cpus call functions in libgcc to 3538 // perform atomic operations. The implementation in libgcc then calls into 3539 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3540 // is that if we assume the kernel is at least as recent as the hardware, 3541 // it is safe to use atomic instructions on armv6 and newer. 3542 if (T.getOS() != llvm::Triple::Linux && T.getOS() != llvm::Triple::FreeBSD) 3543 return false; 3544 StringRef ArchName = T.getArchName(); 3545 if (T.getArch() == llvm::Triple::arm) { 3546 if (!ArchName.startswith("armv")) 3547 return false; 3548 StringRef VersionStr = ArchName.substr(4); 3549 unsigned Version; 3550 if (VersionStr.getAsInteger(10, Version)) 3551 return false; 3552 return Version >= 6; 3553 } 3554 assert(T.getArch() == llvm::Triple::thumb); 3555 if (!ArchName.startswith("thumbv")) 3556 return false; 3557 StringRef VersionStr = ArchName.substr(6); 3558 unsigned Version; 3559 if (VersionStr.getAsInteger(10, Version)) 3560 return false; 3561 return Version >= 7; 3562 } 3563 3564public: 3565 ARMTargetInfo(const std::string &TripleStr) 3566 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true) 3567 { 3568 BigEndian = false; 3569 SizeType = UnsignedInt; 3570 PtrDiffType = SignedInt; 3571 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3572 WCharType = UnsignedInt; 3573 3574 // {} in inline assembly are neon specifiers, not assembly variant 3575 // specifiers. 3576 NoAsmVariants = true; 3577 3578 // FIXME: Should we just treat this as a feature? 3579 IsThumb = getTriple().getArchName().startswith("thumb"); 3580 if (IsThumb) { 3581 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3582 // so set preferred for small types to 32. 3583 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3584 "i64:64:64-f32:32:32-f64:64:64-" 3585 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3586 } else { 3587 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3588 "i64:64:64-f32:32:32-f64:64:64-" 3589 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3590 } 3591 3592 // ARM targets default to using the ARM C++ ABI. 3593 TheCXXABI.set(TargetCXXABI::GenericARM); 3594 3595 // ARM has atomics up to 8 bytes 3596 MaxAtomicPromoteWidth = 64; 3597 if (shouldUseInlineAtomic(getTriple())) 3598 MaxAtomicInlineWidth = 64; 3599 3600 // Do force alignment of members that follow zero length bitfields. If 3601 // the alignment of the zero-length bitfield is greater than the member 3602 // that follows it, `bar', `bar' will be aligned as the type of the 3603 // zero length bitfield. 3604 UseZeroLengthBitfieldAlignment = true; 3605 } 3606 virtual const char *getABI() const { return ABI.c_str(); } 3607 virtual bool setABI(const std::string &Name) { 3608 ABI = Name; 3609 3610 // The defaults (above) are for AAPCS, check if we need to change them. 3611 // 3612 // FIXME: We need support for -meabi... we could just mangle it into the 3613 // name. 3614 if (Name == "apcs-gnu") { 3615 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3616 // size_t is unsigned int on FreeBSD. 3617 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3618 SizeType = UnsignedLong; 3619 3620 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3621 WCharType = SignedInt; 3622 3623 // Do not respect the alignment of bit-field types when laying out 3624 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3625 UseBitFieldTypeAlignment = false; 3626 3627 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3628 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3629 /// gcc. 3630 ZeroLengthBitfieldBoundary = 32; 3631 3632 IsAAPCS = false; 3633 3634 if (IsThumb) { 3635 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3636 // so set preferred for small types to 32. 3637 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3638 "i64:32:64-f32:32:32-f64:32:64-" 3639 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3640 } else { 3641 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3642 "i64:32:64-f32:32:32-f64:32:64-" 3643 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3644 } 3645 3646 // FIXME: Override "preferred align" for double and long long. 3647 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3648 IsAAPCS = true; 3649 // FIXME: Enumerated types are variable width in straight AAPCS. 3650 } else if (Name == "aapcs-linux") { 3651 IsAAPCS = true; 3652 } else 3653 return false; 3654 3655 return true; 3656 } 3657 3658 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3659 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3660 Features["vfp2"] = true; 3661 else if (CPU == "cortex-a8" || CPU == "cortex-a15" || 3662 CPU == "cortex-a9" || CPU == "cortex-a9-mp") 3663 Features["neon"] = true; 3664 else if (CPU == "swift" || CPU == "cortex-a7") { 3665 Features["vfp4"] = true; 3666 Features["neon"] = true; 3667 } 3668 } 3669 3670 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3671 StringRef Name, 3672 bool Enabled) const { 3673 if (Name == "soft-float" || Name == "soft-float-abi" || 3674 Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" || 3675 Name == "d16" || Name == "neonfp") { 3676 Features[Name] = Enabled; 3677 } else 3678 return false; 3679 3680 return true; 3681 } 3682 3683 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3684 FPU = 0; 3685 SoftFloat = SoftFloatABI = false; 3686 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3687 if (Features[i] == "+soft-float") 3688 SoftFloat = true; 3689 else if (Features[i] == "+soft-float-abi") 3690 SoftFloatABI = true; 3691 else if (Features[i] == "+vfp2") 3692 FPU |= VFP2FPU; 3693 else if (Features[i] == "+vfp3") 3694 FPU |= VFP3FPU; 3695 else if (Features[i] == "+vfp4") 3696 FPU |= VFP4FPU; 3697 else if (Features[i] == "+neon") 3698 FPU |= NeonFPU; 3699 } 3700 3701 // Remove front-end specific options which the backend handles differently. 3702 std::vector<std::string>::iterator it; 3703 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3704 if (it != Features.end()) 3705 Features.erase(it); 3706 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3707 if (it != Features.end()) 3708 Features.erase(it); 3709 } 3710 3711 virtual bool hasFeature(StringRef Feature) const { 3712 return llvm::StringSwitch<bool>(Feature) 3713 .Case("arm", true) 3714 .Case("softfloat", SoftFloat) 3715 .Case("thumb", IsThumb) 3716 .Case("neon", FPU == NeonFPU && !SoftFloat && 3717 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 3718 .Default(false); 3719 } 3720 // FIXME: Should we actually have some table instead of these switches? 3721 static const char *getCPUDefineSuffix(StringRef Name) { 3722 return llvm::StringSwitch<const char*>(Name) 3723 .Cases("arm8", "arm810", "4") 3724 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3725 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3726 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3727 .Case("ep9312", "4T") 3728 .Cases("arm10tdmi", "arm1020t", "5T") 3729 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3730 .Case("arm926ej-s", "5TEJ") 3731 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3732 .Cases("xscale", "iwmmxt", "5TE") 3733 .Case("arm1136j-s", "6J") 3734 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3735 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3736 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3737 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 3738 .Cases("cortex-a9", "cortex-a15", "7A") 3739 .Case("cortex-r5", "7R") 3740 .Case("cortex-a9-mp", "7F") 3741 .Case("swift", "7S") 3742 .Cases("cortex-m3", "cortex-m4", "7M") 3743 .Case("cortex-m0", "6M") 3744 .Default(0); 3745 } 3746 static const char *getCPUProfile(StringRef Name) { 3747 return llvm::StringSwitch<const char*>(Name) 3748 .Cases("cortex-a8", "cortex-a9", "A") 3749 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3750 .Case("cortex-r5", "R") 3751 .Default(""); 3752 } 3753 virtual bool setCPU(const std::string &Name) { 3754 if (!getCPUDefineSuffix(Name)) 3755 return false; 3756 3757 CPU = Name; 3758 return true; 3759 } 3760 virtual void getTargetDefines(const LangOptions &Opts, 3761 MacroBuilder &Builder) const { 3762 // Target identification. 3763 Builder.defineMacro("__arm"); 3764 Builder.defineMacro("__arm__"); 3765 3766 // Target properties. 3767 Builder.defineMacro("__ARMEL__"); 3768 Builder.defineMacro("__LITTLE_ENDIAN__"); 3769 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3770 3771 StringRef CPUArch = getCPUDefineSuffix(CPU); 3772 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3773 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3774 StringRef CPUProfile = getCPUProfile(CPU); 3775 if (!CPUProfile.empty()) 3776 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3777 3778 // Subtarget options. 3779 3780 // FIXME: It's more complicated than this and we don't really support 3781 // interworking. 3782 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 3783 Builder.defineMacro("__THUMB_INTERWORK__"); 3784 3785 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3786 // M-class CPUs on Darwin follow AAPCS, but not EABI. 3787 if (!(getTriple().isOSDarwin() && CPUProfile == "M")) 3788 Builder.defineMacro("__ARM_EABI__"); 3789 Builder.defineMacro("__ARM_PCS", "1"); 3790 3791 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3792 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3793 } 3794 3795 if (SoftFloat) 3796 Builder.defineMacro("__SOFTFP__"); 3797 3798 if (CPU == "xscale") 3799 Builder.defineMacro("__XSCALE__"); 3800 3801 bool IsARMv7 = CPUArch.startswith("7"); 3802 if (IsThumb) { 3803 Builder.defineMacro("__THUMBEL__"); 3804 Builder.defineMacro("__thumb__"); 3805 if (CPUArch == "6T2" || IsARMv7) 3806 Builder.defineMacro("__thumb2__"); 3807 } 3808 3809 // Note, this is always on in gcc, even though it doesn't make sense. 3810 Builder.defineMacro("__APCS_32__"); 3811 3812 if (FPUModeIsVFP((FPUMode) FPU)) { 3813 Builder.defineMacro("__VFP_FP__"); 3814 if (FPU & VFP2FPU) 3815 Builder.defineMacro("__ARM_VFPV2__"); 3816 if (FPU & VFP3FPU) 3817 Builder.defineMacro("__ARM_VFPV3__"); 3818 if (FPU & VFP4FPU) 3819 Builder.defineMacro("__ARM_VFPV4__"); 3820 } 3821 3822 // This only gets set when Neon instructions are actually available, unlike 3823 // the VFP define, hence the soft float and arch check. This is subtly 3824 // different from gcc, we follow the intent which was that it should be set 3825 // when Neon instructions are actually available. 3826 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7) 3827 Builder.defineMacro("__ARM_NEON__"); 3828 } 3829 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3830 unsigned &NumRecords) const { 3831 Records = BuiltinInfo; 3832 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3833 } 3834 virtual bool isCLZForZeroUndef() const { return false; } 3835 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3836 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3837 } 3838 virtual void getGCCRegNames(const char * const *&Names, 3839 unsigned &NumNames) const; 3840 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3841 unsigned &NumAliases) const; 3842 virtual bool validateAsmConstraint(const char *&Name, 3843 TargetInfo::ConstraintInfo &Info) const { 3844 switch (*Name) { 3845 default: break; 3846 case 'l': // r0-r7 3847 case 'h': // r8-r15 3848 case 'w': // VFP Floating point register single precision 3849 case 'P': // VFP Floating point register double precision 3850 Info.setAllowsRegister(); 3851 return true; 3852 case 'Q': // A memory address that is a single base register. 3853 Info.setAllowsMemory(); 3854 return true; 3855 case 'U': // a memory reference... 3856 switch (Name[1]) { 3857 case 'q': // ...ARMV4 ldrsb 3858 case 'v': // ...VFP load/store (reg+constant offset) 3859 case 'y': // ...iWMMXt load/store 3860 case 't': // address valid for load/store opaque types wider 3861 // than 128-bits 3862 case 'n': // valid address for Neon doubleword vector load/store 3863 case 'm': // valid address for Neon element and structure load/store 3864 case 's': // valid address for non-offset loads/stores of quad-word 3865 // values in four ARM registers 3866 Info.setAllowsMemory(); 3867 Name++; 3868 return true; 3869 } 3870 } 3871 return false; 3872 } 3873 virtual std::string convertConstraint(const char *&Constraint) const { 3874 std::string R; 3875 switch (*Constraint) { 3876 case 'U': // Two-character constraint; add "^" hint for later parsing. 3877 R = std::string("^") + std::string(Constraint, 2); 3878 Constraint++; 3879 break; 3880 case 'p': // 'p' should be translated to 'r' by default. 3881 R = std::string("r"); 3882 break; 3883 default: 3884 return std::string(1, *Constraint); 3885 } 3886 return R; 3887 } 3888 virtual bool validateConstraintModifier(StringRef Constraint, 3889 const char Modifier, 3890 unsigned Size) const { 3891 bool isOutput = (Constraint[0] == '='); 3892 bool isInOut = (Constraint[0] == '+'); 3893 3894 // Strip off constraint modifiers. 3895 while (Constraint[0] == '=' || 3896 Constraint[0] == '+' || 3897 Constraint[0] == '&') 3898 Constraint = Constraint.substr(1); 3899 3900 switch (Constraint[0]) { 3901 default: break; 3902 case 'r': { 3903 switch (Modifier) { 3904 default: 3905 return isInOut || (isOutput && Size >= 32) || 3906 (!isOutput && !isInOut && Size <= 32); 3907 case 'q': 3908 // A register of size 32 cannot fit a vector type. 3909 return false; 3910 } 3911 } 3912 } 3913 3914 return true; 3915 } 3916 virtual const char *getClobbers() const { 3917 // FIXME: Is this really right? 3918 return ""; 3919 } 3920 3921 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3922 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 3923 } 3924 3925 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 3926 if (RegNo == 0) return 0; 3927 if (RegNo == 1) return 1; 3928 return -1; 3929 } 3930}; 3931 3932const char * const ARMTargetInfo::GCCRegNames[] = { 3933 // Integer registers 3934 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3935 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 3936 3937 // Float registers 3938 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3939 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3940 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3941 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3942 3943 // Double registers 3944 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3945 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3946 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3947 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3948 3949 // Quad registers 3950 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3951 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 3952}; 3953 3954void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 3955 unsigned &NumNames) const { 3956 Names = GCCRegNames; 3957 NumNames = llvm::array_lengthof(GCCRegNames); 3958} 3959 3960const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 3961 { { "a1" }, "r0" }, 3962 { { "a2" }, "r1" }, 3963 { { "a3" }, "r2" }, 3964 { { "a4" }, "r3" }, 3965 { { "v1" }, "r4" }, 3966 { { "v2" }, "r5" }, 3967 { { "v3" }, "r6" }, 3968 { { "v4" }, "r7" }, 3969 { { "v5" }, "r8" }, 3970 { { "v6", "rfp" }, "r9" }, 3971 { { "sl" }, "r10" }, 3972 { { "fp" }, "r11" }, 3973 { { "ip" }, "r12" }, 3974 { { "r13" }, "sp" }, 3975 { { "r14" }, "lr" }, 3976 { { "r15" }, "pc" }, 3977 // The S, D and Q registers overlap, but aren't really aliases; we 3978 // don't want to substitute one of these for a different-sized one. 3979}; 3980 3981void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3982 unsigned &NumAliases) const { 3983 Aliases = GCCRegAliases; 3984 NumAliases = llvm::array_lengthof(GCCRegAliases); 3985} 3986 3987const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 3988#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3989#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3990 ALL_LANGUAGES }, 3991#include "clang/Basic/BuiltinsARM.def" 3992}; 3993} // end anonymous namespace. 3994 3995namespace { 3996class DarwinARMTargetInfo : 3997 public DarwinTargetInfo<ARMTargetInfo> { 3998protected: 3999 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4000 MacroBuilder &Builder) const { 4001 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4002 } 4003 4004public: 4005 DarwinARMTargetInfo(const std::string& triple) 4006 : DarwinTargetInfo<ARMTargetInfo>(triple) { 4007 HasAlignMac68kSupport = true; 4008 // iOS always has 64-bit atomic instructions. 4009 // FIXME: This should be based off of the target features in ARMTargetInfo. 4010 MaxAtomicInlineWidth = 64; 4011 4012 // Darwin on iOS uses a variant of the ARM C++ ABI. 4013 TheCXXABI.set(TargetCXXABI::iOS); 4014 } 4015}; 4016} // end anonymous namespace. 4017 4018 4019namespace { 4020// Hexagon abstract base class 4021class HexagonTargetInfo : public TargetInfo { 4022 static const Builtin::Info BuiltinInfo[]; 4023 static const char * const GCCRegNames[]; 4024 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4025 std::string CPU; 4026public: 4027 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) { 4028 BigEndian = false; 4029 DescriptionString = ("e-p:32:32:32-" 4030 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 4031 "f64:64:64-f32:32:32-a0:0-n32"); 4032 4033 // {} in inline assembly are packet specifiers, not assembly variant 4034 // specifiers. 4035 NoAsmVariants = true; 4036 } 4037 4038 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4039 unsigned &NumRecords) const { 4040 Records = BuiltinInfo; 4041 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4042 } 4043 4044 virtual bool validateAsmConstraint(const char *&Name, 4045 TargetInfo::ConstraintInfo &Info) const { 4046 return true; 4047 } 4048 4049 virtual void getTargetDefines(const LangOptions &Opts, 4050 MacroBuilder &Builder) const; 4051 4052 virtual bool hasFeature(StringRef Feature) const { 4053 return Feature == "hexagon"; 4054 } 4055 4056 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4057 return TargetInfo::CharPtrBuiltinVaList; 4058 } 4059 virtual void getGCCRegNames(const char * const *&Names, 4060 unsigned &NumNames) const; 4061 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4062 unsigned &NumAliases) const; 4063 virtual const char *getClobbers() const { 4064 return ""; 4065 } 4066 4067 static const char *getHexagonCPUSuffix(StringRef Name) { 4068 return llvm::StringSwitch<const char*>(Name) 4069 .Case("hexagonv4", "4") 4070 .Case("hexagonv5", "5") 4071 .Default(0); 4072 } 4073 4074 virtual bool setCPU(const std::string &Name) { 4075 if (!getHexagonCPUSuffix(Name)) 4076 return false; 4077 4078 CPU = Name; 4079 return true; 4080 } 4081}; 4082 4083void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4084 MacroBuilder &Builder) const { 4085 Builder.defineMacro("qdsp6"); 4086 Builder.defineMacro("__qdsp6", "1"); 4087 Builder.defineMacro("__qdsp6__", "1"); 4088 4089 Builder.defineMacro("hexagon"); 4090 Builder.defineMacro("__hexagon", "1"); 4091 Builder.defineMacro("__hexagon__", "1"); 4092 4093 if(CPU == "hexagonv1") { 4094 Builder.defineMacro("__HEXAGON_V1__"); 4095 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4096 if(Opts.HexagonQdsp6Compat) { 4097 Builder.defineMacro("__QDSP6_V1__"); 4098 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4099 } 4100 } 4101 else if(CPU == "hexagonv2") { 4102 Builder.defineMacro("__HEXAGON_V2__"); 4103 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4104 if(Opts.HexagonQdsp6Compat) { 4105 Builder.defineMacro("__QDSP6_V2__"); 4106 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4107 } 4108 } 4109 else if(CPU == "hexagonv3") { 4110 Builder.defineMacro("__HEXAGON_V3__"); 4111 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4112 if(Opts.HexagonQdsp6Compat) { 4113 Builder.defineMacro("__QDSP6_V3__"); 4114 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4115 } 4116 } 4117 else if(CPU == "hexagonv4") { 4118 Builder.defineMacro("__HEXAGON_V4__"); 4119 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4120 if(Opts.HexagonQdsp6Compat) { 4121 Builder.defineMacro("__QDSP6_V4__"); 4122 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4123 } 4124 } 4125 else if(CPU == "hexagonv5") { 4126 Builder.defineMacro("__HEXAGON_V5__"); 4127 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4128 if(Opts.HexagonQdsp6Compat) { 4129 Builder.defineMacro("__QDSP6_V5__"); 4130 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4131 } 4132 } 4133} 4134 4135const char * const HexagonTargetInfo::GCCRegNames[] = { 4136 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4137 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4138 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4139 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4140 "p0", "p1", "p2", "p3", 4141 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4142}; 4143 4144void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4145 unsigned &NumNames) const { 4146 Names = GCCRegNames; 4147 NumNames = llvm::array_lengthof(GCCRegNames); 4148} 4149 4150 4151const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4152 { { "sp" }, "r29" }, 4153 { { "fp" }, "r30" }, 4154 { { "lr" }, "r31" }, 4155 }; 4156 4157void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4158 unsigned &NumAliases) const { 4159 Aliases = GCCRegAliases; 4160 NumAliases = llvm::array_lengthof(GCCRegAliases); 4161} 4162 4163 4164const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4165#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4166#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4167 ALL_LANGUAGES }, 4168#include "clang/Basic/BuiltinsHexagon.def" 4169}; 4170} 4171 4172 4173namespace { 4174// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4175class SparcTargetInfo : public TargetInfo { 4176 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4177 static const char * const GCCRegNames[]; 4178 bool SoftFloat; 4179public: 4180 SparcTargetInfo(const std::string &triple) : TargetInfo(triple) {} 4181 4182 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 4183 StringRef Name, 4184 bool Enabled) const { 4185 if (Name == "soft-float") 4186 Features[Name] = Enabled; 4187 else 4188 return false; 4189 4190 return true; 4191 } 4192 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 4193 SoftFloat = false; 4194 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4195 if (Features[i] == "+soft-float") 4196 SoftFloat = true; 4197 } 4198 virtual void getTargetDefines(const LangOptions &Opts, 4199 MacroBuilder &Builder) const { 4200 DefineStd(Builder, "sparc", Opts); 4201 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4202 4203 if (SoftFloat) 4204 Builder.defineMacro("SOFT_FLOAT", "1"); 4205 } 4206 4207 virtual bool hasFeature(StringRef Feature) const { 4208 return llvm::StringSwitch<bool>(Feature) 4209 .Case("softfloat", SoftFloat) 4210 .Case("sparc", true) 4211 .Default(false); 4212 } 4213 4214 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4215 unsigned &NumRecords) const { 4216 // FIXME: Implement! 4217 } 4218 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4219 return TargetInfo::VoidPtrBuiltinVaList; 4220 } 4221 virtual void getGCCRegNames(const char * const *&Names, 4222 unsigned &NumNames) const; 4223 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4224 unsigned &NumAliases) const; 4225 virtual bool validateAsmConstraint(const char *&Name, 4226 TargetInfo::ConstraintInfo &info) const { 4227 // FIXME: Implement! 4228 return false; 4229 } 4230 virtual const char *getClobbers() const { 4231 // FIXME: Implement! 4232 return ""; 4233 } 4234}; 4235 4236const char * const SparcTargetInfo::GCCRegNames[] = { 4237 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4238 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4239 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4240 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4241}; 4242 4243void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4244 unsigned &NumNames) const { 4245 Names = GCCRegNames; 4246 NumNames = llvm::array_lengthof(GCCRegNames); 4247} 4248 4249const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4250 { { "g0" }, "r0" }, 4251 { { "g1" }, "r1" }, 4252 { { "g2" }, "r2" }, 4253 { { "g3" }, "r3" }, 4254 { { "g4" }, "r4" }, 4255 { { "g5" }, "r5" }, 4256 { { "g6" }, "r6" }, 4257 { { "g7" }, "r7" }, 4258 { { "o0" }, "r8" }, 4259 { { "o1" }, "r9" }, 4260 { { "o2" }, "r10" }, 4261 { { "o3" }, "r11" }, 4262 { { "o4" }, "r12" }, 4263 { { "o5" }, "r13" }, 4264 { { "o6", "sp" }, "r14" }, 4265 { { "o7" }, "r15" }, 4266 { { "l0" }, "r16" }, 4267 { { "l1" }, "r17" }, 4268 { { "l2" }, "r18" }, 4269 { { "l3" }, "r19" }, 4270 { { "l4" }, "r20" }, 4271 { { "l5" }, "r21" }, 4272 { { "l6" }, "r22" }, 4273 { { "l7" }, "r23" }, 4274 { { "i0" }, "r24" }, 4275 { { "i1" }, "r25" }, 4276 { { "i2" }, "r26" }, 4277 { { "i3" }, "r27" }, 4278 { { "i4" }, "r28" }, 4279 { { "i5" }, "r29" }, 4280 { { "i6", "fp" }, "r30" }, 4281 { { "i7" }, "r31" }, 4282}; 4283 4284void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4285 unsigned &NumAliases) const { 4286 Aliases = GCCRegAliases; 4287 NumAliases = llvm::array_lengthof(GCCRegAliases); 4288} 4289 4290// SPARC v8 is the 32-bit mode selected by Triple::sparc. 4291class SparcV8TargetInfo : public SparcTargetInfo { 4292public: 4293 SparcV8TargetInfo(const std::string& triple) : SparcTargetInfo(triple) { 4294 // FIXME: Support Sparc quad-precision long double? 4295 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4296 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4297 } 4298 4299 virtual void getTargetDefines(const LangOptions &Opts, 4300 MacroBuilder &Builder) const { 4301 SparcTargetInfo::getTargetDefines(Opts, Builder); 4302 Builder.defineMacro("__sparcv8"); 4303 } 4304}; 4305 4306// SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4307class SparcV9TargetInfo : public SparcTargetInfo { 4308public: 4309 SparcV9TargetInfo(const std::string& triple) : SparcTargetInfo(triple) { 4310 // FIXME: Support Sparc quad-precision long double? 4311 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4312 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"; 4313 } 4314 4315 virtual void getTargetDefines(const LangOptions &Opts, 4316 MacroBuilder &Builder) const { 4317 SparcTargetInfo::getTargetDefines(Opts, Builder); 4318 Builder.defineMacro("__sparcv9"); 4319 Builder.defineMacro("__arch64__"); 4320 // Solaris and its derivative AuroraUX don't need these variants, but the 4321 // BSDs do. 4322 if (getTriple().getOS() != llvm::Triple::Solaris && 4323 getTriple().getOS() != llvm::Triple::AuroraUX) { 4324 Builder.defineMacro("__sparc64__"); 4325 Builder.defineMacro("__sparc_v9__"); 4326 Builder.defineMacro("__sparcv9__"); 4327 } 4328 } 4329}; 4330 4331} // end anonymous namespace. 4332 4333namespace { 4334class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4335public: 4336 AuroraUXSparcV8TargetInfo(const std::string& triple) : 4337 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) { 4338 SizeType = UnsignedInt; 4339 PtrDiffType = SignedInt; 4340 } 4341}; 4342class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4343public: 4344 SolarisSparcV8TargetInfo(const std::string& triple) : 4345 SolarisTargetInfo<SparcV8TargetInfo>(triple) { 4346 SizeType = UnsignedInt; 4347 PtrDiffType = SignedInt; 4348 } 4349}; 4350} // end anonymous namespace. 4351 4352namespace { 4353 class SystemZTargetInfo : public TargetInfo { 4354 static const char *const GCCRegNames[]; 4355 4356 public: 4357 SystemZTargetInfo(const std::string& triple) : TargetInfo(triple) { 4358 TLSSupported = true; 4359 IntWidth = IntAlign = 32; 4360 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4361 PointerWidth = PointerAlign = 64; 4362 LongDoubleWidth = 128; 4363 LongDoubleAlign = 64; 4364 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4365 MinGlobalAlign = 16; 4366 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64" 4367 "-f32:32-f64:64-f128:64-a0:8:16-n32:64"; 4368 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4369 } 4370 virtual void getTargetDefines(const LangOptions &Opts, 4371 MacroBuilder &Builder) const { 4372 Builder.defineMacro("__s390__"); 4373 Builder.defineMacro("__s390x__"); 4374 Builder.defineMacro("__zarch__"); 4375 Builder.defineMacro("__LONG_DOUBLE_128__"); 4376 } 4377 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4378 unsigned &NumRecords) const { 4379 // FIXME: Implement. 4380 Records = 0; 4381 NumRecords = 0; 4382 } 4383 4384 virtual void getGCCRegNames(const char *const *&Names, 4385 unsigned &NumNames) const; 4386 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4387 unsigned &NumAliases) const { 4388 // No aliases. 4389 Aliases = 0; 4390 NumAliases = 0; 4391 } 4392 virtual bool validateAsmConstraint(const char *&Name, 4393 TargetInfo::ConstraintInfo &info) const; 4394 virtual const char *getClobbers() const { 4395 // FIXME: Is this really right? 4396 return ""; 4397 } 4398 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4399 return TargetInfo::SystemZBuiltinVaList; 4400 } 4401 }; 4402 4403 const char *const SystemZTargetInfo::GCCRegNames[] = { 4404 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4405 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4406 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4407 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4408 }; 4409 4410 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4411 unsigned &NumNames) const { 4412 Names = GCCRegNames; 4413 NumNames = llvm::array_lengthof(GCCRegNames); 4414 } 4415 4416 bool SystemZTargetInfo:: 4417 validateAsmConstraint(const char *&Name, 4418 TargetInfo::ConstraintInfo &Info) const { 4419 switch (*Name) { 4420 default: 4421 return false; 4422 4423 case 'a': // Address register 4424 case 'd': // Data register (equivalent to 'r') 4425 case 'f': // Floating-point register 4426 Info.setAllowsRegister(); 4427 return true; 4428 4429 case 'I': // Unsigned 8-bit constant 4430 case 'J': // Unsigned 12-bit constant 4431 case 'K': // Signed 16-bit constant 4432 case 'L': // Signed 20-bit displacement (on all targets we support) 4433 case 'M': // 0x7fffffff 4434 return true; 4435 4436 case 'Q': // Memory with base and unsigned 12-bit displacement 4437 case 'R': // Likewise, plus an index 4438 case 'S': // Memory with base and signed 20-bit displacement 4439 case 'T': // Likewise, plus an index 4440 Info.setAllowsMemory(); 4441 return true; 4442 } 4443 } 4444} 4445 4446namespace { 4447 class MSP430TargetInfo : public TargetInfo { 4448 static const char * const GCCRegNames[]; 4449 public: 4450 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) { 4451 BigEndian = false; 4452 TLSSupported = false; 4453 IntWidth = 16; IntAlign = 16; 4454 LongWidth = 32; LongLongWidth = 64; 4455 LongAlign = LongLongAlign = 16; 4456 PointerWidth = 16; PointerAlign = 16; 4457 SuitableAlign = 16; 4458 SizeType = UnsignedInt; 4459 IntMaxType = SignedLong; 4460 UIntMaxType = UnsignedLong; 4461 IntPtrType = SignedShort; 4462 PtrDiffType = SignedInt; 4463 SigAtomicType = SignedLong; 4464 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 4465 } 4466 virtual void getTargetDefines(const LangOptions &Opts, 4467 MacroBuilder &Builder) const { 4468 Builder.defineMacro("MSP430"); 4469 Builder.defineMacro("__MSP430__"); 4470 // FIXME: defines for different 'flavours' of MCU 4471 } 4472 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4473 unsigned &NumRecords) const { 4474 // FIXME: Implement. 4475 Records = 0; 4476 NumRecords = 0; 4477 } 4478 virtual bool hasFeature(StringRef Feature) const { 4479 return Feature == "msp430"; 4480 } 4481 virtual void getGCCRegNames(const char * const *&Names, 4482 unsigned &NumNames) const; 4483 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4484 unsigned &NumAliases) const { 4485 // No aliases. 4486 Aliases = 0; 4487 NumAliases = 0; 4488 } 4489 virtual bool validateAsmConstraint(const char *&Name, 4490 TargetInfo::ConstraintInfo &info) const { 4491 // No target constraints for now. 4492 return false; 4493 } 4494 virtual const char *getClobbers() const { 4495 // FIXME: Is this really right? 4496 return ""; 4497 } 4498 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4499 // FIXME: implement 4500 return TargetInfo::CharPtrBuiltinVaList; 4501 } 4502 }; 4503 4504 const char * const MSP430TargetInfo::GCCRegNames[] = { 4505 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4506 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4507 }; 4508 4509 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4510 unsigned &NumNames) const { 4511 Names = GCCRegNames; 4512 NumNames = llvm::array_lengthof(GCCRegNames); 4513 } 4514} 4515 4516namespace { 4517 4518 // LLVM and Clang cannot be used directly to output native binaries for 4519 // target, but is used to compile C code to llvm bitcode with correct 4520 // type and alignment information. 4521 // 4522 // TCE uses the llvm bitcode as input and uses it for generating customized 4523 // target processor and program binary. TCE co-design environment is 4524 // publicly available in http://tce.cs.tut.fi 4525 4526 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4527 3, // opencl_global 4528 4, // opencl_local 4529 5, // opencl_constant 4530 0, // cuda_device 4531 0, // cuda_constant 4532 0 // cuda_shared 4533 }; 4534 4535 class TCETargetInfo : public TargetInfo{ 4536 public: 4537 TCETargetInfo(const std::string& triple) : TargetInfo(triple) { 4538 TLSSupported = false; 4539 IntWidth = 32; 4540 LongWidth = LongLongWidth = 32; 4541 PointerWidth = 32; 4542 IntAlign = 32; 4543 LongAlign = LongLongAlign = 32; 4544 PointerAlign = 32; 4545 SuitableAlign = 32; 4546 SizeType = UnsignedInt; 4547 IntMaxType = SignedLong; 4548 UIntMaxType = UnsignedLong; 4549 IntPtrType = SignedInt; 4550 PtrDiffType = SignedInt; 4551 FloatWidth = 32; 4552 FloatAlign = 32; 4553 DoubleWidth = 32; 4554 DoubleAlign = 32; 4555 LongDoubleWidth = 32; 4556 LongDoubleAlign = 32; 4557 FloatFormat = &llvm::APFloat::IEEEsingle; 4558 DoubleFormat = &llvm::APFloat::IEEEsingle; 4559 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4560 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 4561 "i16:16:32-i32:32:32-i64:32:32-" 4562 "f32:32:32-f64:32:32-v64:32:32-" 4563 "v128:32:32-a0:0:32-n32"; 4564 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4565 } 4566 4567 virtual void getTargetDefines(const LangOptions &Opts, 4568 MacroBuilder &Builder) const { 4569 DefineStd(Builder, "tce", Opts); 4570 Builder.defineMacro("__TCE__"); 4571 Builder.defineMacro("__TCE_V1__"); 4572 } 4573 virtual bool hasFeature(StringRef Feature) const { 4574 return Feature == "tce"; 4575 } 4576 4577 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4578 unsigned &NumRecords) const {} 4579 virtual const char *getClobbers() const { 4580 return ""; 4581 } 4582 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4583 return TargetInfo::VoidPtrBuiltinVaList; 4584 } 4585 virtual void getGCCRegNames(const char * const *&Names, 4586 unsigned &NumNames) const {} 4587 virtual bool validateAsmConstraint(const char *&Name, 4588 TargetInfo::ConstraintInfo &info) const { 4589 return true; 4590 } 4591 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4592 unsigned &NumAliases) const {} 4593 }; 4594} 4595 4596namespace { 4597class MipsTargetInfoBase : public TargetInfo { 4598 static const Builtin::Info BuiltinInfo[]; 4599 std::string CPU; 4600 bool IsMips16; 4601 bool IsMicromips; 4602 bool IsSingleFloat; 4603 enum MipsFloatABI { 4604 HardFloat, SoftFloat 4605 } FloatABI; 4606 enum DspRevEnum { 4607 NoDSP, DSP1, DSP2 4608 } DspRev; 4609 4610protected: 4611 std::string ABI; 4612 4613public: 4614 MipsTargetInfoBase(const std::string& triple, 4615 const std::string& ABIStr, 4616 const std::string& CPUStr) 4617 : TargetInfo(triple), 4618 CPU(CPUStr), 4619 IsMips16(false), 4620 IsMicromips(false), 4621 IsSingleFloat(false), 4622 FloatABI(HardFloat), 4623 DspRev(NoDSP), 4624 ABI(ABIStr) 4625 {} 4626 4627 virtual const char *getABI() const { return ABI.c_str(); } 4628 virtual bool setABI(const std::string &Name) = 0; 4629 virtual bool setCPU(const std::string &Name) { 4630 CPU = Name; 4631 return true; 4632 } 4633 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4634 Features[ABI] = true; 4635 Features[CPU] = true; 4636 } 4637 4638 virtual void getTargetDefines(const LangOptions &Opts, 4639 MacroBuilder &Builder) const { 4640 DefineStd(Builder, "mips", Opts); 4641 Builder.defineMacro("_mips"); 4642 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4643 4644 switch (FloatABI) { 4645 case HardFloat: 4646 Builder.defineMacro("__mips_hard_float", Twine(1)); 4647 break; 4648 case SoftFloat: 4649 Builder.defineMacro("__mips_soft_float", Twine(1)); 4650 break; 4651 } 4652 4653 if (IsSingleFloat) 4654 Builder.defineMacro("__mips_single_float", Twine(1)); 4655 4656 if (IsMips16) 4657 Builder.defineMacro("__mips16", Twine(1)); 4658 4659 if (IsMicromips) 4660 Builder.defineMacro("__mips_micromips", Twine(1)); 4661 4662 switch (DspRev) { 4663 default: 4664 break; 4665 case DSP1: 4666 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4667 Builder.defineMacro("__mips_dsp", Twine(1)); 4668 break; 4669 case DSP2: 4670 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4671 Builder.defineMacro("__mips_dspr2", Twine(1)); 4672 Builder.defineMacro("__mips_dsp", Twine(1)); 4673 break; 4674 } 4675 4676 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4677 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4678 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4679 4680 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4681 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4682 } 4683 4684 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4685 unsigned &NumRecords) const { 4686 Records = BuiltinInfo; 4687 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4688 } 4689 virtual bool hasFeature(StringRef Feature) const { 4690 return Feature == "mips"; 4691 } 4692 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4693 return TargetInfo::VoidPtrBuiltinVaList; 4694 } 4695 virtual void getGCCRegNames(const char * const *&Names, 4696 unsigned &NumNames) const { 4697 static const char * const GCCRegNames[] = { 4698 // CPU register names 4699 // Must match second column of GCCRegAliases 4700 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4701 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4702 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4703 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4704 // Floating point register names 4705 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4706 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4707 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4708 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4709 // Hi/lo and condition register names 4710 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4711 "$fcc5","$fcc6","$fcc7" 4712 }; 4713 Names = GCCRegNames; 4714 NumNames = llvm::array_lengthof(GCCRegNames); 4715 } 4716 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4717 unsigned &NumAliases) const = 0; 4718 virtual bool validateAsmConstraint(const char *&Name, 4719 TargetInfo::ConstraintInfo &Info) const { 4720 switch (*Name) { 4721 default: 4722 return false; 4723 4724 case 'r': // CPU registers. 4725 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4726 case 'y': // Equivalent to "r", backwards compatibility only. 4727 case 'f': // floating-point registers. 4728 case 'c': // $25 for indirect jumps 4729 case 'l': // lo register 4730 case 'x': // hilo register pair 4731 Info.setAllowsRegister(); 4732 return true; 4733 case 'R': // An address that can be used in a non-macro load or store 4734 Info.setAllowsMemory(); 4735 return true; 4736 } 4737 } 4738 4739 virtual const char *getClobbers() const { 4740 // FIXME: Implement! 4741 return ""; 4742 } 4743 4744 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 4745 StringRef Name, 4746 bool Enabled) const { 4747 if (Name == "soft-float" || Name == "single-float" || 4748 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" || 4749 Name == "mips32" || Name == "mips32r2" || 4750 Name == "mips64" || Name == "mips64r2" || 4751 Name == "mips16" || Name == "micromips" || 4752 Name == "dsp" || Name == "dspr2") { 4753 Features[Name] = Enabled; 4754 return true; 4755 } else if (Name == "32") { 4756 Features["o32"] = Enabled; 4757 return true; 4758 } else if (Name == "64") { 4759 Features["n64"] = Enabled; 4760 return true; 4761 } 4762 return false; 4763 } 4764 4765 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 4766 IsMips16 = false; 4767 IsMicromips = false; 4768 IsSingleFloat = false; 4769 FloatABI = HardFloat; 4770 DspRev = NoDSP; 4771 4772 for (std::vector<std::string>::iterator it = Features.begin(), 4773 ie = Features.end(); it != ie; ++it) { 4774 if (*it == "+single-float") 4775 IsSingleFloat = true; 4776 else if (*it == "+soft-float") 4777 FloatABI = SoftFloat; 4778 else if (*it == "+mips16") 4779 IsMips16 = true; 4780 else if (*it == "+micromips") 4781 IsMicromips = true; 4782 else if (*it == "+dsp") 4783 DspRev = std::max(DspRev, DSP1); 4784 else if (*it == "+dspr2") 4785 DspRev = std::max(DspRev, DSP2); 4786 } 4787 4788 // Remove front-end specific option. 4789 std::vector<std::string>::iterator it = 4790 std::find(Features.begin(), Features.end(), "+soft-float"); 4791 if (it != Features.end()) 4792 Features.erase(it); 4793 } 4794 4795 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4796 if (RegNo == 0) return 4; 4797 if (RegNo == 1) return 5; 4798 return -1; 4799 } 4800}; 4801 4802const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 4803#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4804#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4805 ALL_LANGUAGES }, 4806#include "clang/Basic/BuiltinsMips.def" 4807}; 4808 4809class Mips32TargetInfoBase : public MipsTargetInfoBase { 4810public: 4811 Mips32TargetInfoBase(const std::string& triple) : 4812 MipsTargetInfoBase(triple, "o32", "mips32") { 4813 SizeType = UnsignedInt; 4814 PtrDiffType = SignedInt; 4815 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 4816 } 4817 virtual bool setABI(const std::string &Name) { 4818 if ((Name == "o32") || (Name == "eabi")) { 4819 ABI = Name; 4820 return true; 4821 } else if (Name == "32") { 4822 ABI = "o32"; 4823 return true; 4824 } else 4825 return false; 4826 } 4827 virtual void getTargetDefines(const LangOptions &Opts, 4828 MacroBuilder &Builder) const { 4829 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4830 4831 if (ABI == "o32") { 4832 Builder.defineMacro("__mips_o32"); 4833 Builder.defineMacro("_ABIO32", "1"); 4834 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 4835 } 4836 else if (ABI == "eabi") 4837 Builder.defineMacro("__mips_eabi"); 4838 else 4839 llvm_unreachable("Invalid ABI for Mips32."); 4840 } 4841 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4842 unsigned &NumAliases) const { 4843 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4844 { { "at" }, "$1" }, 4845 { { "v0" }, "$2" }, 4846 { { "v1" }, "$3" }, 4847 { { "a0" }, "$4" }, 4848 { { "a1" }, "$5" }, 4849 { { "a2" }, "$6" }, 4850 { { "a3" }, "$7" }, 4851 { { "t0" }, "$8" }, 4852 { { "t1" }, "$9" }, 4853 { { "t2" }, "$10" }, 4854 { { "t3" }, "$11" }, 4855 { { "t4" }, "$12" }, 4856 { { "t5" }, "$13" }, 4857 { { "t6" }, "$14" }, 4858 { { "t7" }, "$15" }, 4859 { { "s0" }, "$16" }, 4860 { { "s1" }, "$17" }, 4861 { { "s2" }, "$18" }, 4862 { { "s3" }, "$19" }, 4863 { { "s4" }, "$20" }, 4864 { { "s5" }, "$21" }, 4865 { { "s6" }, "$22" }, 4866 { { "s7" }, "$23" }, 4867 { { "t8" }, "$24" }, 4868 { { "t9" }, "$25" }, 4869 { { "k0" }, "$26" }, 4870 { { "k1" }, "$27" }, 4871 { { "gp" }, "$28" }, 4872 { { "sp","$sp" }, "$29" }, 4873 { { "fp","$fp" }, "$30" }, 4874 { { "ra" }, "$31" } 4875 }; 4876 Aliases = GCCRegAliases; 4877 NumAliases = llvm::array_lengthof(GCCRegAliases); 4878 } 4879}; 4880 4881class Mips32EBTargetInfo : public Mips32TargetInfoBase { 4882public: 4883 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 4884 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4885 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4886 } 4887 virtual void getTargetDefines(const LangOptions &Opts, 4888 MacroBuilder &Builder) const { 4889 DefineStd(Builder, "MIPSEB", Opts); 4890 Builder.defineMacro("_MIPSEB"); 4891 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4892 } 4893}; 4894 4895class Mips32ELTargetInfo : public Mips32TargetInfoBase { 4896public: 4897 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 4898 BigEndian = false; 4899 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4900 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4901 } 4902 virtual void getTargetDefines(const LangOptions &Opts, 4903 MacroBuilder &Builder) const { 4904 DefineStd(Builder, "MIPSEL", Opts); 4905 Builder.defineMacro("_MIPSEL"); 4906 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4907 } 4908}; 4909 4910class Mips64TargetInfoBase : public MipsTargetInfoBase { 4911 virtual void SetDescriptionString(const std::string &Name) = 0; 4912public: 4913 Mips64TargetInfoBase(const std::string& triple) : 4914 MipsTargetInfoBase(triple, "n64", "mips64") { 4915 LongWidth = LongAlign = 64; 4916 PointerWidth = PointerAlign = 64; 4917 LongDoubleWidth = LongDoubleAlign = 128; 4918 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4919 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 4920 LongDoubleWidth = LongDoubleAlign = 64; 4921 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4922 } 4923 SuitableAlign = 128; 4924 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4925 } 4926 virtual bool setABI(const std::string &Name) { 4927 SetDescriptionString(Name); 4928 if (Name == "n32") { 4929 LongWidth = LongAlign = 32; 4930 PointerWidth = PointerAlign = 32; 4931 ABI = Name; 4932 return true; 4933 } else if (Name == "n64") { 4934 ABI = Name; 4935 return true; 4936 } else if (Name == "64") { 4937 ABI = "n64"; 4938 return true; 4939 } else 4940 return false; 4941 } 4942 virtual void getTargetDefines(const LangOptions &Opts, 4943 MacroBuilder &Builder) const { 4944 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4945 4946 Builder.defineMacro("__mips64"); 4947 Builder.defineMacro("__mips64__"); 4948 4949 if (ABI == "n32") { 4950 Builder.defineMacro("__mips_n32"); 4951 Builder.defineMacro("_ABIN32", "2"); 4952 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 4953 } 4954 else if (ABI == "n64") { 4955 Builder.defineMacro("__mips_n64"); 4956 Builder.defineMacro("_ABI64", "3"); 4957 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 4958 } 4959 else 4960 llvm_unreachable("Invalid ABI for Mips64."); 4961 } 4962 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4963 unsigned &NumAliases) const { 4964 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4965 { { "at" }, "$1" }, 4966 { { "v0" }, "$2" }, 4967 { { "v1" }, "$3" }, 4968 { { "a0" }, "$4" }, 4969 { { "a1" }, "$5" }, 4970 { { "a2" }, "$6" }, 4971 { { "a3" }, "$7" }, 4972 { { "a4" }, "$8" }, 4973 { { "a5" }, "$9" }, 4974 { { "a6" }, "$10" }, 4975 { { "a7" }, "$11" }, 4976 { { "t0" }, "$12" }, 4977 { { "t1" }, "$13" }, 4978 { { "t2" }, "$14" }, 4979 { { "t3" }, "$15" }, 4980 { { "s0" }, "$16" }, 4981 { { "s1" }, "$17" }, 4982 { { "s2" }, "$18" }, 4983 { { "s3" }, "$19" }, 4984 { { "s4" }, "$20" }, 4985 { { "s5" }, "$21" }, 4986 { { "s6" }, "$22" }, 4987 { { "s7" }, "$23" }, 4988 { { "t8" }, "$24" }, 4989 { { "t9" }, "$25" }, 4990 { { "k0" }, "$26" }, 4991 { { "k1" }, "$27" }, 4992 { { "gp" }, "$28" }, 4993 { { "sp","$sp" }, "$29" }, 4994 { { "fp","$fp" }, "$30" }, 4995 { { "ra" }, "$31" } 4996 }; 4997 Aliases = GCCRegAliases; 4998 NumAliases = llvm::array_lengthof(GCCRegAliases); 4999 } 5000}; 5001 5002class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5003 virtual void SetDescriptionString(const std::string &Name) { 5004 // Change DescriptionString only if ABI is n32. 5005 if (Name == "n32") 5006 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5007 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5008 "v64:64:64-n32:64-S128"; 5009 } 5010public: 5011 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 5012 // Default ABI is n64. 5013 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5014 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5015 "v64:64:64-n32:64-S128"; 5016 } 5017 virtual void getTargetDefines(const LangOptions &Opts, 5018 MacroBuilder &Builder) const { 5019 DefineStd(Builder, "MIPSEB", Opts); 5020 Builder.defineMacro("_MIPSEB"); 5021 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5022 } 5023}; 5024 5025class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5026 virtual void SetDescriptionString(const std::string &Name) { 5027 // Change DescriptionString only if ABI is n32. 5028 if (Name == "n32") 5029 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5030 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 5031 "-v64:64:64-n32:64-S128"; 5032 } 5033public: 5034 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 5035 // Default ABI is n64. 5036 BigEndian = false; 5037 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5038 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5039 "v64:64:64-n32:64-S128"; 5040 } 5041 virtual void getTargetDefines(const LangOptions &Opts, 5042 MacroBuilder &Builder) const { 5043 DefineStd(Builder, "MIPSEL", Opts); 5044 Builder.defineMacro("_MIPSEL"); 5045 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5046 } 5047}; 5048} // end anonymous namespace. 5049 5050namespace { 5051class PNaClTargetInfo : public TargetInfo { 5052public: 5053 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) { 5054 BigEndian = false; 5055 this->UserLabelPrefix = ""; 5056 this->LongAlign = 32; 5057 this->LongWidth = 32; 5058 this->PointerAlign = 32; 5059 this->PointerWidth = 32; 5060 this->IntMaxType = TargetInfo::SignedLongLong; 5061 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5062 this->Int64Type = TargetInfo::SignedLongLong; 5063 this->DoubleAlign = 64; 5064 this->LongDoubleWidth = 64; 5065 this->LongDoubleAlign = 64; 5066 this->SizeType = TargetInfo::UnsignedInt; 5067 this->PtrDiffType = TargetInfo::SignedInt; 5068 this->IntPtrType = TargetInfo::SignedInt; 5069 this->RegParmMax = 0; // Disallow regparm 5070 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5071 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 5072 } 5073 5074 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5075 } 5076 virtual void getArchDefines(const LangOptions &Opts, 5077 MacroBuilder &Builder) const { 5078 Builder.defineMacro("__le32__"); 5079 Builder.defineMacro("__pnacl__"); 5080 } 5081 virtual void getTargetDefines(const LangOptions &Opts, 5082 MacroBuilder &Builder) const { 5083 Builder.defineMacro("__LITTLE_ENDIAN__"); 5084 getArchDefines(Opts, Builder); 5085 } 5086 virtual bool hasFeature(StringRef Feature) const { 5087 return Feature == "pnacl"; 5088 } 5089 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5090 unsigned &NumRecords) const { 5091 } 5092 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5093 return TargetInfo::PNaClABIBuiltinVaList; 5094 } 5095 virtual void getGCCRegNames(const char * const *&Names, 5096 unsigned &NumNames) const; 5097 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5098 unsigned &NumAliases) const; 5099 virtual bool validateAsmConstraint(const char *&Name, 5100 TargetInfo::ConstraintInfo &Info) const { 5101 return false; 5102 } 5103 5104 virtual const char *getClobbers() const { 5105 return ""; 5106 } 5107}; 5108 5109void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5110 unsigned &NumNames) const { 5111 Names = NULL; 5112 NumNames = 0; 5113} 5114 5115void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5116 unsigned &NumAliases) const { 5117 Aliases = NULL; 5118 NumAliases = 0; 5119} 5120} // end anonymous namespace. 5121 5122namespace { 5123 static const unsigned SPIRAddrSpaceMap[] = { 5124 1, // opencl_global 5125 3, // opencl_local 5126 2, // opencl_constant 5127 0, // cuda_device 5128 0, // cuda_constant 5129 0 // cuda_shared 5130 }; 5131 class SPIRTargetInfo : public TargetInfo { 5132 static const char * const GCCRegNames[]; 5133 static const Builtin::Info BuiltinInfo[]; 5134 std::vector<StringRef> AvailableFeatures; 5135 public: 5136 SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) { 5137 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5138 "SPIR target must use unknown OS"); 5139 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5140 "SPIR target must use unknown environment type"); 5141 BigEndian = false; 5142 TLSSupported = false; 5143 LongWidth = LongAlign = 64; 5144 AddrSpaceMap = &SPIRAddrSpaceMap; 5145 // Define available target features 5146 // These must be defined in sorted order! 5147 NoAsmVariants = true; 5148 } 5149 virtual void getTargetDefines(const LangOptions &Opts, 5150 MacroBuilder &Builder) const { 5151 DefineStd(Builder, "SPIR", Opts); 5152 } 5153 virtual bool hasFeature(StringRef Feature) const { 5154 return Feature == "spir"; 5155 } 5156 5157 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5158 unsigned &NumRecords) const {} 5159 virtual const char *getClobbers() const { 5160 return ""; 5161 } 5162 virtual void getGCCRegNames(const char * const *&Names, 5163 unsigned &NumNames) const {} 5164 virtual bool validateAsmConstraint(const char *&Name, 5165 TargetInfo::ConstraintInfo &info) const { 5166 return true; 5167 } 5168 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5169 unsigned &NumAliases) const {} 5170 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5171 return TargetInfo::VoidPtrBuiltinVaList; 5172 } 5173 }; 5174 5175 5176 class SPIR32TargetInfo : public SPIRTargetInfo { 5177 public: 5178 SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) { 5179 PointerWidth = PointerAlign = 32; 5180 SizeType = TargetInfo::UnsignedInt; 5181 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5182 DescriptionString 5183 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5184 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5185 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5186 "v512:512:512-v1024:1024:1024"; 5187 } 5188 virtual void getTargetDefines(const LangOptions &Opts, 5189 MacroBuilder &Builder) const { 5190 DefineStd(Builder, "SPIR32", Opts); 5191 } 5192 }; 5193 5194 class SPIR64TargetInfo : public SPIRTargetInfo { 5195 public: 5196 SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) { 5197 PointerWidth = PointerAlign = 64; 5198 SizeType = TargetInfo::UnsignedLong; 5199 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5200 DescriptionString 5201 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5202 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5203 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5204 "v512:512:512-v1024:1024:1024"; 5205 } 5206 virtual void getTargetDefines(const LangOptions &Opts, 5207 MacroBuilder &Builder) const { 5208 DefineStd(Builder, "SPIR64", Opts); 5209 } 5210 }; 5211} 5212 5213 5214//===----------------------------------------------------------------------===// 5215// Driver code 5216//===----------------------------------------------------------------------===// 5217 5218static TargetInfo *AllocateTarget(const std::string &T) { 5219 llvm::Triple Triple(T); 5220 llvm::Triple::OSType os = Triple.getOS(); 5221 5222 switch (Triple.getArch()) { 5223 default: 5224 return NULL; 5225 5226 case llvm::Triple::hexagon: 5227 return new HexagonTargetInfo(T); 5228 5229 case llvm::Triple::aarch64: 5230 switch (os) { 5231 case llvm::Triple::Linux: 5232 return new LinuxTargetInfo<AArch64TargetInfo>(T); 5233 default: 5234 return new AArch64TargetInfo(T); 5235 } 5236 5237 case llvm::Triple::arm: 5238 case llvm::Triple::thumb: 5239 if (Triple.isOSDarwin()) 5240 return new DarwinARMTargetInfo(T); 5241 5242 switch (os) { 5243 case llvm::Triple::Linux: 5244 return new LinuxTargetInfo<ARMTargetInfo>(T); 5245 case llvm::Triple::FreeBSD: 5246 return new FreeBSDTargetInfo<ARMTargetInfo>(T); 5247 case llvm::Triple::NetBSD: 5248 return new NetBSDTargetInfo<ARMTargetInfo>(T); 5249 case llvm::Triple::OpenBSD: 5250 return new OpenBSDTargetInfo<ARMTargetInfo>(T); 5251 case llvm::Triple::Bitrig: 5252 return new BitrigTargetInfo<ARMTargetInfo>(T); 5253 case llvm::Triple::RTEMS: 5254 return new RTEMSTargetInfo<ARMTargetInfo>(T); 5255 case llvm::Triple::NaCl: 5256 return new NaClTargetInfo<ARMTargetInfo>(T); 5257 default: 5258 return new ARMTargetInfo(T); 5259 } 5260 5261 case llvm::Triple::msp430: 5262 return new MSP430TargetInfo(T); 5263 5264 case llvm::Triple::mips: 5265 switch (os) { 5266 case llvm::Triple::Linux: 5267 return new LinuxTargetInfo<Mips32EBTargetInfo>(T); 5268 case llvm::Triple::RTEMS: 5269 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T); 5270 case llvm::Triple::FreeBSD: 5271 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T); 5272 case llvm::Triple::NetBSD: 5273 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T); 5274 default: 5275 return new Mips32EBTargetInfo(T); 5276 } 5277 5278 case llvm::Triple::mipsel: 5279 switch (os) { 5280 case llvm::Triple::Linux: 5281 return new LinuxTargetInfo<Mips32ELTargetInfo>(T); 5282 case llvm::Triple::RTEMS: 5283 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T); 5284 case llvm::Triple::FreeBSD: 5285 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T); 5286 case llvm::Triple::NetBSD: 5287 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T); 5288 default: 5289 return new Mips32ELTargetInfo(T); 5290 } 5291 5292 case llvm::Triple::mips64: 5293 switch (os) { 5294 case llvm::Triple::Linux: 5295 return new LinuxTargetInfo<Mips64EBTargetInfo>(T); 5296 case llvm::Triple::RTEMS: 5297 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T); 5298 case llvm::Triple::FreeBSD: 5299 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T); 5300 case llvm::Triple::NetBSD: 5301 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T); 5302 case llvm::Triple::OpenBSD: 5303 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T); 5304 default: 5305 return new Mips64EBTargetInfo(T); 5306 } 5307 5308 case llvm::Triple::mips64el: 5309 switch (os) { 5310 case llvm::Triple::Linux: 5311 return new LinuxTargetInfo<Mips64ELTargetInfo>(T); 5312 case llvm::Triple::RTEMS: 5313 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T); 5314 case llvm::Triple::FreeBSD: 5315 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T); 5316 case llvm::Triple::NetBSD: 5317 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T); 5318 case llvm::Triple::OpenBSD: 5319 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T); 5320 default: 5321 return new Mips64ELTargetInfo(T); 5322 } 5323 5324 case llvm::Triple::le32: 5325 switch (os) { 5326 case llvm::Triple::NaCl: 5327 return new NaClTargetInfo<PNaClTargetInfo>(T); 5328 default: 5329 return NULL; 5330 } 5331 5332 case llvm::Triple::ppc: 5333 if (Triple.isOSDarwin()) 5334 return new DarwinPPC32TargetInfo(T); 5335 switch (os) { 5336 case llvm::Triple::Linux: 5337 return new LinuxTargetInfo<PPC32TargetInfo>(T); 5338 case llvm::Triple::FreeBSD: 5339 return new FreeBSDTargetInfo<PPC32TargetInfo>(T); 5340 case llvm::Triple::NetBSD: 5341 return new NetBSDTargetInfo<PPC32TargetInfo>(T); 5342 case llvm::Triple::OpenBSD: 5343 return new OpenBSDTargetInfo<PPC32TargetInfo>(T); 5344 case llvm::Triple::RTEMS: 5345 return new RTEMSTargetInfo<PPC32TargetInfo>(T); 5346 default: 5347 return new PPC32TargetInfo(T); 5348 } 5349 5350 case llvm::Triple::ppc64: 5351 if (Triple.isOSDarwin()) 5352 return new DarwinPPC64TargetInfo(T); 5353 switch (os) { 5354 case llvm::Triple::Linux: 5355 return new LinuxTargetInfo<PPC64TargetInfo>(T); 5356 case llvm::Triple::Lv2: 5357 return new PS3PPUTargetInfo<PPC64TargetInfo>(T); 5358 case llvm::Triple::FreeBSD: 5359 return new FreeBSDTargetInfo<PPC64TargetInfo>(T); 5360 case llvm::Triple::NetBSD: 5361 return new NetBSDTargetInfo<PPC64TargetInfo>(T); 5362 default: 5363 return new PPC64TargetInfo(T); 5364 } 5365 5366 case llvm::Triple::nvptx: 5367 return new NVPTX32TargetInfo(T); 5368 case llvm::Triple::nvptx64: 5369 return new NVPTX64TargetInfo(T); 5370 5371 case llvm::Triple::mblaze: 5372 return new MBlazeTargetInfo(T); 5373 5374 case llvm::Triple::r600: 5375 return new R600TargetInfo(T); 5376 5377 case llvm::Triple::sparc: 5378 switch (os) { 5379 case llvm::Triple::Linux: 5380 return new LinuxTargetInfo<SparcV8TargetInfo>(T); 5381 case llvm::Triple::AuroraUX: 5382 return new AuroraUXSparcV8TargetInfo(T); 5383 case llvm::Triple::Solaris: 5384 return new SolarisSparcV8TargetInfo(T); 5385 case llvm::Triple::NetBSD: 5386 return new NetBSDTargetInfo<SparcV8TargetInfo>(T); 5387 case llvm::Triple::OpenBSD: 5388 return new OpenBSDTargetInfo<SparcV8TargetInfo>(T); 5389 case llvm::Triple::RTEMS: 5390 return new RTEMSTargetInfo<SparcV8TargetInfo>(T); 5391 default: 5392 return new SparcV8TargetInfo(T); 5393 } 5394 5395 case llvm::Triple::sparcv9: 5396 switch (os) { 5397 case llvm::Triple::Linux: 5398 return new LinuxTargetInfo<SparcV9TargetInfo>(T); 5399 case llvm::Triple::AuroraUX: 5400 return new AuroraUXTargetInfo<SparcV9TargetInfo>(T); 5401 case llvm::Triple::Solaris: 5402 return new SolarisTargetInfo<SparcV9TargetInfo>(T); 5403 case llvm::Triple::NetBSD: 5404 return new NetBSDTargetInfo<SparcV9TargetInfo>(T); 5405 case llvm::Triple::OpenBSD: 5406 return new OpenBSDTargetInfo<SparcV9TargetInfo>(T); 5407 case llvm::Triple::FreeBSD: 5408 return new FreeBSDTargetInfo<SparcV9TargetInfo>(T); 5409 default: 5410 return new SparcV9TargetInfo(T); 5411 } 5412 5413 case llvm::Triple::systemz: 5414 switch (os) { 5415 case llvm::Triple::Linux: 5416 return new LinuxTargetInfo<SystemZTargetInfo>(T); 5417 default: 5418 return new SystemZTargetInfo(T); 5419 } 5420 5421 case llvm::Triple::tce: 5422 return new TCETargetInfo(T); 5423 5424 case llvm::Triple::x86: 5425 if (Triple.isOSDarwin()) 5426 return new DarwinI386TargetInfo(T); 5427 5428 switch (os) { 5429 case llvm::Triple::AuroraUX: 5430 return new AuroraUXTargetInfo<X86_32TargetInfo>(T); 5431 case llvm::Triple::Linux: 5432 return new LinuxTargetInfo<X86_32TargetInfo>(T); 5433 case llvm::Triple::DragonFly: 5434 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T); 5435 case llvm::Triple::NetBSD: 5436 return new NetBSDI386TargetInfo(T); 5437 case llvm::Triple::OpenBSD: 5438 return new OpenBSDI386TargetInfo(T); 5439 case llvm::Triple::Bitrig: 5440 return new BitrigI386TargetInfo(T); 5441 case llvm::Triple::FreeBSD: 5442 return new FreeBSDTargetInfo<X86_32TargetInfo>(T); 5443 case llvm::Triple::Minix: 5444 return new MinixTargetInfo<X86_32TargetInfo>(T); 5445 case llvm::Triple::Solaris: 5446 return new SolarisTargetInfo<X86_32TargetInfo>(T); 5447 case llvm::Triple::Cygwin: 5448 return new CygwinX86_32TargetInfo(T); 5449 case llvm::Triple::MinGW32: 5450 return new MinGWX86_32TargetInfo(T); 5451 case llvm::Triple::Win32: 5452 return new VisualStudioWindowsX86_32TargetInfo(T); 5453 case llvm::Triple::Haiku: 5454 return new HaikuX86_32TargetInfo(T); 5455 case llvm::Triple::RTEMS: 5456 return new RTEMSX86_32TargetInfo(T); 5457 case llvm::Triple::NaCl: 5458 return new NaClTargetInfo<X86_32TargetInfo>(T); 5459 default: 5460 return new X86_32TargetInfo(T); 5461 } 5462 5463 case llvm::Triple::x86_64: 5464 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5465 return new DarwinX86_64TargetInfo(T); 5466 5467 switch (os) { 5468 case llvm::Triple::AuroraUX: 5469 return new AuroraUXTargetInfo<X86_64TargetInfo>(T); 5470 case llvm::Triple::Linux: 5471 return new LinuxTargetInfo<X86_64TargetInfo>(T); 5472 case llvm::Triple::DragonFly: 5473 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T); 5474 case llvm::Triple::NetBSD: 5475 return new NetBSDTargetInfo<X86_64TargetInfo>(T); 5476 case llvm::Triple::OpenBSD: 5477 return new OpenBSDX86_64TargetInfo(T); 5478 case llvm::Triple::Bitrig: 5479 return new BitrigX86_64TargetInfo(T); 5480 case llvm::Triple::FreeBSD: 5481 return new FreeBSDTargetInfo<X86_64TargetInfo>(T); 5482 case llvm::Triple::Solaris: 5483 return new SolarisTargetInfo<X86_64TargetInfo>(T); 5484 case llvm::Triple::MinGW32: 5485 return new MinGWX86_64TargetInfo(T); 5486 case llvm::Triple::Win32: // This is what Triple.h supports now. 5487 return new VisualStudioWindowsX86_64TargetInfo(T); 5488 case llvm::Triple::NaCl: 5489 return new NaClTargetInfo<X86_64TargetInfo>(T); 5490 default: 5491 return new X86_64TargetInfo(T); 5492 } 5493 5494 case llvm::Triple::spir: { 5495 llvm::Triple Triple(T); 5496 if (Triple.getOS() != llvm::Triple::UnknownOS || 5497 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5498 return NULL; 5499 return new SPIR32TargetInfo(T); 5500 } 5501 case llvm::Triple::spir64: { 5502 llvm::Triple Triple(T); 5503 if (Triple.getOS() != llvm::Triple::UnknownOS || 5504 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5505 return NULL; 5506 return new SPIR64TargetInfo(T); 5507 } 5508 } 5509} 5510 5511/// CreateTargetInfo - Return the target info object for the specified target 5512/// triple. 5513TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5514 TargetOptions *Opts) { 5515 llvm::Triple Triple(Opts->Triple); 5516 5517 // Construct the target 5518 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str())); 5519 if (!Target) { 5520 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5521 return 0; 5522 } 5523 Target->setTargetOpts(Opts); 5524 5525 // Set the target CPU if specified. 5526 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5527 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5528 return 0; 5529 } 5530 5531 // Set the target ABI if specified. 5532 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5533 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5534 return 0; 5535 } 5536 5537 // Set the target C++ ABI. 5538 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 5539 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 5540 return 0; 5541 } 5542 5543 // Compute the default target features, we need the target to handle this 5544 // because features may have dependencies on one another. 5545 llvm::StringMap<bool> Features; 5546 Target->getDefaultFeatures(Features); 5547 5548 // Apply the user specified deltas. 5549 // First the enables. 5550 for (std::vector<std::string>::const_iterator 5551 it = Opts->FeaturesAsWritten.begin(), 5552 ie = Opts->FeaturesAsWritten.end(); 5553 it != ie; ++it) { 5554 const char *Name = it->c_str(); 5555 5556 if (Name[0] != '+') 5557 continue; 5558 5559 // Apply the feature via the target. 5560 if (!Target->setFeatureEnabled(Features, Name + 1, true)) { 5561 Diags.Report(diag::err_target_invalid_feature) << Name; 5562 return 0; 5563 } 5564 } 5565 5566 // Then the disables. 5567 for (std::vector<std::string>::const_iterator 5568 it = Opts->FeaturesAsWritten.begin(), 5569 ie = Opts->FeaturesAsWritten.end(); 5570 it != ie; ++it) { 5571 const char *Name = it->c_str(); 5572 5573 if (Name[0] == '+') 5574 continue; 5575 5576 // Apply the feature via the target. 5577 if (Name[0] != '-' || 5578 !Target->setFeatureEnabled(Features, Name + 1, false)) { 5579 Diags.Report(diag::err_target_invalid_feature) << Name; 5580 return 0; 5581 } 5582 } 5583 5584 // Add the features to the compile options. 5585 // 5586 // FIXME: If we are completely confident that we have the right set, we only 5587 // need to pass the minuses. 5588 Opts->Features.clear(); 5589 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5590 ie = Features.end(); it != ie; ++it) 5591 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5592 Target->HandleTargetFeatures(Opts->Features); 5593 5594 return Target.take(); 5595} 5596