1//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for Sandy Bridge to support instruction 11// scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15def SandyBridgeModel : SchedMachineModel { 16 // All x86 instructions are modeled as a single micro-op, and SB can decode 4 17 // instructions per cycle. 18 // FIXME: Identify instructions that aren't a single fused micro-op. 19 let IssueWidth = 4; 20 let MinLatency = 0; // 0 = Out-of-order execution. 21 let LoadLatency = 4; 22 let ILPWindow = 20; 23 let MispredictPenalty = 16; 24} 25 26let SchedModel = SandyBridgeModel in { 27 28// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 29 30// Ports 0, 1, and 5 handle all computation. 31def SBPort0 : ProcResource<1>; 32def SBPort1 : ProcResource<1>; 33def SBPort5 : ProcResource<1>; 34 35// Ports 2 and 3 are identical. They handle loads and the address half of 36// stores. 37def SBPort23 : ProcResource<2>; 38 39// Port 4 gets the data half of stores. Store data can be available later than 40// the store address, but since we don't model the latency of stores, we can 41// ignore that. 42def SBPort4 : ProcResource<1>; 43 44// Many micro-ops are capable of issuing on multiple ports. 45def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 46def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 47def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 48 49// Integer division issued on port 0. 50def SBDivider : ProcResource<1>; 51 52// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 53// cycles after the memory operand. 54def : ReadAdvance<ReadAfterLd, 4>; 55 56// Many SchedWrites are defined in pairs with and without a folded load. 57// Instructions with folded loads are usually micro-fused, so they only appear 58// as two micro-ops when queued in the reservation station. 59// This multiclass defines the resource usage for variants with and without 60// folded loads. 61multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW, 62 ProcResourceKind ExePort, 63 int Lat> { 64 // Register variant is using a single cycle on ExePort. 65 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 66 67 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the 68 // latency. 69 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> { 70 let Latency = !add(Lat, 4); 71 } 72} 73 74// A folded store needs a cycle on port 4 for the store data, but it does not 75// need an extra port 2/3 cycle to recompute the address. 76def : WriteRes<WriteRMW, [SBPort4]>; 77 78def : WriteRes<WriteStore, [SBPort23, SBPort4]>; 79def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; } 80def : WriteRes<WriteMove, [SBPort015]>; 81def : WriteRes<WriteZero, []>; 82 83defm : SBWriteResPair<WriteALU, SBPort015, 1>; 84defm : SBWriteResPair<WriteIMul, SBPort1, 3>; 85defm : SBWriteResPair<WriteShift, SBPort05, 1>; 86defm : SBWriteResPair<WriteJump, SBPort5, 1>; 87 88// This is for simple LEAs with one or two input operands. 89// The complex ones can only execute on port 1, and they require two cycles on 90// the port to read all inputs. We don't model that. 91def : WriteRes<WriteLEA, [SBPort15]>; 92 93// This is quite rough, latency depends on the dividend. 94def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> { 95 let Latency = 25; 96 let ResourceCycles = [1, 10]; 97} 98def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> { 99 let Latency = 29; 100 let ResourceCycles = [1, 1, 10]; 101} 102 103// Scalar and vector floating point. 104defm : SBWriteResPair<WriteFAdd, SBPort1, 3>; 105defm : SBWriteResPair<WriteFMul, SBPort0, 5>; 106defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles. 107defm : SBWriteResPair<WriteFRcp, SBPort0, 5>; 108defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>; 109defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>; 110defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>; 111defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>; 112 113// Vector integer operations. 114defm : SBWriteResPair<WriteVecShift, SBPort05, 1>; 115defm : SBWriteResPair<WriteVecLogic, SBPort015, 1>; 116defm : SBWriteResPair<WriteVecALU, SBPort15, 1>; 117defm : SBWriteResPair<WriteVecIMul, SBPort0, 5>; 118defm : SBWriteResPair<WriteShuffle, SBPort15, 1>; 119 120def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 121def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 122} // SchedModel 123