197049Speter//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===// 2174993Srafan// 397049Speter// The LLVM Compiler Infrastructure 497049Speter// 597049Speter// This file is distributed under the University of Illinois Open Source 697049Speter// License. See LICENSE.TXT for details. 797049Speter// 897049Speter//===----------------------------------------------------------------------===// 997049Speter// 1097049Speter/// \file 1197049Speter/// \brief Interface definition for SIInstrInfo. 1297049Speter// 1397049Speter//===----------------------------------------------------------------------===// 1497049Speter 1597049Speter 1697049Speter#ifndef SIINSTRINFO_H 1797049Speter#define SIINSTRINFO_H 1897049Speter 1997049Speter#include "AMDGPUInstrInfo.h" 2097049Speter#include "SIRegisterInfo.h" 2197049Speter 2297049Speternamespace llvm { 2397049Speter 2497049Speterclass SIInstrInfo : public AMDGPUInstrInfo { 2597049Speterprivate: 2697049Speter const SIRegisterInfo RI; 2797049Speter 2897049Speterpublic: 2997049Speter explicit SIInstrInfo(AMDGPUTargetMachine &tm); 30174993Srafan 3197049Speter const SIRegisterInfo &getRegisterInfo() const; 3297049Speter 3397049Speter virtual void copyPhysReg(MachineBasicBlock &MBB, 3497049Speter MachineBasicBlock::iterator MI, DebugLoc DL, 3597049Speter unsigned DestReg, unsigned SrcReg, 3697049Speter bool KillSrc) const; 3797049Speter 3897049Speter unsigned commuteOpcode(unsigned Opcode) const; 3997049Speter 4097049Speter virtual MachineInstr *commuteInstruction(MachineInstr *MI, 4197049Speter bool NewMI=false) const; 42174993Srafan 4397049Speter virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, 4497049Speter int64_t Imm) const; 45174993Srafan 4697049Speter virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;} 4797049Speter virtual bool isMov(unsigned Opcode) const; 4897049Speter 49174993Srafan virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 5097049Speter 5197049Speter virtual int getIndirectIndexBegin(const MachineFunction &MF) const; 52174993Srafan 53166124Srafan virtual int getIndirectIndexEnd(const MachineFunction &MF) const; 54174993Srafan 5597049Speter virtual unsigned calculateIndirectAddress(unsigned RegIndex, 56166124Srafan unsigned Channel) const; 57174993Srafan 58174993Srafan virtual const TargetRegisterClass *getIndirectAddrStoreRegClass( 59166124Srafan unsigned SourceReg) const; 6097049Speter 61174993Srafan virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const; 62174993Srafan 63174993Srafan virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 6497049Speter MachineBasicBlock::iterator I, 65174993Srafan unsigned ValueReg, 66174993Srafan unsigned Address, 67174993Srafan unsigned OffsetReg) const; 68174993Srafan 69166124Srafan virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 70174993Srafan MachineBasicBlock::iterator I, 71166124Srafan unsigned ValueReg, 7297049Speter unsigned Address, 7397049Speter unsigned OffsetReg) const; 7497049Speter 7597049Speter virtual const TargetRegisterClass *getSuperIndirectRegClass() const; 7697049Speter }; 77 78namespace AMDGPU { 79 80 int getVOPe64(uint16_t Opcode); 81 int getCommuteRev(uint16_t Opcode); 82 int getCommuteOrig(uint16_t Opcode); 83 int isMIMG(uint16_t Opcode); 84 85} // End namespace AMDGPU 86 87} // End namespace llvm 88 89namespace SIInstrFlags { 90 enum Flags { 91 // First 4 bits are the instruction encoding 92 VM_CNT = 1 << 0, 93 EXP_CNT = 1 << 1, 94 LGKM_CNT = 1 << 2 95 }; 96} 97 98#endif //SIINSTRINFO_H 99