1//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for SIInstrInfo.
12//
13//===----------------------------------------------------------------------===//
14
15
16#ifndef SIINSTRINFO_H
17#define SIINSTRINFO_H
18
19#include "AMDGPUInstrInfo.h"
20#include "SIRegisterInfo.h"
21
22namespace llvm {
23
24class SIInstrInfo : public AMDGPUInstrInfo {
25private:
26  const SIRegisterInfo RI;
27
28public:
29  explicit SIInstrInfo(AMDGPUTargetMachine &tm);
30
31  const SIRegisterInfo &getRegisterInfo() const;
32
33  virtual void copyPhysReg(MachineBasicBlock &MBB,
34                           MachineBasicBlock::iterator MI, DebugLoc DL,
35                           unsigned DestReg, unsigned SrcReg,
36                           bool KillSrc) const;
37
38  unsigned commuteOpcode(unsigned Opcode) const;
39
40  virtual MachineInstr *commuteInstruction(MachineInstr *MI,
41                                           bool NewMI=false) const;
42
43  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
44                                        int64_t Imm) const;
45
46  virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
47  virtual bool isMov(unsigned Opcode) const;
48
49  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
50
51  virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
52
53  virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
54
55  virtual unsigned calculateIndirectAddress(unsigned RegIndex,
56                                            unsigned Channel) const;
57
58  virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
59                                                      unsigned SourceReg) const;
60
61  virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
62
63  virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
64                                                 MachineBasicBlock::iterator I,
65                                                 unsigned ValueReg,
66                                                 unsigned Address,
67                                                 unsigned OffsetReg) const;
68
69  virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
70                                                MachineBasicBlock::iterator I,
71                                                unsigned ValueReg,
72                                                unsigned Address,
73                                                unsigned OffsetReg) const;
74
75  virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
76  };
77
78namespace AMDGPU {
79
80  int getVOPe64(uint16_t Opcode);
81  int getCommuteRev(uint16_t Opcode);
82  int getCommuteOrig(uint16_t Opcode);
83  int isMIMG(uint16_t Opcode);
84
85} // End namespace AMDGPU
86
87} // End namespace llvm
88
89namespace SIInstrFlags {
90  enum Flags {
91    // First 4 bits are the instruction encoding
92    VM_CNT = 1 << 0,
93    EXP_CNT = 1 << 1,
94    LGKM_CNT = 1 << 2
95  };
96}
97
98#endif //SIINSTRINFO_H
99