1//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef POWERPC32_REGISTERINFO_H
16#define POWERPC32_REGISTERINFO_H
17
18#include "llvm/ADT/DenseMap.h"
19#include "PPC.h"
20
21#define GET_REGINFO_HEADER
22#include "PPCGenRegisterInfo.inc"
23
24namespace llvm {
25class PPCSubtarget;
26class TargetInstrInfo;
27class Type;
28
29class PPCRegisterInfo : public PPCGenRegisterInfo {
30  DenseMap<unsigned, unsigned> ImmToIdxMap;
31  const PPCSubtarget &Subtarget;
32  const TargetInstrInfo &TII;
33public:
34  PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
35
36  /// getPointerRegClass - Return the register class to use to hold pointers.
37  /// This is used for addressing modes.
38  virtual const TargetRegisterClass *
39  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
40
41  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
42                               MachineFunction &MF) const;
43
44  /// Code Generation virtual methods...
45  const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
46  const uint32_t *getCallPreservedMask(CallingConv::ID CC) const;
47  const uint32_t *getNoPreservedMask() const;
48
49  BitVector getReservedRegs(const MachineFunction &MF) const;
50
51  /// We require the register scavenger.
52  bool requiresRegisterScavenging(const MachineFunction &MF) const {
53    return true;
54  }
55
56  bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
57    return true;
58  }
59
60  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
61    return true;
62  }
63
64  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
65    return true;
66  }
67
68  void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
69  void lowerCRSpilling(MachineBasicBlock::iterator II,
70                       unsigned FrameIndex) const;
71  void lowerCRRestore(MachineBasicBlock::iterator II,
72                      unsigned FrameIndex) const;
73  void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
74                           unsigned FrameIndex) const;
75  void lowerVRSAVERestore(MachineBasicBlock::iterator II,
76                          unsigned FrameIndex) const;
77
78  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
79			    int &FrameIdx) const;
80  void eliminateFrameIndex(MachineBasicBlock::iterator II,
81                           int SPAdj, unsigned FIOperandNum,
82                           RegScavenger *RS = NULL) const;
83
84  // Support for virtual base registers.
85  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
86  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
87                                    unsigned BaseReg, int FrameIdx,
88                                    int64_t Offset) const;
89  void resolveFrameIndex(MachineBasicBlock::iterator I,
90                         unsigned BaseReg, int64_t Offset) const;
91  bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
92
93  // Debug information queries.
94  unsigned getFrameRegister(const MachineFunction &MF) const;
95
96  // Exception handling queries.
97  unsigned getEHExceptionRegister() const;
98  unsigned getEHHandlerRegister() const;
99};
100
101} // end namespace llvm
102
103#endif
104