PPCInstr64Bit.td revision 234353
1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27} 28def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31} 32 33//===----------------------------------------------------------------------===// 34// 64-bit transformation functions. 35// 36 37def SHL64 : SDNodeXForm<imm, [{ 38 // Transformation function: 63 - imm 39 return getI32Imm(63 - N->getZExtValue()); 40}]>; 41 42def SRL64 : SDNodeXForm<imm, [{ 43 // Transformation function: 64 - imm 44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 45}]>; 46 47def HI32_48 : SDNodeXForm<imm, [{ 48 // Transformation function: shift the immediate value down into the low bits. 49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 50}]>; 51 52def HI48_64 : SDNodeXForm<imm, [{ 53 // Transformation function: shift the immediate value down into the low bits. 54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 55}]>; 56 57 58//===----------------------------------------------------------------------===// 59// Calls. 60// 61 62let Defs = [LR8] in 63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>, 64 PPC970_Unit_BRU; 65 66// Darwin ABI Calls. 67let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 68 // Convenient aliases for call instructions 69 let Uses = [RM] in { 70 def BL8_Darwin : IForm<18, 0, 1, 71 (outs), (ins calltarget:$func, variable_ops), 72 "bl $func", BrB, []>; // See Pat patterns below. 73 def BLA8_Darwin : IForm<18, 1, 1, 74 (outs), (ins aaddr:$func, variable_ops), 75 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 76 } 77 let Uses = [CTR8, RM] in { 78 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 79 (outs), (ins variable_ops), 80 "bctrl", BrB, 81 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 82 } 83} 84 85// ELF 64 ABI Calls = Darwin ABI Calls 86// Used to define BL8_ELF and BLA8_ELF 87let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 88 // Convenient aliases for call instructions 89 let Uses = [RM] in { 90 def BL8_ELF : IForm<18, 0, 1, 91 (outs), (ins calltarget:$func, variable_ops), 92 "bl $func", BrB, []>; // See Pat patterns below. 93 94 let isCodeGenOnly = 1 in 95 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24, 96 (outs), (ins calltarget:$func, variable_ops), 97 "bl $func\n\tnop", BrB, []>; 98 99 def BLA8_ELF : IForm<18, 1, 1, 100 (outs), (ins aaddr:$func, variable_ops), 101 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 102 103 let isCodeGenOnly = 1 in 104 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24, 105 (outs), (ins aaddr:$func, variable_ops), 106 "bla $func\n\tnop", BrB, 107 [(PPCcall_nop_SVR4 (i64 imm:$func))]>; 108 } 109 let Uses = [X11, CTR8, RM] in { 110 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 111 (outs), (ins variable_ops), 112 "bctrl", BrB, 113 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 114 } 115} 116 117 118// Calls 119def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 120 (BL8_Darwin tglobaladdr:$dst)>; 121def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 122 (BL8_Darwin texternalsym:$dst)>; 123 124def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 125 (BL8_ELF tglobaladdr:$dst)>; 126def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)), 127 (BL8_NOP_ELF tglobaladdr:$dst)>; 128 129def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 130 (BL8_ELF texternalsym:$dst)>; 131def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)), 132 (BL8_NOP_ELF texternalsym:$dst)>; 133 134def : Pat<(PPCnop), 135 (NOP)>; 136 137// Atomic operations 138let usesCustomInserter = 1 in { 139 let Defs = [CR0] in { 140 def ATOMIC_LOAD_ADD_I64 : Pseudo< 141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 142 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 143 def ATOMIC_LOAD_SUB_I64 : Pseudo< 144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 145 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 146 def ATOMIC_LOAD_OR_I64 : Pseudo< 147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 148 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 149 def ATOMIC_LOAD_XOR_I64 : Pseudo< 150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 151 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 152 def ATOMIC_LOAD_AND_I64 : Pseudo< 153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 154 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 155 def ATOMIC_LOAD_NAND_I64 : Pseudo< 156 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 157 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 158 159 def ATOMIC_CMP_SWAP_I64 : Pseudo< 160 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "", 161 [(set G8RC:$dst, 162 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 163 164 def ATOMIC_SWAP_I64 : Pseudo< 165 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "", 166 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 167 } 168} 169 170// Instructions to support atomic operations 171def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 172 "ldarx $rD, $ptr", LdStLDARX, 173 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 174 175let Defs = [CR0] in 176def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 177 "stdcx. $rS, $dst", LdStSTDCX, 178 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 179 isDOT; 180 181let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 182def TCRETURNdi8 :Pseudo< (outs), 183 (ins calltarget:$dst, i32imm:$offset, variable_ops), 184 "#TC_RETURNd8 $dst $offset", 185 []>; 186 187let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 188def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 189 "#TC_RETURNa8 $func $offset", 190 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 191 192let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 193def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), 194 "#TC_RETURNr8 $dst $offset", 195 []>; 196 197 198let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 199 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 200 let isReturn = 1 in { 201 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 202 Requires<[In64BitMode]>; 203 } 204 205 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 206 Requires<[In64BitMode]>; 207} 208 209 210let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 211 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 212def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 213 "b $dst", BrB, 214 []>; 215 216 217let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 218 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 219def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 220 "ba $dst", BrB, 221 []>; 222 223def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 224 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 225 226def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 227 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 228 229def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 230 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 231 232// 64-but CR instructions 233def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 234 "mtcrf $FXM, $rS", BrMCRX>, 235 PPC970_MicroCode, PPC970_Unit_CRU; 236 237def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 238 "", SprMFCR>, 239 PPC970_MicroCode, PPC970_Unit_CRU; 240 241def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 242 "mfcr $rT", SprMFCR>, 243 PPC970_MicroCode, PPC970_Unit_CRU; 244 245//===----------------------------------------------------------------------===// 246// 64-bit SPR manipulation instrs. 247 248let Uses = [CTR8] in { 249def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 250 "mfctr $rT", SprMFSPR>, 251 PPC970_DGroup_First, PPC970_Unit_FXU; 252} 253let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 254def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 255 "mtctr $rS", SprMTSPR>, 256 PPC970_DGroup_First, PPC970_Unit_FXU; 257} 258 259let Defs = [X1], Uses = [X1] in 260def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"", 261 [(set G8RC:$result, 262 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 263 264let Defs = [LR8] in { 265def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 266 "mtlr $rS", SprMTSPR>, 267 PPC970_DGroup_First, PPC970_Unit_FXU; 268} 269let Uses = [LR8] in { 270def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 271 "mflr $rT", SprMFSPR>, 272 PPC970_DGroup_First, PPC970_Unit_FXU; 273} 274 275//===----------------------------------------------------------------------===// 276// Fixed point instructions. 277// 278 279let PPC970_Unit = 1 in { // FXU Operations. 280 281// Copies, extends, truncates. 282def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), 283 "or $rA, $rS, $rB", IntGeneral, 284 []>; 285def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), 286 "or $rA, $rS, $rB", IntGeneral, 287 []>; 288 289def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 290 "li $rD, $imm", IntGeneral, 291 [(set G8RC:$rD, immSExt16:$imm)]>; 292def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 293 "lis $rD, $imm", IntGeneral, 294 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 295 296// Logical ops. 297def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 298 "nand $rA, $rS, $rB", IntGeneral, 299 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 300def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 301 "and $rA, $rS, $rB", IntGeneral, 302 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 303def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 304 "andc $rA, $rS, $rB", IntGeneral, 305 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 306def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 307 "or $rA, $rS, $rB", IntGeneral, 308 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 309def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 310 "nor $rA, $rS, $rB", IntGeneral, 311 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 312def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 313 "orc $rA, $rS, $rB", IntGeneral, 314 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 315def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 316 "eqv $rA, $rS, $rB", IntGeneral, 317 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 318def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 319 "xor $rA, $rS, $rB", IntGeneral, 320 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 321 322// Logical ops with immediate. 323def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 324 "andi. $dst, $src1, $src2", IntGeneral, 325 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 326 isDOT; 327def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 328 "andis. $dst, $src1, $src2", IntGeneral, 329 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 330 isDOT; 331def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 332 "ori $dst, $src1, $src2", IntGeneral, 333 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 334def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 335 "oris $dst, $src1, $src2", IntGeneral, 336 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 337def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 338 "xori $dst, $src1, $src2", IntGeneral, 339 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 340def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 341 "xoris $dst, $src1, $src2", IntGeneral, 342 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 343 344def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 345 "add $rT, $rA, $rB", IntGeneral, 346 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 347 348let Defs = [CARRY] in { 349def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 350 "addc $rT, $rA, $rB", IntGeneral, 351 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 352 PPC970_DGroup_Cracked; 353def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 354 "addic $rD, $rA, $imm", IntGeneral, 355 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 356} 357def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 358 "addi $rD, $rA, $imm", IntGeneral, 359 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 360def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 361 "addis $rD, $rA, $imm", IntGeneral, 362 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 363 364let Defs = [CARRY] in { 365def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 366 "subfic $rD, $rA, $imm", IntGeneral, 367 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 368def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 369 "subfc $rT, $rA, $rB", IntGeneral, 370 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 371 PPC970_DGroup_Cracked; 372} 373def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 374 "subf $rT, $rA, $rB", IntGeneral, 375 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 376def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 377 "neg $rT, $rA", IntGeneral, 378 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 379let Uses = [CARRY], Defs = [CARRY] in { 380def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 381 "adde $rT, $rA, $rB", IntGeneral, 382 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 383def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 384 "addme $rT, $rA", IntGeneral, 385 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 386def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 387 "addze $rT, $rA", IntGeneral, 388 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 389def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 390 "subfe $rT, $rA, $rB", IntGeneral, 391 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 392def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 393 "subfme $rT, $rA", IntGeneral, 394 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 395def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 396 "subfze $rT, $rA", IntGeneral, 397 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 398} 399 400 401def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 402 "mulhd $rT, $rA, $rB", IntMulHW, 403 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 404def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 405 "mulhdu $rT, $rA, $rB", IntMulHWU, 406 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 407 408def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 409 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 410def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 411 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 412def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 413 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 414def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 415 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 416 417def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 418 "sld $rA, $rS, $rB", IntRotateD, 419 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 420def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 421 "srd $rA, $rS, $rB", IntRotateD, 422 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 423let Defs = [CARRY] in { 424def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 425 "srad $rA, $rS, $rB", IntRotateD, 426 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 427} 428 429def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 430 "extsb $rA, $rS", IntGeneral, 431 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 432def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 433 "extsh $rA, $rS", IntGeneral, 434 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 435 436def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 437 "extsw $rA, $rS", IntGeneral, 438 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 439/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 440def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 441 "extsw $rA, $rS", IntGeneral, 442 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 443def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 444 "extsw $rA, $rS", IntGeneral, 445 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 446 447let Defs = [CARRY] in { 448def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 449 "sradi $rA, $rS, $SH", IntRotateD, 450 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 451} 452def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 453 "cntlzd $rA, $rS", IntGeneral, 454 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 455 456def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 457 "divd $rT, $rA, $rB", IntDivD, 458 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 459 PPC970_DGroup_First, PPC970_DGroup_Cracked; 460def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 461 "divdu $rT, $rA, $rB", IntDivD, 462 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 463 PPC970_DGroup_First, PPC970_DGroup_Cracked; 464def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 465 "mulld $rT, $rA, $rB", IntMulHD, 466 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 467 468 469let isCommutable = 1 in { 470def RLDIMI : MDForm_1<30, 3, 471 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 472 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 473 []>, isPPC64, RegConstraint<"$rSi = $rA">, 474 NoEncode<"$rSi">; 475} 476 477// Rotate instructions. 478def RLDCL : MDForm_1<30, 0, 479 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 480 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 481 []>, isPPC64; 482def RLDICL : MDForm_1<30, 0, 483 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 484 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 485 []>, isPPC64; 486def RLDICR : MDForm_1<30, 1, 487 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 488 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 489 []>, isPPC64; 490 491def RLWINM8 : MForm_2<21, 492 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 493 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 494 []>; 495 496} // End FXU Operations. 497 498 499//===----------------------------------------------------------------------===// 500// Load/Store instructions. 501// 502 503 504// Sign extending loads. 505let canFoldAsLoad = 1, PPC970_Unit = 2 in { 506def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 507 "lha $rD, $src", LdStLHA, 508 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 509 PPC970_DGroup_Cracked; 510def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 511 "lwa $rD, $src", LdStLWA, 512 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 513 PPC970_DGroup_Cracked; 514def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 515 "lhax $rD, $src", LdStLHA, 516 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 517 PPC970_DGroup_Cracked; 518def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 519 "lwax $rD, $src", LdStLHA, 520 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 521 PPC970_DGroup_Cracked; 522 523// Update forms. 524let mayLoad = 1 in 525def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 526 ptr_rc:$rA), 527 "lhau $rD, $disp($rA)", LdStLoad, 528 []>, RegConstraint<"$rA = $ea_result">, 529 NoEncode<"$ea_result">; 530// NO LWAU! 531 532} 533 534// Zero extending loads. 535let canFoldAsLoad = 1, PPC970_Unit = 2 in { 536def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 537 "lbz $rD, $src", LdStLoad, 538 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 539def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 540 "lhz $rD, $src", LdStLoad, 541 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 542def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 543 "lwz $rD, $src", LdStLoad, 544 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 545 546def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 547 "lbzx $rD, $src", LdStLoad, 548 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 549def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 550 "lhzx $rD, $src", LdStLoad, 551 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 552def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 553 "lwzx $rD, $src", LdStLoad, 554 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 555 556 557// Update forms. 558let mayLoad = 1 in { 559def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 560 "lbzu $rD, $addr", LdStLoad, 561 []>, RegConstraint<"$addr.reg = $ea_result">, 562 NoEncode<"$ea_result">; 563def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 564 "lhzu $rD, $addr", LdStLoad, 565 []>, RegConstraint<"$addr.reg = $ea_result">, 566 NoEncode<"$ea_result">; 567def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 568 "lwzu $rD, $addr", LdStLoad, 569 []>, RegConstraint<"$addr.reg = $ea_result">, 570 NoEncode<"$ea_result">; 571} 572} 573 574 575// Full 8-byte loads. 576let canFoldAsLoad = 1, PPC970_Unit = 2 in { 577def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 578 "ld $rD, $src", LdStLD, 579 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 580def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 581 "", 582 [(set G8RC:$rD, 583 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 584 585let hasSideEffects = 1 in { 586let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 587def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg), 588 "ld 2, 8($reg)", LdStLD, 589 [(PPCload_toc G8RC:$reg)]>, isPPC64; 590 591let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 592def LDtoc_restore : DSForm_1<58, 0, (outs), (ins), 593 "ld 2, 40(1)", LdStLD, 594 [(PPCtoc_restore)]>, isPPC64; 595} 596def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 597 "ldx $rD, $src", LdStLD, 598 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 599 600let mayLoad = 1 in 601def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 602 "ldu $rD, $addr", LdStLD, 603 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 604 NoEncode<"$ea_result">; 605 606} 607 608def : Pat<(PPCload ixaddr:$src), 609 (LD ixaddr:$src)>; 610def : Pat<(PPCload xaddr:$src), 611 (LDX xaddr:$src)>; 612 613let PPC970_Unit = 2 in { 614// Truncating stores. 615def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 616 "stb $rS, $src", LdStStore, 617 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 618def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 619 "sth $rS, $src", LdStStore, 620 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 621def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 622 "stw $rS, $src", LdStStore, 623 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 624def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 625 "stbx $rS, $dst", LdStStore, 626 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 627 PPC970_DGroup_Cracked; 628def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 629 "sthx $rS, $dst", LdStStore, 630 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 631 PPC970_DGroup_Cracked; 632def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 633 "stwx $rS, $dst", LdStStore, 634 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 635 PPC970_DGroup_Cracked; 636// Normal 8-byte stores. 637def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 638 "std $rS, $dst", LdStSTD, 639 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 640def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 641 "stdx $rS, $dst", LdStSTD, 642 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 643 PPC970_DGroup_Cracked; 644} 645 646let PPC970_Unit = 2 in { 647 648def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 649 symbolLo:$ptroff, ptr_rc:$ptrreg), 650 "stbu $rS, $ptroff($ptrreg)", LdStStore, 651 [(set ptr_rc:$ea_res, 652 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 653 iaddroff:$ptroff))]>, 654 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 655def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 656 symbolLo:$ptroff, ptr_rc:$ptrreg), 657 "sthu $rS, $ptroff($ptrreg)", LdStStore, 658 [(set ptr_rc:$ea_res, 659 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 660 iaddroff:$ptroff))]>, 661 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 662 663def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 664 s16immX4:$ptroff, ptr_rc:$ptrreg), 665 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 666 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 667 iaddroff:$ptroff))]>, 668 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 669 isPPC64; 670 671let mayStore = 1 in 672def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), 673 "stdux $rS, $dst", LdStSTD, 674 []>, isPPC64; 675 676// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 677def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 678 "std $rT, $dst", LdStSTD, 679 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 680def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 681 "stdx $rT, $dst", LdStSTD, 682 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 683 PPC970_DGroup_Cracked; 684} 685 686 687 688//===----------------------------------------------------------------------===// 689// Floating point instructions. 690// 691 692 693let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 694def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 695 "fcfid $frD, $frB", FPGeneral, 696 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 697def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 698 "fctidz $frD, $frB", FPGeneral, 699 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 700} 701 702 703//===----------------------------------------------------------------------===// 704// Instruction Patterns 705// 706 707// Extensions and truncates to/from 32-bit regs. 708def : Pat<(i64 (zext GPRC:$in)), 709 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 710def : Pat<(i64 (anyext GPRC:$in)), 711 (OR4To8 GPRC:$in, GPRC:$in)>; 712def : Pat<(i32 (trunc G8RC:$in)), 713 (OR8To4 G8RC:$in, G8RC:$in)>; 714 715// Extending loads with i64 targets. 716def : Pat<(zextloadi1 iaddr:$src), 717 (LBZ8 iaddr:$src)>; 718def : Pat<(zextloadi1 xaddr:$src), 719 (LBZX8 xaddr:$src)>; 720def : Pat<(extloadi1 iaddr:$src), 721 (LBZ8 iaddr:$src)>; 722def : Pat<(extloadi1 xaddr:$src), 723 (LBZX8 xaddr:$src)>; 724def : Pat<(extloadi8 iaddr:$src), 725 (LBZ8 iaddr:$src)>; 726def : Pat<(extloadi8 xaddr:$src), 727 (LBZX8 xaddr:$src)>; 728def : Pat<(extloadi16 iaddr:$src), 729 (LHZ8 iaddr:$src)>; 730def : Pat<(extloadi16 xaddr:$src), 731 (LHZX8 xaddr:$src)>; 732def : Pat<(extloadi32 iaddr:$src), 733 (LWZ8 iaddr:$src)>; 734def : Pat<(extloadi32 xaddr:$src), 735 (LWZX8 xaddr:$src)>; 736 737// Standard shifts. These are represented separately from the real shifts above 738// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 739// amounts. 740def : Pat<(sra G8RC:$rS, GPRC:$rB), 741 (SRAD G8RC:$rS, GPRC:$rB)>; 742def : Pat<(srl G8RC:$rS, GPRC:$rB), 743 (SRD G8RC:$rS, GPRC:$rB)>; 744def : Pat<(shl G8RC:$rS, GPRC:$rB), 745 (SLD G8RC:$rS, GPRC:$rB)>; 746 747// SHL/SRL 748def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 749 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 750def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 751 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 752 753// ROTL 754def : Pat<(rotl G8RC:$in, GPRC:$sh), 755 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 756def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 757 (RLDICL G8RC:$in, imm:$imm, 0)>; 758 759// Hi and Lo for Darwin Global Addresses. 760def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 761def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 762def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 763def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 764def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 765def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 766def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 767def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 768def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 769 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 770def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 771 (ADDIS8 G8RC:$in, tconstpool:$g)>; 772def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 773 (ADDIS8 G8RC:$in, tjumptable:$g)>; 774def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 775 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 776