1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21} 22def u16imm64 : Operand<i64> { 23 let PrintMethod = "printU16ImmOperand"; 24 let ParserMatchClass = PPCU16ImmAsmOperand; 25} 26def symbolHi64 : Operand<i64> { 27 let PrintMethod = "printSymbolHi"; 28 let EncoderMethod = "getHA16Encoding"; 29 let ParserMatchClass = PPCS16ImmAsmOperand; 30} 31def symbolLo64 : Operand<i64> { 32 let PrintMethod = "printSymbolLo"; 33 let EncoderMethod = "getLO16Encoding"; 34 let ParserMatchClass = PPCS16ImmAsmOperand; 35} 36def tocentry : Operand<iPTR> { 37 let MIOperandInfo = (ops i64imm:$imm); 38} 39def tlsreg : Operand<i64> { 40 let EncoderMethod = "getTLSRegEncoding"; 41} 42def tlsgd : Operand<i64> {} 43 44//===----------------------------------------------------------------------===// 45// 64-bit transformation functions. 46// 47 48def SHL64 : SDNodeXForm<imm, [{ 49 // Transformation function: 63 - imm 50 return getI32Imm(63 - N->getZExtValue()); 51}]>; 52 53def SRL64 : SDNodeXForm<imm, [{ 54 // Transformation function: 64 - imm 55 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 56}]>; 57 58def HI32_48 : SDNodeXForm<imm, [{ 59 // Transformation function: shift the immediate value down into the low bits. 60 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 61}]>; 62 63def HI48_64 : SDNodeXForm<imm, [{ 64 // Transformation function: shift the immediate value down into the low bits. 65 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 66}]>; 67 68 69//===----------------------------------------------------------------------===// 70// Calls. 71// 72 73let Interpretation64Bit = 1 in { 74let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 75 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 76 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 77 Requires<[In64BitMode]>; 78 79 let isCodeGenOnly = 1 in 80 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 81 "b${cond:cc}ctr ${cond:reg}", BrB, []>, 82 Requires<[In64BitMode]>; 83 } 84} 85 86let Defs = [LR8] in 87 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 88 PPC970_Unit_BRU; 89 90let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 91 let Defs = [CTR8], Uses = [CTR8] in { 92 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 93 "bdz $dst">; 94 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 95 "bdnz $dst">; 96 } 97 98 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 99 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 100 "bdzlr", BrB, []>; 101 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 102 "bdnzlr", BrB, []>; 103 } 104} 105 106 107 108let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 109 // Convenient aliases for call instructions 110 let Uses = [RM] in { 111 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 112 "bl $func", BrB, []>; // See Pat patterns below. 113 114 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func), 115 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>; 116 } 117 let Uses = [RM], isCodeGenOnly = 1 in { 118 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 119 (outs), (ins calltarget:$func), 120 "bl $func\n\tnop", BrB, []>; 121 122 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24, 123 (outs), (ins calltarget:$func, tlsgd:$sym), 124 "bl $func($sym)\n\tnop", BrB, []>; 125 126 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24, 127 (outs), (ins calltarget:$func, tlsgd:$sym), 128 "bl $func($sym)\n\tnop", BrB, []>; 129 130 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 131 (outs), (ins aaddr:$func), 132 "bla $func\n\tnop", BrB, 133 [(PPCcall_nop (i64 imm:$func))]>; 134 } 135 let Uses = [CTR8, RM] in { 136 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 137 "bctrl", BrB, [(PPCbctrl)]>, 138 Requires<[In64BitMode]>; 139 140 let isCodeGenOnly = 1 in 141 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 142 "b${cond:cc}ctrl ${cond:reg}", BrB, []>, 143 Requires<[In64BitMode]>; 144 } 145} 146} // Interpretation64Bit 147 148// Calls 149def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 150 (BL8 tglobaladdr:$dst)>; 151def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 152 (BL8_NOP tglobaladdr:$dst)>; 153 154def : Pat<(PPCcall (i64 texternalsym:$dst)), 155 (BL8 texternalsym:$dst)>; 156def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 157 (BL8_NOP texternalsym:$dst)>; 158 159// Atomic operations 160let usesCustomInserter = 1 in { 161 let Defs = [CR0] in { 162 def ATOMIC_LOAD_ADD_I64 : Pseudo< 163 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 164 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 165 def ATOMIC_LOAD_SUB_I64 : Pseudo< 166 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 167 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 168 def ATOMIC_LOAD_OR_I64 : Pseudo< 169 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 170 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 171 def ATOMIC_LOAD_XOR_I64 : Pseudo< 172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 173 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 174 def ATOMIC_LOAD_AND_I64 : Pseudo< 175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 176 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 177 def ATOMIC_LOAD_NAND_I64 : Pseudo< 178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 179 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 180 181 def ATOMIC_CMP_SWAP_I64 : Pseudo< 182 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 183 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 184 185 def ATOMIC_SWAP_I64 : Pseudo< 186 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 187 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 188 } 189} 190 191// Instructions to support atomic operations 192def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 193 "ldarx $rD, $ptr", LdStLDARX, 194 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>; 195 196let Defs = [CR0] in 197def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 198 "stdcx. $rS, $dst", LdStSTDCX, 199 [(PPCstcx i64:$rS, xoaddr:$dst)]>, 200 isDOT; 201 202let Interpretation64Bit = 1 in { 203let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 204def TCRETURNdi8 :Pseudo< (outs), 205 (ins calltarget:$dst, i32imm:$offset), 206 "#TC_RETURNd8 $dst $offset", 207 []>; 208 209let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 210def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 211 "#TC_RETURNa8 $func $offset", 212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 213 214let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 215def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 216 "#TC_RETURNr8 $dst $offset", 217 []>; 218 219let isCodeGenOnly = 1 in { 220 221let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 222 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 223def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 224 Requires<[In64BitMode]>; 225 226 227let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 228 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 229def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 230 "b $dst", BrB, 231 []>; 232 233 234let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 235 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 236def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 237 "ba $dst", BrB, 238 []>; 239 240} 241} // Interpretation64Bit 242 243def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 244 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 245 246def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 247 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 248 249def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 250 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 251 252 253// 64-bit CR instructions 254let Interpretation64Bit = 1 in { 255let neverHasSideEffects = 1 in { 256def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS), 257 "mtcrf $FXM, $rS", BrMCRX>, 258 PPC970_MicroCode, PPC970_Unit_CRU; 259 260let isCodeGenOnly = 1 in 261def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 262 "#MFCR8pseud", SprMFCR>, 263 PPC970_MicroCode, PPC970_Unit_CRU; 264} // neverHasSideEffects = 1 265 266let neverHasSideEffects = 1 in 267def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 268 "mfcr $rT", SprMFCR>, 269 PPC970_MicroCode, PPC970_Unit_CRU; 270 271let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 272 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 273 "#EH_SJLJ_SETJMP64", 274 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 275 Requires<[In64BitMode]>; 276 let isTerminator = 1 in 277 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 278 "#EH_SJLJ_LONGJMP64", 279 [(PPCeh_sjlj_longjmp addr:$buf)]>, 280 Requires<[In64BitMode]>; 281} 282 283//===----------------------------------------------------------------------===// 284// 64-bit SPR manipulation instrs. 285 286let Uses = [CTR8] in { 287def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 288 "mfctr $rT", SprMFSPR>, 289 PPC970_DGroup_First, PPC970_Unit_FXU; 290} 291let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 292def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 293 "mtctr $rS", SprMTSPR>, 294 PPC970_DGroup_First, PPC970_Unit_FXU; 295} 296 297let Pattern = [(set i64:$rT, readcyclecounter)] in 298def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 299 "mfspr $rT, 268", SprMFTB>, 300 PPC970_DGroup_First, PPC970_Unit_FXU; 301// Note that encoding mftb using mfspr is now the preferred form, 302// and has been since at least ISA v2.03. The mftb instruction has 303// now been phased out. Using mfspr, however, is known not to work on 304// the POWER3. 305 306let Defs = [X1], Uses = [X1] in 307def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 308 [(set i64:$result, 309 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 310 311let Defs = [LR8] in { 312def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 313 "mtlr $rS", SprMTSPR>, 314 PPC970_DGroup_First, PPC970_Unit_FXU; 315} 316let Uses = [LR8] in { 317def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 318 "mflr $rT", SprMFSPR>, 319 PPC970_DGroup_First, PPC970_Unit_FXU; 320} 321} // Interpretation64Bit 322 323//===----------------------------------------------------------------------===// 324// Fixed point instructions. 325// 326 327let PPC970_Unit = 1 in { // FXU Operations. 328let Interpretation64Bit = 1 in { 329let neverHasSideEffects = 1 in { 330 331let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 332def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins symbolLo64:$imm), 333 "li $rD, $imm", IntSimple, 334 [(set i64:$rD, immSExt16:$imm)]>; 335def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins symbolHi64:$imm), 336 "lis $rD, $imm", IntSimple, 337 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 338} 339 340// Logical ops. 341defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 342 "nand", "$rA, $rS, $rB", IntSimple, 343 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 344defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 345 "and", "$rA, $rS, $rB", IntSimple, 346 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 347defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 348 "andc", "$rA, $rS, $rB", IntSimple, 349 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 350defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 351 "or", "$rA, $rS, $rB", IntSimple, 352 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 353defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 354 "nor", "$rA, $rS, $rB", IntSimple, 355 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 356defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 357 "orc", "$rA, $rS, $rB", IntSimple, 358 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 359defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 360 "eqv", "$rA, $rS, $rB", IntSimple, 361 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 362defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 363 "xor", "$rA, $rS, $rB", IntSimple, 364 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 365 366// Logical ops with immediate. 367let Defs = [CR0] in { 368def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 369 "andi. $dst, $src1, $src2", IntGeneral, 370 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 371 isDOT; 372def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 373 "andis. $dst, $src1, $src2", IntGeneral, 374 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 375 isDOT; 376} 377def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 378 "ori $dst, $src1, $src2", IntSimple, 379 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 380def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 381 "oris $dst, $src1, $src2", IntSimple, 382 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 383def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 384 "xori $dst, $src1, $src2", IntSimple, 385 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 386def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 387 "xoris $dst, $src1, $src2", IntSimple, 388 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 389 390defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 391 "add", "$rT, $rA, $rB", IntSimple, 392 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 393// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 394// initial-exec thread-local storage model. 395let isCodeGenOnly = 1 in 396def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 397 "add $rT, $rA, $rB@tls", IntSimple, 398 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 399 400defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 401 "addc", "$rT, $rA, $rB", IntGeneral, 402 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 403 PPC970_DGroup_Cracked; 404let Defs = [CARRY] in 405def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 406 "addic $rD, $rA, $imm", IntGeneral, 407 [(set i64:$rD, (addc i64:$rA, immSExt16:$imm))]>; 408def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, symbolLo64:$imm), 409 "addi $rD, $rA, $imm", IntSimple, 410 [(set i64:$rD, (add i64:$rA, immSExt16:$imm))]>; 411def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, symbolHi64:$imm), 412 "addis $rD, $rA, $imm", IntSimple, 413 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 414 415let Defs = [CARRY] in { 416def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 417 "subfic $rD, $rA, $imm", IntGeneral, 418 [(set i64:$rD, (subc immSExt16:$imm, i64:$rA))]>; 419defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 420 "subfc", "$rT, $rA, $rB", IntGeneral, 421 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 422 PPC970_DGroup_Cracked; 423} 424defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 425 "subf", "$rT, $rA, $rB", IntGeneral, 426 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 427defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 428 "neg", "$rT, $rA", IntSimple, 429 [(set i64:$rT, (ineg i64:$rA))]>; 430let Uses = [CARRY] in { 431defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 432 "adde", "$rT, $rA, $rB", IntGeneral, 433 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 434defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 435 "addme", "$rT, $rA", IntGeneral, 436 [(set i64:$rT, (adde i64:$rA, -1))]>; 437defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 438 "addze", "$rT, $rA", IntGeneral, 439 [(set i64:$rT, (adde i64:$rA, 0))]>; 440defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 441 "subfe", "$rT, $rA, $rB", IntGeneral, 442 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 443defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 444 "subfme", "$rT, $rA", IntGeneral, 445 [(set i64:$rT, (sube -1, i64:$rA))]>; 446defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 447 "subfze", "$rT, $rA", IntGeneral, 448 [(set i64:$rT, (sube 0, i64:$rA))]>; 449} 450 451 452defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 453 "mulhd", "$rT, $rA, $rB", IntMulHW, 454 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 455defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 456 "mulhdu", "$rT, $rA, $rB", IntMulHWU, 457 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 458} 459} // Interpretation64Bit 460 461let isCompare = 1, neverHasSideEffects = 1 in { 462 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 463 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 464 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 465 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 466 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm), 467 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 468 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2), 469 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 470} 471 472let neverHasSideEffects = 1 in { 473defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 474 "sld", "$rA, $rS, $rB", IntRotateD, 475 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 476defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 477 "srd", "$rA, $rS, $rB", IntRotateD, 478 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 479defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 480 "srad", "$rA, $rS, $rB", IntRotateD, 481 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 482 483let Interpretation64Bit = 1 in { 484defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 485 "extsb", "$rA, $rS", IntSimple, 486 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 487defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 488 "extsh", "$rA, $rS", IntSimple, 489 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 490} // Interpretation64Bit 491 492defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 493 "extsw", "$rA, $rS", IntSimple, 494 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 495let Interpretation64Bit = 1 in 496defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 497 "extsw", "$rA, $rS", IntSimple, 498 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 499 500defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 501 "sradi", "$rA, $rS, $SH", IntRotateDI, 502 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 503defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 504 "cntlzd", "$rA, $rS", IntGeneral, 505 [(set i64:$rA, (ctlz i64:$rS))]>; 506defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 507 "popcntd", "$rA, $rS", IntGeneral, 508 [(set i64:$rA, (ctpop i64:$rS))]>; 509 510// popcntw also does a population count on the high 32 bits (storing the 511// results in the high 32-bits of the output). We'll ignore that here (which is 512// safe because we never separately use the high part of the 64-bit registers). 513defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS), 514 "popcntw", "$rA, $rS", IntGeneral, 515 [(set i32:$rA, (ctpop i32:$rS))]>; 516 517defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 518 "divd", "$rT, $rA, $rB", IntDivD, 519 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, 520 PPC970_DGroup_First, PPC970_DGroup_Cracked; 521defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 522 "divdu", "$rT, $rA, $rB", IntDivD, 523 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, 524 PPC970_DGroup_First, PPC970_DGroup_Cracked; 525defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 526 "mulld", "$rT, $rA, $rB", IntMulHD, 527 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 528} 529 530let neverHasSideEffects = 1 in { 531let isCommutable = 1 in { 532defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 533 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 534 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI, 535 []>, isPPC64, RegConstraint<"$rSi = $rA">, 536 NoEncode<"$rSi">; 537} 538 539// Rotate instructions. 540defm RLDCL : MDSForm_1r<30, 8, 541 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 542 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD, 543 []>, isPPC64; 544defm RLDICL : MDForm_1r<30, 0, 545 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 546 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI, 547 []>, isPPC64; 548defm RLDICR : MDForm_1r<30, 1, 549 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 550 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI, 551 []>, isPPC64; 552 553let Interpretation64Bit = 1 in { 554defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 555 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 556 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral, 557 []>; 558 559let isSelect = 1 in 560def ISEL8 : AForm_4<31, 15, 561 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 562 "isel $rT, $rA, $rB, $cond", IntGeneral, 563 []>; 564} // Interpretation64Bit 565} // neverHasSideEffects = 1 566} // End FXU Operations. 567 568 569//===----------------------------------------------------------------------===// 570// Load/Store instructions. 571// 572 573 574// Sign extending loads. 575let canFoldAsLoad = 1, PPC970_Unit = 2 in { 576let Interpretation64Bit = 1 in 577def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 578 "lha $rD, $src", LdStLHA, 579 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 580 PPC970_DGroup_Cracked; 581def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 582 "lwa $rD, $src", LdStLWA, 583 [(set i64:$rD, 584 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 585 PPC970_DGroup_Cracked; 586let Interpretation64Bit = 1 in 587def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 588 "lhax $rD, $src", LdStLHA, 589 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 590 PPC970_DGroup_Cracked; 591def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 592 "lwax $rD, $src", LdStLHA, 593 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 594 PPC970_DGroup_Cracked; 595 596// Update forms. 597let mayLoad = 1, neverHasSideEffects = 1 in { 598let Interpretation64Bit = 1 in 599def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 600 (ins memri:$addr), 601 "lhau $rD, $addr", LdStLHAU, 602 []>, RegConstraint<"$addr.reg = $ea_result">, 603 NoEncode<"$ea_result">; 604// NO LWAU! 605 606let Interpretation64Bit = 1 in 607def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 608 (ins memrr:$addr), 609 "lhaux $rD, $addr", LdStLHAU, 610 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 611 NoEncode<"$ea_result">; 612def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 613 (ins memrr:$addr), 614 "lwaux $rD, $addr", LdStLHAU, 615 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 616 NoEncode<"$ea_result">, isPPC64; 617} 618} 619 620let Interpretation64Bit = 1 in { 621// Zero extending loads. 622let canFoldAsLoad = 1, PPC970_Unit = 2 in { 623def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 624 "lbz $rD, $src", LdStLoad, 625 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 626def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 627 "lhz $rD, $src", LdStLoad, 628 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 629def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 630 "lwz $rD, $src", LdStLoad, 631 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 632 633def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 634 "lbzx $rD, $src", LdStLoad, 635 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 636def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 637 "lhzx $rD, $src", LdStLoad, 638 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 639def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 640 "lwzx $rD, $src", LdStLoad, 641 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 642 643 644// Update forms. 645let mayLoad = 1, neverHasSideEffects = 1 in { 646def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 647 "lbzu $rD, $addr", LdStLoadUpd, 648 []>, RegConstraint<"$addr.reg = $ea_result">, 649 NoEncode<"$ea_result">; 650def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 651 "lhzu $rD, $addr", LdStLoadUpd, 652 []>, RegConstraint<"$addr.reg = $ea_result">, 653 NoEncode<"$ea_result">; 654def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 655 "lwzu $rD, $addr", LdStLoadUpd, 656 []>, RegConstraint<"$addr.reg = $ea_result">, 657 NoEncode<"$ea_result">; 658 659def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 660 (ins memrr:$addr), 661 "lbzux $rD, $addr", LdStLoadUpd, 662 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 663 NoEncode<"$ea_result">; 664def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 665 (ins memrr:$addr), 666 "lhzux $rD, $addr", LdStLoadUpd, 667 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 668 NoEncode<"$ea_result">; 669def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 670 (ins memrr:$addr), 671 "lwzux $rD, $addr", LdStLoadUpd, 672 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 673 NoEncode<"$ea_result">; 674} 675} 676} // Interpretation64Bit 677 678 679// Full 8-byte loads. 680let canFoldAsLoad = 1, PPC970_Unit = 2 in { 681def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 682 "ld $rD, $src", LdStLD, 683 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 684// The following three definitions are selected for small code model only. 685// Otherwise, we need to create two instructions to form a 32-bit offset, 686// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 687def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 688 "#LDtoc", 689 [(set i64:$rD, 690 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 691def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 692 "#LDtocJTI", 693 [(set i64:$rD, 694 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 695def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 696 "#LDtocCPT", 697 [(set i64:$rD, 698 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 699 700let hasSideEffects = 1, isCodeGenOnly = 1 in { 701let RST = 2, DS = 2 in 702def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), 703 "ld 2, 8($reg)", LdStLD, 704 [(PPCload_toc i64:$reg)]>, isPPC64; 705 706let RST = 2, DS = 10, RA = 1 in 707def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 708 "ld 2, 40(1)", LdStLD, 709 [(PPCtoc_restore)]>, isPPC64; 710} 711def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 712 "ldx $rD, $src", LdStLD, 713 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 714def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 715 "ldbrx $rD, $src", LdStLoad, 716 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 717 718let mayLoad = 1, neverHasSideEffects = 1 in { 719def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 720 "ldu $rD, $addr", LdStLDU, 721 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 722 NoEncode<"$ea_result">; 723 724def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 725 (ins memrr:$addr), 726 "ldux $rD, $addr", LdStLDU, 727 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 728 NoEncode<"$ea_result">, isPPC64; 729} 730} 731 732def : Pat<(PPCload ixaddr:$src), 733 (LD ixaddr:$src)>; 734def : Pat<(PPCload xaddr:$src), 735 (LDX xaddr:$src)>; 736 737// Support for medium and large code model. 738def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 739 "#ADDIStocHA", 740 [(set i64:$rD, 741 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, 742 isPPC64; 743def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 744 "#LDtocL", 745 [(set i64:$rD, 746 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; 747def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 748 "#ADDItocL", 749 [(set i64:$rD, 750 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; 751 752// Support for thread-local storage. 753def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp), 754 "#ADDISgotTprelHA", 755 [(set i64:$rD, 756 (PPCaddisGotTprelHA i64:$reg, 757 tglobaltlsaddr:$disp))]>, 758 isPPC64; 759def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins symbolLo64:$disp, g8rc_nox0:$reg), 760 "#LDgotTprelL", 761 [(set i64:$rD, 762 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 763 isPPC64; 764def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 765 (ADD8TLS $in, tglobaltlsaddr:$g)>; 766def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp), 767 "#ADDIStlsgdHA", 768 [(set i64:$rD, 769 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 770 isPPC64; 771def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp), 772 "#ADDItlsgdL", 773 [(set i64:$rD, 774 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 775 isPPC64; 776def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 777 "#GETtlsADDR", 778 [(set i64:$rD, 779 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 780 isPPC64; 781def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp), 782 "#ADDIStlsldHA", 783 [(set i64:$rD, 784 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 785 isPPC64; 786def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp), 787 "#ADDItlsldL", 788 [(set i64:$rD, 789 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 790 isPPC64; 791def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 792 "#GETtlsldADDR", 793 [(set i64:$rD, 794 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 795 isPPC64; 796def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp), 797 "#ADDISdtprelHA", 798 [(set i64:$rD, 799 (PPCaddisDtprelHA i64:$reg, 800 tglobaltlsaddr:$disp))]>, 801 isPPC64; 802def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp), 803 "#ADDIdtprelL", 804 [(set i64:$rD, 805 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 806 isPPC64; 807 808let PPC970_Unit = 2 in { 809let Interpretation64Bit = 1 in { 810// Truncating stores. 811def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 812 "stb $rS, $src", LdStStore, 813 [(truncstorei8 i64:$rS, iaddr:$src)]>; 814def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 815 "sth $rS, $src", LdStStore, 816 [(truncstorei16 i64:$rS, iaddr:$src)]>; 817def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 818 "stw $rS, $src", LdStStore, 819 [(truncstorei32 i64:$rS, iaddr:$src)]>; 820def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 821 "stbx $rS, $dst", LdStStore, 822 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 823 PPC970_DGroup_Cracked; 824def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 825 "sthx $rS, $dst", LdStStore, 826 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 827 PPC970_DGroup_Cracked; 828def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 829 "stwx $rS, $dst", LdStStore, 830 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 831 PPC970_DGroup_Cracked; 832} // Interpretation64Bit 833 834// Normal 8-byte stores. 835def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 836 "std $rS, $dst", LdStSTD, 837 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 838def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 839 "stdx $rS, $dst", LdStSTD, 840 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 841 PPC970_DGroup_Cracked; 842def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 843 "stdbrx $rS, $dst", LdStStore, 844 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 845 PPC970_DGroup_Cracked; 846} 847 848// Stores with Update (pre-inc). 849let PPC970_Unit = 2, mayStore = 1 in { 850let Interpretation64Bit = 1 in { 851def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 852 "stbu $rS, $dst", LdStStoreUpd, []>, 853 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 854def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 855 "sthu $rS, $dst", LdStStoreUpd, []>, 856 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 857def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 858 "stwu $rS, $dst", LdStStoreUpd, []>, 859 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 860def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 861 "stdu $rS, $dst", LdStSTDU, []>, 862 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 863 isPPC64; 864 865def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 866 "stbux $rS, $dst", LdStStoreUpd, []>, 867 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 868 PPC970_DGroup_Cracked; 869def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 870 "sthux $rS, $dst", LdStStoreUpd, []>, 871 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 872 PPC970_DGroup_Cracked; 873def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 874 "stwux $rS, $dst", LdStStoreUpd, []>, 875 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 876 PPC970_DGroup_Cracked; 877} // Interpretation64Bit 878 879def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 880 "stdux $rS, $dst", LdStSTDU, []>, 881 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 882 PPC970_DGroup_Cracked, isPPC64; 883} 884 885// Patterns to match the pre-inc stores. We can't put the patterns on 886// the instruction definitions directly as ISel wants the address base 887// and offset to be separate operands, not a single complex operand. 888def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 889 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 890def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 891 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 892def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 893 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 894def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 895 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 896 897def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 898 (STBUX8 $rS, $ptrreg, $ptroff)>; 899def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 900 (STHUX8 $rS, $ptrreg, $ptroff)>; 901def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 902 (STWUX8 $rS, $ptrreg, $ptroff)>; 903def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 904 (STDUX $rS, $ptrreg, $ptroff)>; 905 906 907//===----------------------------------------------------------------------===// 908// Floating point instructions. 909// 910 911 912let PPC970_Unit = 3, neverHasSideEffects = 1, 913 Uses = [RM] in { // FPU Operations. 914defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 915 "fcfid", "$frD, $frB", FPGeneral, 916 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 917defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 918 "fctidz", "$frD, $frB", FPGeneral, 919 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 920 921defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 922 "fcfidu", "$frD, $frB", FPGeneral, 923 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 924defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 925 "fcfids", "$frD, $frB", FPGeneral, 926 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 927defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 928 "fcfidus", "$frD, $frB", FPGeneral, 929 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 930defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 931 "fctiduz", "$frD, $frB", FPGeneral, 932 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 933defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 934 "fctiwuz", "$frD, $frB", FPGeneral, 935 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 936} 937 938 939//===----------------------------------------------------------------------===// 940// Instruction Patterns 941// 942 943// Extensions and truncates to/from 32-bit regs. 944def : Pat<(i64 (zext i32:$in)), 945 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 946 0, 32)>; 947def : Pat<(i64 (anyext i32:$in)), 948 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 949def : Pat<(i32 (trunc i64:$in)), 950 (EXTRACT_SUBREG $in, sub_32)>; 951 952// Extending loads with i64 targets. 953def : Pat<(zextloadi1 iaddr:$src), 954 (LBZ8 iaddr:$src)>; 955def : Pat<(zextloadi1 xaddr:$src), 956 (LBZX8 xaddr:$src)>; 957def : Pat<(extloadi1 iaddr:$src), 958 (LBZ8 iaddr:$src)>; 959def : Pat<(extloadi1 xaddr:$src), 960 (LBZX8 xaddr:$src)>; 961def : Pat<(extloadi8 iaddr:$src), 962 (LBZ8 iaddr:$src)>; 963def : Pat<(extloadi8 xaddr:$src), 964 (LBZX8 xaddr:$src)>; 965def : Pat<(extloadi16 iaddr:$src), 966 (LHZ8 iaddr:$src)>; 967def : Pat<(extloadi16 xaddr:$src), 968 (LHZX8 xaddr:$src)>; 969def : Pat<(extloadi32 iaddr:$src), 970 (LWZ8 iaddr:$src)>; 971def : Pat<(extloadi32 xaddr:$src), 972 (LWZX8 xaddr:$src)>; 973 974// Standard shifts. These are represented separately from the real shifts above 975// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 976// amounts. 977def : Pat<(sra i64:$rS, i32:$rB), 978 (SRAD $rS, $rB)>; 979def : Pat<(srl i64:$rS, i32:$rB), 980 (SRD $rS, $rB)>; 981def : Pat<(shl i64:$rS, i32:$rB), 982 (SLD $rS, $rB)>; 983 984// SHL/SRL 985def : Pat<(shl i64:$in, (i32 imm:$imm)), 986 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 987def : Pat<(srl i64:$in, (i32 imm:$imm)), 988 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 989 990// ROTL 991def : Pat<(rotl i64:$in, i32:$sh), 992 (RLDCL $in, $sh, 0)>; 993def : Pat<(rotl i64:$in, (i32 imm:$imm)), 994 (RLDICL $in, imm:$imm, 0)>; 995 996// Hi and Lo for Darwin Global Addresses. 997def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 998def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 999def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1000def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1001def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1002def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1003def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1004def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1005def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1006 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1007def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1008 (ADDI8 $in, tglobaltlsaddr:$g)>; 1009def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1010 (ADDIS8 $in, tglobaladdr:$g)>; 1011def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1012 (ADDIS8 $in, tconstpool:$g)>; 1013def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1014 (ADDIS8 $in, tjumptable:$g)>; 1015def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1016 (ADDIS8 $in, tblockaddress:$g)>; 1017 1018// Patterns to match r+r indexed loads and stores for 1019// addresses without at least 4-byte alignment. 1020def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1021 (LWAX xoaddr:$src)>; 1022def : Pat<(i64 (unaligned4load xoaddr:$src)), 1023 (LDX xoaddr:$src)>; 1024def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1025 (STDX $rS, xoaddr:$dst)>; 1026 1027