PPCInstr64Bit.td revision 195340
1//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26} 27def symbolLo64 : Operand<i64> { 28 let PrintMethod = "printSymbolLo"; 29} 30 31//===----------------------------------------------------------------------===// 32// 64-bit transformation functions. 33// 34 35def SHL64 : SDNodeXForm<imm, [{ 36 // Transformation function: 63 - imm 37 return getI32Imm(63 - N->getZExtValue()); 38}]>; 39 40def SRL64 : SDNodeXForm<imm, [{ 41 // Transformation function: 64 - imm 42 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 43}]>; 44 45def HI32_48 : SDNodeXForm<imm, [{ 46 // Transformation function: shift the immediate value down into the low bits. 47 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 48}]>; 49 50def HI48_64 : SDNodeXForm<imm, [{ 51 // Transformation function: shift the immediate value down into the low bits. 52 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 53}]>; 54 55 56//===----------------------------------------------------------------------===// 57// Calls. 58// 59 60let Defs = [LR8] in 61 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, 62 PPC970_Unit_BRU; 63 64// Darwin ABI Calls. 65let isCall = 1, PPC970_Unit = 7, 66 // All calls clobber the PPC64 non-callee saved registers. 67 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 68 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 69 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 70 LR8,CTR8, 71 CR0,CR1,CR5,CR6,CR7] in { 72 // Convenient aliases for call instructions 73 let Uses = [RM] in { 74 def BL8_Darwin : IForm<18, 0, 1, 75 (outs), (ins calltarget:$func, variable_ops), 76 "bl $func", BrB, []>; // See Pat patterns below. 77 def BLA8_Darwin : IForm<18, 1, 1, 78 (outs), (ins aaddr:$func, variable_ops), 79 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 80 } 81 let Uses = [CTR8, RM] in { 82 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 83 (outs), (ins variable_ops), 84 "bctrl", BrB, 85 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 86 } 87} 88 89// ELF 64 ABI Calls = Darwin ABI Calls 90// Used to define BL8_ELF and BLA8_ELF 91let isCall = 1, PPC970_Unit = 7, 92 // All calls clobber the PPC64 non-callee saved registers. 93 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 94 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 95 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 96 LR8,CTR8, 97 CR0,CR1,CR5,CR6,CR7] in { 98 // Convenient aliases for call instructions 99 let Uses = [RM] in { 100 def BL8_ELF : IForm<18, 0, 1, 101 (outs), (ins calltarget:$func, variable_ops), 102 "bl $func", BrB, []>; // See Pat patterns below. 103 def BLA8_ELF : IForm<18, 1, 1, 104 (outs), (ins aaddr:$func, variable_ops), 105 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 106 } 107 let Uses = [CTR8, RM] in { 108 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 109 (outs), (ins variable_ops), 110 "bctrl", BrB, 111 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 112 } 113} 114 115 116// Calls 117def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 118 (BL8_Darwin tglobaladdr:$dst)>; 119def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 120 (BL8_Darwin texternalsym:$dst)>; 121 122def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 123 (BL8_ELF tglobaladdr:$dst)>; 124def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 125 (BL8_ELF texternalsym:$dst)>; 126 127// Atomic operations 128let usesCustomDAGSchedInserter = 1 in { 129 let Uses = [CR0] in { 130 def ATOMIC_LOAD_ADD_I64 : Pseudo< 131 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 132 "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!", 133 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 134 def ATOMIC_LOAD_SUB_I64 : Pseudo< 135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 136 "${:comment} ATOMIC_LOAD_SUB_I64 PSEUDO!", 137 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 138 def ATOMIC_LOAD_OR_I64 : Pseudo< 139 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 140 "${:comment} ATOMIC_LOAD_OR_I64 PSEUDO!", 141 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 142 def ATOMIC_LOAD_XOR_I64 : Pseudo< 143 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 144 "${:comment} ATOMIC_LOAD_XOR_I64 PSEUDO!", 145 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 146 def ATOMIC_LOAD_AND_I64 : Pseudo< 147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 148 "${:comment} ATOMIC_LOAD_AND_I64 PSEUDO!", 149 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 150 def ATOMIC_LOAD_NAND_I64 : Pseudo< 151 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), 152 "${:comment} ATOMIC_LOAD_NAND_I64 PSEUDO!", 153 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 154 155 def ATOMIC_CMP_SWAP_I64 : Pseudo< 156 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), 157 "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!", 158 [(set G8RC:$dst, 159 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 160 161 def ATOMIC_SWAP_I64 : Pseudo< 162 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), 163 "${:comment} ATOMIC_SWAP_I64 PSEUDO!", 164 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 165 } 166} 167 168// Instructions to support atomic operations 169def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 170 "ldarx $rD, $ptr", LdStLDARX, 171 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 172 173let Defs = [CR0] in 174def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 175 "stdcx. $rS, $dst", LdStSTDCX, 176 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 177 isDOT; 178 179let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 180def TCRETURNdi8 :Pseudo< (outs), 181 (ins calltarget:$dst, i32imm:$offset, variable_ops), 182 "#TC_RETURNd8 $dst $offset", 183 []>; 184 185let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 186def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 187 "#TC_RETURNa8 $func $offset", 188 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 189 190let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 191def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), 192 "#TC_RETURNr8 $dst $offset", 193 []>; 194 195 196let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 197 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 198def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 199 Requires<[In64BitMode]>; 200 201 202 203let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 204 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 205def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 206 "b $dst", BrB, 207 []>; 208 209 210let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 211 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 212def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 213 "ba $dst", BrB, 214 []>; 215 216def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 217 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 218 219def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 220 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 221 222def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 223 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 224 225 226//===----------------------------------------------------------------------===// 227// 64-bit SPR manipulation instrs. 228 229let Uses = [CTR8] in { 230def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 231 "mfctr $rT", SprMFSPR>, 232 PPC970_DGroup_First, PPC970_Unit_FXU; 233} 234let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 235def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 236 "mtctr $rS", SprMTSPR>, 237 PPC970_DGroup_First, PPC970_Unit_FXU; 238} 239 240let Defs = [X1], Uses = [X1] in 241def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi), 242 "${:comment} DYNALLOC8 $result, $negsize, $fpsi", 243 [(set G8RC:$result, 244 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 245 246let Defs = [LR8] in { 247def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 248 "mtlr $rS", SprMTSPR>, 249 PPC970_DGroup_First, PPC970_Unit_FXU; 250} 251let Uses = [LR8] in { 252def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 253 "mflr $rT", SprMFSPR>, 254 PPC970_DGroup_First, PPC970_Unit_FXU; 255} 256 257//===----------------------------------------------------------------------===// 258// Fixed point instructions. 259// 260 261let PPC970_Unit = 1 in { // FXU Operations. 262 263// Copies, extends, truncates. 264def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), 265 "or $rA, $rS, $rB", IntGeneral, 266 []>; 267def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), 268 "or $rA, $rS, $rB", IntGeneral, 269 []>; 270 271def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 272 "li $rD, $imm", IntGeneral, 273 [(set G8RC:$rD, immSExt16:$imm)]>; 274def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 275 "lis $rD, $imm", IntGeneral, 276 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 277 278// Logical ops. 279def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 280 "nand $rA, $rS, $rB", IntGeneral, 281 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 282def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 283 "and $rA, $rS, $rB", IntGeneral, 284 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 285def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 286 "andc $rA, $rS, $rB", IntGeneral, 287 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 288def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 289 "or $rA, $rS, $rB", IntGeneral, 290 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 291def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 292 "nor $rA, $rS, $rB", IntGeneral, 293 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 294def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 295 "orc $rA, $rS, $rB", IntGeneral, 296 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 297def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 298 "eqv $rA, $rS, $rB", IntGeneral, 299 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 300def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 301 "xor $rA, $rS, $rB", IntGeneral, 302 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 303 304// Logical ops with immediate. 305def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 306 "andi. $dst, $src1, $src2", IntGeneral, 307 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 308 isDOT; 309def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 310 "andis. $dst, $src1, $src2", IntGeneral, 311 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 312 isDOT; 313def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 314 "ori $dst, $src1, $src2", IntGeneral, 315 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 316def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 317 "oris $dst, $src1, $src2", IntGeneral, 318 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 319def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 320 "xori $dst, $src1, $src2", IntGeneral, 321 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 322def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 323 "xoris $dst, $src1, $src2", IntGeneral, 324 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 325 326def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 327 "add $rT, $rA, $rB", IntGeneral, 328 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 329 330def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 331 "addc $rT, $rA, $rB", IntGeneral, 332 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 333 PPC970_DGroup_Cracked; 334def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 335 "adde $rT, $rA, $rB", IntGeneral, 336 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 337 338def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 339 "addi $rD, $rA, $imm", IntGeneral, 340 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 341def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 342 "addis $rD, $rA, $imm", IntGeneral, 343 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 344 345def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 346 "subfic $rD, $rA, $imm", IntGeneral, 347 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 348def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 349 "subf $rT, $rA, $rB", IntGeneral, 350 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 351def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 352 "subfc $rT, $rA, $rB", IntGeneral, 353 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 354 PPC970_DGroup_Cracked; 355 356def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 357 "subfe $rT, $rA, $rB", IntGeneral, 358 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 359def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 360 "addme $rT, $rA", IntGeneral, 361 [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>; 362def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 363 "addze $rT, $rA", IntGeneral, 364 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 365def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 366 "neg $rT, $rA", IntGeneral, 367 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 368def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 369 "subfme $rT, $rA", IntGeneral, 370 [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>; 371def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 372 "subfze $rT, $rA", IntGeneral, 373 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 374 375 376 377def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 378 "mulhd $rT, $rA, $rB", IntMulHW, 379 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 380def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 381 "mulhdu $rT, $rA, $rB", IntMulHWU, 382 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 383 384def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 385 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 386def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 387 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 388def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 389 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 390def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 391 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 392 393def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 394 "sld $rA, $rS, $rB", IntRotateD, 395 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 396def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 397 "srd $rA, $rS, $rB", IntRotateD, 398 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 399def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 400 "srad $rA, $rS, $rB", IntRotateD, 401 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 402 403def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 404 "extsb $rA, $rS", IntGeneral, 405 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 406def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 407 "extsh $rA, $rS", IntGeneral, 408 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 409 410def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 411 "extsw $rA, $rS", IntGeneral, 412 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 413/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 414def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 415 "extsw $rA, $rS", IntGeneral, 416 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 417def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 418 "extsw $rA, $rS", IntGeneral, 419 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 420 421def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 422 "sradi $rA, $rS, $SH", IntRotateD, 423 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 424def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 425 "cntlzd $rA, $rS", IntGeneral, 426 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 427 428def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 429 "divd $rT, $rA, $rB", IntDivD, 430 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 431 PPC970_DGroup_First, PPC970_DGroup_Cracked; 432def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 433 "divdu $rT, $rA, $rB", IntDivD, 434 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 435 PPC970_DGroup_First, PPC970_DGroup_Cracked; 436def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 437 "mulld $rT, $rA, $rB", IntMulHD, 438 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 439 440 441let isCommutable = 1 in { 442def RLDIMI : MDForm_1<30, 3, 443 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 444 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 445 []>, isPPC64, RegConstraint<"$rSi = $rA">, 446 NoEncode<"$rSi">; 447} 448 449// Rotate instructions. 450def RLDCL : MDForm_1<30, 0, 451 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 452 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 453 []>, isPPC64; 454def RLDICL : MDForm_1<30, 0, 455 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 456 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 457 []>, isPPC64; 458def RLDICR : MDForm_1<30, 1, 459 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 460 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 461 []>, isPPC64; 462} // End FXU Operations. 463 464 465//===----------------------------------------------------------------------===// 466// Load/Store instructions. 467// 468 469 470// Sign extending loads. 471let canFoldAsLoad = 1, PPC970_Unit = 2 in { 472def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 473 "lha $rD, $src", LdStLHA, 474 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 475 PPC970_DGroup_Cracked; 476def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 477 "lwa $rD, $src", LdStLWA, 478 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 479 PPC970_DGroup_Cracked; 480def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 481 "lhax $rD, $src", LdStLHA, 482 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 483 PPC970_DGroup_Cracked; 484def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 485 "lwax $rD, $src", LdStLHA, 486 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 487 PPC970_DGroup_Cracked; 488 489// Update forms. 490let mayLoad = 1 in 491def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 492 ptr_rc:$rA), 493 "lhau $rD, $disp($rA)", LdStGeneral, 494 []>, RegConstraint<"$rA = $ea_result">, 495 NoEncode<"$ea_result">; 496// NO LWAU! 497 498} 499 500// Zero extending loads. 501let canFoldAsLoad = 1, PPC970_Unit = 2 in { 502def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 503 "lbz $rD, $src", LdStGeneral, 504 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 505def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 506 "lhz $rD, $src", LdStGeneral, 507 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 508def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 509 "lwz $rD, $src", LdStGeneral, 510 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 511 512def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 513 "lbzx $rD, $src", LdStGeneral, 514 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 515def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 516 "lhzx $rD, $src", LdStGeneral, 517 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 518def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 519 "lwzx $rD, $src", LdStGeneral, 520 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 521 522 523// Update forms. 524let mayLoad = 1 in { 525def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 526 "lbzu $rD, $addr", LdStGeneral, 527 []>, RegConstraint<"$addr.reg = $ea_result">, 528 NoEncode<"$ea_result">; 529def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 530 "lhzu $rD, $addr", LdStGeneral, 531 []>, RegConstraint<"$addr.reg = $ea_result">, 532 NoEncode<"$ea_result">; 533def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 534 "lwzu $rD, $addr", LdStGeneral, 535 []>, RegConstraint<"$addr.reg = $ea_result">, 536 NoEncode<"$ea_result">; 537} 538} 539 540 541// Full 8-byte loads. 542let canFoldAsLoad = 1, PPC970_Unit = 2 in { 543def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 544 "ld $rD, $src", LdStLD, 545 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 546def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 547 "ldx $rD, $src", LdStLD, 548 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 549 550let mayLoad = 1 in 551def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 552 "ldu $rD, $addr", LdStLD, 553 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 554 NoEncode<"$ea_result">; 555 556} 557 558let PPC970_Unit = 2 in { 559// Truncating stores. 560def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 561 "stb $rS, $src", LdStGeneral, 562 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 563def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 564 "sth $rS, $src", LdStGeneral, 565 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 566def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 567 "stw $rS, $src", LdStGeneral, 568 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 569def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 570 "stbx $rS, $dst", LdStGeneral, 571 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 572 PPC970_DGroup_Cracked; 573def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 574 "sthx $rS, $dst", LdStGeneral, 575 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 576 PPC970_DGroup_Cracked; 577def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 578 "stwx $rS, $dst", LdStGeneral, 579 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 580 PPC970_DGroup_Cracked; 581// Normal 8-byte stores. 582def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 583 "std $rS, $dst", LdStSTD, 584 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 585def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 586 "stdx $rS, $dst", LdStSTD, 587 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 588 PPC970_DGroup_Cracked; 589} 590 591let PPC970_Unit = 2 in { 592 593def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 594 symbolLo:$ptroff, ptr_rc:$ptrreg), 595 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 596 [(set ptr_rc:$ea_res, 597 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 598 iaddroff:$ptroff))]>, 599 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 600def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 601 symbolLo:$ptroff, ptr_rc:$ptrreg), 602 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 603 [(set ptr_rc:$ea_res, 604 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 605 iaddroff:$ptroff))]>, 606 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 607def STWU8 : DForm_1<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 608 symbolLo:$ptroff, ptr_rc:$ptrreg), 609 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 610 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 611 iaddroff:$ptroff))]>, 612 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 613 614 615def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 616 s16immX4:$ptroff, ptr_rc:$ptrreg), 617 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 618 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 619 iaddroff:$ptroff))]>, 620 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 621 isPPC64; 622 623let mayStore = 1 in 624def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), 625 "stdux $rS, $dst", LdStSTD, 626 []>, isPPC64; 627 628// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 629def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 630 "std $rT, $dst", LdStSTD, 631 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 632def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 633 "stdx $rT, $dst", LdStSTD, 634 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 635 PPC970_DGroup_Cracked; 636} 637 638 639 640//===----------------------------------------------------------------------===// 641// Floating point instructions. 642// 643 644 645let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 646def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 647 "fcfid $frD, $frB", FPGeneral, 648 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 649def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 650 "fctidz $frD, $frB", FPGeneral, 651 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 652} 653 654 655//===----------------------------------------------------------------------===// 656// Instruction Patterns 657// 658 659// Extensions and truncates to/from 32-bit regs. 660def : Pat<(i64 (zext GPRC:$in)), 661 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 662def : Pat<(i64 (anyext GPRC:$in)), 663 (OR4To8 GPRC:$in, GPRC:$in)>; 664def : Pat<(i32 (trunc G8RC:$in)), 665 (OR8To4 G8RC:$in, G8RC:$in)>; 666 667// Extending loads with i64 targets. 668def : Pat<(zextloadi1 iaddr:$src), 669 (LBZ8 iaddr:$src)>; 670def : Pat<(zextloadi1 xaddr:$src), 671 (LBZX8 xaddr:$src)>; 672def : Pat<(extloadi1 iaddr:$src), 673 (LBZ8 iaddr:$src)>; 674def : Pat<(extloadi1 xaddr:$src), 675 (LBZX8 xaddr:$src)>; 676def : Pat<(extloadi8 iaddr:$src), 677 (LBZ8 iaddr:$src)>; 678def : Pat<(extloadi8 xaddr:$src), 679 (LBZX8 xaddr:$src)>; 680def : Pat<(extloadi16 iaddr:$src), 681 (LHZ8 iaddr:$src)>; 682def : Pat<(extloadi16 xaddr:$src), 683 (LHZX8 xaddr:$src)>; 684def : Pat<(extloadi32 iaddr:$src), 685 (LWZ8 iaddr:$src)>; 686def : Pat<(extloadi32 xaddr:$src), 687 (LWZX8 xaddr:$src)>; 688 689// Standard shifts. These are represented separately from the real shifts above 690// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 691// amounts. 692def : Pat<(sra G8RC:$rS, GPRC:$rB), 693 (SRAD G8RC:$rS, GPRC:$rB)>; 694def : Pat<(srl G8RC:$rS, GPRC:$rB), 695 (SRD G8RC:$rS, GPRC:$rB)>; 696def : Pat<(shl G8RC:$rS, GPRC:$rB), 697 (SLD G8RC:$rS, GPRC:$rB)>; 698 699// SHL/SRL 700def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 701 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 702def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 703 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 704 705// ROTL 706def : Pat<(rotl G8RC:$in, GPRC:$sh), 707 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 708def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 709 (RLDICL G8RC:$in, imm:$imm, 0)>; 710 711// Hi and Lo for Darwin Global Addresses. 712def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 713def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 714def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 715def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 716def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 717def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 718def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 719 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 720def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 721 (ADDIS8 G8RC:$in, tconstpool:$g)>; 722def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 723 (ADDIS8 G8RC:$in, tjumptable:$g)>; 724