1//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains small standalone helper functions and enum definitions for 11// the AArch64 target useful for the compiler back-end and the MC libraries. 12// As such, it deliberately does not include references to LLVM core 13// code gen types, passes, etc.. 14// 15//===----------------------------------------------------------------------===// 16 17#ifndef LLVM_AARCH64_BASEINFO_H 18#define LLVM_AARCH64_BASEINFO_H 19 20#include "llvm/ADT/StringSwitch.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/Support/ErrorHandling.h" 23 24namespace llvm { 25 26// // Enums corresponding to AArch64 condition codes 27namespace A64CC { 28 // The CondCodes constants map directly to the 4-bit encoding of the 29 // condition field for predicated instructions. 30 enum CondCodes { // Meaning (integer) Meaning (floating-point) 31 EQ = 0, // Equal Equal 32 NE, // Not equal Not equal, or unordered 33 HS, // Unsigned higher or same >, ==, or unordered 34 LO, // Unsigned lower or same Less than 35 MI, // Minus, negative Less than 36 PL, // Plus, positive or zero >, ==, or unordered 37 VS, // Overflow Unordered 38 VC, // No overflow Ordered 39 HI, // Unsigned higher Greater than, or unordered 40 LS, // Unsigned lower or same Less than or equal 41 GE, // Greater than or equal Greater than or equal 42 LT, // Less than Less than, or unordered 43 GT, // Signed greater than Greater than 44 LE, // Signed less than or equal <, ==, or unordered 45 AL, // Always (unconditional) Always (unconditional) 46 NV, // Always (unconditional) Always (unconditional) 47 // Note the NV exists purely to disassemble 0b1111. Execution 48 // is "always". 49 Invalid 50 }; 51 52} // namespace A64CC 53 54inline static const char *A64CondCodeToString(A64CC::CondCodes CC) { 55 switch (CC) { 56 default: llvm_unreachable("Unknown condition code"); 57 case A64CC::EQ: return "eq"; 58 case A64CC::NE: return "ne"; 59 case A64CC::HS: return "hs"; 60 case A64CC::LO: return "lo"; 61 case A64CC::MI: return "mi"; 62 case A64CC::PL: return "pl"; 63 case A64CC::VS: return "vs"; 64 case A64CC::VC: return "vc"; 65 case A64CC::HI: return "hi"; 66 case A64CC::LS: return "ls"; 67 case A64CC::GE: return "ge"; 68 case A64CC::LT: return "lt"; 69 case A64CC::GT: return "gt"; 70 case A64CC::LE: return "le"; 71 case A64CC::AL: return "al"; 72 case A64CC::NV: return "nv"; 73 } 74} 75 76inline static A64CC::CondCodes A64StringToCondCode(StringRef CondStr) { 77 return StringSwitch<A64CC::CondCodes>(CondStr.lower()) 78 .Case("eq", A64CC::EQ) 79 .Case("ne", A64CC::NE) 80 .Case("ne", A64CC::NE) 81 .Case("hs", A64CC::HS) 82 .Case("cs", A64CC::HS) 83 .Case("lo", A64CC::LO) 84 .Case("cc", A64CC::LO) 85 .Case("mi", A64CC::MI) 86 .Case("pl", A64CC::PL) 87 .Case("vs", A64CC::VS) 88 .Case("vc", A64CC::VC) 89 .Case("hi", A64CC::HI) 90 .Case("ls", A64CC::LS) 91 .Case("ge", A64CC::GE) 92 .Case("lt", A64CC::LT) 93 .Case("gt", A64CC::GT) 94 .Case("le", A64CC::LE) 95 .Case("al", A64CC::AL) 96 .Case("nv", A64CC::NV) 97 .Default(A64CC::Invalid); 98} 99 100inline static A64CC::CondCodes A64InvertCondCode(A64CC::CondCodes CC) { 101 // It turns out that the condition codes have been designed so that in order 102 // to reverse the intent of the condition you only have to invert the low bit: 103 104 return static_cast<A64CC::CondCodes>(static_cast<unsigned>(CC) ^ 0x1); 105} 106 107/// Instances of this class can perform bidirectional mapping from random 108/// identifier strings to operand encodings. For example "MSR" takes a named 109/// system-register which must be encoded somehow and decoded for printing. This 110/// central location means that the information for those transformations is not 111/// duplicated and remains in sync. 112/// 113/// FIXME: currently the algorithm is a completely unoptimised linear 114/// search. Obviously this could be improved, but we would probably want to work 115/// out just how often these instructions are emitted before working on it. It 116/// might even be optimal to just reorder the tables for the common instructions 117/// rather than changing the algorithm. 118struct NamedImmMapper { 119 struct Mapping { 120 const char *Name; 121 uint32_t Value; 122 }; 123 124 template<int N> 125 NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm) 126 : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {} 127 128 StringRef toString(uint32_t Value, bool &Valid) const; 129 uint32_t fromString(StringRef Name, bool &Valid) const; 130 131 /// Many of the instructions allow an alternative assembly form consisting of 132 /// a simple immediate. Currently the only valid forms are ranges [0, N) where 133 /// N being 0 indicates no immediate syntax-form is allowed. 134 bool validImm(uint32_t Value) const; 135protected: 136 const Mapping *Pairs; 137 size_t NumPairs; 138 uint32_t TooBigImm; 139}; 140 141namespace A64AT { 142 enum ATValues { 143 Invalid = -1, // Op0 Op1 CRn CRm Op2 144 S1E1R = 0x43c0, // 01 000 0111 1000 000 145 S1E2R = 0x63c0, // 01 100 0111 1000 000 146 S1E3R = 0x73c0, // 01 110 0111 1000 000 147 S1E1W = 0x43c1, // 01 000 0111 1000 001 148 S1E2W = 0x63c1, // 01 100 0111 1000 001 149 S1E3W = 0x73c1, // 01 110 0111 1000 001 150 S1E0R = 0x43c2, // 01 000 0111 1000 010 151 S1E0W = 0x43c3, // 01 000 0111 1000 011 152 S12E1R = 0x63c4, // 01 100 0111 1000 100 153 S12E1W = 0x63c5, // 01 100 0111 1000 101 154 S12E0R = 0x63c6, // 01 100 0111 1000 110 155 S12E0W = 0x63c7 // 01 100 0111 1000 111 156 }; 157 158 struct ATMapper : NamedImmMapper { 159 const static Mapping ATPairs[]; 160 161 ATMapper(); 162 }; 163 164} 165namespace A64DB { 166 enum DBValues { 167 Invalid = -1, 168 OSHLD = 0x1, 169 OSHST = 0x2, 170 OSH = 0x3, 171 NSHLD = 0x5, 172 NSHST = 0x6, 173 NSH = 0x7, 174 ISHLD = 0x9, 175 ISHST = 0xa, 176 ISH = 0xb, 177 LD = 0xd, 178 ST = 0xe, 179 SY = 0xf 180 }; 181 182 struct DBarrierMapper : NamedImmMapper { 183 const static Mapping DBarrierPairs[]; 184 185 DBarrierMapper(); 186 }; 187} 188 189namespace A64DC { 190 enum DCValues { 191 Invalid = -1, // Op1 CRn CRm Op2 192 ZVA = 0x5ba1, // 01 011 0111 0100 001 193 IVAC = 0x43b1, // 01 000 0111 0110 001 194 ISW = 0x43b2, // 01 000 0111 0110 010 195 CVAC = 0x5bd1, // 01 011 0111 1010 001 196 CSW = 0x43d2, // 01 000 0111 1010 010 197 CVAU = 0x5bd9, // 01 011 0111 1011 001 198 CIVAC = 0x5bf1, // 01 011 0111 1110 001 199 CISW = 0x43f2 // 01 000 0111 1110 010 200 }; 201 202 struct DCMapper : NamedImmMapper { 203 const static Mapping DCPairs[]; 204 205 DCMapper(); 206 }; 207 208} 209 210namespace A64IC { 211 enum ICValues { 212 Invalid = -1, // Op1 CRn CRm Op2 213 IALLUIS = 0x0388, // 000 0111 0001 000 214 IALLU = 0x03a8, // 000 0111 0101 000 215 IVAU = 0x1ba9 // 011 0111 0101 001 216 }; 217 218 219 struct ICMapper : NamedImmMapper { 220 const static Mapping ICPairs[]; 221 222 ICMapper(); 223 }; 224 225 static inline bool NeedsRegister(ICValues Val) { 226 return Val == IVAU; 227 } 228} 229 230namespace A64ISB { 231 enum ISBValues { 232 Invalid = -1, 233 SY = 0xf 234 }; 235 struct ISBMapper : NamedImmMapper { 236 const static Mapping ISBPairs[]; 237 238 ISBMapper(); 239 }; 240} 241 242namespace A64PRFM { 243 enum PRFMValues { 244 Invalid = -1, 245 PLDL1KEEP = 0x00, 246 PLDL1STRM = 0x01, 247 PLDL2KEEP = 0x02, 248 PLDL2STRM = 0x03, 249 PLDL3KEEP = 0x04, 250 PLDL3STRM = 0x05, 251 PLIL1KEEP = 0x08, 252 PLIL1STRM = 0x09, 253 PLIL2KEEP = 0x0a, 254 PLIL2STRM = 0x0b, 255 PLIL3KEEP = 0x0c, 256 PLIL3STRM = 0x0d, 257 PSTL1KEEP = 0x10, 258 PSTL1STRM = 0x11, 259 PSTL2KEEP = 0x12, 260 PSTL2STRM = 0x13, 261 PSTL3KEEP = 0x14, 262 PSTL3STRM = 0x15 263 }; 264 265 struct PRFMMapper : NamedImmMapper { 266 const static Mapping PRFMPairs[]; 267 268 PRFMMapper(); 269 }; 270} 271 272namespace A64PState { 273 enum PStateValues { 274 Invalid = -1, 275 SPSel = 0x05, 276 DAIFSet = 0x1e, 277 DAIFClr = 0x1f 278 }; 279 280 struct PStateMapper : NamedImmMapper { 281 const static Mapping PStatePairs[]; 282 283 PStateMapper(); 284 }; 285 286} 287 288namespace A64SE { 289 enum ShiftExtSpecifiers { 290 Invalid = -1, 291 LSL, 292 LSR, 293 ASR, 294 ROR, 295 296 UXTB, 297 UXTH, 298 UXTW, 299 UXTX, 300 301 SXTB, 302 SXTH, 303 SXTW, 304 SXTX 305 }; 306} 307 308namespace A64SysReg { 309 enum SysRegROValues { 310 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 311 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 312 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 313 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 314 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 315 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 316 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 317 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 318 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 319 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 320 CTR_EL0 = 0xd801, // 11 011 0000 0000 001 321 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 322 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 323 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 324 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 325 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 326 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 327 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 328 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 329 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 330 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 331 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 332 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 333 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 334 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 335 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 336 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 337 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 338 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 339 ID_AA64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 340 ID_AA64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 341 ID_AA64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 342 ID_AA64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 343 ID_AA64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 344 ID_AA64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 345 ID_AA64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 346 ID_AA64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 347 ID_AA64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 348 ID_AA64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 349 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 350 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 351 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 352 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 353 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 354 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 355 ISR_EL1 = 0xc608, // 11 000 1100 0001 000 356 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 357 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 358 359 // Trace registers 360 TRCSTATR = 0x8818, // 10 001 0000 0011 000 361 TRCIDR8 = 0x8806, // 10 001 0000 0000 110 362 TRCIDR9 = 0x880e, // 10 001 0000 0001 110 363 TRCIDR10 = 0x8816, // 10 001 0000 0010 110 364 TRCIDR11 = 0x881e, // 10 001 0000 0011 110 365 TRCIDR12 = 0x8826, // 10 001 0000 0100 110 366 TRCIDR13 = 0x882e, // 10 001 0000 0101 110 367 TRCIDR0 = 0x8847, // 10 001 0000 1000 111 368 TRCIDR1 = 0x884f, // 10 001 0000 1001 111 369 TRCIDR2 = 0x8857, // 10 001 0000 1010 111 370 TRCIDR3 = 0x885f, // 10 001 0000 1011 111 371 TRCIDR4 = 0x8867, // 10 001 0000 1100 111 372 TRCIDR5 = 0x886f, // 10 001 0000 1101 111 373 TRCIDR6 = 0x8877, // 10 001 0000 1110 111 374 TRCIDR7 = 0x887f, // 10 001 0000 1111 111 375 TRCOSLSR = 0x888c, // 10 001 0001 0001 100 376 TRCPDSR = 0x88ac, // 10 001 0001 0101 100 377 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 378 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 379 TRCLSR = 0x8bee, // 10 001 0111 1101 110 380 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 381 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 382 TRCDEVID = 0x8b97, // 10 001 0111 0010 111 383 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 384 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 385 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 386 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 387 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 388 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 389 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 390 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 391 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 392 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 393 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 394 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 395 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 396 397 // GICv3 registers 398 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 399 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 400 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 401 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 402 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 403 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 404 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 405 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101 406 }; 407 408 enum SysRegWOValues { 409 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 410 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 411 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 412 413 // Trace Registers 414 TRCOSLAR = 0x8884, // 10 001 0001 0000 100 415 TRCLAR = 0x8be6, // 10 001 0111 1100 110 416 417 // GICv3 registers 418 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 419 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 420 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 421 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 422 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 423 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111 424 }; 425 426 enum SysRegValues { 427 Invalid = -1, // Op0 Op1 CRn CRm Op2 428 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010 429 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010 430 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000 431 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000 432 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010 433 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000 434 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010 435 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000 436 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100 437 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100 438 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100 439 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100 440 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100 441 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100 442 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100 443 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100 444 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100 445 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100 446 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100 447 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100 448 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100 449 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100 450 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100 451 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100 452 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101 453 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101 454 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101 455 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101 456 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101 457 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101 458 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101 459 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101 460 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101 461 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101 462 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101 463 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101 464 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101 465 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101 466 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101 467 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101 468 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110 469 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110 470 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110 471 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110 472 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110 473 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110 474 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110 475 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110 476 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110 477 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110 478 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110 479 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110 480 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110 481 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110 482 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110 483 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110 484 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111 485 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111 486 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111 487 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111 488 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111 489 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111 490 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111 491 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111 492 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111 493 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111 494 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111 495 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111 496 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111 497 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111 498 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111 499 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111 500 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000 501 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100 502 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100 503 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110 504 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110 505 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000 506 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000 507 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101 508 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010 509 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000 510 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000 511 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000 512 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001 513 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001 514 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001 515 HCR_EL2 = 0xe088, // 11 100 0001 0001 000 516 SCR_EL3 = 0xf088, // 11 110 0001 0001 000 517 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001 518 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001 519 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010 520 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010 521 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011 522 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111 523 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001 524 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000 525 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000 526 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000 527 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001 528 TCR_EL1 = 0xc102, // 11 000 0010 0000 010 529 TCR_EL2 = 0xe102, // 11 100 0010 0000 010 530 TCR_EL3 = 0xf102, // 11 110 0010 0000 010 531 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000 532 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010 533 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000 534 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000 535 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000 536 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000 537 ELR_EL1 = 0xc201, // 11 000 0100 0000 001 538 ELR_EL2 = 0xe201, // 11 100 0100 0000 001 539 ELR_EL3 = 0xf201, // 11 110 0100 0000 001 540 SP_EL0 = 0xc208, // 11 000 0100 0001 000 541 SP_EL1 = 0xe208, // 11 100 0100 0001 000 542 SP_EL2 = 0xf208, // 11 110 0100 0001 000 543 SPSel = 0xc210, // 11 000 0100 0010 000 544 NZCV = 0xda10, // 11 011 0100 0010 000 545 DAIF = 0xda11, // 11 011 0100 0010 001 546 CurrentEL = 0xc212, // 11 000 0100 0010 010 547 SPSR_irq = 0xe218, // 11 100 0100 0011 000 548 SPSR_abt = 0xe219, // 11 100 0100 0011 001 549 SPSR_und = 0xe21a, // 11 100 0100 0011 010 550 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011 551 FPCR = 0xda20, // 11 011 0100 0100 000 552 FPSR = 0xda21, // 11 011 0100 0100 001 553 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000 554 DLR_EL0 = 0xda29, // 11 011 0100 0101 001 555 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001 556 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000 557 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000 558 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000 559 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001 560 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001 561 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001 562 ESR_EL1 = 0xc290, // 11 000 0101 0010 000 563 ESR_EL2 = 0xe290, // 11 100 0101 0010 000 564 ESR_EL3 = 0xf290, // 11 110 0101 0010 000 565 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000 566 FAR_EL1 = 0xc300, // 11 000 0110 0000 000 567 FAR_EL2 = 0xe300, // 11 100 0110 0000 000 568 FAR_EL3 = 0xf300, // 11 110 0110 0000 000 569 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100 570 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000 571 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000 572 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001 573 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010 574 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011 575 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101 576 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000 577 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001 578 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010 579 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000 580 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001 581 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010 582 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011 583 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000 584 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000 585 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000 586 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000 587 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000 588 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000 589 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000 590 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000 591 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000 592 RMR_EL1 = 0xc602, // 11 000 1100 0000 010 593 RMR_EL2 = 0xe602, // 11 100 1100 0000 010 594 RMR_EL3 = 0xf602, // 11 110 1100 0000 010 595 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001 596 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010 597 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010 598 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010 599 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011 600 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100 601 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000 602 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011 603 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000 604 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000 605 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000 606 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000 607 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000 608 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001 609 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001 610 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001 611 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010 612 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010 613 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010 614 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000 615 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001 616 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010 617 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000 618 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001 619 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010 620 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011 621 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100 622 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101 623 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110 624 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111 625 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000 626 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001 627 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010 628 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011 629 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100 630 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101 631 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110 632 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111 633 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000 634 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001 635 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010 636 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011 637 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100 638 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101 639 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110 640 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111 641 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000 642 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001 643 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010 644 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011 645 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100 646 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101 647 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110 648 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111 649 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000 650 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001 651 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010 652 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011 653 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100 654 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101 655 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110 656 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111 657 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000 658 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001 659 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010 660 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011 661 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100 662 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101 663 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110 664 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111 665 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000 666 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001 667 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010 668 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011 669 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100 670 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101 671 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110 672 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111 673 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000 674 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001 675 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010 676 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011 677 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100 678 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101 679 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110 680 681 // Trace registers 682 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000 683 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000 684 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000 685 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000 686 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000 687 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000 688 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000 689 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000 690 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000 691 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000 692 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000 693 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001 694 TRCQCTLR = 0x8809, // 10 001 0000 0001 001 695 TRCVICTLR = 0x8802, // 10 001 0000 0000 010 696 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010 697 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010 698 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010 699 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010 700 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010 701 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010 702 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100 703 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100 704 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100 705 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100 706 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100 707 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100 708 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101 709 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101 710 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101 711 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101 712 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101 713 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101 714 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101 715 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101 716 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101 717 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101 718 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101 719 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101 720 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111 721 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111 722 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111 723 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111 724 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111 725 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111 726 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111 727 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111 728 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000 729 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000 730 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000 731 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000 732 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000 733 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000 734 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000 735 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000 736 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000 737 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000 738 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000 739 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000 740 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000 741 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000 742 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001 743 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001 744 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001 745 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001 746 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001 747 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001 748 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001 749 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001 750 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001 751 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001 752 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001 753 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001 754 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001 755 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001 756 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001 757 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001 758 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010 759 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010 760 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010 761 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010 762 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010 763 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010 764 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010 765 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010 766 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010 767 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010 768 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010 769 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010 770 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010 771 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010 772 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010 773 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010 774 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011 775 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011 776 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011 777 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011 778 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011 779 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011 780 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011 781 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011 782 TRCPDCR = 0x88a4, // 10 001 0001 0100 100 783 TRCACVR0 = 0x8900, // 10 001 0010 0000 000 784 TRCACVR1 = 0x8910, // 10 001 0010 0010 000 785 TRCACVR2 = 0x8920, // 10 001 0010 0100 000 786 TRCACVR3 = 0x8930, // 10 001 0010 0110 000 787 TRCACVR4 = 0x8940, // 10 001 0010 1000 000 788 TRCACVR5 = 0x8950, // 10 001 0010 1010 000 789 TRCACVR6 = 0x8960, // 10 001 0010 1100 000 790 TRCACVR7 = 0x8970, // 10 001 0010 1110 000 791 TRCACVR8 = 0x8901, // 10 001 0010 0000 001 792 TRCACVR9 = 0x8911, // 10 001 0010 0010 001 793 TRCACVR10 = 0x8921, // 10 001 0010 0100 001 794 TRCACVR11 = 0x8931, // 10 001 0010 0110 001 795 TRCACVR12 = 0x8941, // 10 001 0010 1000 001 796 TRCACVR13 = 0x8951, // 10 001 0010 1010 001 797 TRCACVR14 = 0x8961, // 10 001 0010 1100 001 798 TRCACVR15 = 0x8971, // 10 001 0010 1110 001 799 TRCACATR0 = 0x8902, // 10 001 0010 0000 010 800 TRCACATR1 = 0x8912, // 10 001 0010 0010 010 801 TRCACATR2 = 0x8922, // 10 001 0010 0100 010 802 TRCACATR3 = 0x8932, // 10 001 0010 0110 010 803 TRCACATR4 = 0x8942, // 10 001 0010 1000 010 804 TRCACATR5 = 0x8952, // 10 001 0010 1010 010 805 TRCACATR6 = 0x8962, // 10 001 0010 1100 010 806 TRCACATR7 = 0x8972, // 10 001 0010 1110 010 807 TRCACATR8 = 0x8903, // 10 001 0010 0000 011 808 TRCACATR9 = 0x8913, // 10 001 0010 0010 011 809 TRCACATR10 = 0x8923, // 10 001 0010 0100 011 810 TRCACATR11 = 0x8933, // 10 001 0010 0110 011 811 TRCACATR12 = 0x8943, // 10 001 0010 1000 011 812 TRCACATR13 = 0x8953, // 10 001 0010 1010 011 813 TRCACATR14 = 0x8963, // 10 001 0010 1100 011 814 TRCACATR15 = 0x8973, // 10 001 0010 1110 011 815 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100 816 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100 817 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100 818 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100 819 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101 820 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101 821 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101 822 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101 823 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110 824 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110 825 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110 826 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110 827 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111 828 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111 829 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111 830 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111 831 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000 832 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000 833 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000 834 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000 835 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000 836 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000 837 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000 838 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000 839 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001 840 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001 841 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001 842 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001 843 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001 844 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001 845 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001 846 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001 847 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010 848 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010 849 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010 850 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010 851 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100 852 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110 853 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110 854 855 // GICv3 registers 856 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011 857 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011 858 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000 859 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100 860 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100 861 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101 862 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101 863 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101 864 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110 865 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111 866 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111 867 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000 868 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100 869 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101 870 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110 871 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111 872 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000 873 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001 874 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010 875 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011 876 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000 877 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001 878 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010 879 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011 880 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000 881 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001 882 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010 883 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011 884 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000 885 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010 886 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111 887 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100 888 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000 889 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001 890 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010 891 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011 892 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100 893 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101 894 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110 895 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111 896 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000 897 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001 898 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010 899 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011 900 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100 901 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101 902 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110 903 ICH_LR15_EL2 = 0xe66f // 11 100 1100 1101 111 904 }; 905 906 // Note that these do not inherit from NamedImmMapper. This class is 907 // sufficiently different in its behaviour that I don't believe it's worth 908 // burdening the common NamedImmMapper with abstractions only needed in 909 // this one case. 910 struct SysRegMapper { 911 static const NamedImmMapper::Mapping SysRegPairs[]; 912 913 const NamedImmMapper::Mapping *InstPairs; 914 size_t NumInstPairs; 915 916 SysRegMapper() {} 917 uint32_t fromString(StringRef Name, bool &Valid) const; 918 std::string toString(uint32_t Bits, bool &Valid) const; 919 }; 920 921 struct MSRMapper : SysRegMapper { 922 static const NamedImmMapper::Mapping MSRPairs[]; 923 MSRMapper(); 924 }; 925 926 struct MRSMapper : SysRegMapper { 927 static const NamedImmMapper::Mapping MRSPairs[]; 928 MRSMapper(); 929 }; 930 931 uint32_t ParseGenericRegister(StringRef Name, bool &Valid); 932} 933 934namespace A64TLBI { 935 enum TLBIValues { 936 Invalid = -1, // Op0 Op1 CRn CRm Op2 937 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001 938 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101 939 VMALLE1IS = 0x4418, // 01 000 1000 0011 000 940 ALLE2IS = 0x6418, // 01 100 1000 0011 000 941 ALLE3IS = 0x7418, // 01 110 1000 0011 000 942 VAE1IS = 0x4419, // 01 000 1000 0011 001 943 VAE2IS = 0x6419, // 01 100 1000 0011 001 944 VAE3IS = 0x7419, // 01 110 1000 0011 001 945 ASIDE1IS = 0x441a, // 01 000 1000 0011 010 946 VAAE1IS = 0x441b, // 01 000 1000 0011 011 947 ALLE1IS = 0x641c, // 01 100 1000 0011 100 948 VALE1IS = 0x441d, // 01 000 1000 0011 101 949 VALE2IS = 0x641d, // 01 100 1000 0011 101 950 VALE3IS = 0x741d, // 01 110 1000 0011 101 951 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110 952 VAALE1IS = 0x441f, // 01 000 1000 0011 111 953 IPAS2E1 = 0x6421, // 01 100 1000 0100 001 954 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101 955 VMALLE1 = 0x4438, // 01 000 1000 0111 000 956 ALLE2 = 0x6438, // 01 100 1000 0111 000 957 ALLE3 = 0x7438, // 01 110 1000 0111 000 958 VAE1 = 0x4439, // 01 000 1000 0111 001 959 VAE2 = 0x6439, // 01 100 1000 0111 001 960 VAE3 = 0x7439, // 01 110 1000 0111 001 961 ASIDE1 = 0x443a, // 01 000 1000 0111 010 962 VAAE1 = 0x443b, // 01 000 1000 0111 011 963 ALLE1 = 0x643c, // 01 100 1000 0111 100 964 VALE1 = 0x443d, // 01 000 1000 0111 101 965 VALE2 = 0x643d, // 01 100 1000 0111 101 966 VALE3 = 0x743d, // 01 110 1000 0111 101 967 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110 968 VAALE1 = 0x443f // 01 000 1000 0111 111 969 }; 970 971 struct TLBIMapper : NamedImmMapper { 972 const static Mapping TLBIPairs[]; 973 974 TLBIMapper(); 975 }; 976 977 static inline bool NeedsRegister(TLBIValues Val) { 978 switch (Val) { 979 case VMALLE1IS: 980 case ALLE2IS: 981 case ALLE3IS: 982 case ALLE1IS: 983 case VMALLS12E1IS: 984 case VMALLE1: 985 case ALLE2: 986 case ALLE3: 987 case ALLE1: 988 case VMALLS12E1: 989 return false; 990 default: 991 return true; 992 } 993 } 994} 995 996namespace AArch64II { 997 998 enum TOF { 999 //===--------------------------------------------------------------===// 1000 // AArch64 Specific MachineOperand flags. 1001 1002 MO_NO_FLAG, 1003 1004 // MO_GOT - Represents a relocation referring to the GOT entry of a given 1005 // symbol. Used in adrp. 1006 MO_GOT, 1007 1008 // MO_GOT_LO12 - Represents a relocation referring to the low 12 bits of the 1009 // GOT entry of a given symbol. Used in ldr only. 1010 MO_GOT_LO12, 1011 1012 // MO_DTPREL_* - Represents a relocation referring to the offset from a 1013 // module's dynamic thread pointer. Used in the local-dynamic TLS access 1014 // model. 1015 MO_DTPREL_G1, 1016 MO_DTPREL_G0_NC, 1017 1018 // MO_GOTTPREL_* - Represents a relocation referring to a GOT entry 1019 // providing the offset of a variable from the thread-pointer. Used in 1020 // initial-exec TLS model where this offset is assigned in the static thread 1021 // block and thus known by the dynamic linker. 1022 MO_GOTTPREL, 1023 MO_GOTTPREL_LO12, 1024 1025 // MO_TLSDESC_* - Represents a relocation referring to a GOT entry providing 1026 // a TLS descriptor chosen by the dynamic linker. Used for the 1027 // general-dynamic and local-dynamic TLS access models where very littls is 1028 // known at link-time. 1029 MO_TLSDESC, 1030 MO_TLSDESC_LO12, 1031 1032 // MO_TPREL_* - Represents a relocation referring to the offset of a 1033 // variable from the thread pointer itself. Used in the local-exec TLS 1034 // access model. 1035 MO_TPREL_G1, 1036 MO_TPREL_G0_NC, 1037 1038 // MO_LO12 - On a symbol operand, this represents a relocation containing 1039 // lower 12 bits of the address. Used in add/sub/ldr/str. 1040 MO_LO12, 1041 1042 // MO_ABS_G* - Represent the 16-bit granules of an absolute reference using 1043 // movz/movk instructions. 1044 MO_ABS_G3, 1045 MO_ABS_G2_NC, 1046 MO_ABS_G1_NC, 1047 MO_ABS_G0_NC 1048 }; 1049} 1050 1051class APFloat; 1052 1053namespace A64Imms { 1054 bool isFPImm(const APFloat &Val, uint32_t &Imm8Bits); 1055 1056 inline bool isFPImm(const APFloat &Val) { 1057 uint32_t Imm8; 1058 return isFPImm(Val, Imm8); 1059 } 1060 1061 bool isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits); 1062 bool isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t &Imm); 1063 1064 bool isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift); 1065 bool isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift); 1066 1067 // We sometimes want to know whether the immediate is representable with a 1068 // MOVN but *not* with a MOVZ (because that would take priority). 1069 bool isOnlyMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift); 1070 1071} 1072 1073} // end namespace llvm; 1074 1075#endif 1076