1;; Predicate definitions for SPARC. 2;; Copyright (C) 2005 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 2, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to 18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19;; Boston, MA 02110-1301, USA. 20 21;; Predicates for numerical constants. 22 23;; Return true if OP is the zero constant for MODE. 24(define_predicate "const_zero_operand" 25 (and (match_code "const_int,const_double,const_vector") 26 (match_test "op == CONST0_RTX (mode)"))) 27 28;; Return true if OP is the one constant for MODE. 29(define_predicate "const_one_operand" 30 (and (match_code "const_int,const_double,const_vector") 31 (match_test "op == CONST1_RTX (mode)"))) 32 33;; Return true if OP is the integer constant 4096. 34(define_predicate "const_4096_operand" 35 (and (match_code "const_int") 36 (match_test "INTVAL (op) == 4096"))) 37 38;; Return true if OP is a constant that is representable by a 13-bit 39;; signed field. This is an acceptable immediate operand for most 40;; 3-address instructions. 41(define_predicate "small_int_operand" 42 (and (match_code "const_int") 43 (match_test "SPARC_SIMM13_P (INTVAL (op))"))) 44 45;; Return true if OP is a constant operand for the umul instruction. That 46;; instruction sign-extends immediate values just like all other SPARC 47;; instructions, but interprets the extended result as an unsigned number. 48(define_predicate "uns_small_int_operand" 49 (match_code "const_int,const_double") 50{ 51#if HOST_BITS_PER_WIDE_INT == 32 52 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) 53 || (GET_CODE (op) == CONST_DOUBLE 54 && CONST_DOUBLE_HIGH (op) == 0 55 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); 56#else 57 return (GET_CODE (op) == CONST_INT 58 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) 59 || (INTVAL (op) >= 0xFFFFF000 60 && INTVAL (op) <= 0xFFFFFFFF))); 61#endif 62}) 63 64;; Return true if OP is a constant that can be loaded by the sethi instruction. 65;; The first test avoids emitting sethi to load zero for example. 66(define_predicate "const_high_operand" 67 (and (match_code "const_int") 68 (and (not (match_operand 0 "small_int_operand")) 69 (match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))")))) 70 71;; Return true if OP is a constant whose 1's complement can be loaded by the 72;; sethi instruction. 73(define_predicate "const_compl_high_operand" 74 (and (match_code "const_int") 75 (and (not (match_operand 0 "small_int_operand")) 76 (match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))")))) 77 78;; Return true if OP is a FP constant that needs to be loaded by the sethi/losum 79;; pair of instructions. 80(define_predicate "fp_const_high_losum_operand" 81 (match_operand 0 "const_double_operand") 82{ 83 gcc_assert (mode == SFmode); 84 return fp_high_losum_p (op); 85}) 86 87 88;; Predicates for symbolic constants. 89 90;; Return true if OP is either a symbol reference or a sum of a symbol 91;; reference and a constant. 92(define_predicate "symbolic_operand" 93 (match_code "symbol_ref,label_ref,const") 94{ 95 enum machine_mode omode = GET_MODE (op); 96 97 if (omode != mode && omode != VOIDmode && mode != VOIDmode) 98 return false; 99 100 switch (GET_CODE (op)) 101 { 102 case SYMBOL_REF: 103 return !SYMBOL_REF_TLS_MODEL (op); 104 105 case LABEL_REF: 106 return true; 107 108 case CONST: 109 op = XEXP (op, 0); 110 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 111 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) 112 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 113 && GET_CODE (XEXP (op, 1)) == CONST_INT); 114 115 default: 116 gcc_unreachable (); 117 } 118}) 119 120;; Return true if OP is a symbolic operand for the TLS Global Dynamic model. 121(define_predicate "tgd_symbolic_operand" 122 (and (match_code "symbol_ref") 123 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_GLOBAL_DYNAMIC"))) 124 125;; Return true if OP is a symbolic operand for the TLS Local Dynamic model. 126(define_predicate "tld_symbolic_operand" 127 (and (match_code "symbol_ref") 128 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_DYNAMIC"))) 129 130;; Return true if OP is a symbolic operand for the TLS Initial Exec model. 131(define_predicate "tie_symbolic_operand" 132 (and (match_code "symbol_ref") 133 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC"))) 134 135;; Return true if OP is a symbolic operand for the TLS Local Exec model. 136(define_predicate "tle_symbolic_operand" 137 (and (match_code "symbol_ref") 138 (match_test "SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC"))) 139 140;; Return true if the operand is an argument used in generating PIC references 141;; in either the medium/low or embedded medium/anywhere code models on V9. 142;; Check for (const (minus (symbol_ref:GOT) 143;; (const (minus (label) (pc))))) 144(define_predicate "medium_pic_operand" 145 (match_code "const") 146{ 147 /* Check for (const (minus (symbol_ref:GOT) 148 (const (minus (label) (pc))))). */ 149 op = XEXP (op, 0); 150 return GET_CODE (op) == MINUS 151 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF 152 && GET_CODE (XEXP (op, 1)) == CONST 153 && GET_CODE (XEXP (XEXP (op, 1), 0)) == MINUS; 154}) 155 156;; Return true if OP is a LABEL_REF of mode MODE. 157(define_predicate "label_ref_operand" 158 (and (match_code "label_ref") 159 (match_test "GET_MODE (op) == mode"))) 160 161;; Return true if OP is a data segment reference. This includes the readonly 162;; data segment or, in other words, anything but the text segment. 163;; This is needed in the embedded medium/anywhere code model on V9. These 164;; values are accessed with EMBMEDANY_BASE_REG. */ 165(define_predicate "data_segment_operand" 166 (match_code "symbol_ref,plus,const") 167{ 168 switch (GET_CODE (op)) 169 { 170 case SYMBOL_REF : 171 return ! SYMBOL_REF_FUNCTION_P (op); 172 case PLUS : 173 /* Assume canonical format of symbol + constant. 174 Fall through. */ 175 case CONST : 176 return data_segment_operand (XEXP (op, 0), VOIDmode); 177 default : 178 gcc_unreachable (); 179 } 180}) 181 182;; Return true if OP is a text segment reference. 183;; This is needed in the embedded medium/anywhere code model on V9. 184(define_predicate "text_segment_operand" 185 (match_code "label_ref,symbol_ref,plus,const") 186{ 187 switch (GET_CODE (op)) 188 { 189 case LABEL_REF : 190 return true; 191 case SYMBOL_REF : 192 return SYMBOL_REF_FUNCTION_P (op); 193 case PLUS : 194 /* Assume canonical format of symbol + constant. 195 Fall through. */ 196 case CONST : 197 return text_segment_operand (XEXP (op, 0), VOIDmode); 198 default : 199 gcc_unreachable (); 200 } 201}) 202 203 204;; Predicates for registers. 205 206;; Return true if OP is either the zero constant or a register. 207(define_predicate "register_or_zero_operand" 208 (ior (match_operand 0 "register_operand") 209 (match_operand 0 "const_zero_operand"))) 210 211;; Return true if OP is a register operand in a floating point register. 212(define_predicate "fp_register_operand" 213 (match_operand 0 "register_operand") 214{ 215 if (GET_CODE (op) == SUBREG) 216 op = SUBREG_REG (op); /* Possibly a MEM */ 217 return REG_P (op) && SPARC_FP_REG_P (REGNO (op)); 218}) 219 220;; Return true if OP is an integer register. 221(define_special_predicate "int_register_operand" 222 (ior (match_test "register_operand (op, SImode)") 223 (match_test "TARGET_ARCH64 && register_operand (op, DImode)"))) 224 225;; Return true if OP is a floating point condition code register. 226(define_predicate "fcc_register_operand" 227 (match_code "reg") 228{ 229 if (mode != VOIDmode && mode != GET_MODE (op)) 230 return false; 231 if (mode == VOIDmode 232 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 233 return false; 234 235#if 0 /* ??? 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ 236 if (reg_renumber == 0) 237 return REGNO (op) >= FIRST_PSEUDO_REGISTER; 238 return REGNO_OK_FOR_CCFP_P (REGNO (op)); 239#else 240 return ((unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG) < 4; 241#endif 242}) 243 244;; Return true if OP is the floating point condition code register fcc0. 245(define_predicate "fcc0_register_operand" 246 (match_code "reg") 247{ 248 if (mode != VOIDmode && mode != GET_MODE (op)) 249 return false; 250 if (mode == VOIDmode 251 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 252 return false; 253 254 return REGNO (op) == SPARC_FCC_REG; 255}) 256 257;; Return true if OP is an integer or floating point condition code register. 258(define_predicate "icc_or_fcc_register_operand" 259 (match_code "reg") 260{ 261 if (REGNO (op) == SPARC_ICC_REG) 262 { 263 if (mode != VOIDmode && mode != GET_MODE (op)) 264 return false; 265 if (mode == VOIDmode 266 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) 267 return false; 268 269 return true; 270 } 271 272 return fcc_register_operand (op, mode); 273}) 274 275 276;; Predicates for arithmetic instructions. 277 278;; Return true if OP is a register, or is a constant that is representable 279;; by a 13-bit signed field. This is an acceptable operand for most 280;; 3-address instructions. 281(define_predicate "arith_operand" 282 (ior (match_operand 0 "register_operand") 283 (match_operand 0 "small_int_operand"))) 284 285;; 64-bit: Same as above. 286;; 32-bit: Return true if OP is a register, or is a constant that is 287;; representable by a couple of 13-bit signed fields. This is an 288;; acceptable operand for most 3-address splitters. 289(define_predicate "arith_double_operand" 290 (match_code "const_int,const_double,reg,subreg") 291{ 292 bool arith_simple_operand = arith_operand (op, mode); 293 HOST_WIDE_INT m1, m2; 294 295 if (TARGET_ARCH64 || arith_simple_operand) 296 return arith_simple_operand; 297 298#if HOST_BITS_PER_WIDE_INT == 32 299 if (GET_CODE (op) != CONST_DOUBLE) 300 return false; 301 m1 = CONST_DOUBLE_LOW (op); 302 m2 = CONST_DOUBLE_HIGH (op); 303#else 304 if (GET_CODE (op) != CONST_INT) 305 return false; 306 m1 = trunc_int_for_mode (INTVAL (op), SImode); 307 m2 = trunc_int_for_mode (INTVAL (op) >> 32, SImode); 308#endif 309 310 return SPARC_SIMM13_P (m1) && SPARC_SIMM13_P (m2); 311}) 312 313;; Return true if OP is suitable as second operand for add/sub. 314(define_predicate "arith_add_operand" 315 (ior (match_operand 0 "arith_operand") 316 (match_operand 0 "const_4096_operand"))) 317 318;; Return true if OP is suitable as second double operand for add/sub. 319(define_predicate "arith_double_add_operand" 320 (match_code "const_int,const_double,reg,subreg") 321{ 322 bool _arith_double_operand = arith_double_operand (op, mode); 323 324 if (_arith_double_operand) 325 return true; 326 327 return TARGET_ARCH64 && const_4096_operand (op, mode); 328}) 329 330;; Return true if OP is a register, or is a CONST_INT that can fit in a 331;; signed 10-bit immediate field. This is an acceptable SImode operand for 332;; the movrcc instructions. 333(define_predicate "arith10_operand" 334 (ior (match_operand 0 "register_operand") 335 (and (match_code "const_int") 336 (match_test "SPARC_SIMM10_P (INTVAL (op))")))) 337 338;; Return true if OP is a register, or is a CONST_INT that can fit in a 339;; signed 11-bit immediate field. This is an acceptable SImode operand for 340;; the movcc instructions. 341(define_predicate "arith11_operand" 342 (ior (match_operand 0 "register_operand") 343 (and (match_code "const_int") 344 (match_test "SPARC_SIMM11_P (INTVAL (op))")))) 345 346;; Return true if OP is a register or a constant for the umul instruction. 347(define_predicate "uns_arith_operand" 348 (ior (match_operand 0 "register_operand") 349 (match_operand 0 "uns_small_int_operand"))) 350 351 352;; Predicates for miscellaneous instructions. 353 354;; Return true if OP is valid for the lhs of a comparison insn. 355(define_predicate "compare_operand" 356 (match_code "reg,subreg,zero_extract") 357{ 358 if (GET_CODE (op) == ZERO_EXTRACT) 359 return (register_operand (XEXP (op, 0), mode) 360 && small_int_operand (XEXP (op, 1), mode) 361 && small_int_operand (XEXP (op, 2), mode) 362 /* This matches cmp_zero_extract. */ 363 && ((mode == SImode 364 && INTVAL (XEXP (op, 2)) > 19) 365 /* This matches cmp_zero_extract_sp64. */ 366 || (TARGET_ARCH64 367 && mode == DImode 368 && INTVAL (XEXP (op, 2)) > 51))); 369 else 370 return register_operand (op, mode); 371}) 372 373;; Return true if OP is a valid operand for the source of a move insn. 374(define_predicate "input_operand" 375 (match_code "const_int,const_double,const_vector,reg,subreg,mem") 376{ 377 enum mode_class mclass; 378 379 /* If both modes are non-void they must be the same. */ 380 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) 381 return false; 382 383 mclass = GET_MODE_CLASS (mode); 384 385 /* Allow any 1-instruction integer constant. */ 386 if (mclass == MODE_INT 387 && (small_int_operand (op, mode) || const_high_operand (op, mode))) 388 return true; 389 390 /* If 32-bit mode and this is a DImode constant, allow it 391 so that the splits can be generated. */ 392 if (TARGET_ARCH32 393 && mode == DImode 394 && (GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)) 395 return true; 396 397 if ((mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE) 398 || (mclass == MODE_VECTOR_INT && GET_CODE (op) == CONST_VECTOR)) 399 return true; 400 401 if (register_operand (op, mode)) 402 return true; 403 404 /* If this is a SUBREG, look inside so that we handle paradoxical ones. */ 405 if (GET_CODE (op) == SUBREG) 406 op = SUBREG_REG (op); 407 408 /* Check for valid MEM forms. */ 409 if (GET_CODE (op) == MEM) 410 return memory_address_p (mode, XEXP (op, 0)); 411 412 return false; 413}) 414 415;; Return true if OP is an address suitable for a call insn. 416;; Call insn on SPARC can take a PC-relative constant address 417;; or any regular memory address. 418(define_predicate "call_address_operand" 419 (ior (match_operand 0 "symbolic_operand") 420 (match_test "memory_address_p (Pmode, op)"))) 421 422;; Return true if OP is an operand suitable for a call insn. 423(define_predicate "call_operand" 424 (and (match_code "mem") 425 (match_test "call_address_operand (XEXP (op, 0), mode)"))) 426 427 428;; Predicates for operators. 429 430;; Return true if OP is a comparison operator. This allows the use of 431;; MATCH_OPERATOR to recognize all the branch insns. 432(define_predicate "noov_compare_operator" 433 (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu") 434{ 435 enum rtx_code code = GET_CODE (op); 436 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode 437 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 438 /* These are the only branches which work with CC_NOOVmode. */ 439 return (code == EQ || code == NE || code == GE || code == LT); 440 return true; 441}) 442 443;; Return true if OP is a 64-bit comparison operator. This allows the use of 444;; MATCH_OPERATOR to recognize all the branch insns. 445(define_predicate "noov_compare64_operator" 446 (and (match_code "ne,eq,ge,gt,le,lt,geu,gtu,leu,ltu") 447 (match_test "TARGET_V9")) 448{ 449 enum rtx_code code = GET_CODE (op); 450 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 451 /* These are the only branches which work with CCX_NOOVmode. */ 452 return (code == EQ || code == NE || code == GE || code == LT); 453 return (GET_MODE (XEXP (op, 0)) == CCXmode); 454}) 455 456;; Return true if OP is a comparison operator suitable for use in V9 457;; conditional move or branch on register contents instructions. 458(define_predicate "v9_register_compare_operator" 459 (match_code "eq,ne,ge,lt,le,gt")) 460 461;; Return true if OP is an operator which can set the condition codes 462;; explicitly. We do not include PLUS and MINUS because these 463;; require CC_NOOVmode, which we handle explicitly. 464(define_predicate "cc_arith_operator" 465 (match_code "and,ior,xor")) 466 467;; Return true if OP is an operator which can bitwise complement its 468;; second operand and set the condition codes explicitly. 469;; XOR is not here because combine canonicalizes (xor (not ...) ...) 470;; and (xor ... (not ...)) to (not (xor ...)). */ 471(define_predicate "cc_arith_not_operator" 472 (match_code "and,ior")) 473 474;; Return true if OP is memory operand with just [%reg] addressing mode. 475(define_predicate "memory_reg_operand" 476 (and (match_code "mem") 477 (and (match_operand 0 "memory_operand") 478 (match_test "REG_P (XEXP (op, 0))")))) 479