1;; Scheduling description for HyperSPARC.
2;;   Copyright (C) 2002 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 2, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to
18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19;; Boston, MA 02110-1301, USA.
20
21;; The HyperSPARC is a dual-issue processor.  It is not all that fancy.
22
23;; ??? There are some things not modelled.  For example, sethi+or
24;; ??? coming right after each other are specifically identified and
25;; ??? dual-issued by the processor.  Similarly for sethi+ld[reg+lo].
26;; ??? Actually, to be more precise that rule is sort of modelled now.
27
28(define_automaton "hypersparc_0,hypersparc_1")
29
30;; HyperSPARC/sparclite86x scheduling
31
32(define_cpu_unit "hs_memory,hs_branch,hs_shift,hs_fpalu" "hypersparc_0")
33(define_cpu_unit "hs_fpmds" "hypersparc_1")
34
35(define_insn_reservation "hs_load" 1
36  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
37    (eq_attr "type" "load,sload,fpload"))
38  "hs_memory")
39
40(define_insn_reservation "hs_store" 2
41  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
42    (eq_attr "type" "store,fpstore"))
43  "hs_memory, nothing")
44
45(define_insn_reservation "hs_slbranch" 1
46  (and (eq_attr "cpu" "sparclite86x")
47    (eq_attr "type" "branch"))
48  "hs_branch")
49
50(define_insn_reservation "hs_slshift" 1
51  (and (eq_attr "cpu" "sparclite86x")
52    (eq_attr "type" "shift"))
53  "hs_shift")
54
55(define_insn_reservation "hs_fp_alu" 1
56  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
57    (eq_attr "type" "fp,fpmove,fpcmp"))
58  "hs_fpalu")
59
60(define_insn_reservation "hs_fp_mult" 1
61  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
62    (eq_attr "type" "fpmul"))
63  "hs_fpmds")
64
65(define_insn_reservation "hs_fp_divs" 8
66  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
67    (eq_attr "type" "fpdivs"))
68  "hs_fpmds*6, nothing*2")
69
70(define_insn_reservation "hs_fp_divd" 12
71  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
72    (eq_attr "type" "fpdivd"))
73  "hs_fpmds*10, nothing*2")
74
75(define_insn_reservation "hs_fp_sqrt" 17
76  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
77    (eq_attr "type" "fpsqrts,fpsqrtd"))
78  "hs_fpmds*15, nothing*2")
79
80(define_insn_reservation "hs_imul" 17
81  (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
82    (eq_attr "type" "imul"))
83  "hs_fpmds*15, nothing*2")
84