1/* Definitions of target machine for GNU compiler, for IBM S/390
2   Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4                  Ulrich Weigand (uweigand@de.ibm.com).
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2, or (at your option) any later
11version.
12
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING.  If not, write to the Free
20Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
2102110-1301, USA.  */
22
23/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
24INT_MODE (OI, 32);
25
26/* Define TFmode to work around reload problem PR 20927.  */
27FLOAT_MODE (TF, 16, ieee_quad_format);
28
29/* Add any extra modes needed to represent the condition code.  */
30
31/*
32
33Condition Codes
34
35Check for zero
36
37CCZ:  EQ          NE           NE          NE
38CCZ1: EQ          NE                                  (CS)
39
40Unsigned compares
41
42CCU:  EQ          LTU          GTU         NE         (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
43CCUR: EQ          GTU          LTU         NE         (CLGF/R)
44
45Signed compares
46
47CCS:  EQ          LT           GT          UNORDERED  (LTGFR, LTGR, LTR, ICM/Y,
48                                                       LTDBR, LTDR, LTEBR, LTER,
49                                                       CG/R, C/R/Y, CGHI, CHI,
50                                                       CDB/R, CD/R, CEB/R, CE/R,
51                                                       ADB/R, AEB/R, SDB/R, SEB/R,
52                                                       SRAG, SRA, SRDA)
53CCSR: EQ          GT           LT          UNORDERED  (CGF/R, CH/Y)
54
55Condition codes resulting from add with overflow
56
57CCA:  EQ          LT           GT          Overflow
58CCAP: EQ          LT           GT          LT         (AGHI, AHI)
59CCAN: EQ          LT           GT          GT         (AGHI, AHI)
60
61Condition codes of unsigned adds and subs
62
63CCL:  EQ          NE           EQ          NE         (ALGF/R, ALG/R, AL/R/Y,
64                                                       ALCG/R, ALC/R,
65                                                       SLGF/R, SLG/R, SL/R/Y,
66                                                       SLBG/R, SLB/R)
67CCL1: GEU         GEU          LTU         LTU        (ALG/R, AL/R/Y)
68CCL2: GTU         GTU          LEU         LEU        (SLG/R, SL/R/Y)
69CCL3: EQ          LTU          EQ          GTU        (SLG/R, SL/R/Y)
70
71Test under mask checks
72
73CCT:  EQ          NE           NE          NE         (ICM/Y, TML, CG/R, CGHI,
74                                                       C/R/Y, CHI, NG/R, N/R/Y,
75                                                       OG/R, O/R/Y, XG/R, X/R/Y)
76CCT1: NE          EQ           NE          NE         (TMH, TML)
77CCT2: NE          NE           EQ          NE         (TMH, TML)
78CCT3: NE          NE           NE          EQ         (TMH, TML)
79
80CCA and CCT modes are request only modes. These modes are never returned by
81s390_select_cc_mode. They are only intended to match other modes.
82
83Requested mode            -> Destination CC register mode
84
85CCS, CCU, CCT, CCSR, CCUR -> CCZ
86CCA                       -> CCAP, CCAN
87
88
89*** Comments ***
90
91CCAP, CCAN
92
93The CC obtained from add instruction usually can't be used for comparisons
94because its coupling with overflow flag. In case of an overflow the
95less than/greater than data are lost. Nevertheless a comparison can be done
96whenever immediate values are involved because they are known at compile time.
97If you know whether the used constant is positive or negative you can predict
98the sign of the result even in case of an overflow.
99
100
101CCT, CCT1, CCT2, CCT3
102
103If bits of an integer masked with an AND instruction are checked, the test under
104mask instructions turn out to be very handy for a set of special cases.
105The simple cases are checks whether all masked bits are zero or ones:
106
107  int a;
108  if ((a & (16 + 128)) == 0)          -> CCT/CCZ
109  if ((a & (16 + 128)) == 16 + 128)   -> CCT3
110
111Using two extra modes makes it possible to do complete checks on two bits of an
112integer (This is possible on register operands only. TM does not provide the
113information necessary for CCT1 and CCT2 modes.):
114
115  int a;
116  if ((a & (16 + 128)) == 16)         -> CCT1
117  if ((a & (16 + 128)) == 128)        -> CCT2
118
119
120CCSR, CCUR
121
122There are several instructions comparing 32 bit with 64 bit unsigned/signed
123values. Such instructions can be considered to have a builtin zero/sign_extend.
124The problem is that in the RTL (to be canonical) the zero/sign extended operand
125has to be the first one but the machine instructions like it the other way
126around. The following both modes can be considered as CCS and CCU modes with
127exchanged operands.
128
129
130CCL1, CCL2
131
132These modes represent the result of overflow checks.
133
134if (a + b < a) -> CCL1 state of the carry bit   (CC2 | CC3)
135if (a - b > a) -> CCL2 state of the borrow bit  (CC0 | CC1)
136
137They are used when multi word numbers are computed dealing one SImode part after
138another or whenever manual overflow checks like the examples above are
139compiled.
140
141
142CCL3
143
144A logical subtract instruction sets the borrow bit in case of an overflow.
145The resulting condition code of those instructions is represented by the
146CCL3 mode. Together with the CCU mode this mode is used for jumpless
147implementations of several if-constructs - see s390_expand_addcc for more
148details.
149
150CCZ1
151
152The compare and swap instructions sets the condition code to 0/1 if the
153operands were equal/unequal. The CCZ1 mode ensures the result can be
154effectively placed into a register.
155
156*/
157
158
159CC_MODE (CCZ);
160CC_MODE (CCZ1);
161CC_MODE (CCA);
162CC_MODE (CCAP);
163CC_MODE (CCAN);
164CC_MODE (CCL);
165CC_MODE (CCL1);
166CC_MODE (CCL2);
167CC_MODE (CCL3);
168CC_MODE (CCU);
169CC_MODE (CCUR);
170CC_MODE (CCS);
171CC_MODE (CCSR);
172CC_MODE (CCT);
173CC_MODE (CCT1);
174CC_MODE (CCT2);
175CC_MODE (CCT3);
176