1/* Definitions of target machine GNU compiler.  IA-64 version.
2   Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3   Contributed by James E. Wilson <wilson@cygnus.com> and
4   		  David Mosberger <davidm@hpl.hp.com>.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 2, or (at your option)
11any later version.
12
13GCC is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING.  If not, write to
20the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21Boston, MA 02110-1301, USA.  */
22
23/* IA64 requires both XF and TF modes.
24   XFmode is __float80 is IEEE extended; TFmode is __float128
25   is IEEE quad.  Both these modes occupy 16 bytes, but XFmode
26   only has 80 significant bits.  RFmode is __fpreg is IA64 internal
27   register format with 82 significant bits but otherwise handled like
28   XFmode.  */
29
30FRACTIONAL_FLOAT_MODE (XF, 80, 16, ieee_extended_intel_128_format);
31FRACTIONAL_FLOAT_MODE (RF, 82, 16, ieee_extended_intel_128_format);
32FLOAT_MODE (TF, 16, ieee_quad_format);
33
34/* The above produces:
35
36   mode	  ILP32 size/align	LP64 size/align
37   XF	  16/16			16/16
38   TF	  16/16			16/16
39
40   psABI expectations:
41
42   mode   ILP32 size/align	LP64 size/align
43   XF	  12/4			-
44   TF	  -			-
45
46   HPUX expectations:
47
48   mode	  ILP32 size/align	LP64 size/align
49   XF	  -			-
50   TF	  16/8			-
51
52   We fix this up here.  */
53
54ADJUST_FLOAT_FORMAT (XF, (TARGET_ILP32 && !TARGET_HPUX)
55			 ? &ieee_extended_intel_96_format
56			 : &ieee_extended_intel_128_format);
57ADJUST_BYTESIZE  (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
58ADJUST_ALIGNMENT (XF, (TARGET_ILP32 && !TARGET_HPUX) ?  4 : 16);
59
60ADJUST_FLOAT_FORMAT (RF, (TARGET_ILP32 && !TARGET_HPUX)
61			 ? &ieee_extended_intel_96_format
62			 : &ieee_extended_intel_128_format);
63ADJUST_BYTESIZE  (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
64ADJUST_ALIGNMENT (RF, (TARGET_ILP32 && !TARGET_HPUX) ?  4 : 16);
65
66ADJUST_ALIGNMENT (TF, (TARGET_ILP32 &&  TARGET_HPUX) ?  8 : 16);
67
68/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
69INT_MODE (OI, 32);
70
71/* Add any extra modes needed to represent the condition code.
72
73   CCImode is used to mark a single predicate register instead
74   of a register pair.  This is currently only used in reg_raw_mode
75   so that flow doesn't do something stupid.  */
76
77CC_MODE (CCI);
78
79/* Vector modes.  */
80VECTOR_MODES (INT, 4);		/* V4QI V2HI */
81VECTOR_MODES (INT, 8);		/* V8QI V4HI V2SI */
82VECTOR_MODE (INT, QI, 16);
83VECTOR_MODE (INT, HI, 8);
84VECTOR_MODE (INT, SI, 4);
85VECTOR_MODE (FLOAT, SF, 2);
86VECTOR_MODE (FLOAT, SF, 4);
87
88