1/*- 2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 3 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 341606 2018-12-05 21:49:39Z emaste $ 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 341606 2018-12-05 21:49:39Z emaste $"); 32 33#include <sys/param.h> 34#include <sys/linker_set.h> 35#include <sys/stat.h> 36#include <sys/uio.h> 37#include <sys/ioctl.h> 38#include <sys/disk.h> 39#include <sys/ata.h> 40#include <sys/endian.h> 41 42#include <errno.h> 43#include <fcntl.h> 44#include <stdio.h> 45#include <stdlib.h> 46#include <stdint.h> 47#include <string.h> 48#include <strings.h> 49#include <unistd.h> 50#include <assert.h> 51#include <pthread.h> 52#include <pthread_np.h> 53#include <inttypes.h> 54#include <md5.h> 55 56#include "bhyverun.h" 57#include "pci_emul.h" 58#include "ahci.h" 59#include "block_if.h" 60 61#define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 62#define MAX_PORTS 32 /* AHCI supports 32 ports */ 63 64#define PxSIG_ATA 0x00000101 /* ATA drive */ 65#define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 66 67enum sata_fis_type { 68 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 69 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 70 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 71 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 72 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 73 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 74 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 75 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 76}; 77 78/* 79 * SCSI opcodes 80 */ 81#define TEST_UNIT_READY 0x00 82#define REQUEST_SENSE 0x03 83#define INQUIRY 0x12 84#define START_STOP_UNIT 0x1B 85#define PREVENT_ALLOW 0x1E 86#define READ_CAPACITY 0x25 87#define READ_10 0x28 88#define POSITION_TO_ELEMENT 0x2B 89#define READ_TOC 0x43 90#define GET_EVENT_STATUS_NOTIFICATION 0x4A 91#define MODE_SENSE_10 0x5A 92#define REPORT_LUNS 0xA0 93#define READ_12 0xA8 94#define READ_CD 0xBE 95 96/* 97 * SCSI mode page codes 98 */ 99#define MODEPAGE_RW_ERROR_RECOVERY 0x01 100#define MODEPAGE_CD_CAPABILITIES 0x2A 101 102/* 103 * ATA commands 104 */ 105#define ATA_SF_ENAB_SATA_SF 0x10 106#define ATA_SATA_SF_AN 0x05 107#define ATA_SF_DIS_SATA_SF 0x90 108 109/* 110 * Debug printf 111 */ 112#ifdef AHCI_DEBUG 113static FILE *dbg; 114#define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 115#else 116#define DPRINTF(format, arg...) 117#endif 118#define WPRINTF(format, arg...) printf(format, ##arg) 119 120struct ahci_ioreq { 121 struct blockif_req io_req; 122 struct ahci_port *io_pr; 123 STAILQ_ENTRY(ahci_ioreq) io_flist; 124 TAILQ_ENTRY(ahci_ioreq) io_blist; 125 uint8_t *cfis; 126 uint32_t len; 127 uint32_t done; 128 int slot; 129 int more; 130}; 131 132struct ahci_port { 133 struct blockif_ctxt *bctx; 134 struct pci_ahci_softc *pr_sc; 135 uint8_t *cmd_lst; 136 uint8_t *rfis; 137 char ident[20 + 1]; 138 int port; 139 int atapi; 140 int reset; 141 int waitforclear; 142 int mult_sectors; 143 uint8_t xfermode; 144 uint8_t err_cfis[20]; 145 uint8_t sense_key; 146 uint8_t asc; 147 u_int ccs; 148 uint32_t pending; 149 150 uint32_t clb; 151 uint32_t clbu; 152 uint32_t fb; 153 uint32_t fbu; 154 uint32_t is; 155 uint32_t ie; 156 uint32_t cmd; 157 uint32_t unused0; 158 uint32_t tfd; 159 uint32_t sig; 160 uint32_t ssts; 161 uint32_t sctl; 162 uint32_t serr; 163 uint32_t sact; 164 uint32_t ci; 165 uint32_t sntf; 166 uint32_t fbs; 167 168 /* 169 * i/o request info 170 */ 171 struct ahci_ioreq *ioreq; 172 int ioqsz; 173 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 174 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd; 175}; 176 177struct ahci_cmd_hdr { 178 uint16_t flags; 179 uint16_t prdtl; 180 uint32_t prdbc; 181 uint64_t ctba; 182 uint32_t reserved[4]; 183}; 184 185struct ahci_prdt_entry { 186 uint64_t dba; 187 uint32_t reserved; 188#define DBCMASK 0x3fffff 189 uint32_t dbc; 190}; 191 192struct pci_ahci_softc { 193 struct pci_devinst *asc_pi; 194 pthread_mutex_t mtx; 195 int ports; 196 uint32_t cap; 197 uint32_t ghc; 198 uint32_t is; 199 uint32_t pi; 200 uint32_t vs; 201 uint32_t ccc_ctl; 202 uint32_t ccc_pts; 203 uint32_t em_loc; 204 uint32_t em_ctl; 205 uint32_t cap2; 206 uint32_t bohc; 207 uint32_t lintr; 208 struct ahci_port port[MAX_PORTS]; 209}; 210#define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 211 212static void ahci_handle_port(struct ahci_port *p); 213 214static inline void lba_to_msf(uint8_t *buf, int lba) 215{ 216 lba += 150; 217 buf[0] = (lba / 75) / 60; 218 buf[1] = (lba / 75) % 60; 219 buf[2] = lba % 75; 220} 221 222/* 223 * Generate HBA interrupts on global IS register write. 224 */ 225static void 226ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask) 227{ 228 struct pci_devinst *pi = sc->asc_pi; 229 struct ahci_port *p; 230 int i, nmsg; 231 uint32_t mmask; 232 233 /* Update global IS from PxIS/PxIE. */ 234 for (i = 0; i < sc->ports; i++) { 235 p = &sc->port[i]; 236 if (p->is & p->ie) 237 sc->is |= (1 << i); 238 } 239 DPRINTF("%s(%08x) %08x\n", __func__, mask, sc->is); 240 241 /* If there is nothing enabled -- clear legacy interrupt and exit. */ 242 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) { 243 if (sc->lintr) { 244 pci_lintr_deassert(pi); 245 sc->lintr = 0; 246 } 247 return; 248 } 249 250 /* If there is anything and no MSI -- assert legacy interrupt. */ 251 nmsg = pci_msi_maxmsgnum(pi); 252 if (nmsg == 0) { 253 if (!sc->lintr) { 254 sc->lintr = 1; 255 pci_lintr_assert(pi); 256 } 257 return; 258 } 259 260 /* Assert respective MSIs for ports that were touched. */ 261 for (i = 0; i < nmsg; i++) { 262 if (sc->ports <= nmsg || i < nmsg - 1) 263 mmask = 1 << i; 264 else 265 mmask = 0xffffffff << i; 266 if (sc->is & mask && mmask & mask) 267 pci_generate_msi(pi, i); 268 } 269} 270 271/* 272 * Generate HBA interrupt on specific port event. 273 */ 274static void 275ahci_port_intr(struct ahci_port *p) 276{ 277 struct pci_ahci_softc *sc = p->pr_sc; 278 struct pci_devinst *pi = sc->asc_pi; 279 int nmsg; 280 281 DPRINTF("%s(%d) %08x/%08x %08x\n", __func__, 282 p->port, p->is, p->ie, sc->is); 283 284 /* If there is nothing enabled -- we are done. */ 285 if ((p->is & p->ie) == 0) 286 return; 287 288 /* In case of non-shared MSI always generate interrupt. */ 289 nmsg = pci_msi_maxmsgnum(pi); 290 if (sc->ports <= nmsg || p->port < nmsg - 1) { 291 sc->is |= (1 << p->port); 292 if ((sc->ghc & AHCI_GHC_IE) == 0) 293 return; 294 pci_generate_msi(pi, p->port); 295 return; 296 } 297 298 /* If IS for this port is already set -- do nothing. */ 299 if (sc->is & (1 << p->port)) 300 return; 301 302 sc->is |= (1 << p->port); 303 304 /* If interrupts are enabled -- generate one. */ 305 if ((sc->ghc & AHCI_GHC_IE) == 0) 306 return; 307 if (nmsg > 0) { 308 pci_generate_msi(pi, nmsg - 1); 309 } else if (!sc->lintr) { 310 sc->lintr = 1; 311 pci_lintr_assert(pi); 312 } 313} 314 315static void 316ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 317{ 318 int offset, len, irq; 319 320 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 321 return; 322 323 switch (ft) { 324 case FIS_TYPE_REGD2H: 325 offset = 0x40; 326 len = 20; 327 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0; 328 break; 329 case FIS_TYPE_SETDEVBITS: 330 offset = 0x58; 331 len = 8; 332 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0; 333 break; 334 case FIS_TYPE_PIOSETUP: 335 offset = 0x20; 336 len = 20; 337 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0; 338 break; 339 default: 340 WPRINTF("unsupported fis type %d\n", ft); 341 return; 342 } 343 if (fis[2] & ATA_S_ERROR) { 344 p->waitforclear = 1; 345 irq |= AHCI_P_IX_TFE; 346 } 347 memcpy(p->rfis + offset, fis, len); 348 if (irq) { 349 if (~p->is & irq) { 350 p->is |= irq; 351 ahci_port_intr(p); 352 } 353 } 354} 355 356static void 357ahci_write_fis_piosetup(struct ahci_port *p) 358{ 359 uint8_t fis[20]; 360 361 memset(fis, 0, sizeof(fis)); 362 fis[0] = FIS_TYPE_PIOSETUP; 363 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 364} 365 366static void 367ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 368{ 369 uint8_t fis[8]; 370 uint8_t error; 371 372 error = (tfd >> 8) & 0xff; 373 tfd &= 0x77; 374 memset(fis, 0, sizeof(fis)); 375 fis[0] = FIS_TYPE_SETDEVBITS; 376 fis[1] = (1 << 6); 377 fis[2] = tfd; 378 fis[3] = error; 379 if (fis[2] & ATA_S_ERROR) { 380 p->err_cfis[0] = slot; 381 p->err_cfis[2] = tfd; 382 p->err_cfis[3] = error; 383 memcpy(&p->err_cfis[4], cfis + 4, 16); 384 } else { 385 *(uint32_t *)(fis + 4) = (1 << slot); 386 p->sact &= ~(1 << slot); 387 } 388 p->tfd &= ~0x77; 389 p->tfd |= tfd; 390 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 391} 392 393static void 394ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 395{ 396 uint8_t fis[20]; 397 uint8_t error; 398 399 error = (tfd >> 8) & 0xff; 400 memset(fis, 0, sizeof(fis)); 401 fis[0] = FIS_TYPE_REGD2H; 402 fis[1] = (1 << 6); 403 fis[2] = tfd & 0xff; 404 fis[3] = error; 405 fis[4] = cfis[4]; 406 fis[5] = cfis[5]; 407 fis[6] = cfis[6]; 408 fis[7] = cfis[7]; 409 fis[8] = cfis[8]; 410 fis[9] = cfis[9]; 411 fis[10] = cfis[10]; 412 fis[11] = cfis[11]; 413 fis[12] = cfis[12]; 414 fis[13] = cfis[13]; 415 if (fis[2] & ATA_S_ERROR) { 416 p->err_cfis[0] = 0x80; 417 p->err_cfis[2] = tfd & 0xff; 418 p->err_cfis[3] = error; 419 memcpy(&p->err_cfis[4], cfis + 4, 16); 420 } else 421 p->ci &= ~(1 << slot); 422 p->tfd = tfd; 423 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 424} 425 426static void 427ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot) 428{ 429 uint8_t fis[20]; 430 431 p->tfd = ATA_S_READY | ATA_S_DSC; 432 memset(fis, 0, sizeof(fis)); 433 fis[0] = FIS_TYPE_REGD2H; 434 fis[1] = 0; /* No interrupt */ 435 fis[2] = p->tfd; /* Status */ 436 fis[3] = 0; /* No error */ 437 p->ci &= ~(1 << slot); 438 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 439} 440 441static void 442ahci_write_reset_fis_d2h(struct ahci_port *p) 443{ 444 uint8_t fis[20]; 445 446 memset(fis, 0, sizeof(fis)); 447 fis[0] = FIS_TYPE_REGD2H; 448 fis[3] = 1; 449 fis[4] = 1; 450 if (p->atapi) { 451 fis[5] = 0x14; 452 fis[6] = 0xeb; 453 } 454 fis[12] = 1; 455 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 456} 457 458static void 459ahci_check_stopped(struct ahci_port *p) 460{ 461 /* 462 * If we are no longer processing the command list and nothing 463 * is in-flight, clear the running bit, the current command 464 * slot, the command issue and active bits. 465 */ 466 if (!(p->cmd & AHCI_P_CMD_ST)) { 467 if (p->pending == 0) { 468 p->ccs = 0; 469 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 470 p->ci = 0; 471 p->sact = 0; 472 p->waitforclear = 0; 473 } 474 } 475} 476 477static void 478ahci_port_stop(struct ahci_port *p) 479{ 480 struct ahci_ioreq *aior; 481 uint8_t *cfis; 482 int slot; 483 int ncq; 484 int error; 485 486 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx)); 487 488 TAILQ_FOREACH(aior, &p->iobhd, io_blist) { 489 /* 490 * Try to cancel the outstanding blockif request. 491 */ 492 error = blockif_cancel(p->bctx, &aior->io_req); 493 if (error != 0) 494 continue; 495 496 slot = aior->slot; 497 cfis = aior->cfis; 498 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 499 cfis[2] == ATA_READ_FPDMA_QUEUED || 500 cfis[2] == ATA_SEND_FPDMA_QUEUED) 501 ncq = 1; 502 503 if (ncq) 504 p->sact &= ~(1 << slot); 505 else 506 p->ci &= ~(1 << slot); 507 508 /* 509 * This command is now done. 510 */ 511 p->pending &= ~(1 << slot); 512 513 /* 514 * Delete the blockif request from the busy list 515 */ 516 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 517 518 /* 519 * Move the blockif request back to the free list 520 */ 521 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 522 } 523 524 ahci_check_stopped(p); 525} 526 527static void 528ahci_port_reset(struct ahci_port *pr) 529{ 530 pr->serr = 0; 531 pr->sact = 0; 532 pr->xfermode = ATA_UDMA6; 533 pr->mult_sectors = 128; 534 535 if (!pr->bctx) { 536 pr->ssts = ATA_SS_DET_NO_DEVICE; 537 pr->sig = 0xFFFFFFFF; 538 pr->tfd = 0x7F; 539 return; 540 } 541 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE; 542 if (pr->sctl & ATA_SC_SPD_MASK) 543 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK); 544 else 545 pr->ssts |= ATA_SS_SPD_GEN3; 546 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 547 if (!pr->atapi) { 548 pr->sig = PxSIG_ATA; 549 pr->tfd |= ATA_S_READY; 550 } else 551 pr->sig = PxSIG_ATAPI; 552 ahci_write_reset_fis_d2h(pr); 553} 554 555static void 556ahci_reset(struct pci_ahci_softc *sc) 557{ 558 int i; 559 560 sc->ghc = AHCI_GHC_AE; 561 sc->is = 0; 562 563 if (sc->lintr) { 564 pci_lintr_deassert(sc->asc_pi); 565 sc->lintr = 0; 566 } 567 568 for (i = 0; i < sc->ports; i++) { 569 sc->port[i].ie = 0; 570 sc->port[i].is = 0; 571 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD); 572 if (sc->port[i].bctx) 573 sc->port[i].cmd |= AHCI_P_CMD_CPS; 574 sc->port[i].sctl = 0; 575 ahci_port_reset(&sc->port[i]); 576 } 577} 578 579static void 580ata_string(uint8_t *dest, const char *src, int len) 581{ 582 int i; 583 584 for (i = 0; i < len; i++) { 585 if (*src) 586 dest[i ^ 1] = *src++; 587 else 588 dest[i ^ 1] = ' '; 589 } 590} 591 592static void 593atapi_string(uint8_t *dest, const char *src, int len) 594{ 595 int i; 596 597 for (i = 0; i < len; i++) { 598 if (*src) 599 dest[i] = *src++; 600 else 601 dest[i] = ' '; 602 } 603} 604 605/* 606 * Build up the iovec based on the PRDT, 'done' and 'len'. 607 */ 608static void 609ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior, 610 struct ahci_prdt_entry *prdt, uint16_t prdtl) 611{ 612 struct blockif_req *breq = &aior->io_req; 613 int i, j, skip, todo, left, extra; 614 uint32_t dbcsz; 615 616 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */ 617 skip = aior->done; 618 left = aior->len - aior->done; 619 todo = 0; 620 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0; 621 i++, prdt++) { 622 dbcsz = (prdt->dbc & DBCMASK) + 1; 623 /* Skip already done part of the PRDT */ 624 if (dbcsz <= skip) { 625 skip -= dbcsz; 626 continue; 627 } 628 dbcsz -= skip; 629 if (dbcsz > left) 630 dbcsz = left; 631 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc), 632 prdt->dba + skip, dbcsz); 633 breq->br_iov[j].iov_len = dbcsz; 634 todo += dbcsz; 635 left -= dbcsz; 636 skip = 0; 637 j++; 638 } 639 640 /* If we got limited by IOV length, round I/O down to sector size. */ 641 if (j == BLOCKIF_IOV_MAX) { 642 extra = todo % blockif_sectsz(p->bctx); 643 todo -= extra; 644 assert(todo > 0); 645 while (extra > 0) { 646 if (breq->br_iov[j - 1].iov_len > extra) { 647 breq->br_iov[j - 1].iov_len -= extra; 648 break; 649 } 650 extra -= breq->br_iov[j - 1].iov_len; 651 j--; 652 } 653 } 654 655 breq->br_iovcnt = j; 656 breq->br_resid = todo; 657 aior->done += todo; 658 aior->more = (aior->done < aior->len && i < prdtl); 659} 660 661static void 662ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 663{ 664 struct ahci_ioreq *aior; 665 struct blockif_req *breq; 666 struct ahci_prdt_entry *prdt; 667 struct ahci_cmd_hdr *hdr; 668 uint64_t lba; 669 uint32_t len; 670 int err, first, ncq, readop; 671 672 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 673 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 674 ncq = 0; 675 readop = 1; 676 first = (done == 0); 677 678 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 || 679 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 || 680 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 681 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 682 readop = 0; 683 684 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 685 cfis[2] == ATA_READ_FPDMA_QUEUED) { 686 lba = ((uint64_t)cfis[10] << 40) | 687 ((uint64_t)cfis[9] << 32) | 688 ((uint64_t)cfis[8] << 24) | 689 ((uint64_t)cfis[6] << 16) | 690 ((uint64_t)cfis[5] << 8) | 691 cfis[4]; 692 len = cfis[11] << 8 | cfis[3]; 693 if (!len) 694 len = 65536; 695 ncq = 1; 696 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 || 697 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 || 698 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 699 lba = ((uint64_t)cfis[10] << 40) | 700 ((uint64_t)cfis[9] << 32) | 701 ((uint64_t)cfis[8] << 24) | 702 ((uint64_t)cfis[6] << 16) | 703 ((uint64_t)cfis[5] << 8) | 704 cfis[4]; 705 len = cfis[13] << 8 | cfis[12]; 706 if (!len) 707 len = 65536; 708 } else { 709 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 710 (cfis[5] << 8) | cfis[4]; 711 len = cfis[12]; 712 if (!len) 713 len = 256; 714 } 715 lba *= blockif_sectsz(p->bctx); 716 len *= blockif_sectsz(p->bctx); 717 718 /* Pull request off free list */ 719 aior = STAILQ_FIRST(&p->iofhd); 720 assert(aior != NULL); 721 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 722 723 aior->cfis = cfis; 724 aior->slot = slot; 725 aior->len = len; 726 aior->done = done; 727 breq = &aior->io_req; 728 breq->br_offset = lba + done; 729 ahci_build_iov(p, aior, prdt, hdr->prdtl); 730 731 /* Mark this command in-flight. */ 732 p->pending |= 1 << slot; 733 734 /* Stuff request onto busy list. */ 735 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 736 737 if (ncq && first) 738 ahci_write_fis_d2h_ncq(p, slot); 739 740 if (readop) 741 err = blockif_read(p->bctx, breq); 742 else 743 err = blockif_write(p->bctx, breq); 744 assert(err == 0); 745} 746 747static void 748ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 749{ 750 struct ahci_ioreq *aior; 751 struct blockif_req *breq; 752 int err; 753 754 /* 755 * Pull request off free list 756 */ 757 aior = STAILQ_FIRST(&p->iofhd); 758 assert(aior != NULL); 759 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 760 aior->cfis = cfis; 761 aior->slot = slot; 762 aior->len = 0; 763 aior->done = 0; 764 aior->more = 0; 765 breq = &aior->io_req; 766 767 /* 768 * Mark this command in-flight. 769 */ 770 p->pending |= 1 << slot; 771 772 /* 773 * Stuff request onto busy list 774 */ 775 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 776 777 err = blockif_flush(p->bctx, breq); 778 assert(err == 0); 779} 780 781static inline void 782read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 783 void *buf, int size) 784{ 785 struct ahci_cmd_hdr *hdr; 786 struct ahci_prdt_entry *prdt; 787 void *to; 788 int i, len; 789 790 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 791 len = size; 792 to = buf; 793 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 794 for (i = 0; i < hdr->prdtl && len; i++) { 795 uint8_t *ptr; 796 uint32_t dbcsz; 797 int sublen; 798 799 dbcsz = (prdt->dbc & DBCMASK) + 1; 800 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 801 sublen = MIN(len, dbcsz); 802 memcpy(to, ptr, sublen); 803 len -= sublen; 804 to += sublen; 805 prdt++; 806 } 807} 808 809static void 810ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 811{ 812 struct ahci_ioreq *aior; 813 struct blockif_req *breq; 814 uint8_t *entry; 815 uint64_t elba; 816 uint32_t len, elen; 817 int err, first, ncq; 818 uint8_t buf[512]; 819 820 first = (done == 0); 821 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) { 822 len = (uint16_t)cfis[13] << 8 | cfis[12]; 823 len *= 512; 824 ncq = 0; 825 } else { /* ATA_SEND_FPDMA_QUEUED */ 826 len = (uint16_t)cfis[11] << 8 | cfis[3]; 827 len *= 512; 828 ncq = 1; 829 } 830 read_prdt(p, slot, cfis, buf, sizeof(buf)); 831 832next: 833 entry = &buf[done]; 834 elba = ((uint64_t)entry[5] << 40) | 835 ((uint64_t)entry[4] << 32) | 836 ((uint64_t)entry[3] << 24) | 837 ((uint64_t)entry[2] << 16) | 838 ((uint64_t)entry[1] << 8) | 839 entry[0]; 840 elen = (uint16_t)entry[7] << 8 | entry[6]; 841 done += 8; 842 if (elen == 0) { 843 if (done >= len) { 844 if (ncq) { 845 if (first) 846 ahci_write_fis_d2h_ncq(p, slot); 847 ahci_write_fis_sdb(p, slot, cfis, 848 ATA_S_READY | ATA_S_DSC); 849 } else { 850 ahci_write_fis_d2h(p, slot, cfis, 851 ATA_S_READY | ATA_S_DSC); 852 } 853 p->pending &= ~(1 << slot); 854 ahci_check_stopped(p); 855 if (!first) 856 ahci_handle_port(p); 857 return; 858 } 859 goto next; 860 } 861 862 /* 863 * Pull request off free list 864 */ 865 aior = STAILQ_FIRST(&p->iofhd); 866 assert(aior != NULL); 867 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 868 aior->cfis = cfis; 869 aior->slot = slot; 870 aior->len = len; 871 aior->done = done; 872 aior->more = (len != done); 873 874 breq = &aior->io_req; 875 breq->br_offset = elba * blockif_sectsz(p->bctx); 876 breq->br_resid = elen * blockif_sectsz(p->bctx); 877 878 /* 879 * Mark this command in-flight. 880 */ 881 p->pending |= 1 << slot; 882 883 /* 884 * Stuff request onto busy list 885 */ 886 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 887 888 if (ncq && first) 889 ahci_write_fis_d2h_ncq(p, slot); 890 891 err = blockif_delete(p->bctx, breq); 892 assert(err == 0); 893} 894 895static inline void 896write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 897 void *buf, int size) 898{ 899 struct ahci_cmd_hdr *hdr; 900 struct ahci_prdt_entry *prdt; 901 void *from; 902 int i, len; 903 904 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 905 len = size; 906 from = buf; 907 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 908 for (i = 0; i < hdr->prdtl && len; i++) { 909 uint8_t *ptr; 910 uint32_t dbcsz; 911 int sublen; 912 913 dbcsz = (prdt->dbc & DBCMASK) + 1; 914 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 915 sublen = MIN(len, dbcsz); 916 memcpy(ptr, from, sublen); 917 len -= sublen; 918 from += sublen; 919 prdt++; 920 } 921 hdr->prdbc = size - len; 922} 923 924static void 925ahci_checksum(uint8_t *buf, int size) 926{ 927 int i; 928 uint8_t sum = 0; 929 930 for (i = 0; i < size - 1; i++) 931 sum += buf[i]; 932 buf[size - 1] = 0x100 - sum; 933} 934 935static void 936ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis) 937{ 938 struct ahci_cmd_hdr *hdr; 939 uint32_t buf[128]; 940 uint8_t *buf8 = (uint8_t *)buf; 941 uint16_t *buf16 = (uint16_t *)buf; 942 943 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 944 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 || 945 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) { 946 ahci_write_fis_d2h(p, slot, cfis, 947 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 948 return; 949 } 950 951 memset(buf, 0, sizeof(buf)); 952 if (cfis[4] == 0x00) { /* Log directory */ 953 buf16[0x00] = 1; /* Version -- 1 */ 954 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */ 955 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */ 956 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */ 957 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis)); 958 ahci_checksum(buf8, sizeof(buf)); 959 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */ 960 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) { 961 buf[0x00] = 1; /* SFQ DSM supported */ 962 buf[0x01] = 1; /* SFQ DSM TRIM supported */ 963 } 964 } else { 965 ahci_write_fis_d2h(p, slot, cfis, 966 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 967 return; 968 } 969 970 if (cfis[2] == ATA_READ_LOG_EXT) 971 ahci_write_fis_piosetup(p); 972 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 973 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 974} 975 976static void 977handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 978{ 979 struct ahci_cmd_hdr *hdr; 980 981 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 982 if (p->atapi || hdr->prdtl == 0) { 983 ahci_write_fis_d2h(p, slot, cfis, 984 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 985 } else { 986 uint16_t buf[256]; 987 uint64_t sectors; 988 int sectsz, psectsz, psectoff, candelete, ro; 989 uint16_t cyl; 990 uint8_t sech, heads; 991 992 ro = blockif_is_ro(p->bctx); 993 candelete = blockif_candelete(p->bctx); 994 sectsz = blockif_sectsz(p->bctx); 995 sectors = blockif_size(p->bctx) / sectsz; 996 blockif_chs(p->bctx, &cyl, &heads, &sech); 997 blockif_psectsz(p->bctx, &psectsz, &psectoff); 998 memset(buf, 0, sizeof(buf)); 999 buf[0] = 0x0040; 1000 buf[1] = cyl; 1001 buf[3] = heads; 1002 buf[6] = sech; 1003 ata_string((uint8_t *)(buf+10), p->ident, 20); 1004 ata_string((uint8_t *)(buf+23), "001", 8); 1005 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40); 1006 buf[47] = (0x8000 | 128); 1007 buf[48] = 0; 1008 buf[49] = (1 << 8 | 1 << 9 | 1 << 11); 1009 buf[50] = (1 << 14); 1010 buf[53] = (1 << 1 | 1 << 2); 1011 if (p->mult_sectors) 1012 buf[59] = (0x100 | p->mult_sectors); 1013 if (sectors <= 0x0fffffff) { 1014 buf[60] = sectors; 1015 buf[61] = (sectors >> 16); 1016 } else { 1017 buf[60] = 0xffff; 1018 buf[61] = 0x0fff; 1019 } 1020 buf[63] = 0x7; 1021 if (p->xfermode & ATA_WDMA0) 1022 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 1023 buf[64] = 0x3; 1024 buf[65] = 120; 1025 buf[66] = 120; 1026 buf[67] = 120; 1027 buf[68] = 120; 1028 buf[69] = 0; 1029 buf[75] = 31; 1030 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 | 1031 ATA_SUPPORT_NCQ); 1032 buf[77] = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED | 1033 (p->ssts & ATA_SS_SPD_MASK) >> 3); 1034 buf[80] = 0x3f0; 1035 buf[81] = 0x28; 1036 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE| 1037 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 1038 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 1039 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14); 1040 buf[84] = (1 << 14); 1041 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE| 1042 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 1043 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 1044 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15); 1045 buf[87] = (1 << 14); 1046 buf[88] = 0x7f; 1047 if (p->xfermode & ATA_UDMA0) 1048 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 1049 buf[100] = sectors; 1050 buf[101] = (sectors >> 16); 1051 buf[102] = (sectors >> 32); 1052 buf[103] = (sectors >> 48); 1053 if (candelete && !ro) { 1054 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT; 1055 buf[105] = 1; 1056 buf[169] = ATA_SUPPORT_DSM_TRIM; 1057 } 1058 buf[106] = 0x4000; 1059 buf[209] = 0x4000; 1060 if (psectsz > sectsz) { 1061 buf[106] |= 0x2000; 1062 buf[106] |= ffsl(psectsz / sectsz) - 1; 1063 buf[209] |= (psectoff / sectsz); 1064 } 1065 if (sectsz > 512) { 1066 buf[106] |= 0x1000; 1067 buf[117] = sectsz / 2; 1068 buf[118] = ((sectsz / 2) >> 16); 1069 } 1070 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14); 1071 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14); 1072 buf[222] = 0x1020; 1073 buf[255] = 0x00a5; 1074 ahci_checksum((uint8_t *)buf, sizeof(buf)); 1075 ahci_write_fis_piosetup(p); 1076 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 1077 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1078 } 1079} 1080 1081static void 1082handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 1083{ 1084 if (!p->atapi) { 1085 ahci_write_fis_d2h(p, slot, cfis, 1086 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1087 } else { 1088 uint16_t buf[256]; 1089 1090 memset(buf, 0, sizeof(buf)); 1091 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5); 1092 ata_string((uint8_t *)(buf+10), p->ident, 20); 1093 ata_string((uint8_t *)(buf+23), "001", 8); 1094 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40); 1095 buf[49] = (1 << 9 | 1 << 8); 1096 buf[50] = (1 << 14 | 1); 1097 buf[53] = (1 << 2 | 1 << 1); 1098 buf[62] = 0x3f; 1099 buf[63] = 7; 1100 if (p->xfermode & ATA_WDMA0) 1101 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 1102 buf[64] = 3; 1103 buf[65] = 120; 1104 buf[66] = 120; 1105 buf[67] = 120; 1106 buf[68] = 120; 1107 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3); 1108 buf[77] = ((p->ssts & ATA_SS_SPD_MASK) >> 3); 1109 buf[78] = (1 << 5); 1110 buf[80] = 0x3f0; 1111 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET | 1112 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP); 1113 buf[83] = (1 << 14); 1114 buf[84] = (1 << 14); 1115 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET | 1116 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP); 1117 buf[87] = (1 << 14); 1118 buf[88] = 0x7f; 1119 if (p->xfermode & ATA_UDMA0) 1120 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 1121 buf[222] = 0x1020; 1122 buf[255] = 0x00a5; 1123 ahci_checksum((uint8_t *)buf, sizeof(buf)); 1124 ahci_write_fis_piosetup(p); 1125 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 1126 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1127 } 1128} 1129 1130static void 1131atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 1132{ 1133 uint8_t buf[36]; 1134 uint8_t *acmd; 1135 int len; 1136 uint32_t tfd; 1137 1138 acmd = cfis + 0x40; 1139 1140 if (acmd[1] & 1) { /* VPD */ 1141 if (acmd[2] == 0) { /* Supported VPD pages */ 1142 buf[0] = 0x05; 1143 buf[1] = 0; 1144 buf[2] = 0; 1145 buf[3] = 1; 1146 buf[4] = 0; 1147 len = 4 + buf[3]; 1148 } else { 1149 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1150 p->asc = 0x24; 1151 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1152 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1153 ahci_write_fis_d2h(p, slot, cfis, tfd); 1154 return; 1155 } 1156 } else { 1157 buf[0] = 0x05; 1158 buf[1] = 0x80; 1159 buf[2] = 0x00; 1160 buf[3] = 0x21; 1161 buf[4] = 31; 1162 buf[5] = 0; 1163 buf[6] = 0; 1164 buf[7] = 0; 1165 atapi_string(buf + 8, "BHYVE", 8); 1166 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 1167 atapi_string(buf + 32, "001", 4); 1168 len = sizeof(buf); 1169 } 1170 1171 if (len > acmd[4]) 1172 len = acmd[4]; 1173 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1174 write_prdt(p, slot, cfis, buf, len); 1175 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1176} 1177 1178static void 1179atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 1180{ 1181 uint8_t buf[8]; 1182 uint64_t sectors; 1183 1184 sectors = blockif_size(p->bctx) / 2048; 1185 be32enc(buf, sectors - 1); 1186 be32enc(buf + 4, 2048); 1187 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1188 write_prdt(p, slot, cfis, buf, sizeof(buf)); 1189 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1190} 1191 1192static void 1193atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 1194{ 1195 uint8_t *acmd; 1196 uint8_t format; 1197 int len; 1198 1199 acmd = cfis + 0x40; 1200 1201 len = be16dec(acmd + 7); 1202 format = acmd[9] >> 6; 1203 switch (format) { 1204 case 0: 1205 { 1206 int msf, size; 1207 uint64_t sectors; 1208 uint8_t start_track, buf[20], *bp; 1209 1210 msf = (acmd[1] >> 1) & 1; 1211 start_track = acmd[6]; 1212 if (start_track > 1 && start_track != 0xaa) { 1213 uint32_t tfd; 1214 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1215 p->asc = 0x24; 1216 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1217 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1218 ahci_write_fis_d2h(p, slot, cfis, tfd); 1219 return; 1220 } 1221 bp = buf + 2; 1222 *bp++ = 1; 1223 *bp++ = 1; 1224 if (start_track <= 1) { 1225 *bp++ = 0; 1226 *bp++ = 0x14; 1227 *bp++ = 1; 1228 *bp++ = 0; 1229 if (msf) { 1230 *bp++ = 0; 1231 lba_to_msf(bp, 0); 1232 bp += 3; 1233 } else { 1234 *bp++ = 0; 1235 *bp++ = 0; 1236 *bp++ = 0; 1237 *bp++ = 0; 1238 } 1239 } 1240 *bp++ = 0; 1241 *bp++ = 0x14; 1242 *bp++ = 0xaa; 1243 *bp++ = 0; 1244 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1245 sectors >>= 2; 1246 if (msf) { 1247 *bp++ = 0; 1248 lba_to_msf(bp, sectors); 1249 bp += 3; 1250 } else { 1251 be32enc(bp, sectors); 1252 bp += 4; 1253 } 1254 size = bp - buf; 1255 be16enc(buf, size - 2); 1256 if (len > size) 1257 len = size; 1258 write_prdt(p, slot, cfis, buf, len); 1259 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1260 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1261 break; 1262 } 1263 case 1: 1264 { 1265 uint8_t buf[12]; 1266 1267 memset(buf, 0, sizeof(buf)); 1268 buf[1] = 0xa; 1269 buf[2] = 0x1; 1270 buf[3] = 0x1; 1271 if (len > sizeof(buf)) 1272 len = sizeof(buf); 1273 write_prdt(p, slot, cfis, buf, len); 1274 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1275 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1276 break; 1277 } 1278 case 2: 1279 { 1280 int msf, size; 1281 uint64_t sectors; 1282 uint8_t start_track, *bp, buf[50]; 1283 1284 msf = (acmd[1] >> 1) & 1; 1285 start_track = acmd[6]; 1286 bp = buf + 2; 1287 *bp++ = 1; 1288 *bp++ = 1; 1289 1290 *bp++ = 1; 1291 *bp++ = 0x14; 1292 *bp++ = 0; 1293 *bp++ = 0xa0; 1294 *bp++ = 0; 1295 *bp++ = 0; 1296 *bp++ = 0; 1297 *bp++ = 0; 1298 *bp++ = 1; 1299 *bp++ = 0; 1300 *bp++ = 0; 1301 1302 *bp++ = 1; 1303 *bp++ = 0x14; 1304 *bp++ = 0; 1305 *bp++ = 0xa1; 1306 *bp++ = 0; 1307 *bp++ = 0; 1308 *bp++ = 0; 1309 *bp++ = 0; 1310 *bp++ = 1; 1311 *bp++ = 0; 1312 *bp++ = 0; 1313 1314 *bp++ = 1; 1315 *bp++ = 0x14; 1316 *bp++ = 0; 1317 *bp++ = 0xa2; 1318 *bp++ = 0; 1319 *bp++ = 0; 1320 *bp++ = 0; 1321 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1322 sectors >>= 2; 1323 if (msf) { 1324 *bp++ = 0; 1325 lba_to_msf(bp, sectors); 1326 bp += 3; 1327 } else { 1328 be32enc(bp, sectors); 1329 bp += 4; 1330 } 1331 1332 *bp++ = 1; 1333 *bp++ = 0x14; 1334 *bp++ = 0; 1335 *bp++ = 1; 1336 *bp++ = 0; 1337 *bp++ = 0; 1338 *bp++ = 0; 1339 if (msf) { 1340 *bp++ = 0; 1341 lba_to_msf(bp, 0); 1342 bp += 3; 1343 } else { 1344 *bp++ = 0; 1345 *bp++ = 0; 1346 *bp++ = 0; 1347 *bp++ = 0; 1348 } 1349 1350 size = bp - buf; 1351 be16enc(buf, size - 2); 1352 if (len > size) 1353 len = size; 1354 write_prdt(p, slot, cfis, buf, len); 1355 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1356 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1357 break; 1358 } 1359 default: 1360 { 1361 uint32_t tfd; 1362 1363 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1364 p->asc = 0x24; 1365 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1366 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1367 ahci_write_fis_d2h(p, slot, cfis, tfd); 1368 break; 1369 } 1370 } 1371} 1372 1373static void 1374atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis) 1375{ 1376 uint8_t buf[16]; 1377 1378 memset(buf, 0, sizeof(buf)); 1379 buf[3] = 8; 1380 1381 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1382 write_prdt(p, slot, cfis, buf, sizeof(buf)); 1383 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1384} 1385 1386static void 1387atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 1388{ 1389 struct ahci_ioreq *aior; 1390 struct ahci_cmd_hdr *hdr; 1391 struct ahci_prdt_entry *prdt; 1392 struct blockif_req *breq; 1393 struct pci_ahci_softc *sc; 1394 uint8_t *acmd; 1395 uint64_t lba; 1396 uint32_t len; 1397 int err; 1398 1399 sc = p->pr_sc; 1400 acmd = cfis + 0x40; 1401 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1402 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1403 1404 lba = be32dec(acmd + 2); 1405 if (acmd[0] == READ_10) 1406 len = be16dec(acmd + 7); 1407 else 1408 len = be32dec(acmd + 6); 1409 if (len == 0) { 1410 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1411 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1412 } 1413 lba *= 2048; 1414 len *= 2048; 1415 1416 /* 1417 * Pull request off free list 1418 */ 1419 aior = STAILQ_FIRST(&p->iofhd); 1420 assert(aior != NULL); 1421 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 1422 aior->cfis = cfis; 1423 aior->slot = slot; 1424 aior->len = len; 1425 aior->done = done; 1426 breq = &aior->io_req; 1427 breq->br_offset = lba + done; 1428 ahci_build_iov(p, aior, prdt, hdr->prdtl); 1429 1430 /* Mark this command in-flight. */ 1431 p->pending |= 1 << slot; 1432 1433 /* Stuff request onto busy list. */ 1434 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 1435 1436 err = blockif_read(p->bctx, breq); 1437 assert(err == 0); 1438} 1439 1440static void 1441atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1442{ 1443 uint8_t buf[64]; 1444 uint8_t *acmd; 1445 int len; 1446 1447 acmd = cfis + 0x40; 1448 len = acmd[4]; 1449 if (len > sizeof(buf)) 1450 len = sizeof(buf); 1451 memset(buf, 0, len); 1452 buf[0] = 0x70 | (1 << 7); 1453 buf[2] = p->sense_key; 1454 buf[7] = 10; 1455 buf[12] = p->asc; 1456 write_prdt(p, slot, cfis, buf, len); 1457 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1458 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1459} 1460 1461static void 1462atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1463{ 1464 uint8_t *acmd = cfis + 0x40; 1465 uint32_t tfd; 1466 1467 switch (acmd[4] & 3) { 1468 case 0: 1469 case 1: 1470 case 3: 1471 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1472 tfd = ATA_S_READY | ATA_S_DSC; 1473 break; 1474 case 2: 1475 /* TODO eject media */ 1476 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1477 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1478 p->asc = 0x53; 1479 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1480 break; 1481 } 1482 ahci_write_fis_d2h(p, slot, cfis, tfd); 1483} 1484 1485static void 1486atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1487{ 1488 uint8_t *acmd; 1489 uint32_t tfd; 1490 uint8_t pc, code; 1491 int len; 1492 1493 acmd = cfis + 0x40; 1494 len = be16dec(acmd + 7); 1495 pc = acmd[2] >> 6; 1496 code = acmd[2] & 0x3f; 1497 1498 switch (pc) { 1499 case 0: 1500 switch (code) { 1501 case MODEPAGE_RW_ERROR_RECOVERY: 1502 { 1503 uint8_t buf[16]; 1504 1505 if (len > sizeof(buf)) 1506 len = sizeof(buf); 1507 1508 memset(buf, 0, sizeof(buf)); 1509 be16enc(buf, 16 - 2); 1510 buf[2] = 0x70; 1511 buf[8] = 0x01; 1512 buf[9] = 16 - 10; 1513 buf[11] = 0x05; 1514 write_prdt(p, slot, cfis, buf, len); 1515 tfd = ATA_S_READY | ATA_S_DSC; 1516 break; 1517 } 1518 case MODEPAGE_CD_CAPABILITIES: 1519 { 1520 uint8_t buf[30]; 1521 1522 if (len > sizeof(buf)) 1523 len = sizeof(buf); 1524 1525 memset(buf, 0, sizeof(buf)); 1526 be16enc(buf, 30 - 2); 1527 buf[2] = 0x70; 1528 buf[8] = 0x2A; 1529 buf[9] = 30 - 10; 1530 buf[10] = 0x08; 1531 buf[12] = 0x71; 1532 be16enc(&buf[18], 2); 1533 be16enc(&buf[20], 512); 1534 write_prdt(p, slot, cfis, buf, len); 1535 tfd = ATA_S_READY | ATA_S_DSC; 1536 break; 1537 } 1538 default: 1539 goto error; 1540 break; 1541 } 1542 break; 1543 case 3: 1544 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1545 p->asc = 0x39; 1546 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1547 break; 1548error: 1549 case 1: 1550 case 2: 1551 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1552 p->asc = 0x24; 1553 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1554 break; 1555 } 1556 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1557 ahci_write_fis_d2h(p, slot, cfis, tfd); 1558} 1559 1560static void 1561atapi_get_event_status_notification(struct ahci_port *p, int slot, 1562 uint8_t *cfis) 1563{ 1564 uint8_t *acmd; 1565 uint32_t tfd; 1566 1567 acmd = cfis + 0x40; 1568 1569 /* we don't support asynchronous operation */ 1570 if (!(acmd[1] & 1)) { 1571 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1572 p->asc = 0x24; 1573 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1574 } else { 1575 uint8_t buf[8]; 1576 int len; 1577 1578 len = be16dec(acmd + 7); 1579 if (len > sizeof(buf)) 1580 len = sizeof(buf); 1581 1582 memset(buf, 0, sizeof(buf)); 1583 be16enc(buf, 8 - 2); 1584 buf[2] = 0x04; 1585 buf[3] = 0x10; 1586 buf[5] = 0x02; 1587 write_prdt(p, slot, cfis, buf, len); 1588 tfd = ATA_S_READY | ATA_S_DSC; 1589 } 1590 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1591 ahci_write_fis_d2h(p, slot, cfis, tfd); 1592} 1593 1594static void 1595handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1596{ 1597 uint8_t *acmd; 1598 1599 acmd = cfis + 0x40; 1600 1601#ifdef AHCI_DEBUG 1602 { 1603 int i; 1604 DPRINTF("ACMD:"); 1605 for (i = 0; i < 16; i++) 1606 DPRINTF("%02x ", acmd[i]); 1607 DPRINTF("\n"); 1608 } 1609#endif 1610 1611 switch (acmd[0]) { 1612 case TEST_UNIT_READY: 1613 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1614 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1615 break; 1616 case INQUIRY: 1617 atapi_inquiry(p, slot, cfis); 1618 break; 1619 case READ_CAPACITY: 1620 atapi_read_capacity(p, slot, cfis); 1621 break; 1622 case PREVENT_ALLOW: 1623 /* TODO */ 1624 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1625 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1626 break; 1627 case READ_TOC: 1628 atapi_read_toc(p, slot, cfis); 1629 break; 1630 case REPORT_LUNS: 1631 atapi_report_luns(p, slot, cfis); 1632 break; 1633 case READ_10: 1634 case READ_12: 1635 atapi_read(p, slot, cfis, 0); 1636 break; 1637 case REQUEST_SENSE: 1638 atapi_request_sense(p, slot, cfis); 1639 break; 1640 case START_STOP_UNIT: 1641 atapi_start_stop_unit(p, slot, cfis); 1642 break; 1643 case MODE_SENSE_10: 1644 atapi_mode_sense(p, slot, cfis); 1645 break; 1646 case GET_EVENT_STATUS_NOTIFICATION: 1647 atapi_get_event_status_notification(p, slot, cfis); 1648 break; 1649 default: 1650 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1651 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1652 p->asc = 0x20; 1653 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1654 ATA_S_READY | ATA_S_ERROR); 1655 break; 1656 } 1657} 1658 1659static void 1660ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1661{ 1662 1663 p->tfd |= ATA_S_BUSY; 1664 switch (cfis[2]) { 1665 case ATA_ATA_IDENTIFY: 1666 handle_identify(p, slot, cfis); 1667 break; 1668 case ATA_SETFEATURES: 1669 { 1670 switch (cfis[3]) { 1671 case ATA_SF_ENAB_SATA_SF: 1672 switch (cfis[12]) { 1673 case ATA_SATA_SF_AN: 1674 p->tfd = ATA_S_DSC | ATA_S_READY; 1675 break; 1676 default: 1677 p->tfd = ATA_S_ERROR | ATA_S_READY; 1678 p->tfd |= (ATA_ERROR_ABORT << 8); 1679 break; 1680 } 1681 break; 1682 case ATA_SF_ENAB_WCACHE: 1683 case ATA_SF_DIS_WCACHE: 1684 case ATA_SF_ENAB_RCACHE: 1685 case ATA_SF_DIS_RCACHE: 1686 p->tfd = ATA_S_DSC | ATA_S_READY; 1687 break; 1688 case ATA_SF_SETXFER: 1689 { 1690 switch (cfis[12] & 0xf8) { 1691 case ATA_PIO: 1692 case ATA_PIO0: 1693 break; 1694 case ATA_WDMA0: 1695 case ATA_UDMA0: 1696 p->xfermode = (cfis[12] & 0x7); 1697 break; 1698 } 1699 p->tfd = ATA_S_DSC | ATA_S_READY; 1700 break; 1701 } 1702 default: 1703 p->tfd = ATA_S_ERROR | ATA_S_READY; 1704 p->tfd |= (ATA_ERROR_ABORT << 8); 1705 break; 1706 } 1707 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1708 break; 1709 } 1710 case ATA_SET_MULTI: 1711 if (cfis[12] != 0 && 1712 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1713 p->tfd = ATA_S_ERROR | ATA_S_READY; 1714 p->tfd |= (ATA_ERROR_ABORT << 8); 1715 } else { 1716 p->mult_sectors = cfis[12]; 1717 p->tfd = ATA_S_DSC | ATA_S_READY; 1718 } 1719 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1720 break; 1721 case ATA_READ: 1722 case ATA_WRITE: 1723 case ATA_READ48: 1724 case ATA_WRITE48: 1725 case ATA_READ_MUL: 1726 case ATA_WRITE_MUL: 1727 case ATA_READ_MUL48: 1728 case ATA_WRITE_MUL48: 1729 case ATA_READ_DMA: 1730 case ATA_WRITE_DMA: 1731 case ATA_READ_DMA48: 1732 case ATA_WRITE_DMA48: 1733 case ATA_READ_FPDMA_QUEUED: 1734 case ATA_WRITE_FPDMA_QUEUED: 1735 ahci_handle_rw(p, slot, cfis, 0); 1736 break; 1737 case ATA_FLUSHCACHE: 1738 case ATA_FLUSHCACHE48: 1739 ahci_handle_flush(p, slot, cfis); 1740 break; 1741 case ATA_DATA_SET_MANAGEMENT: 1742 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM && 1743 cfis[13] == 0 && cfis[12] == 1) { 1744 ahci_handle_dsm_trim(p, slot, cfis, 0); 1745 break; 1746 } 1747 ahci_write_fis_d2h(p, slot, cfis, 1748 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1749 break; 1750 case ATA_SEND_FPDMA_QUEUED: 1751 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM && 1752 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM && 1753 cfis[11] == 0 && cfis[3] == 1) { 1754 ahci_handle_dsm_trim(p, slot, cfis, 0); 1755 break; 1756 } 1757 ahci_write_fis_d2h(p, slot, cfis, 1758 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1759 break; 1760 case ATA_READ_LOG_EXT: 1761 case ATA_READ_LOG_DMA_EXT: 1762 ahci_handle_read_log(p, slot, cfis); 1763 break; 1764 case ATA_SECURITY_FREEZE_LOCK: 1765 case ATA_SMART_CMD: 1766 case ATA_NOP: 1767 ahci_write_fis_d2h(p, slot, cfis, 1768 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1769 break; 1770 case ATA_CHECK_POWER_MODE: 1771 cfis[12] = 0xff; /* always on */ 1772 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1773 break; 1774 case ATA_STANDBY_CMD: 1775 case ATA_STANDBY_IMMEDIATE: 1776 case ATA_IDLE_CMD: 1777 case ATA_IDLE_IMMEDIATE: 1778 case ATA_SLEEP: 1779 case ATA_READ_VERIFY: 1780 case ATA_READ_VERIFY48: 1781 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1782 break; 1783 case ATA_ATAPI_IDENTIFY: 1784 handle_atapi_identify(p, slot, cfis); 1785 break; 1786 case ATA_PACKET_CMD: 1787 if (!p->atapi) { 1788 ahci_write_fis_d2h(p, slot, cfis, 1789 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1790 } else 1791 handle_packet_cmd(p, slot, cfis); 1792 break; 1793 default: 1794 WPRINTF("Unsupported cmd:%02x\n", cfis[2]); 1795 ahci_write_fis_d2h(p, slot, cfis, 1796 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1797 break; 1798 } 1799} 1800 1801static void 1802ahci_handle_slot(struct ahci_port *p, int slot) 1803{ 1804 struct ahci_cmd_hdr *hdr; 1805#ifdef AHCI_DEBUG 1806 struct ahci_prdt_entry *prdt; 1807#endif 1808 struct pci_ahci_softc *sc; 1809 uint8_t *cfis; 1810#ifdef AHCI_DEBUG 1811 int cfl, i; 1812#endif 1813 1814 sc = p->pr_sc; 1815 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1816#ifdef AHCI_DEBUG 1817 cfl = (hdr->flags & 0x1f) * 4; 1818#endif 1819 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1820 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1821#ifdef AHCI_DEBUG 1822 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1823 1824 DPRINTF("\ncfis:"); 1825 for (i = 0; i < cfl; i++) { 1826 if (i % 10 == 0) 1827 DPRINTF("\n"); 1828 DPRINTF("%02x ", cfis[i]); 1829 } 1830 DPRINTF("\n"); 1831 1832 for (i = 0; i < hdr->prdtl; i++) { 1833 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); 1834 prdt++; 1835 } 1836#endif 1837 1838 if (cfis[0] != FIS_TYPE_REGH2D) { 1839 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]); 1840 return; 1841 } 1842 1843 if (cfis[1] & 0x80) { 1844 ahci_handle_cmd(p, slot, cfis); 1845 } else { 1846 if (cfis[15] & (1 << 2)) 1847 p->reset = 1; 1848 else if (p->reset) { 1849 p->reset = 0; 1850 ahci_port_reset(p); 1851 } 1852 p->ci &= ~(1 << slot); 1853 } 1854} 1855 1856static void 1857ahci_handle_port(struct ahci_port *p) 1858{ 1859 1860 if (!(p->cmd & AHCI_P_CMD_ST)) 1861 return; 1862 1863 /* 1864 * Search for any new commands to issue ignoring those that 1865 * are already in-flight. Stop if device is busy or in error. 1866 */ 1867 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) { 1868 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0) 1869 break; 1870 if (p->waitforclear) 1871 break; 1872 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) { 1873 p->cmd &= ~AHCI_P_CMD_CCS_MASK; 1874 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT; 1875 ahci_handle_slot(p, p->ccs); 1876 } 1877 } 1878} 1879 1880/* 1881 * blockif callback routine - this runs in the context of the blockif 1882 * i/o thread, so the mutex needs to be acquired. 1883 */ 1884static void 1885ata_ioreq_cb(struct blockif_req *br, int err) 1886{ 1887 struct ahci_cmd_hdr *hdr; 1888 struct ahci_ioreq *aior; 1889 struct ahci_port *p; 1890 struct pci_ahci_softc *sc; 1891 uint32_t tfd; 1892 uint8_t *cfis; 1893 int slot, ncq, dsm; 1894 1895 DPRINTF("%s %d\n", __func__, err); 1896 1897 ncq = dsm = 0; 1898 aior = br->br_param; 1899 p = aior->io_pr; 1900 cfis = aior->cfis; 1901 slot = aior->slot; 1902 sc = p->pr_sc; 1903 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1904 1905 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1906 cfis[2] == ATA_READ_FPDMA_QUEUED || 1907 cfis[2] == ATA_SEND_FPDMA_QUEUED) 1908 ncq = 1; 1909 if (cfis[2] == ATA_DATA_SET_MANAGEMENT || 1910 (cfis[2] == ATA_SEND_FPDMA_QUEUED && 1911 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM)) 1912 dsm = 1; 1913 1914 pthread_mutex_lock(&sc->mtx); 1915 1916 /* 1917 * Delete the blockif request from the busy list 1918 */ 1919 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1920 1921 /* 1922 * Move the blockif request back to the free list 1923 */ 1924 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1925 1926 if (!err) 1927 hdr->prdbc = aior->done; 1928 1929 if (!err && aior->more) { 1930 if (dsm) 1931 ahci_handle_dsm_trim(p, slot, cfis, aior->done); 1932 else 1933 ahci_handle_rw(p, slot, cfis, aior->done); 1934 goto out; 1935 } 1936 1937 if (!err) 1938 tfd = ATA_S_READY | ATA_S_DSC; 1939 else 1940 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1941 if (ncq) 1942 ahci_write_fis_sdb(p, slot, cfis, tfd); 1943 else 1944 ahci_write_fis_d2h(p, slot, cfis, tfd); 1945 1946 /* 1947 * This command is now complete. 1948 */ 1949 p->pending &= ~(1 << slot); 1950 1951 ahci_check_stopped(p); 1952 ahci_handle_port(p); 1953out: 1954 pthread_mutex_unlock(&sc->mtx); 1955 DPRINTF("%s exit\n", __func__); 1956} 1957 1958static void 1959atapi_ioreq_cb(struct blockif_req *br, int err) 1960{ 1961 struct ahci_cmd_hdr *hdr; 1962 struct ahci_ioreq *aior; 1963 struct ahci_port *p; 1964 struct pci_ahci_softc *sc; 1965 uint8_t *cfis; 1966 uint32_t tfd; 1967 int slot; 1968 1969 DPRINTF("%s %d\n", __func__, err); 1970 1971 aior = br->br_param; 1972 p = aior->io_pr; 1973 cfis = aior->cfis; 1974 slot = aior->slot; 1975 sc = p->pr_sc; 1976 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 1977 1978 pthread_mutex_lock(&sc->mtx); 1979 1980 /* 1981 * Delete the blockif request from the busy list 1982 */ 1983 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1984 1985 /* 1986 * Move the blockif request back to the free list 1987 */ 1988 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1989 1990 if (!err) 1991 hdr->prdbc = aior->done; 1992 1993 if (!err && aior->more) { 1994 atapi_read(p, slot, cfis, aior->done); 1995 goto out; 1996 } 1997 1998 if (!err) { 1999 tfd = ATA_S_READY | ATA_S_DSC; 2000 } else { 2001 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 2002 p->asc = 0x21; 2003 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 2004 } 2005 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 2006 ahci_write_fis_d2h(p, slot, cfis, tfd); 2007 2008 /* 2009 * This command is now complete. 2010 */ 2011 p->pending &= ~(1 << slot); 2012 2013 ahci_check_stopped(p); 2014 ahci_handle_port(p); 2015out: 2016 pthread_mutex_unlock(&sc->mtx); 2017 DPRINTF("%s exit\n", __func__); 2018} 2019 2020static void 2021pci_ahci_ioreq_init(struct ahci_port *pr) 2022{ 2023 struct ahci_ioreq *vr; 2024 int i; 2025 2026 pr->ioqsz = blockif_queuesz(pr->bctx); 2027 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 2028 STAILQ_INIT(&pr->iofhd); 2029 2030 /* 2031 * Add all i/o request entries to the free queue 2032 */ 2033 for (i = 0; i < pr->ioqsz; i++) { 2034 vr = &pr->ioreq[i]; 2035 vr->io_pr = pr; 2036 if (!pr->atapi) 2037 vr->io_req.br_callback = ata_ioreq_cb; 2038 else 2039 vr->io_req.br_callback = atapi_ioreq_cb; 2040 vr->io_req.br_param = vr; 2041 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist); 2042 } 2043 2044 TAILQ_INIT(&pr->iobhd); 2045} 2046 2047static void 2048pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 2049{ 2050 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 2051 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 2052 struct ahci_port *p = &sc->port[port]; 2053 2054 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 2055 port, offset, value); 2056 2057 switch (offset) { 2058 case AHCI_P_CLB: 2059 p->clb = value; 2060 break; 2061 case AHCI_P_CLBU: 2062 p->clbu = value; 2063 break; 2064 case AHCI_P_FB: 2065 p->fb = value; 2066 break; 2067 case AHCI_P_FBU: 2068 p->fbu = value; 2069 break; 2070 case AHCI_P_IS: 2071 p->is &= ~value; 2072 ahci_port_intr(p); 2073 break; 2074 case AHCI_P_IE: 2075 p->ie = value & 0xFDC000FF; 2076 ahci_port_intr(p); 2077 break; 2078 case AHCI_P_CMD: 2079 { 2080 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD | 2081 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE | 2082 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE | 2083 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK); 2084 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD | 2085 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE | 2086 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE | 2087 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value; 2088 2089 if (!(value & AHCI_P_CMD_ST)) { 2090 ahci_port_stop(p); 2091 } else { 2092 uint64_t clb; 2093 2094 p->cmd |= AHCI_P_CMD_CR; 2095 clb = (uint64_t)p->clbu << 32 | p->clb; 2096 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 2097 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 2098 } 2099 2100 if (value & AHCI_P_CMD_FRE) { 2101 uint64_t fb; 2102 2103 p->cmd |= AHCI_P_CMD_FR; 2104 fb = (uint64_t)p->fbu << 32 | p->fb; 2105 /* we don't support FBSCP, so rfis size is 256Bytes */ 2106 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 2107 } else { 2108 p->cmd &= ~AHCI_P_CMD_FR; 2109 } 2110 2111 if (value & AHCI_P_CMD_CLO) { 2112 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ); 2113 p->cmd &= ~AHCI_P_CMD_CLO; 2114 } 2115 2116 if (value & AHCI_P_CMD_ICC_MASK) { 2117 p->cmd &= ~AHCI_P_CMD_ICC_MASK; 2118 } 2119 2120 ahci_handle_port(p); 2121 break; 2122 } 2123 case AHCI_P_TFD: 2124 case AHCI_P_SIG: 2125 case AHCI_P_SSTS: 2126 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); 2127 break; 2128 case AHCI_P_SCTL: 2129 p->sctl = value; 2130 if (!(p->cmd & AHCI_P_CMD_ST)) { 2131 if (value & ATA_SC_DET_RESET) 2132 ahci_port_reset(p); 2133 } 2134 break; 2135 case AHCI_P_SERR: 2136 p->serr &= ~value; 2137 break; 2138 case AHCI_P_SACT: 2139 p->sact |= value; 2140 break; 2141 case AHCI_P_CI: 2142 p->ci |= value; 2143 ahci_handle_port(p); 2144 break; 2145 case AHCI_P_SNTF: 2146 case AHCI_P_FBS: 2147 default: 2148 break; 2149 } 2150} 2151 2152static void 2153pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 2154{ 2155 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 2156 offset, value); 2157 2158 switch (offset) { 2159 case AHCI_CAP: 2160 case AHCI_PI: 2161 case AHCI_VS: 2162 case AHCI_CAP2: 2163 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); 2164 break; 2165 case AHCI_GHC: 2166 if (value & AHCI_GHC_HR) { 2167 ahci_reset(sc); 2168 break; 2169 } 2170 if (value & AHCI_GHC_IE) 2171 sc->ghc |= AHCI_GHC_IE; 2172 else 2173 sc->ghc &= ~AHCI_GHC_IE; 2174 ahci_generate_intr(sc, 0xffffffff); 2175 break; 2176 case AHCI_IS: 2177 sc->is &= ~value; 2178 ahci_generate_intr(sc, value); 2179 break; 2180 default: 2181 break; 2182 } 2183} 2184 2185static void 2186pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 2187 int baridx, uint64_t offset, int size, uint64_t value) 2188{ 2189 struct pci_ahci_softc *sc = pi->pi_arg; 2190 2191 assert(baridx == 5); 2192 assert((offset % 4) == 0 && size == 4); 2193 2194 pthread_mutex_lock(&sc->mtx); 2195 2196 if (offset < AHCI_OFFSET) 2197 pci_ahci_host_write(sc, offset, value); 2198 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2199 pci_ahci_port_write(sc, offset, value); 2200 else 2201 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); 2202 2203 pthread_mutex_unlock(&sc->mtx); 2204} 2205 2206static uint64_t 2207pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 2208{ 2209 uint32_t value; 2210 2211 switch (offset) { 2212 case AHCI_CAP: 2213 case AHCI_GHC: 2214 case AHCI_IS: 2215 case AHCI_PI: 2216 case AHCI_VS: 2217 case AHCI_CCCC: 2218 case AHCI_CCCP: 2219 case AHCI_EM_LOC: 2220 case AHCI_EM_CTL: 2221 case AHCI_CAP2: 2222 { 2223 uint32_t *p = &sc->cap; 2224 p += (offset - AHCI_CAP) / sizeof(uint32_t); 2225 value = *p; 2226 break; 2227 } 2228 default: 2229 value = 0; 2230 break; 2231 } 2232 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", 2233 offset, value); 2234 2235 return (value); 2236} 2237 2238static uint64_t 2239pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 2240{ 2241 uint32_t value; 2242 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 2243 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 2244 2245 switch (offset) { 2246 case AHCI_P_CLB: 2247 case AHCI_P_CLBU: 2248 case AHCI_P_FB: 2249 case AHCI_P_FBU: 2250 case AHCI_P_IS: 2251 case AHCI_P_IE: 2252 case AHCI_P_CMD: 2253 case AHCI_P_TFD: 2254 case AHCI_P_SIG: 2255 case AHCI_P_SSTS: 2256 case AHCI_P_SCTL: 2257 case AHCI_P_SERR: 2258 case AHCI_P_SACT: 2259 case AHCI_P_CI: 2260 case AHCI_P_SNTF: 2261 case AHCI_P_FBS: 2262 { 2263 uint32_t *p= &sc->port[port].clb; 2264 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 2265 value = *p; 2266 break; 2267 } 2268 default: 2269 value = 0; 2270 break; 2271 } 2272 2273 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", 2274 port, offset, value); 2275 2276 return value; 2277} 2278 2279static uint64_t 2280pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2281 uint64_t regoff, int size) 2282{ 2283 struct pci_ahci_softc *sc = pi->pi_arg; 2284 uint64_t offset; 2285 uint32_t value; 2286 2287 assert(baridx == 5); 2288 assert(size == 1 || size == 2 || size == 4); 2289 assert((regoff & (size - 1)) == 0); 2290 2291 pthread_mutex_lock(&sc->mtx); 2292 2293 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */ 2294 if (offset < AHCI_OFFSET) 2295 value = pci_ahci_host_read(sc, offset); 2296 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2297 value = pci_ahci_port_read(sc, offset); 2298 else { 2299 value = 0; 2300 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", 2301 regoff); 2302 } 2303 value >>= 8 * (regoff & 0x3); 2304 2305 pthread_mutex_unlock(&sc->mtx); 2306 2307 return (value); 2308} 2309 2310static int 2311pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi) 2312{ 2313 char bident[sizeof("XX:XX:XX")]; 2314 struct blockif_ctxt *bctxt; 2315 struct pci_ahci_softc *sc; 2316 int ret, slots, p; 2317 MD5_CTX mdctx; 2318 u_char digest[16]; 2319 char *next, *next2; 2320 2321 ret = 0; 2322 2323#ifdef AHCI_DEBUG 2324 dbg = fopen("/tmp/log", "w+"); 2325#endif 2326 2327 sc = calloc(1, sizeof(struct pci_ahci_softc)); 2328 pi->pi_arg = sc; 2329 sc->asc_pi = pi; 2330 pthread_mutex_init(&sc->mtx, NULL); 2331 sc->ports = 0; 2332 sc->pi = 0; 2333 slots = 32; 2334 2335 for (p = 0; p < MAX_PORTS && opts != NULL; p++, opts = next) { 2336 /* Identify and cut off type of present port. */ 2337 if (strncmp(opts, "hd:", 3) == 0) { 2338 atapi = 0; 2339 opts += 3; 2340 } else if (strncmp(opts, "cd:", 3) == 0) { 2341 atapi = 1; 2342 opts += 3; 2343 } 2344 2345 /* Find and cut off the next port options. */ 2346 next = strstr(opts, ",hd:"); 2347 next2 = strstr(opts, ",cd:"); 2348 if (next == NULL || (next2 != NULL && next2 < next)) 2349 next = next2; 2350 if (next != NULL) { 2351 next[0] = 0; 2352 next++; 2353 } 2354 2355 if (opts[0] == 0) 2356 continue; 2357 2358 /* 2359 * Attempt to open the backing image. Use the PCI slot/func 2360 * and the port number for the identifier string. 2361 */ 2362 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot, 2363 pi->pi_func, p); 2364 bctxt = blockif_open(opts, bident); 2365 if (bctxt == NULL) { 2366 sc->ports = p; 2367 ret = 1; 2368 goto open_fail; 2369 } 2370 sc->port[p].bctx = bctxt; 2371 sc->port[p].pr_sc = sc; 2372 sc->port[p].port = p; 2373 sc->port[p].atapi = atapi; 2374 2375 /* 2376 * Create an identifier for the backing file. 2377 * Use parts of the md5 sum of the filename 2378 */ 2379 MD5Init(&mdctx); 2380 MD5Update(&mdctx, opts, strlen(opts)); 2381 MD5Final(digest, &mdctx); 2382 sprintf(sc->port[p].ident, "BHYVE-%02X%02X-%02X%02X-%02X%02X", 2383 digest[0], digest[1], digest[2], digest[3], digest[4], 2384 digest[5]); 2385 2386 /* 2387 * Allocate blockif request structures and add them 2388 * to the free list 2389 */ 2390 pci_ahci_ioreq_init(&sc->port[p]); 2391 2392 sc->pi |= (1 << p); 2393 if (sc->port[p].ioqsz < slots) 2394 slots = sc->port[p].ioqsz; 2395 } 2396 sc->ports = p; 2397 2398 /* Intel ICH8 AHCI */ 2399 --slots; 2400 if (sc->ports < DEF_PORTS) 2401 sc->ports = DEF_PORTS; 2402 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 2403 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 2404 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 2405 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 2406 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 2407 2408 sc->vs = 0x10300; 2409 sc->cap2 = AHCI_CAP2_APST; 2410 ahci_reset(sc); 2411 2412 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 2413 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2414 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 2415 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 2416 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 2417 p = MIN(sc->ports, 16); 2418 p = flsl(p) - ((p & (p - 1)) ? 0 : 1); 2419 pci_emul_add_msicap(pi, 1 << p); 2420 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 2421 AHCI_OFFSET + sc->ports * AHCI_STEP); 2422 2423 pci_lintr_request(pi); 2424 2425open_fail: 2426 if (ret) { 2427 for (p = 0; p < sc->ports; p++) { 2428 if (sc->port[p].bctx != NULL) 2429 blockif_close(sc->port[p].bctx); 2430 } 2431 free(sc); 2432 } 2433 2434 return (ret); 2435} 2436 2437static int 2438pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2439{ 2440 2441 return (pci_ahci_init(ctx, pi, opts, 0)); 2442} 2443 2444static int 2445pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2446{ 2447 2448 return (pci_ahci_init(ctx, pi, opts, 1)); 2449} 2450 2451/* 2452 * Use separate emulation names to distinguish drive and atapi devices 2453 */ 2454struct pci_devemu pci_de_ahci = { 2455 .pe_emu = "ahci", 2456 .pe_init = pci_ahci_hd_init, 2457 .pe_barwrite = pci_ahci_write, 2458 .pe_barread = pci_ahci_read 2459}; 2460PCI_EMUL_SET(pci_de_ahci); 2461 2462struct pci_devemu pci_de_ahci_hd = { 2463 .pe_emu = "ahci-hd", 2464 .pe_init = pci_ahci_hd_init, 2465 .pe_barwrite = pci_ahci_write, 2466 .pe_barread = pci_ahci_read 2467}; 2468PCI_EMUL_SET(pci_de_ahci_hd); 2469 2470struct pci_devemu pci_de_ahci_cd = { 2471 .pe_emu = "ahci-cd", 2472 .pe_init = pci_ahci_atapi_init, 2473 .pe_barwrite = pci_ahci_write, 2474 .pe_barread = pci_ahci_read 2475}; 2476PCI_EMUL_SET(pci_de_ahci_cd); 2477