1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2015 by Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 *    derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *	from: NetBSD: psycho.c,v 1.35 2001/09/10 16:17:06 eeh Exp
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD$");
35
36#include "opt_ofw_pci.h"
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/bus.h>
41#include <sys/kernel.h>
42#include <sys/rman.h>
43
44#include <dev/ofw/ofw_bus.h>
45#include <dev/ofw/ofw_pci.h>
46#include <dev/ofw/openfirm.h>
47
48#include <dev/pci/pcireg.h>
49#include <dev/pci/pcivar.h>
50
51#include <machine/asi.h>
52#include <machine/bus.h>
53#include <machine/bus_private.h>
54#include <machine/cpufunc.h>
55#include <machine/fsr.h>
56#include <machine/resource.h>
57
58#include <sparc64/pci/ofw_pci.h>
59
60/* XXX */
61extern struct bus_space_tag nexus_bustag;
62
63int
64ofw_pci_attach_common(device_t dev, bus_dma_tag_t dmat, u_long iosize,
65    u_long memsize)
66{
67	struct ofw_pci_softc *sc;
68	struct ofw_pci_ranges *range;
69	phandle_t node;
70	uint32_t prop_array[2];
71	u_int i, j, nrange;
72
73	sc = device_get_softc(dev);
74	node = ofw_bus_get_node(dev);
75	sc->sc_node = node;
76	sc->sc_pci_dmat = dmat;
77
78	/* Initialize memory and I/O rmans. */
79	sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
80	sc->sc_pci_io_rman.rm_descr = "PCI I/O Ports";
81	if (rman_init(&sc->sc_pci_io_rman) != 0 ||
82	    rman_manage_region(&sc->sc_pci_io_rman, 0, iosize) != 0) {
83		device_printf(dev, "failed to set up I/O rman\n");
84		return (ENXIO);
85	}
86	sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
87	sc->sc_pci_mem_rman.rm_descr = "PCI Memory";
88	if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
89	    rman_manage_region(&sc->sc_pci_mem_rman, 0, memsize) != 0) {
90		device_printf(dev, "failed to set up memory rman\n");
91		return (ENXIO);
92	}
93
94	/*
95	 * Find the addresses of the various bus spaces.  The physical
96	 * start addresses of the ranges are the configuration, I/O and
97	 * memory handles.  There should not be multiple ones of one kind.
98	 */
99	nrange = OF_getprop_alloc(node, "ranges", sizeof(*range),
100	    (void **)&range);
101	for (i = 0; i < nrange; i++) {
102		j = OFW_PCI_RANGE_CS(&range[i]);
103		if (sc->sc_pci_bh[j] != 0) {
104			device_printf(dev, "duplicate range for space %d\n",
105			    j);
106			free(range, M_OFWPROP);
107			return (EINVAL);
108		}
109		sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
110	}
111	free(range, M_OFWPROP);
112
113	/*
114	 * Make sure that the expected ranges are actually present.
115	 * The OFW_PCI_CS_MEM64 one is not currently used.
116	 */
117	if (sc->sc_pci_bh[OFW_PCI_CS_CONFIG] == 0) {
118		device_printf(dev, "missing CONFIG range\n");
119		return (ENXIO);
120	}
121	if (sc->sc_pci_bh[OFW_PCI_CS_IO] == 0) {
122		device_printf(dev, "missing IO range\n");
123		return (ENXIO);
124	}
125	if (sc->sc_pci_bh[OFW_PCI_CS_MEM32] == 0) {
126		device_printf(dev, "missing MEM32 range\n");
127		return (ENXIO);
128	}
129
130	/* Allocate our tags. */
131	sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, &nexus_bustag,
132	    PCI_IO_BUS_SPACE, NULL);
133	if (sc->sc_pci_iot == NULL) {
134		device_printf(dev, "could not allocate PCI I/O tag\n");
135		return (ENXIO);
136	}
137	sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, &nexus_bustag,
138	    PCI_CONFIG_BUS_SPACE, NULL);
139	if (sc->sc_pci_cfgt == NULL) {
140		device_printf(dev,
141		    "could not allocate PCI configuration space tag\n");
142		return (ENXIO);
143	}
144
145	/*
146	 * Get the bus range from the firmware.
147	 */
148	i = OF_getprop(node, "bus-range", (void *)prop_array,
149	    sizeof(prop_array));
150	if (i == -1) {
151		device_printf(dev, "could not get bus-range\n");
152		return (ENXIO);
153	}
154	if (i != sizeof(prop_array)) {
155		device_printf(dev, "broken bus-range (%d)", i);
156		return (EINVAL);
157	}
158	sc->sc_pci_secbus = prop_array[0];
159	sc->sc_pci_subbus = prop_array[1];
160	if (bootverbose != 0)
161		device_printf(dev, "bus range %u to %u; PCI bus %d\n",
162		    sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
163
164	ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
165
166	return (0);
167}
168
169uint32_t
170ofw_pci_read_config_common(device_t dev, u_int regmax, u_long offset,
171    u_int bus, u_int slot, u_int func, u_int reg, int width)
172{
173	struct ofw_pci_softc *sc;
174	bus_space_handle_t bh;
175	uint32_t r, wrd;
176	int i;
177	uint16_t shrt;
178	uint8_t byte;
179
180	sc = device_get_softc(dev);
181	if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
182	    slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > regmax)
183		return (-1);
184
185	bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
186	switch (width) {
187	case 1:
188		i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
189		r = byte;
190		break;
191	case 2:
192		i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
193		r = shrt;
194		break;
195	case 4:
196		i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
197		r = wrd;
198		break;
199	default:
200		panic("%s: bad width %d", __func__, width);
201		/* NOTREACHED */
202	}
203
204	if (i) {
205#ifdef OFW_PCI_DEBUG
206		printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
207		    __func__, bus, slot, func, reg);
208#endif
209		r = -1;
210	}
211	return (r);
212}
213
214void
215ofw_pci_write_config_common(device_t dev, u_int regmax, u_long offset,
216    u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int width)
217{
218	struct ofw_pci_softc *sc;
219	bus_space_handle_t bh;
220
221	sc = device_get_softc(dev);
222	if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
223	    slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > regmax)
224		return;
225
226	bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
227	switch (width) {
228	case 1:
229		bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
230		break;
231	case 2:
232		bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
233		break;
234	case 4:
235		bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
236		break;
237	default:
238		panic("%s: bad width %d", __func__, width);
239		/* NOTREACHED */
240	}
241}
242
243ofw_pci_intr_t
244ofw_pci_route_interrupt_common(device_t bridge, device_t dev, int pin)
245{
246	struct ofw_pci_softc *sc;
247	struct ofw_pci_register reg;
248	ofw_pci_intr_t pintr, mintr;
249
250	sc = device_get_softc(bridge);
251	pintr = pin;
252	if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
253	    &reg, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
254	    NULL) != 0)
255		return (mintr);
256	return (PCI_INVALID_IRQ);
257}
258
259void
260ofw_pci_dmamap_sync_stst_order_common(void)
261{
262	static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
263	register_t reg, s;
264
265	s = intr_disable();
266	reg = rd(fprs);
267	wr(fprs, reg | FPRS_FEF, 0);
268	__asm __volatile("stda %%f0, [%0] %1"
269	    : : "r" (buf), "n" (ASI_BLK_COMMIT_S));
270	membar(Sync);
271	wr(fprs, reg, 0);
272	intr_restore(s);
273}
274
275int
276ofw_pci_read_ivar(device_t dev, device_t child __unused, int which,
277    uintptr_t *result)
278{
279	struct ofw_pci_softc *sc;
280
281	switch (which) {
282	case PCIB_IVAR_DOMAIN:
283		*result = device_get_unit(dev);
284		return (0);
285	case PCIB_IVAR_BUS:
286		sc = device_get_softc(dev);
287		*result = sc->sc_pci_secbus;
288		return (0);
289	}
290	return (ENOENT);
291}
292
293struct resource *
294ofw_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
295    u_long start, u_long end, u_long count, u_int flags)
296{
297	struct ofw_pci_softc *sc;
298	struct resource *rv;
299	struct rman *rm;
300
301	sc = device_get_softc(bus);
302	switch (type) {
303	case SYS_RES_IRQ:
304		/*
305		 * XXX: Don't accept blank ranges for now, only single
306		 * interrupts.  The other case should not happen with
307		 * the MI PCI code ...
308		 * XXX: This may return a resource that is out of the
309		 * range that was specified.  Is this correct ...?
310		 */
311		if (start != end)
312			panic("%s: XXX: interrupt range", __func__);
313		return (bus_generic_alloc_resource(bus, child, type, rid,
314		    start, end, count, flags));
315	case SYS_RES_MEMORY:
316		rm = &sc->sc_pci_mem_rman;
317		break;
318	case SYS_RES_IOPORT:
319		rm = &sc->sc_pci_io_rman;
320		break;
321	default:
322		return (NULL);
323	}
324
325	rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
326	    child);
327	if (rv == NULL)
328		return (NULL);
329	rman_set_rid(rv, *rid);
330
331	if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
332	    *rid, rv) != 0) {
333		rman_release_resource(rv);
334		return (NULL);
335	}
336	return (rv);
337}
338
339int
340ofw_pci_activate_resource(device_t bus, device_t child, int type, int rid,
341    struct resource *r)
342{
343	struct ofw_pci_softc *sc;
344	struct bus_space_tag *tag;
345
346	sc = device_get_softc(bus);
347	switch (type) {
348	case SYS_RES_IRQ:
349		return (bus_generic_activate_resource(bus, child, type, rid,
350		    r));
351	case SYS_RES_MEMORY:
352		tag = sparc64_alloc_bus_tag(r, &nexus_bustag,
353		    PCI_MEMORY_BUS_SPACE, NULL);
354		if (tag == NULL)
355			return (ENOMEM);
356		rman_set_bustag(r, tag);
357		rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
358		    rman_get_start(r));
359		break;
360	case SYS_RES_IOPORT:
361		rman_set_bustag(r, sc->sc_pci_iot);
362		rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
363		    rman_get_start(r));
364		break;
365	}
366	return (rman_activate_resource(r));
367}
368
369int
370ofw_pci_adjust_resource(device_t bus, device_t child, int type,
371    struct resource *r, u_long start, u_long end)
372{
373	struct ofw_pci_softc *sc;
374	struct rman *rm;
375
376	sc = device_get_softc(bus);
377	switch (type) {
378	case SYS_RES_IRQ:
379		return (bus_generic_adjust_resource(bus, child, type, r,
380		    start, end));
381	case SYS_RES_MEMORY:
382		rm = &sc->sc_pci_mem_rman;
383		break;
384	case SYS_RES_IOPORT:
385		rm = &sc->sc_pci_io_rman;
386		break;
387	default:
388		return (EINVAL);
389	}
390	if (rman_is_region_manager(r, rm) == 0)
391		return (EINVAL);
392	return (rman_adjust_resource(r, start, end));
393}
394
395bus_dma_tag_t
396ofw_pci_get_dma_tag(device_t bus, device_t child __unused)
397{
398	struct ofw_pci_softc *sc;
399
400	sc = device_get_softc(bus);
401	return (sc->sc_pci_dmat);
402}
403
404phandle_t
405ofw_pci_get_node(device_t bus, device_t child __unused)
406{
407	struct ofw_pci_softc *sc;
408
409	sc = device_get_softc(bus);
410	/* We only have one child, the PCI bus, which needs our own node. */
411	return (sc->sc_node);
412}
413