1/* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef MLX4_DEVICE_H 34#define MLX4_DEVICE_H 35 36#include <linux/pci.h> 37#include <linux/completion.h> 38#include <linux/radix-tree.h> 39#include <linux/types.h> 40#include <linux/bitops.h> 41#include <linux/workqueue.h> 42#include <asm/atomic.h> 43 44#include <linux/clocksource.h> 45 46#define MAX_MSIX_P_PORT 17 47#define MAX_MSIX 64 48#define MSIX_LEGACY_SZ 4 49#define MIN_MSIX_P_PORT 5 50 51#define MLX4_ROCE_MAX_GIDS 128 52#define MLX4_ROCE_PF_GIDS 16 53 54#define MLX4_NUM_UP 8 55#define MLX4_NUM_TC 8 56#define MLX4_MAX_100M_UNITS_VAL 255 /* 57 * work around: can't set values 58 * greater then this value when 59 * using 100 Mbps units. 60 */ 61#define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 62#define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 63#define MLX4_RATELIMIT_DEFAULT 0x00ff 64 65#define CORE_CLOCK_MASK 0xffffffffffffULL 66 67enum { 68 MLX4_FLAG_MSI_X = 1 << 0, 69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 70 MLX4_FLAG_MASTER = 1 << 2, 71 MLX4_FLAG_SLAVE = 1 << 3, 72 MLX4_FLAG_SRIOV = 1 << 4, 73 MLX4_FLAG_DEV_NUM_STR = 1 << 5, 74 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 75}; 76 77enum { 78 MLX4_PORT_CAP_IS_SM = 1 << 1, 79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 80}; 81 82enum { 83 MLX4_MAX_PORTS = 2, 84 MLX4_MAX_PORT_PKEYS = 128 85}; 86 87/* base qkey for use in sriov tunnel-qp/proxy-qp communication. 88 * These qkeys must not be allowed for general use. This is a 64k range, 89 * and to test for violation, we use the mask (protect against future chg). 90 */ 91#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 92#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 93 94enum { 95 MLX4_BOARD_ID_LEN = 64, 96 MLX4_VSD_LEN = 208 97}; 98 99enum { 100 MLX4_MAX_NUM_PF = 16, 101 MLX4_MAX_NUM_VF = 64, 102 MLX4_MFUNC_MAX = 80, 103 MLX4_MAX_EQ_NUM = 1024, 104 MLX4_MFUNC_EQ_NUM = 4, 105 MLX4_MFUNC_MAX_EQES = 8, 106 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 107}; 108 109/* Driver supports 3 diffrent device methods to manage traffic steering: 110 * -device managed - High level API for ib and eth flow steering. FW is 111 * managing flow steering tables. 112 * - B0 steering mode - Common low level API for ib and (if supported) eth. 113 * - A0 steering mode - Limited low level API for eth. In case of IB, 114 * B0 mode is in use. 115 */ 116enum { 117 MLX4_STEERING_MODE_A0, 118 MLX4_STEERING_MODE_B0, 119 MLX4_STEERING_MODE_DEVICE_MANAGED 120}; 121 122static inline const char *mlx4_steering_mode_str(int steering_mode) 123{ 124 switch (steering_mode) { 125 case MLX4_STEERING_MODE_A0: 126 return "A0 steering"; 127 128 case MLX4_STEERING_MODE_B0: 129 return "B0 steering"; 130 131 case MLX4_STEERING_MODE_DEVICE_MANAGED: 132 return "Device managed flow steering"; 133 134 default: 135 return "Unrecognize steering mode"; 136 } 137} 138 139enum { 140 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 141 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 142 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 143 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 144 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 145 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 146 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 147 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 148 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 149 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 150 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 151 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 152 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 153 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 154 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 155 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 156 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 157 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 158 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 159 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 160 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 161 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 162 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 163 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 164 MLX4_DEV_CAP_FLAG_CROSS_CHANNEL = 1LL << 44, 165 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 166 MLX4_DEV_CAP_FLAG_COUNTERS_EXT = 1LL << 49, 167 MLX4_DEV_CAP_FLAG_SET_PORT_ETH_SCHED = 1LL << 53, 168 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 169 MLX4_DEV_CAP_FLAG_FAST_DROP = 1LL << 57, 170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 171 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 172 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 173}; 174 175enum { 176 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 177 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 178 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 179 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 180 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 4, 181 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 5, 182 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 6, 183 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1LL << 7, 184 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 8, 185 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 9, 186 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 10, 187 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 11, 188 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 12, 189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 13, 190 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14, 191 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 15, 192 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 16, 193 MLX4_DEV_CAP_FLAG2_FS_EN_NCSI = 1LL << 17, 194 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 195 MLX4_DEV_CAP_FLAG2_DMFS_TAG_MODE = 1LL << 19, 196 MLX4_DEV_CAP_FLAG2_ROCEV2 = 1LL << 20, 197 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 21, 198 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 22, 199 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 23, 200 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1LL << 24, 201 MLX4_DEV_CAP_FLAG2_RX_CSUM_MODE = 1LL << 25, 202 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 26, 203}; 204 205/* bit enums for an 8-bit flags field indicating special use 206 * QPs which require special handling in qp_reserve_range. 207 * Currently, this only includes QPs used by the ETH interface, 208 * where we expect to use blueflame. These QPs must not have 209 * bits 6 and 7 set in their qp number. 210 * 211 * This enum may use only bits 0..7. 212 */ 213enum { 214 MLX4_RESERVE_BF_QP = 1 << 7, 215}; 216 217enum { 218 MLX4_DEV_CAP_CQ_FLAG_IO = 1 << 0 219}; 220 221enum { 222 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0 223}; 224 225/* bit enums for an 8-bit flags field indicating special use 226 * QPs which require special handling in qp_reserve_range. 227 * Currently, this only includes QPs used by the ETH interface, 228 * where we expect to use blueflame. These QPs must not have 229 * bits 6 and 7 set in their qp number. 230 * 231 * This enum may use only bits 0..7. 232 */ 233enum { 234 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 235}; 236 237 238enum { 239 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 240 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 241}; 242 243enum { 244 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 245}; 246 247enum { 248 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 249}; 250 251 252#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 253 254enum { 255 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 256 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 257 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 258 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 259 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 260 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 261}; 262 263enum mlx4_event { 264 MLX4_EVENT_TYPE_COMP = 0x00, 265 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 266 MLX4_EVENT_TYPE_COMM_EST = 0x02, 267 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 268 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 269 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 270 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 271 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 272 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 273 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 274 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 275 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 276 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 277 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 278 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 279 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 280 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 281 MLX4_EVENT_TYPE_CMD = 0x0a, 282 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 283 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 284 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 285 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 286 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 287 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 288 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 289 MLX4_EVENT_TYPE_NONE = 0xff, 290}; 291 292enum { 293 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 294 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 295}; 296 297enum { 298 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 299 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 300}; 301 302enum { 303 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 304}; 305 306enum slave_port_state { 307 SLAVE_PORT_DOWN = 0, 308 SLAVE_PENDING_UP, 309 SLAVE_PORT_UP, 310}; 311 312enum slave_port_gen_event { 313 SLAVE_PORT_GEN_EVENT_DOWN = 0, 314 SLAVE_PORT_GEN_EVENT_UP, 315 SLAVE_PORT_GEN_EVENT_NONE, 316}; 317 318enum slave_port_state_event { 319 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 320 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 321 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 322 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 323}; 324 325enum { 326 MLX4_PERM_LOCAL_READ = 1 << 10, 327 MLX4_PERM_LOCAL_WRITE = 1 << 11, 328 MLX4_PERM_REMOTE_READ = 1 << 12, 329 MLX4_PERM_REMOTE_WRITE = 1 << 13, 330 MLX4_PERM_ATOMIC = 1 << 14, 331 MLX4_PERM_BIND_MW = 1 << 15, 332}; 333 334enum { 335 MLX4_OPCODE_NOP = 0x00, 336 MLX4_OPCODE_SEND_INVAL = 0x01, 337 MLX4_OPCODE_RDMA_WRITE = 0x08, 338 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 339 MLX4_OPCODE_SEND = 0x0a, 340 MLX4_OPCODE_SEND_IMM = 0x0b, 341 MLX4_OPCODE_LSO = 0x0e, 342 MLX4_OPCODE_RDMA_READ = 0x10, 343 MLX4_OPCODE_ATOMIC_CS = 0x11, 344 MLX4_OPCODE_ATOMIC_FA = 0x12, 345 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 346 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 347 MLX4_OPCODE_BIND_MW = 0x18, 348 MLX4_OPCODE_FMR = 0x19, 349 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 350 MLX4_OPCODE_CONFIG_CMD = 0x1f, 351 352 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 353 MLX4_RECV_OPCODE_SEND = 0x01, 354 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 355 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 356 357 MLX4_CQE_OPCODE_ERROR = 0x1e, 358 MLX4_CQE_OPCODE_RESIZE = 0x16, 359}; 360 361enum { 362 MLX4_STAT_RATE_OFFSET = 5 363}; 364 365enum mlx4_protocol { 366 MLX4_PROT_IB_IPV6 = 0, 367 MLX4_PROT_ETH, 368 MLX4_PROT_IB_IPV4, 369 MLX4_PROT_FCOE 370}; 371 372enum { 373 MLX4_MTT_FLAG_PRESENT = 1 374}; 375 376enum { 377 MLX4_MAX_MTT_SHIFT = 31 378}; 379 380enum mlx4_qp_region { 381 MLX4_QP_REGION_FW = 0, 382 MLX4_QP_REGION_ETH_ADDR, 383 MLX4_QP_REGION_FC_ADDR, 384 MLX4_QP_REGION_FC_EXCH, 385 MLX4_NUM_QP_REGION 386}; 387 388enum mlx4_port_type { 389 MLX4_PORT_TYPE_NONE = 0, 390 MLX4_PORT_TYPE_IB = 1, 391 MLX4_PORT_TYPE_ETH = 2, 392 MLX4_PORT_TYPE_AUTO = 3, 393 MLX4_PORT_TYPE_NA = 4 394}; 395 396enum mlx4_special_vlan_idx { 397 MLX4_NO_VLAN_IDX = 0, 398 MLX4_VLAN_MISS_IDX, 399 MLX4_VLAN_REGULAR 400}; 401 402enum mlx4_steer_type { 403 MLX4_MC_STEER = 0, 404 MLX4_UC_STEER, 405 MLX4_NUM_STEERS 406}; 407 408enum { 409 MLX4_NUM_FEXCH = 64 * 1024, 410}; 411 412enum { 413 MLX4_MAX_FAST_REG_PAGES = 511, 414}; 415 416enum { 417 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 418 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 419 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 420}; 421 422/* Port mgmt change event handling */ 423enum { 424 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 425 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 426 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 427 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 428 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 429}; 430 431#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 432 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 433 434enum mlx4_module_id { 435 MLX4_MODULE_ID_SFP = 0x3, 436 MLX4_MODULE_ID_QSFP = 0xC, 437 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 438 MLX4_MODULE_ID_QSFP28 = 0x11, 439}; 440 441static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 442{ 443 return (major << 32) | (minor << 16) | subminor; 444} 445 446struct mlx4_phys_caps { 447 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 448 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 449 u32 num_phys_eqs; 450 u32 base_sqpn; 451 u32 base_proxy_sqpn; 452 u32 base_tunnel_sqpn; 453}; 454 455struct mlx4_caps { 456 u64 fw_ver; 457 u32 function; 458 int num_ports; 459 int vl_cap[MLX4_MAX_PORTS + 1]; 460 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 461 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 462 u64 def_mac[MLX4_MAX_PORTS + 1]; 463 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 464 int gid_table_len[MLX4_MAX_PORTS + 1]; 465 int pkey_table_len[MLX4_MAX_PORTS + 1]; 466 int trans_type[MLX4_MAX_PORTS + 1]; 467 int vendor_oui[MLX4_MAX_PORTS + 1]; 468 int wavelength[MLX4_MAX_PORTS + 1]; 469 u64 trans_code[MLX4_MAX_PORTS + 1]; 470 int local_ca_ack_delay; 471 int num_uars; 472 u32 uar_page_size; 473 int bf_reg_size; 474 int bf_regs_per_page; 475 int max_sq_sg; 476 int max_rq_sg; 477 int num_qps; 478 int max_wqes; 479 int max_sq_desc_sz; 480 int max_rq_desc_sz; 481 int max_qp_init_rdma; 482 int max_qp_dest_rdma; 483 u32 *qp0_proxy; 484 u32 *qp1_proxy; 485 u32 *qp0_tunnel; 486 u32 *qp1_tunnel; 487 int num_srqs; 488 int max_srq_wqes; 489 int max_srq_sge; 490 int reserved_srqs; 491 int num_cqs; 492 int max_cqes; 493 int reserved_cqs; 494 int num_sys_eqs; 495 int num_eqs; 496 int reserved_eqs; 497 int num_comp_vectors; 498 int comp_pool; 499 int num_mpts; 500 int max_fmr_maps; 501 u64 num_mtts; 502 int fmr_reserved_mtts; 503 int reserved_mtts; 504 int reserved_mrws; 505 int reserved_uars; 506 int num_mgms; 507 int num_amgms; 508 int reserved_mcgs; 509 int num_qp_per_mgm; 510 int steering_mode; 511 int num_pds; 512 int reserved_pds; 513 int max_xrcds; 514 int reserved_xrcds; 515 int mtt_entry_sz; 516 u32 max_msg_sz; 517 u32 page_size_cap; 518 u64 flags; 519 u64 flags2; 520 u32 bmme_flags; 521 u32 reserved_lkey; 522 u16 stat_rate_support; 523 u8 cq_timestamp; 524 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 525 int max_gso_sz; 526 int max_rss_tbl_sz; 527 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 528 int reserved_qps; 529 int reserved_qps_base[MLX4_NUM_QP_REGION]; 530 int log_num_macs; 531 int log_num_vlans; 532 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 533 u8 supported_type[MLX4_MAX_PORTS + 1]; 534 u8 suggested_type[MLX4_MAX_PORTS + 1]; 535 u8 default_sense[MLX4_MAX_PORTS + 1]; 536 u32 port_mask[MLX4_MAX_PORTS + 1]; 537 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 538 u32 max_counters; 539 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 540 u16 sqp_demux; 541 u32 sync_qp; 542 u32 cq_flags; 543 u32 eqe_size; 544 u32 cqe_size; 545 u8 eqe_factor; 546 u32 userspace_caps; /* userspace must be aware to */ 547 u32 function_caps; /* functions must be aware to */ 548 u8 fast_drop; 549 u16 hca_core_clock; 550 u32 max_basic_counters; 551 u32 max_extended_counters; 552 u8 def_counter_index[MLX4_MAX_PORTS + 1]; 553 u8 alloc_res_qp_mask; 554}; 555 556struct mlx4_buf_list { 557 void *buf; 558 dma_addr_t map; 559}; 560 561struct mlx4_buf { 562 struct mlx4_buf_list direct; 563 struct mlx4_buf_list *page_list; 564 int nbufs; 565 int npages; 566 int page_shift; 567}; 568 569struct mlx4_mtt { 570 u32 offset; 571 int order; 572 int page_shift; 573}; 574 575enum { 576 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 577}; 578 579struct mlx4_db_pgdir { 580 struct list_head list; 581 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 582 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 583 unsigned long *bits[2]; 584 __be32 *db_page; 585 dma_addr_t db_dma; 586}; 587 588struct mlx4_ib_user_db_page; 589 590struct mlx4_db { 591 __be32 *db; 592 union { 593 struct mlx4_db_pgdir *pgdir; 594 struct mlx4_ib_user_db_page *user_page; 595 } u; 596 dma_addr_t dma; 597 int index; 598 int order; 599}; 600 601struct mlx4_hwq_resources { 602 struct mlx4_db db; 603 struct mlx4_mtt mtt; 604 struct mlx4_buf buf; 605}; 606 607struct mlx4_mr { 608 struct mlx4_mtt mtt; 609 u64 iova; 610 u64 size; 611 u32 key; 612 u32 pd; 613 u32 access; 614 int enabled; 615}; 616 617enum mlx4_mw_type { 618 MLX4_MW_TYPE_1 = 1, 619 MLX4_MW_TYPE_2 = 2, 620}; 621 622struct mlx4_mw { 623 u32 key; 624 u32 pd; 625 enum mlx4_mw_type type; 626 int enabled; 627}; 628 629struct mlx4_fmr { 630 struct mlx4_mr mr; 631 struct mlx4_mpt_entry *mpt; 632 __be64 *mtts; 633 dma_addr_t dma_handle; 634 int max_pages; 635 int max_maps; 636 int maps; 637 u8 page_shift; 638}; 639 640struct mlx4_uar { 641 unsigned long pfn; 642 int index; 643 struct list_head bf_list; 644 unsigned free_bf_bmap; 645 void __iomem *map; 646 void __iomem *bf_map; 647}; 648 649struct mlx4_bf { 650 unsigned long offset; 651 int buf_size; 652 struct mlx4_uar *uar; 653 void __iomem *reg; 654}; 655 656struct mlx4_cq { 657 void (*comp) (struct mlx4_cq *); 658 void (*event) (struct mlx4_cq *, enum mlx4_event); 659 660 struct mlx4_uar *uar; 661 662 u32 cons_index; 663 664 __be32 *set_ci_db; 665 __be32 *arm_db; 666 int arm_sn; 667 668 int cqn; 669 unsigned vector; 670 671 atomic_t refcount; 672 struct completion free; 673 int eqn; 674 u16 irq; 675}; 676 677struct mlx4_qp { 678 void (*event) (struct mlx4_qp *, enum mlx4_event); 679 680 int qpn; 681 682 atomic_t refcount; 683 struct completion free; 684}; 685 686struct mlx4_srq { 687 void (*event) (struct mlx4_srq *, enum mlx4_event); 688 689 int srqn; 690 int max; 691 int max_gs; 692 int wqe_shift; 693 694 atomic_t refcount; 695 struct completion free; 696}; 697 698struct mlx4_av { 699 __be32 port_pd; 700 u8 reserved1; 701 u8 g_slid; 702 __be16 dlid; 703 u8 reserved2; 704 u8 gid_index; 705 u8 stat_rate; 706 u8 hop_limit; 707 __be32 sl_tclass_flowlabel; 708 u8 dgid[16]; 709}; 710 711struct mlx4_eth_av { 712 __be32 port_pd; 713 u8 reserved1; 714 u8 smac_idx; 715 u16 reserved2; 716 u8 reserved3; 717 u8 gid_index; 718 u8 stat_rate; 719 u8 hop_limit; 720 __be32 sl_tclass_flowlabel; 721 u8 dgid[16]; 722 u8 s_mac[6]; 723 u8 reserved4[2]; 724 __be16 vlan; 725 u8 mac[6]; 726}; 727 728union mlx4_ext_av { 729 struct mlx4_av ib; 730 struct mlx4_eth_av eth; 731}; 732 733struct mlx4_if_stat_control { 734 u8 reserved1[3]; 735 /* Extended counters enabled */ 736 u8 cnt_mode; 737 /* Number of interfaces */ 738 __be32 num_of_if; 739 __be32 reserved[2]; 740}; 741 742struct mlx4_if_stat_basic { 743 struct mlx4_if_stat_control control; 744 struct { 745 __be64 IfRxFrames; 746 __be64 IfRxOctets; 747 __be64 IfTxFrames; 748 __be64 IfTxOctets; 749 } counters[]; 750}; 751#define MLX4_IF_STAT_BSC_SZ(ports)(sizeof(struct mlx4_if_stat_extended) +\ 752 sizeof(((struct mlx4_if_stat_extended *)0)->\ 753 counters[0]) * ports) 754 755struct mlx4_if_stat_extended { 756 struct mlx4_if_stat_control control; 757 struct { 758 __be64 IfRxUnicastFrames; 759 __be64 IfRxUnicastOctets; 760 __be64 IfRxMulticastFrames; 761 __be64 IfRxMulticastOctets; 762 __be64 IfRxBroadcastFrames; 763 __be64 IfRxBroadcastOctets; 764 __be64 IfRxNoBufferFrames; 765 __be64 IfRxNoBufferOctets; 766 __be64 IfRxErrorFrames; 767 __be64 IfRxErrorOctets; 768 __be32 reserved[39]; 769 __be64 IfTxUnicastFrames; 770 __be64 IfTxUnicastOctets; 771 __be64 IfTxMulticastFrames; 772 __be64 IfTxMulticastOctets; 773 __be64 IfTxBroadcastFrames; 774 __be64 IfTxBroadcastOctets; 775 __be64 IfTxDroppedFrames; 776 __be64 IfTxDroppedOctets; 777 __be64 IfTxRequestedFramesSent; 778 __be64 IfTxGeneratedFramesSent; 779 __be64 IfTxTsoOctets; 780 } __packed counters[]; 781}; 782#define MLX4_IF_STAT_EXT_SZ(ports) (sizeof(struct mlx4_if_stat_extended) +\ 783 sizeof(((struct mlx4_if_stat_extended *)\ 784 0)->counters[0]) * ports) 785 786union mlx4_counter { 787 struct mlx4_if_stat_control control; 788 struct mlx4_if_stat_basic basic; 789 struct mlx4_if_stat_extended ext; 790}; 791#define MLX4_IF_STAT_SZ(ports) MLX4_IF_STAT_EXT_SZ(ports) 792 793struct mlx4_quotas { 794 int qp; 795 int cq; 796 int srq; 797 int mpt; 798 int mtt; 799 int counter; 800 int xrcd; 801}; 802 803struct mlx4_dev { 804 struct pci_dev *pdev; 805 unsigned long flags; 806 unsigned long num_slaves; 807 struct mlx4_caps caps; 808 struct mlx4_phys_caps phys_caps; 809 struct mlx4_quotas quotas; 810 struct radix_tree_root qp_table_tree; 811 u8 rev_id; 812 char board_id[MLX4_BOARD_ID_LEN]; 813 u16 vsd_vendor_id; 814 char vsd[MLX4_VSD_LEN]; 815 int num_vfs; 816 int numa_node; 817 int oper_log_mgm_entry_size; 818 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 819 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 820}; 821 822struct mlx4_clock_params { 823 u64 offset; 824 u8 bar; 825 u8 size; 826}; 827 828struct mlx4_eqe { 829 u8 reserved1; 830 u8 type; 831 u8 reserved2; 832 u8 subtype; 833 union { 834 u32 raw[6]; 835 struct { 836 __be32 cqn; 837 } __packed comp; 838 struct { 839 u16 reserved1; 840 __be16 token; 841 u32 reserved2; 842 u8 reserved3[3]; 843 u8 status; 844 __be64 out_param; 845 } __packed cmd; 846 struct { 847 __be32 qpn; 848 } __packed qp; 849 struct { 850 __be32 srqn; 851 } __packed srq; 852 struct { 853 __be32 cqn; 854 u32 reserved1; 855 u8 reserved2[3]; 856 u8 syndrome; 857 } __packed cq_err; 858 struct { 859 u32 reserved1[2]; 860 __be32 port; 861 } __packed port_change; 862 struct { 863 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 864 u32 reserved; 865 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 866 } __packed comm_channel_arm; 867 struct { 868 u8 port; 869 u8 reserved[3]; 870 __be64 mac; 871 } __packed mac_update; 872 struct { 873 __be32 slave_id; 874 } __packed flr_event; 875 struct { 876 __be16 current_temperature; 877 __be16 warning_threshold; 878 } __packed warming; 879 struct { 880 u8 reserved[3]; 881 u8 port; 882 union { 883 struct { 884 __be16 mstr_sm_lid; 885 __be16 port_lid; 886 __be32 changed_attr; 887 u8 reserved[3]; 888 u8 mstr_sm_sl; 889 __be64 gid_prefix; 890 } __packed port_info; 891 struct { 892 __be32 block_ptr; 893 __be32 tbl_entries_mask; 894 } __packed tbl_change_info; 895 } params; 896 } __packed port_mgmt_change; 897 struct { 898 u8 reserved[3]; 899 u8 port; 900 u32 reserved1[5]; 901 } __packed bad_cable; 902 } event; 903 u8 slave_id; 904 u8 reserved3[2]; 905 u8 owner; 906} __packed; 907 908struct mlx4_init_port_param { 909 int set_guid0; 910 int set_node_guid; 911 int set_si_guid; 912 u16 mtu; 913 int port_width_cap; 914 u16 vl_cap; 915 u16 max_gid; 916 u16 max_pkey; 917 u64 guid0; 918 u64 node_guid; 919 u64 si_guid; 920}; 921 922#define MAD_IFC_DATA_SZ 192 923/* MAD IFC Mailbox */ 924struct mlx4_mad_ifc { 925 u8 base_version; 926 u8 mgmt_class; 927 u8 class_version; 928 u8 method; 929 __be16 status; 930 __be16 class_specific; 931 __be64 tid; 932 __be16 attr_id; 933 __be16 resv; 934 __be32 attr_mod; 935 __be64 mkey; 936 __be16 dr_slid; 937 __be16 dr_dlid; 938 u8 reserved[28]; 939 u8 data[MAD_IFC_DATA_SZ]; 940} __packed; 941 942#define mlx4_foreach_port(port, dev, type) \ 943 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 944 if ((type) == (dev)->caps.port_mask[(port)]) 945 946#define mlx4_foreach_non_ib_transport_port(port, dev) \ 947 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 948 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 949 950#define mlx4_foreach_ib_transport_port(port, dev) \ 951 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 952 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 953 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 954 955#define MLX4_INVALID_SLAVE_ID 0xFF 956 957#define MLX4_SINK_COUNTER_INDEX 0xff 958 959void handle_port_mgmt_change_event(struct work_struct *work); 960 961static inline int mlx4_master_func_num(struct mlx4_dev *dev) 962{ 963 return dev->caps.function; 964} 965 966static inline int mlx4_is_master(struct mlx4_dev *dev) 967{ 968 return dev->flags & MLX4_FLAG_MASTER; 969} 970 971static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 972{ 973 return dev->phys_caps.base_sqpn + 8 + 974 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 975} 976 977static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 978{ 979 return (qpn < dev->phys_caps.base_sqpn + 8 + 980 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); 981} 982 983static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 984{ 985 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 986 987 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 988 return 1; 989 990 return 0; 991} 992 993static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 994{ 995 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 996} 997 998static inline int mlx4_is_slave(struct mlx4_dev *dev) 999{ 1000 return dev->flags & MLX4_FLAG_SLAVE; 1001} 1002 1003int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1004 struct mlx4_buf *buf); 1005void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1006static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1007{ 1008 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 1009 return (u8 *)buf->direct.buf + offset; 1010 else 1011 return (u8 *)buf->page_list[offset >> PAGE_SHIFT].buf + 1012 (offset & (PAGE_SIZE - 1)); 1013} 1014 1015int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1016void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1017int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1018void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1019 1020int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1021void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1022int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1023void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1024 1025int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1026 struct mlx4_mtt *mtt); 1027void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1028u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1029 1030int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1031 int npages, int page_shift, struct mlx4_mr *mr); 1032int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1033int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1034int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1035 struct mlx4_mw *mw); 1036void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1037int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1038int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1039 int start_index, int npages, u64 *page_list); 1040int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1041 struct mlx4_buf *buf); 1042 1043int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 1044void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1045 1046int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1047 int size, int max_direct); 1048void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1049 int size); 1050 1051int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1052 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1053 unsigned vector, int collapsed, int timestamp_en); 1054void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1055 1056int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1057 int *base, u8 flags); 1058void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1059 1060int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 1061void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1062 1063int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1064 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1065void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1066int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1067int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1068 1069int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1070int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1071 1072int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1073 int block_mcast_loopback, enum mlx4_protocol prot); 1074int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1075 enum mlx4_protocol prot); 1076int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1077 u8 port, int block_mcast_loopback, 1078 enum mlx4_protocol protocol, u64 *reg_id); 1079int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1080 enum mlx4_protocol protocol, u64 reg_id); 1081 1082enum { 1083 MLX4_DOMAIN_UVERBS = 0x1000, 1084 MLX4_DOMAIN_ETHTOOL = 0x2000, 1085 MLX4_DOMAIN_RFS = 0x3000, 1086 MLX4_DOMAIN_NIC = 0x5000, 1087}; 1088 1089enum mlx4_net_trans_rule_id { 1090 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1091 MLX4_NET_TRANS_RULE_ID_IB, 1092 MLX4_NET_TRANS_RULE_ID_IPV6, 1093 MLX4_NET_TRANS_RULE_ID_IPV4, 1094 MLX4_NET_TRANS_RULE_ID_TCP, 1095 MLX4_NET_TRANS_RULE_ID_UDP, 1096 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1097 MLX4_NET_TRANS_RULE_DUMMY = -1, /* force enum to be signed */ 1098}; 1099 1100extern const u16 __sw_id_hw[]; 1101 1102static inline int map_hw_to_sw_id(u16 header_id) 1103{ 1104 1105 int i; 1106 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1107 if (header_id == __sw_id_hw[i]) 1108 return i; 1109 } 1110 return -EINVAL; 1111} 1112 1113enum mlx4_net_trans_promisc_mode { 1114 MLX4_FS_REGULAR = 1, 1115 MLX4_FS_ALL_DEFAULT, 1116 MLX4_FS_MC_DEFAULT, 1117 MLX4_FS_UC_SNIFFER, 1118 MLX4_FS_MC_SNIFFER, 1119 MLX4_FS_MODE_NUM, /* should be last */ 1120 MLX4_FS_MODE_DUMMY = -1, /* force enum to be signed */ 1121}; 1122 1123struct mlx4_spec_eth { 1124 u8 dst_mac[6]; 1125 u8 dst_mac_msk[6]; 1126 u8 src_mac[6]; 1127 u8 src_mac_msk[6]; 1128 u8 ether_type_enable; 1129 __be16 ether_type; 1130 __be16 vlan_id_msk; 1131 __be16 vlan_id; 1132}; 1133 1134struct mlx4_spec_tcp_udp { 1135 __be16 dst_port; 1136 __be16 dst_port_msk; 1137 __be16 src_port; 1138 __be16 src_port_msk; 1139}; 1140 1141struct mlx4_spec_ipv4 { 1142 __be32 dst_ip; 1143 __be32 dst_ip_msk; 1144 __be32 src_ip; 1145 __be32 src_ip_msk; 1146}; 1147 1148struct mlx4_spec_ib { 1149 __be32 l3_qpn; 1150 __be32 qpn_msk; 1151 u8 dst_gid[16]; 1152 u8 dst_gid_msk[16]; 1153}; 1154 1155struct mlx4_spec_list { 1156 struct list_head list; 1157 enum mlx4_net_trans_rule_id id; 1158 union { 1159 struct mlx4_spec_eth eth; 1160 struct mlx4_spec_ib ib; 1161 struct mlx4_spec_ipv4 ipv4; 1162 struct mlx4_spec_tcp_udp tcp_udp; 1163 }; 1164}; 1165 1166enum mlx4_net_trans_hw_rule_queue { 1167 MLX4_NET_TRANS_Q_FIFO, 1168 MLX4_NET_TRANS_Q_LIFO, 1169}; 1170 1171struct mlx4_net_trans_rule { 1172 struct list_head list; 1173 enum mlx4_net_trans_hw_rule_queue queue_mode; 1174 bool exclusive; 1175 bool allow_loopback; 1176 enum mlx4_net_trans_promisc_mode promisc_mode; 1177 u8 port; 1178 u16 priority; 1179 u32 qpn; 1180}; 1181 1182struct mlx4_net_trans_rule_hw_ctrl { 1183 __be16 prio; 1184 u8 type; 1185 u8 flags; 1186 u8 rsvd1; 1187 u8 funcid; 1188 u8 vep; 1189 u8 port; 1190 __be32 qpn; 1191 __be32 rsvd2; 1192}; 1193 1194struct mlx4_net_trans_rule_hw_ib { 1195 u8 size; 1196 u8 rsvd1; 1197 __be16 id; 1198 u32 rsvd2; 1199 __be32 l3_qpn; 1200 __be32 qpn_mask; 1201 u8 dst_gid[16]; 1202 u8 dst_gid_msk[16]; 1203} __packed; 1204 1205struct mlx4_net_trans_rule_hw_eth { 1206 u8 size; 1207 u8 rsvd; 1208 __be16 id; 1209 u8 rsvd1[6]; 1210 u8 dst_mac[6]; 1211 u16 rsvd2; 1212 u8 dst_mac_msk[6]; 1213 u16 rsvd3; 1214 u8 src_mac[6]; 1215 u16 rsvd4; 1216 u8 src_mac_msk[6]; 1217 u8 rsvd5; 1218 u8 ether_type_enable; 1219 __be16 ether_type; 1220 __be16 vlan_tag_msk; 1221 __be16 vlan_tag; 1222} __packed; 1223 1224struct mlx4_net_trans_rule_hw_tcp_udp { 1225 u8 size; 1226 u8 rsvd; 1227 __be16 id; 1228 __be16 rsvd1[3]; 1229 __be16 dst_port; 1230 __be16 rsvd2; 1231 __be16 dst_port_msk; 1232 __be16 rsvd3; 1233 __be16 src_port; 1234 __be16 rsvd4; 1235 __be16 src_port_msk; 1236} __packed; 1237 1238struct mlx4_net_trans_rule_hw_ipv4 { 1239 u8 size; 1240 u8 rsvd; 1241 __be16 id; 1242 __be32 rsvd1; 1243 __be32 dst_ip; 1244 __be32 dst_ip_msk; 1245 __be32 src_ip; 1246 __be32 src_ip_msk; 1247} __packed; 1248 1249struct _rule_hw { 1250 union { 1251 struct { 1252 u8 size; 1253 u8 rsvd; 1254 __be16 id; 1255 }; 1256 struct mlx4_net_trans_rule_hw_eth eth; 1257 struct mlx4_net_trans_rule_hw_ib ib; 1258 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1259 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1260 }; 1261}; 1262 1263int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1264 enum mlx4_net_trans_promisc_mode mode); 1265int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1266 enum mlx4_net_trans_promisc_mode mode); 1267int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1268int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1269int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1270int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1271 1272int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1273void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1274int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1275int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1276int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1277 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1278int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1279 u8 promisc); 1280int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 1281int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 1282 u8 *pg, u16 *ratelimit); 1283int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1284int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1285void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1286 1287int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1288 int npages, u64 iova, u32 *lkey, u32 *rkey); 1289int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1290 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1291int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1292void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1293 u32 *lkey, u32 *rkey); 1294int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1295int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1296int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length, 1297 u8 op_modifier, u32 in_offset[], 1298 u32 counter_out[]); 1299 1300int mlx4_test_interrupts(struct mlx4_dev *dev); 1301int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector); 1302void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1303 1304int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1305int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1306 1307int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx); 1308void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx); 1309 1310int mlx4_flow_attach(struct mlx4_dev *dev, 1311 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1312int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1313int map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1314 enum mlx4_net_trans_promisc_mode flow_type); 1315int map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1316 enum mlx4_net_trans_rule_id id); 1317int hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1318 1319void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1320 int i, int val); 1321 1322int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1323 1324int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1325int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1326int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1327int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr, u16 lid, u8 sl); 1328int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1329enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1330int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1331 1332void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1333__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1334int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id); 1335int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid); 1336 1337int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, u32 max_range_qpn); 1338 1339s64 mlx4_read_clock(struct mlx4_dev *dev); 1340int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1341 struct mlx4_clock_params *params); 1342 1343int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1344 u16 offset, u16 size, u8 *data); 1345 1346#endif /* MLX4_DEVICE_H */ 1347