1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36#define LINUXKPI_PARAM_PREFIX mlx4_ 37 38#include <linux/kmod.h> 39/* 40 * kmod.h must be included before module.h since it includes (indirectly) sys/module.h 41 * To use the FBSD macro sys/module.h should define MODULE_VERSION before linux/module does. 42*/ 43#include <linux/module.h> 44#include <linux/errno.h> 45#include <linux/pci.h> 46#include <linux/dma-mapping.h> 47#include <linux/slab.h> 48#include <linux/io-mapping.h> 49#include <linux/delay.h> 50#include <linux/netdevice.h> 51#include <linux/string.h> 52#include <linux/fs.h> 53 54#include <linux/mlx4/device.h> 55#include <linux/mlx4/doorbell.h> 56 57#include "mlx4.h" 58#include "fw.h" 59#include "icm.h" 60#include "mlx4_stats.h" 61 62/* Mellanox ConnectX HCA low-level driver */ 63 64struct workqueue_struct *mlx4_wq; 65 66#ifdef CONFIG_MLX4_DEBUG 67 68int mlx4_debug_level = 0; 69module_param_named(debug_level, mlx4_debug_level, int, 0644); 70MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 71 72#endif /* CONFIG_MLX4_DEBUG */ 73 74#ifdef CONFIG_PCI_MSI 75 76static int msi_x = 1; 77module_param(msi_x, int, 0444); 78MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x (non-SRIOV only)"); 79 80#else /* CONFIG_PCI_MSI */ 81 82#define msi_x (0) 83 84#endif /* CONFIG_PCI_MSI */ 85 86static int enable_sys_tune = 0; 87module_param(enable_sys_tune, int, 0444); 88MODULE_PARM_DESC(enable_sys_tune, "Tune the cpu's for better performance (default 0)"); 89 90int mlx4_blck_lb = 1; 91module_param_named(block_loopback, mlx4_blck_lb, int, 0644); 92MODULE_PARM_DESC(block_loopback, "Block multicast loopback packets if > 0 " 93 "(default: 1)"); 94enum { 95 DEFAULT_DOMAIN = 0, 96 BDF_STR_SIZE = 8, /* bb:dd.f- */ 97 DBDF_STR_SIZE = 13 /* mmmm:bb:dd.f- */ 98}; 99 100enum { 101 NUM_VFS, 102 PROBE_VF, 103 PORT_TYPE_ARRAY 104}; 105 106enum { 107 VALID_DATA, 108 INVALID_DATA, 109 INVALID_STR 110}; 111 112struct param_data { 113 int id; 114 struct mlx4_dbdf2val_lst dbdf2val; 115}; 116 117static struct param_data num_vfs = { 118 .id = NUM_VFS, 119 .dbdf2val = { 120 .name = "num_vfs param", 121 .num_vals = 1, 122 .def_val = {0}, 123 .range = {0, MLX4_MAX_NUM_VF} 124 } 125}; 126module_param_string(num_vfs, num_vfs.dbdf2val.str, 127 sizeof(num_vfs.dbdf2val.str), 0444); 128MODULE_PARM_DESC(num_vfs, 129 "Either single value (e.g. '5') to define uniform num_vfs value for all devices functions\n" 130 "\t\tor a string to map device function numbers to their num_vfs values (e.g. '0000:04:00.0-5,002b:1c:0b.a-15').\n" 131 "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for num_vfs value (e.g. 15)."); 132 133static struct param_data probe_vf = { 134 .id = PROBE_VF, 135 .dbdf2val = { 136 .name = "probe_vf param", 137 .num_vals = 1, 138 .def_val = {0}, 139 .range = {0, MLX4_MAX_NUM_VF} 140 } 141}; 142module_param_string(probe_vf, probe_vf.dbdf2val.str, 143 sizeof(probe_vf.dbdf2val.str), 0444); 144MODULE_PARM_DESC(probe_vf, 145 "Either single value (e.g. '3') to define uniform number of VFs to probe by the pf driver for all devices functions\n" 146 "\t\tor a string to map device function numbers to their probe_vf values (e.g. '0000:04:00.0-3,002b:1c:0b.a-13').\n" 147 "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for probe_vf value (e.g. 13)."); 148 149int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 150 151module_param_named(log_num_mgm_entry_size, 152 mlx4_log_num_mgm_entry_size, int, 0444); 153MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 154 " of qp per mcg, for example:" 155 " 10 gives 248.range: 7 <=" 156 " log_num_mgm_entry_size <= 12." 157 " To activate device managed" 158 " flow steering when available, set to -1"); 159 160static int high_rate_steer; 161module_param(high_rate_steer, int, 0444); 162MODULE_PARM_DESC(high_rate_steer, "Enable steering mode for higher packet rate" 163 " (default off)"); 164 165static int fast_drop; 166module_param_named(fast_drop, fast_drop, int, 0444); 167MODULE_PARM_DESC(fast_drop, 168 "Enable fast packet drop when no recieve WQEs are posted"); 169 170int mlx4_enable_64b_cqe_eqe = 1; 171module_param_named(enable_64b_cqe_eqe, mlx4_enable_64b_cqe_eqe, int, 0644); 172MODULE_PARM_DESC(enable_64b_cqe_eqe, 173 "Enable 64 byte CQEs/EQEs when the the FW supports this if non-zero (default: 1)"); 174 175#define HCA_GLOBAL_CAP_MASK 0 176 177#define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE 178 179static char mlx4_version[] __devinitdata = 180 DRV_NAME ": Mellanox ConnectX VPI driver v" 181 DRV_VERSION " (" DRV_RELDATE ")\n"; 182 183static int log_num_mac = 7; 184module_param_named(log_num_mac, log_num_mac, int, 0444); 185MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 186 187static int log_num_vlan; 188module_param_named(log_num_vlan, log_num_vlan, int, 0444); 189MODULE_PARM_DESC(log_num_vlan, 190 "(Obsolete) Log2 max number of VLANs per ETH port (0-7)"); 191/* Log2 max number of VLANs per ETH port (0-7) */ 192#define MLX4_LOG_NUM_VLANS 7 193 194int log_mtts_per_seg = ilog2(1); 195module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 196MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment " 197 "(0-7) (default: 0)"); 198 199static struct param_data port_type_array = { 200 .id = PORT_TYPE_ARRAY, 201 .dbdf2val = { 202 .name = "port_type_array param", 203 .num_vals = 2, 204 .def_val = {MLX4_PORT_TYPE_ETH, MLX4_PORT_TYPE_ETH}, 205 .range = {MLX4_PORT_TYPE_IB, MLX4_PORT_TYPE_NA} 206 } 207}; 208module_param_string(port_type_array, port_type_array.dbdf2val.str, 209 sizeof(port_type_array.dbdf2val.str), 0444); 210MODULE_PARM_DESC(port_type_array, 211 "Either pair of values (e.g. '1,2') to define uniform port1/port2 types configuration for all devices functions\n" 212 "\t\tor a string to map device function numbers to their pair of port types values (e.g. '0000:04:00.0-1;2,002b:1c:0b.a-1;1').\n" 213 "\t\tValid port types: 1-ib, 2-eth, 3-auto, 4-N/A\n" 214 "\t\tIn case that only one port is available use the N/A port type for port2 (e.g '1,4')."); 215 216 217struct mlx4_port_config { 218 struct list_head list; 219 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 220 struct pci_dev *pdev; 221}; 222 223#define MLX4_LOG_NUM_MTT 20 224/* We limit to 30 as of a bit map issue which uses int and not uint. 225 see mlx4_buddy_init -> bitmap_zero which gets int. 226*/ 227#define MLX4_MAX_LOG_NUM_MTT 30 228static struct mlx4_profile mod_param_profile = { 229 .num_qp = 19, 230 .num_srq = 16, 231 .rdmarc_per_qp = 4, 232 .num_cq = 16, 233 .num_mcg = 13, 234 .num_mpt = 19, 235 .num_mtt_segs = 0, /* max(20, 2*MTTs for host memory)) */ 236}; 237 238module_param_named(log_num_qp, mod_param_profile.num_qp, int, 0444); 239MODULE_PARM_DESC(log_num_qp, "log maximum number of QPs per HCA (default: 19)"); 240 241module_param_named(log_num_srq, mod_param_profile.num_srq, int, 0444); 242MODULE_PARM_DESC(log_num_srq, "log maximum number of SRQs per HCA " 243 "(default: 16)"); 244 245module_param_named(log_rdmarc_per_qp, mod_param_profile.rdmarc_per_qp, int, 246 0444); 247MODULE_PARM_DESC(log_rdmarc_per_qp, "log number of RDMARC buffers per QP " 248 "(default: 4)"); 249 250module_param_named(log_num_cq, mod_param_profile.num_cq, int, 0444); 251MODULE_PARM_DESC(log_num_cq, "log maximum number of CQs per HCA (default: 16)"); 252 253module_param_named(log_num_mcg, mod_param_profile.num_mcg, int, 0444); 254MODULE_PARM_DESC(log_num_mcg, "log maximum number of multicast groups per HCA " 255 "(default: 13)"); 256 257module_param_named(log_num_mpt, mod_param_profile.num_mpt, int, 0444); 258MODULE_PARM_DESC(log_num_mpt, 259 "log maximum number of memory protection table entries per " 260 "HCA (default: 19)"); 261 262module_param_named(log_num_mtt, mod_param_profile.num_mtt_segs, int, 0444); 263MODULE_PARM_DESC(log_num_mtt, 264 "log maximum number of memory translation table segments per " 265 "HCA (default: max(20, 2*MTTs for register all of the host memory limited to 30))"); 266 267enum { 268 MLX4_IF_STATE_BASIC, 269 MLX4_IF_STATE_EXTENDED 270}; 271 272static inline u64 dbdf_to_u64(int domain, int bus, int dev, int fn) 273{ 274 return (domain << 20) | (bus << 12) | (dev << 4) | fn; 275} 276 277static inline void pr_bdf_err(const char *dbdf, const char *pname) 278{ 279 pr_warn("mlx4_core: '%s' is not valid bdf in '%s'\n", dbdf, pname); 280} 281 282static inline void pr_val_err(const char *dbdf, const char *pname, 283 const char *val) 284{ 285 pr_warn("mlx4_core: value '%s' of bdf '%s' in '%s' is not valid\n" 286 , val, dbdf, pname); 287} 288 289static inline void pr_out_of_range_bdf(const char *dbdf, int val, 290 struct mlx4_dbdf2val_lst *dbdf2val) 291{ 292 pr_warn("mlx4_core: value %d in bdf '%s' of '%s' is out of its valid range (%d,%d)\n" 293 , val, dbdf, dbdf2val->name , dbdf2val->range.min, 294 dbdf2val->range.max); 295} 296 297static inline void pr_out_of_range(struct mlx4_dbdf2val_lst *dbdf2val) 298{ 299 pr_warn("mlx4_core: value of '%s' is out of its valid range (%d,%d)\n" 300 , dbdf2val->name , dbdf2val->range.min, dbdf2val->range.max); 301} 302 303static inline int is_in_range(int val, struct mlx4_range *r) 304{ 305 return (val >= r->min && val <= r->max); 306} 307 308static int update_defaults(struct param_data *pdata) 309{ 310 long int val[MLX4_MAX_BDF_VALS]; 311 int ret; 312 char *t, *p = pdata->dbdf2val.str; 313 char sval[32]; 314 int val_len; 315 316 if (!strlen(p) || strchr(p, ':') || strchr(p, '.') || strchr(p, ';')) 317 return INVALID_STR; 318 319 switch (pdata->id) { 320 case PORT_TYPE_ARRAY: 321 t = strchr(p, ','); 322 if (!t || t == p || (t - p) > sizeof(sval)) 323 return INVALID_STR; 324 325 val_len = t - p; 326 strncpy(sval, p, val_len); 327 sval[val_len] = 0; 328 329 ret = kstrtol(sval, 0, &val[0]); 330 if (ret == -EINVAL) 331 return INVALID_STR; 332 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) { 333 pr_out_of_range(&pdata->dbdf2val); 334 return INVALID_DATA; 335 } 336 337 ret = kstrtol(t + 1, 0, &val[1]); 338 if (ret == -EINVAL) 339 return INVALID_STR; 340 if (ret || !is_in_range(val[1], &pdata->dbdf2val.range)) { 341 pr_out_of_range(&pdata->dbdf2val); 342 return INVALID_DATA; 343 } 344 345 pdata->dbdf2val.tbl[0].val[0] = val[0]; 346 pdata->dbdf2val.tbl[0].val[1] = val[1]; 347 break; 348 349 case NUM_VFS: 350 case PROBE_VF: 351 ret = kstrtol(p, 0, &val[0]); 352 if (ret == -EINVAL) 353 return INVALID_STR; 354 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) { 355 pr_out_of_range(&pdata->dbdf2val); 356 return INVALID_DATA; 357 } 358 pdata->dbdf2val.tbl[0].val[0] = val[0]; 359 break; 360 } 361 pdata->dbdf2val.tbl[1].dbdf = MLX4_ENDOF_TBL; 362 363 return VALID_DATA; 364} 365 366int mlx4_fill_dbdf2val_tbl(struct mlx4_dbdf2val_lst *dbdf2val_lst) 367{ 368 int domain, bus, dev, fn; 369 u64 dbdf; 370 char *p, *t, *v; 371 char tmp[32]; 372 char sbdf[32]; 373 char sep = ','; 374 int j, k, str_size, i = 1; 375 int prfx_size; 376 377 p = dbdf2val_lst->str; 378 379 for (j = 0; j < dbdf2val_lst->num_vals; j++) 380 dbdf2val_lst->tbl[0].val[j] = dbdf2val_lst->def_val[j]; 381 dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL; 382 383 str_size = strlen(dbdf2val_lst->str); 384 385 if (str_size == 0) 386 return 0; 387 388 while (strlen(p)) { 389 prfx_size = BDF_STR_SIZE; 390 sbdf[prfx_size] = 0; 391 strncpy(sbdf, p, prfx_size); 392 domain = DEFAULT_DOMAIN; 393 if (sscanf(sbdf, "%02x:%02x.%x-", &bus, &dev, &fn) != 3) { 394 prfx_size = DBDF_STR_SIZE; 395 sbdf[prfx_size] = 0; 396 strncpy(sbdf, p, prfx_size); 397 if (sscanf(sbdf, "%04x:%02x:%02x.%x-", &domain, &bus, 398 &dev, &fn) != 4) { 399 pr_bdf_err(sbdf, dbdf2val_lst->name); 400 goto err; 401 } 402 sprintf(tmp, "%04x:%02x:%02x.%x-", domain, bus, dev, 403 fn); 404 } else { 405 sprintf(tmp, "%02x:%02x.%x-", bus, dev, fn); 406 } 407 408 if (strnicmp(sbdf, tmp, sizeof(tmp))) { 409 pr_bdf_err(sbdf, dbdf2val_lst->name); 410 goto err; 411 } 412 413 dbdf = dbdf_to_u64(domain, bus, dev, fn); 414 415 for (j = 1; j < i; j++) 416 if (dbdf2val_lst->tbl[j].dbdf == dbdf) { 417 pr_warn("mlx4_core: in '%s', %s appears multiple times\n" 418 , dbdf2val_lst->name, sbdf); 419 goto err; 420 } 421 422 if (i >= MLX4_DEVS_TBL_SIZE) { 423 pr_warn("mlx4_core: Too many devices in '%s'\n" 424 , dbdf2val_lst->name); 425 goto err; 426 } 427 428 p += prfx_size; 429 t = strchr(p, sep); 430 t = t ? t : p + strlen(p); 431 if (p >= t) { 432 pr_val_err(sbdf, dbdf2val_lst->name, ""); 433 goto err; 434 } 435 436 for (k = 0; k < dbdf2val_lst->num_vals; k++) { 437 char sval[32]; 438 long int val; 439 int ret, val_len; 440 char vsep = ';'; 441 442 v = (k == dbdf2val_lst->num_vals - 1) ? t : strchr(p, vsep); 443 if (!v || v > t || v == p || (v - p) > sizeof(sval)) { 444 pr_val_err(sbdf, dbdf2val_lst->name, p); 445 goto err; 446 } 447 val_len = v - p; 448 strncpy(sval, p, val_len); 449 sval[val_len] = 0; 450 451 ret = kstrtol(sval, 0, &val); 452 if (ret) { 453 if (strchr(p, vsep)) 454 pr_warn("mlx4_core: too many vals in bdf '%s' of '%s'\n" 455 , sbdf, dbdf2val_lst->name); 456 else 457 pr_val_err(sbdf, dbdf2val_lst->name, 458 sval); 459 goto err; 460 } 461 if (!is_in_range(val, &dbdf2val_lst->range)) { 462 pr_out_of_range_bdf(sbdf, val, dbdf2val_lst); 463 goto err; 464 } 465 466 dbdf2val_lst->tbl[i].val[k] = val; 467 p = v; 468 if (p[0] == vsep) 469 p++; 470 } 471 472 dbdf2val_lst->tbl[i].dbdf = dbdf; 473 if (strlen(p)) { 474 if (p[0] != sep) { 475 pr_warn("mlx4_core: expect separator '%c' before '%s' in '%s'\n" 476 , sep, p, dbdf2val_lst->name); 477 goto err; 478 } 479 p++; 480 } 481 i++; 482 if (i < MLX4_DEVS_TBL_SIZE) 483 dbdf2val_lst->tbl[i].dbdf = MLX4_ENDOF_TBL; 484 } 485 486 return 0; 487 488err: 489 dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL; 490 pr_warn("mlx4_core: The value of '%s' is incorrect. The value is discarded!\n" 491 , dbdf2val_lst->name); 492 493 return -EINVAL; 494} 495EXPORT_SYMBOL(mlx4_fill_dbdf2val_tbl); 496 497int mlx4_get_val(struct mlx4_dbdf2val *tbl, struct pci_dev *pdev, int idx, 498 int *val) 499{ 500 u64 dbdf; 501 int i = 1; 502 503 *val = tbl[0].val[idx]; 504 if (!pdev) 505 return -EINVAL; 506 507 dbdf = dbdf_to_u64(pci_get_domain(pdev->dev.bsddev), pci_get_bus(pdev->dev.bsddev), 508 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 509 510 while ((i < MLX4_DEVS_TBL_SIZE) && (tbl[i].dbdf != MLX4_ENDOF_TBL)) { 511 if (tbl[i].dbdf == dbdf) { 512 *val = tbl[i].val[idx]; 513 return 0; 514 } 515 i++; 516 } 517 518 return 0; 519} 520EXPORT_SYMBOL(mlx4_get_val); 521 522static void process_mod_param_profile(struct mlx4_profile *profile) 523{ 524 vm_size_t hwphyssz; 525 hwphyssz = 0; 526 TUNABLE_ULONG_FETCH("hw.realmem", (u_long *) &hwphyssz); 527 528 profile->num_qp = 1 << mod_param_profile.num_qp; 529 profile->num_srq = 1 << mod_param_profile.num_srq; 530 profile->rdmarc_per_qp = 1 << mod_param_profile.rdmarc_per_qp; 531 profile->num_cq = 1 << mod_param_profile.num_cq; 532 profile->num_mcg = 1 << mod_param_profile.num_mcg; 533 profile->num_mpt = 1 << mod_param_profile.num_mpt; 534 /* 535 * We want to scale the number of MTTs with the size of the 536 * system memory, since it makes sense to register a lot of 537 * memory on a system with a lot of memory. As a heuristic, 538 * make sure we have enough MTTs to register twice the system 539 * memory (with PAGE_SIZE entries). 540 * 541 * This number has to be a power of two and fit into 32 bits 542 * due to device limitations. We cap this at 2^30 as of bit map 543 * limitation to work with int instead of uint (mlx4_buddy_init -> bitmap_zero) 544 * That limits us to 4TB of memory registration per HCA with 545 * 4KB pages, which is probably OK for the next few months. 546 */ 547 if (mod_param_profile.num_mtt_segs) 548 profile->num_mtt_segs = 1 << mod_param_profile.num_mtt_segs; 549 else { 550 profile->num_mtt_segs = 551 roundup_pow_of_two(max_t(unsigned, 552 1 << (MLX4_LOG_NUM_MTT - log_mtts_per_seg), 553 min(1UL << 554 (MLX4_MAX_LOG_NUM_MTT - 555 log_mtts_per_seg), 556 (hwphyssz << 1) 557 >> log_mtts_per_seg))); 558 /* set the actual value, so it will be reflected to the user 559 using the sysfs */ 560 mod_param_profile.num_mtt_segs = ilog2(profile->num_mtt_segs); 561 } 562} 563 564int mlx4_check_port_params(struct mlx4_dev *dev, 565 enum mlx4_port_type *port_type) 566{ 567 int i; 568 569 for (i = 0; i < dev->caps.num_ports - 1; i++) { 570 if (port_type[i] != port_type[i + 1]) { 571 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 572 mlx4_err(dev, "Only same port types supported " 573 "on this HCA, aborting.\n"); 574 return -EINVAL; 575 } 576 } 577 } 578 579 for (i = 0; i < dev->caps.num_ports; i++) { 580 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 581 mlx4_err(dev, "Requested port type for port %d is not " 582 "supported on this HCA\n", i + 1); 583 return -EINVAL; 584 } 585 } 586 return 0; 587} 588 589static void mlx4_set_port_mask(struct mlx4_dev *dev) 590{ 591 int i; 592 593 for (i = 1; i <= dev->caps.num_ports; ++i) 594 dev->caps.port_mask[i] = dev->caps.port_type[i]; 595} 596 597enum { 598 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 599}; 600 601static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 602{ 603 int err = 0; 604 struct mlx4_func func; 605 606 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 607 err = mlx4_QUERY_FUNC(dev, &func, 0); 608 if (err) { 609 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 610 return err; 611 } 612 dev_cap->max_eqs = func.max_eq; 613 dev_cap->reserved_eqs = func.rsvd_eqs; 614 dev_cap->reserved_uars = func.rsvd_uars; 615 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 616 } 617 return err; 618} 619 620static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 621{ 622 int err; 623 int i; 624 625 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 626 if (err) { 627 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 628 return err; 629 } 630 631 if (dev_cap->min_page_sz > PAGE_SIZE) { 632 mlx4_err(dev, "HCA minimum page size of %d bigger than " 633 "kernel PAGE_SIZE of %d, aborting.\n", 634 dev_cap->min_page_sz, (int)PAGE_SIZE); 635 return -ENODEV; 636 } 637 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 638 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 639 "aborting.\n", 640 dev_cap->num_ports, MLX4_MAX_PORTS); 641 return -ENODEV; 642 } 643 644 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { 645 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than " 646 "PCI resource 2 size of 0x%llx, aborting.\n", 647 dev_cap->uar_size, 648 (unsigned long long) pci_resource_len(dev->pdev, 2)); 649 return -ENODEV; 650 } 651 652 dev->caps.num_ports = dev_cap->num_ports; 653 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 654 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 655 dev->caps.num_sys_eqs : 656 MLX4_MAX_EQ_NUM; 657 for (i = 1; i <= dev->caps.num_ports; ++i) { 658 dev->caps.vl_cap[i] = dev_cap->max_vl[i]; 659 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; 660 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; 661 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; 662 /* set gid and pkey table operating lengths by default 663 * to non-sriov values */ 664 dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; 665 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; 666 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; 667 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; 668 dev->caps.def_mac[i] = dev_cap->def_mac[i]; 669 dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; 670 dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; 671 dev->caps.default_sense[i] = dev_cap->default_sense[i]; 672 dev->caps.trans_type[i] = dev_cap->trans_type[i]; 673 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; 674 dev->caps.wavelength[i] = dev_cap->wavelength[i]; 675 dev->caps.trans_code[i] = dev_cap->trans_code[i]; 676 } 677 678 dev->caps.uar_page_size = PAGE_SIZE; 679 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 680 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 681 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 682 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 683 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 684 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 685 dev->caps.max_wqes = dev_cap->max_qp_sz; 686 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 687 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 688 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 689 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 690 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 691 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 692 /* 693 * Subtract 1 from the limit because we need to allocate a 694 * spare CQE to enable resizing the CQ 695 */ 696 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 697 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 698 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 699 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 700 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 701 702 /* The first 128 UARs are used for EQ doorbells */ 703 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); 704 dev->caps.reserved_pds = dev_cap->reserved_pds; 705 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 706 dev_cap->reserved_xrcds : 0; 707 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 708 dev_cap->max_xrcds : 0; 709 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 710 711 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 712 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 713 dev->caps.flags = dev_cap->flags; 714 dev->caps.flags2 = dev_cap->flags2; 715 dev->caps.bmme_flags = dev_cap->bmme_flags; 716 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 717 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 718 dev->caps.cq_timestamp = dev_cap->timestamp_support; 719 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 720 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 721 722 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 723 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 724 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 725 /* Don't do sense port on multifunction devices (for now at least) */ 726 if (mlx4_is_mfunc(dev)) 727 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 728 729 dev->caps.log_num_macs = log_num_mac; 730 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 731 732 dev->caps.fast_drop = fast_drop ? 733 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FAST_DROP) : 734 0; 735 736 for (i = 1; i <= dev->caps.num_ports; ++i) { 737 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 738 if (dev->caps.supported_type[i]) { 739 /* if only ETH is supported - assign ETH */ 740 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 741 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 742 /* if only IB is supported, assign IB */ 743 else if (dev->caps.supported_type[i] == 744 MLX4_PORT_TYPE_IB) 745 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 746 else { 747 /* 748 * if IB and ETH are supported, we set the port 749 * type according to user selection of port type; 750 * if there is no user selection, take the FW hint 751 */ 752 int pta; 753 mlx4_get_val(port_type_array.dbdf2val.tbl, 754 pci_physfn(dev->pdev), i - 1, 755 &pta); 756 if (pta == MLX4_PORT_TYPE_NONE) { 757 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 758 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 759 } else if (pta == MLX4_PORT_TYPE_NA) { 760 mlx4_err(dev, "Port %d is valid port. " 761 "It is not allowed to configure its type to N/A(%d)\n", 762 i, MLX4_PORT_TYPE_NA); 763 return -EINVAL; 764 } else { 765 dev->caps.port_type[i] = pta; 766 } 767 } 768 } 769 /* 770 * Link sensing is allowed on the port if 3 conditions are true: 771 * 1. Both protocols are supported on the port. 772 * 2. Different types are supported on the port 773 * 3. FW declared that it supports link sensing 774 */ 775 mlx4_priv(dev)->sense.sense_allowed[i] = 776 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 777 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 778 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 779 780 /* Disablling auto sense for default Eth ports support */ 781 mlx4_priv(dev)->sense.sense_allowed[i] = 0; 782 783 /* 784 * If "default_sense" bit is set, we move the port to "AUTO" mode 785 * and perform sense_port FW command to try and set the correct 786 * port type from beginning 787 */ 788 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 789 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 790 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 791 mlx4_SENSE_PORT(dev, i, &sensed_port); 792 if (sensed_port != MLX4_PORT_TYPE_NONE) 793 dev->caps.port_type[i] = sensed_port; 794 } else { 795 dev->caps.possible_type[i] = dev->caps.port_type[i]; 796 } 797 798 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { 799 dev->caps.log_num_macs = dev_cap->log_max_macs[i]; 800 mlx4_warn(dev, "Requested number of MACs is too much " 801 "for port %d, reducing to %d.\n", 802 i, 1 << dev->caps.log_num_macs); 803 } 804 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { 805 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; 806 mlx4_warn(dev, "Requested number of VLANs is too much " 807 "for port %d, reducing to %d.\n", 808 i, 1 << dev->caps.log_num_vlans); 809 } 810 } 811 812 dev->caps.max_basic_counters = dev_cap->max_basic_counters; 813 dev->caps.max_extended_counters = dev_cap->max_extended_counters; 814 /* support extended counters if available */ 815 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS_EXT) 816 dev->caps.max_counters = dev->caps.max_extended_counters; 817 else 818 dev->caps.max_counters = dev->caps.max_basic_counters; 819 820 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 821 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 822 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 823 (1 << dev->caps.log_num_macs) * 824 (1 << dev->caps.log_num_vlans) * 825 dev->caps.num_ports; 826 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 827 828 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 829 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 830 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 831 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 832 833 dev->caps.sync_qp = dev_cap->sync_qp; 834 if (dev->pdev->device == 0x1003) 835 dev->caps.cq_flags |= MLX4_DEV_CAP_CQ_FLAG_IO; 836 837 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 838 839 if (!mlx4_enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 840 if (dev_cap->flags & 841 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 842 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 843 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 844 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 845 } 846 } 847 848 if ((dev->caps.flags & 849 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 850 mlx4_is_master(dev)) 851 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 852 853 if (!mlx4_is_slave(dev)) { 854 for (i = 0; i < dev->caps.num_ports; ++i) 855 dev->caps.def_counter_index[i] = i << 1; 856 857 dev->caps.alloc_res_qp_mask = 858 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0); 859 } else { 860 dev->caps.alloc_res_qp_mask = 0; 861 } 862 863 return 0; 864} 865/*The function checks if there are live vf, return the num of them*/ 866static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 867{ 868 struct mlx4_priv *priv = mlx4_priv(dev); 869 struct mlx4_slave_state *s_state; 870 int i; 871 int ret = 0; 872 873 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 874 s_state = &priv->mfunc.master.slave_state[i]; 875 if (s_state->active && s_state->last_cmd != 876 MLX4_COMM_CMD_RESET) { 877 mlx4_warn(dev, "%s: slave: %d is still active\n", 878 __func__, i); 879 ret++; 880 } 881 } 882 return ret; 883} 884 885int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 886{ 887 u32 qk = MLX4_RESERVED_QKEY_BASE; 888 889 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 890 qpn < dev->phys_caps.base_proxy_sqpn) 891 return -EINVAL; 892 893 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 894 /* tunnel qp */ 895 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 896 else 897 qk += qpn - dev->phys_caps.base_proxy_sqpn; 898 *qkey = qk; 899 return 0; 900} 901EXPORT_SYMBOL(mlx4_get_parav_qkey); 902 903void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 904{ 905 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 906 907 if (!mlx4_is_master(dev)) 908 return; 909 910 priv->virt2phys_pkey[slave][port - 1][i] = val; 911} 912EXPORT_SYMBOL(mlx4_sync_pkey_table); 913 914void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 915{ 916 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 917 918 if (!mlx4_is_master(dev)) 919 return; 920 921 priv->slave_node_guids[slave] = guid; 922} 923EXPORT_SYMBOL(mlx4_put_slave_node_guid); 924 925__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 926{ 927 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 928 929 if (!mlx4_is_master(dev)) 930 return 0; 931 932 return priv->slave_node_guids[slave]; 933} 934EXPORT_SYMBOL(mlx4_get_slave_node_guid); 935 936int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 937{ 938 struct mlx4_priv *priv = mlx4_priv(dev); 939 struct mlx4_slave_state *s_slave; 940 941 if (!mlx4_is_master(dev)) 942 return 0; 943 944 s_slave = &priv->mfunc.master.slave_state[slave]; 945 return !!s_slave->active; 946} 947EXPORT_SYMBOL(mlx4_is_slave_active); 948 949static void slave_adjust_steering_mode(struct mlx4_dev *dev, 950 struct mlx4_dev_cap *dev_cap, 951 struct mlx4_init_hca_param *hca_param) 952{ 953 dev->caps.steering_mode = hca_param->steering_mode; 954 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) 955 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 956 else 957 dev->caps.num_qp_per_mgm = 958 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 959 960 mlx4_dbg(dev, "Steering mode is: %s\n", 961 mlx4_steering_mode_str(dev->caps.steering_mode)); 962} 963 964static int mlx4_slave_cap(struct mlx4_dev *dev) 965{ 966 int err; 967 u32 page_size; 968 struct mlx4_dev_cap dev_cap; 969 struct mlx4_func_cap func_cap; 970 struct mlx4_init_hca_param hca_param; 971 int i; 972 973 memset(&hca_param, 0, sizeof(hca_param)); 974 err = mlx4_QUERY_HCA(dev, &hca_param); 975 if (err) { 976 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n"); 977 return err; 978 } 979 980 /*fail if the hca has an unknown capability */ 981 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) != 982 HCA_GLOBAL_CAP_MASK) { 983 mlx4_err(dev, "Unknown hca global capabilities\n"); 984 return -ENOSYS; 985 } 986 987 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; 988 989 dev->caps.hca_core_clock = hca_param.hca_core_clock; 990 991 memset(&dev_cap, 0, sizeof(dev_cap)); 992 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; 993 err = mlx4_dev_cap(dev, &dev_cap); 994 if (err) { 995 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 996 return err; 997 } 998 999 err = mlx4_QUERY_FW(dev); 1000 if (err) 1001 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n"); 1002 1003 if (!hca_param.mw_enable) { 1004 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1005 dev->caps.bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1006 } 1007 1008 page_size = ~dev->caps.page_size_cap + 1; 1009 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 1010 if (page_size > PAGE_SIZE) { 1011 mlx4_err(dev, "HCA minimum page size of %d bigger than " 1012 "kernel PAGE_SIZE of %d, aborting.\n", 1013 page_size, (int)PAGE_SIZE); 1014 return -ENODEV; 1015 } 1016 1017 /* slave gets uar page size from QUERY_HCA fw command */ 1018 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); 1019 1020 /* TODO: relax this assumption */ 1021 if (dev->caps.uar_page_size != PAGE_SIZE) { 1022 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %d\n", 1023 dev->caps.uar_page_size, (int)PAGE_SIZE); 1024 return -ENODEV; 1025 } 1026 1027 memset(&func_cap, 0, sizeof(func_cap)); 1028 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); 1029 if (err) { 1030 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n", 1031 err); 1032 return err; 1033 } 1034 1035 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 1036 PF_CONTEXT_BEHAVIOUR_MASK) { 1037 mlx4_err(dev, "Unknown pf context behaviour\n"); 1038 return -ENOSYS; 1039 } 1040 1041 dev->caps.num_ports = func_cap.num_ports; 1042 dev->quotas.qp = func_cap.qp_quota; 1043 dev->quotas.srq = func_cap.srq_quota; 1044 dev->quotas.cq = func_cap.cq_quota; 1045 dev->quotas.mpt = func_cap.mpt_quota; 1046 dev->quotas.mtt = func_cap.mtt_quota; 1047 dev->caps.num_qps = 1 << hca_param.log_num_qps; 1048 dev->caps.num_srqs = 1 << hca_param.log_num_srqs; 1049 dev->caps.num_cqs = 1 << hca_param.log_num_cqs; 1050 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; 1051 dev->caps.num_eqs = func_cap.max_eq; 1052 dev->caps.reserved_eqs = func_cap.reserved_eq; 1053 dev->caps.num_pds = MLX4_NUM_PDS; 1054 dev->caps.num_mgms = 0; 1055 dev->caps.num_amgms = 0; 1056 1057 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 1058 mlx4_err(dev, "HCA has %d ports, but we only support %d, " 1059 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS); 1060 return -ENODEV; 1061 } 1062 1063 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 1064 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 1065 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 1066 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); 1067 1068 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || 1069 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) { 1070 err = -ENOMEM; 1071 goto err_mem; 1072 } 1073 1074 for (i = 1; i <= dev->caps.num_ports; ++i) { 1075 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap); 1076 if (err) { 1077 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for" 1078 " port %d, aborting (%d).\n", i, err); 1079 goto err_mem; 1080 } 1081 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; 1082 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; 1083 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; 1084 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; 1085 dev->caps.def_counter_index[i - 1] = func_cap.def_counter_index; 1086 1087 dev->caps.port_mask[i] = dev->caps.port_type[i]; 1088 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 1089 &dev->caps.gid_table_len[i], 1090 &dev->caps.pkey_table_len[i]); 1091 if (err) 1092 goto err_mem; 1093 } 1094 1095 if (dev->caps.uar_page_size * (dev->caps.num_uars - 1096 dev->caps.reserved_uars) > 1097 pci_resource_len(dev->pdev, 2)) { 1098 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than " 1099 "PCI resource 2 size of 0x%llx, aborting.\n", 1100 dev->caps.uar_page_size * dev->caps.num_uars, 1101 (unsigned long long) pci_resource_len(dev->pdev, 2)); 1102 err = -ENOMEM; 1103 goto err_mem; 1104 } 1105 1106 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1107 dev->caps.eqe_size = 64; 1108 dev->caps.eqe_factor = 1; 1109 } else { 1110 dev->caps.eqe_size = 32; 1111 dev->caps.eqe_factor = 0; 1112 } 1113 1114 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1115 dev->caps.cqe_size = 64; 1116 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; 1117 } else { 1118 dev->caps.cqe_size = 32; 1119 } 1120 1121 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1122 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n"); 1123 1124 slave_adjust_steering_mode(dev, &dev_cap, &hca_param); 1125 1126 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1127 dev->caps.bf_reg_size) 1128 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1129 1130 return 0; 1131 1132err_mem: 1133 kfree(dev->caps.qp0_tunnel); 1134 kfree(dev->caps.qp0_proxy); 1135 kfree(dev->caps.qp1_tunnel); 1136 kfree(dev->caps.qp1_proxy); 1137 dev->caps.qp0_tunnel = dev->caps.qp0_proxy = 1138 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL; 1139 1140 return err; 1141} 1142 1143static void mlx4_request_modules(struct mlx4_dev *dev) 1144{ 1145 int port; 1146 int has_ib_port = false; 1147 int has_eth_port = false; 1148#define EN_DRV_NAME "mlx4_en" 1149#define IB_DRV_NAME "mlx4_ib" 1150 1151 for (port = 1; port <= dev->caps.num_ports; port++) { 1152 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 1153 has_ib_port = true; 1154 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 1155 has_eth_port = true; 1156 } 1157 1158 if (has_ib_port) 1159 request_module_nowait(IB_DRV_NAME); 1160 if (has_eth_port) 1161 request_module_nowait(EN_DRV_NAME); 1162} 1163 1164/* 1165 * Change the port configuration of the device. 1166 * Every user of this function must hold the port mutex. 1167 */ 1168int mlx4_change_port_types(struct mlx4_dev *dev, 1169 enum mlx4_port_type *port_types) 1170{ 1171 int err = 0; 1172 int change = 0; 1173 int port; 1174 1175 for (port = 0; port < dev->caps.num_ports; port++) { 1176 /* Change the port type only if the new type is different 1177 * from the current, and not set to Auto */ 1178 if (port_types[port] != dev->caps.port_type[port + 1]) 1179 change = 1; 1180 } 1181 if (change) { 1182 mlx4_unregister_device(dev); 1183 for (port = 1; port <= dev->caps.num_ports; port++) { 1184 mlx4_CLOSE_PORT(dev, port); 1185 dev->caps.port_type[port] = port_types[port - 1]; 1186 err = mlx4_SET_PORT(dev, port, -1); 1187 if (err) { 1188 mlx4_err(dev, "Failed to set port %d, " 1189 "aborting\n", port); 1190 goto out; 1191 } 1192 } 1193 mlx4_set_port_mask(dev); 1194 err = mlx4_register_device(dev); 1195 if (err) { 1196 mlx4_err(dev, "Failed to register device\n"); 1197 goto out; 1198 } 1199 mlx4_request_modules(dev); 1200 } 1201 1202out: 1203 return err; 1204} 1205 1206static ssize_t show_port_type(struct device *dev, 1207 struct device_attribute *attr, 1208 char *buf) 1209{ 1210 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1211 port_attr); 1212 struct mlx4_dev *mdev = info->dev; 1213 char type[8]; 1214 1215 sprintf(type, "%s", 1216 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1217 "ib" : "eth"); 1218 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1219 sprintf(buf, "auto (%s)\n", type); 1220 else 1221 sprintf(buf, "%s\n", type); 1222 1223 return strlen(buf); 1224} 1225 1226static ssize_t set_port_type(struct device *dev, 1227 struct device_attribute *attr, 1228 const char *buf, size_t count) 1229{ 1230 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1231 port_attr); 1232 struct mlx4_dev *mdev = info->dev; 1233 struct mlx4_priv *priv = mlx4_priv(mdev); 1234 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1235 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1236 int i; 1237 int err = 0; 1238 1239 if (!strcmp(buf, "ib\n")) 1240 info->tmp_type = MLX4_PORT_TYPE_IB; 1241 else if (!strcmp(buf, "eth\n")) 1242 info->tmp_type = MLX4_PORT_TYPE_ETH; 1243 else if (!strcmp(buf, "auto\n")) 1244 info->tmp_type = MLX4_PORT_TYPE_AUTO; 1245 else { 1246 mlx4_err(mdev, "%s is not supported port type\n", buf); 1247 return -EINVAL; 1248 } 1249 1250 if ((info->tmp_type & mdev->caps.supported_type[info->port]) != 1251 info->tmp_type) { 1252 mlx4_err(mdev, "Requested port type for port %d is not supported on this HCA\n", 1253 info->port); 1254 return -EINVAL; 1255 } 1256 1257 mlx4_stop_sense(mdev); 1258 mutex_lock(&priv->port_mutex); 1259 /* Possible type is always the one that was delivered */ 1260 mdev->caps.possible_type[info->port] = info->tmp_type; 1261 1262 for (i = 0; i < mdev->caps.num_ports; i++) { 1263 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1264 mdev->caps.possible_type[i+1]; 1265 if (types[i] == MLX4_PORT_TYPE_AUTO) 1266 types[i] = mdev->caps.port_type[i+1]; 1267 } 1268 1269 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1270 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1271 for (i = 1; i <= mdev->caps.num_ports; i++) { 1272 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1273 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1274 err = -EINVAL; 1275 } 1276 } 1277 } 1278 if (err) { 1279 mlx4_err(mdev, "Auto sensing is not supported on this HCA. " 1280 "Set only 'eth' or 'ib' for both ports " 1281 "(should be the same)\n"); 1282 goto out; 1283 } 1284 1285 mlx4_do_sense_ports(mdev, new_types, types); 1286 1287 err = mlx4_check_port_params(mdev, new_types); 1288 if (err) 1289 goto out; 1290 1291 /* We are about to apply the changes after the configuration 1292 * was verified, no need to remember the temporary types 1293 * any more */ 1294 for (i = 0; i < mdev->caps.num_ports; i++) 1295 priv->port[i + 1].tmp_type = 0; 1296 1297 err = mlx4_change_port_types(mdev, new_types); 1298 1299out: 1300 mlx4_start_sense(mdev); 1301 mutex_unlock(&priv->port_mutex); 1302 return err ? err : count; 1303} 1304 1305enum ibta_mtu { 1306 IB_MTU_256 = 1, 1307 IB_MTU_512 = 2, 1308 IB_MTU_1024 = 3, 1309 IB_MTU_2048 = 4, 1310 IB_MTU_4096 = 5 1311}; 1312 1313static inline int int_to_ibta_mtu(int mtu) 1314{ 1315 switch (mtu) { 1316 case 256: return IB_MTU_256; 1317 case 512: return IB_MTU_512; 1318 case 1024: return IB_MTU_1024; 1319 case 2048: return IB_MTU_2048; 1320 case 4096: return IB_MTU_4096; 1321 default: return -1; 1322 } 1323} 1324 1325static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1326{ 1327 switch (mtu) { 1328 case IB_MTU_256: return 256; 1329 case IB_MTU_512: return 512; 1330 case IB_MTU_1024: return 1024; 1331 case IB_MTU_2048: return 2048; 1332 case IB_MTU_4096: return 4096; 1333 default: return -1; 1334 } 1335} 1336 1337static ssize_t 1338show_board(struct device *device, struct device_attribute *attr, 1339 char *buf) 1340{ 1341 struct mlx4_hca_info *info = container_of(attr, struct mlx4_hca_info, 1342 board_attr); 1343 struct mlx4_dev *mdev = info->dev; 1344 1345 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 1346 mdev->board_id); 1347} 1348 1349static ssize_t 1350show_hca(struct device *device, struct device_attribute *attr, 1351 char *buf) 1352{ 1353 struct mlx4_hca_info *info = container_of(attr, struct mlx4_hca_info, 1354 hca_attr); 1355 struct mlx4_dev *mdev = info->dev; 1356 1357 return sprintf(buf, "MT%d\n", mdev->pdev->device); 1358} 1359 1360static ssize_t 1361show_firmware_version(struct device *dev, 1362 struct device_attribute *attr, 1363 char *buf) 1364{ 1365 struct mlx4_hca_info *info = container_of(attr, struct mlx4_hca_info, 1366 firmware_attr); 1367 struct mlx4_dev *mdev = info->dev; 1368 1369 return sprintf(buf, "%d.%d.%d\n", (int)(mdev->caps.fw_ver >> 32), 1370 (int)(mdev->caps.fw_ver >> 16) & 0xffff, 1371 (int)mdev->caps.fw_ver & 0xffff); 1372} 1373 1374static ssize_t show_port_ib_mtu(struct device *dev, 1375 struct device_attribute *attr, 1376 char *buf) 1377{ 1378 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1379 port_mtu_attr); 1380 struct mlx4_dev *mdev = info->dev; 1381 1382 /* When port type is eth, port mtu value isn't used. */ 1383 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1384 return -EINVAL; 1385 1386 sprintf(buf, "%d\n", 1387 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1388 return strlen(buf); 1389} 1390 1391static ssize_t set_port_ib_mtu(struct device *dev, 1392 struct device_attribute *attr, 1393 const char *buf, size_t count) 1394{ 1395 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1396 port_mtu_attr); 1397 struct mlx4_dev *mdev = info->dev; 1398 struct mlx4_priv *priv = mlx4_priv(mdev); 1399 int err, port, mtu, ibta_mtu = -1; 1400 1401 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1402 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1403 return -EINVAL; 1404 } 1405 1406 mtu = (int) simple_strtol(buf, NULL, 0); 1407 ibta_mtu = int_to_ibta_mtu(mtu); 1408 1409 if (ibta_mtu < 0) { 1410 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1411 return -EINVAL; 1412 } 1413 1414 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1415 1416 mlx4_stop_sense(mdev); 1417 mutex_lock(&priv->port_mutex); 1418 mlx4_unregister_device(mdev); 1419 for (port = 1; port <= mdev->caps.num_ports; port++) { 1420 mlx4_CLOSE_PORT(mdev, port); 1421 err = mlx4_SET_PORT(mdev, port, -1); 1422 if (err) { 1423 mlx4_err(mdev, "Failed to set port %d, " 1424 "aborting\n", port); 1425 goto err_set_port; 1426 } 1427 } 1428 err = mlx4_register_device(mdev); 1429err_set_port: 1430 mutex_unlock(&priv->port_mutex); 1431 mlx4_start_sense(mdev); 1432 return err ? err : count; 1433} 1434 1435static int mlx4_load_fw(struct mlx4_dev *dev) 1436{ 1437 struct mlx4_priv *priv = mlx4_priv(dev); 1438 int err, unmap_flag = 0; 1439 1440 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1441 GFP_HIGHUSER | __GFP_NOWARN, 0); 1442 if (!priv->fw.fw_icm) { 1443 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n"); 1444 return -ENOMEM; 1445 } 1446 1447 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1448 if (err) { 1449 mlx4_err(dev, "MAP_FA command failed, aborting.\n"); 1450 goto err_free; 1451 } 1452 1453 err = mlx4_RUN_FW(dev); 1454 if (err) { 1455 mlx4_err(dev, "RUN_FW command failed, aborting.\n"); 1456 goto err_unmap_fa; 1457 } 1458 1459 return 0; 1460 1461err_unmap_fa: 1462 unmap_flag = mlx4_UNMAP_FA(dev); 1463 if (unmap_flag) 1464 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n"); 1465 1466err_free: 1467 if (!unmap_flag) 1468 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1469 return err; 1470} 1471 1472static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1473 int cmpt_entry_sz) 1474{ 1475 struct mlx4_priv *priv = mlx4_priv(dev); 1476 int err; 1477 int num_eqs; 1478 1479 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1480 cmpt_base + 1481 ((u64) (MLX4_CMPT_TYPE_QP * 1482 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1483 cmpt_entry_sz, dev->caps.num_qps, 1484 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1485 0, 0); 1486 if (err) 1487 goto err; 1488 1489 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1490 cmpt_base + 1491 ((u64) (MLX4_CMPT_TYPE_SRQ * 1492 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1493 cmpt_entry_sz, dev->caps.num_srqs, 1494 dev->caps.reserved_srqs, 0, 0); 1495 if (err) 1496 goto err_qp; 1497 1498 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1499 cmpt_base + 1500 ((u64) (MLX4_CMPT_TYPE_CQ * 1501 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1502 cmpt_entry_sz, dev->caps.num_cqs, 1503 dev->caps.reserved_cqs, 0, 0); 1504 if (err) 1505 goto err_srq; 1506 1507 num_eqs = dev->phys_caps.num_phys_eqs; 1508 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1509 cmpt_base + 1510 ((u64) (MLX4_CMPT_TYPE_EQ * 1511 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1512 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1513 if (err) 1514 goto err_cq; 1515 1516 return 0; 1517 1518err_cq: 1519 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1520 1521err_srq: 1522 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1523 1524err_qp: 1525 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1526 1527err: 1528 return err; 1529} 1530 1531static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1532 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1533{ 1534 struct mlx4_priv *priv = mlx4_priv(dev); 1535 u64 aux_pages; 1536 int num_eqs; 1537 int err, unmap_flag = 0; 1538 1539 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1540 if (err) { 1541 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n"); 1542 return err; 1543 } 1544 1545 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n", 1546 (unsigned long long) icm_size >> 10, 1547 (unsigned long long) aux_pages << 2); 1548 1549 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1550 GFP_HIGHUSER | __GFP_NOWARN, 0); 1551 if (!priv->fw.aux_icm) { 1552 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n"); 1553 return -ENOMEM; 1554 } 1555 1556 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1557 if (err) { 1558 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n"); 1559 goto err_free_aux; 1560 } 1561 1562 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1563 if (err) { 1564 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n"); 1565 goto err_unmap_aux; 1566 } 1567 1568 1569 num_eqs = dev->phys_caps.num_phys_eqs; 1570 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1571 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1572 num_eqs, num_eqs, 0, 0); 1573 if (err) { 1574 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n"); 1575 goto err_unmap_cmpt; 1576 } 1577 1578 /* 1579 * Reserved MTT entries must be aligned up to a cacheline 1580 * boundary, since the FW will write to them, while the driver 1581 * writes to all other MTT entries. (The variable 1582 * dev->caps.mtt_entry_sz below is really the MTT segment 1583 * size, not the raw entry size) 1584 */ 1585 dev->caps.reserved_mtts = 1586 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1587 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1588 1589 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1590 init_hca->mtt_base, 1591 dev->caps.mtt_entry_sz, 1592 dev->caps.num_mtts, 1593 dev->caps.reserved_mtts, 1, 0); 1594 if (err) { 1595 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n"); 1596 goto err_unmap_eq; 1597 } 1598 1599 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1600 init_hca->dmpt_base, 1601 dev_cap->dmpt_entry_sz, 1602 dev->caps.num_mpts, 1603 dev->caps.reserved_mrws, 1, 1); 1604 if (err) { 1605 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n"); 1606 goto err_unmap_mtt; 1607 } 1608 1609 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1610 init_hca->qpc_base, 1611 dev_cap->qpc_entry_sz, 1612 dev->caps.num_qps, 1613 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1614 0, 0); 1615 if (err) { 1616 mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); 1617 goto err_unmap_dmpt; 1618 } 1619 1620 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1621 init_hca->auxc_base, 1622 dev_cap->aux_entry_sz, 1623 dev->caps.num_qps, 1624 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1625 0, 0); 1626 if (err) { 1627 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); 1628 goto err_unmap_qp; 1629 } 1630 1631 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1632 init_hca->altc_base, 1633 dev_cap->altc_entry_sz, 1634 dev->caps.num_qps, 1635 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1636 0, 0); 1637 if (err) { 1638 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); 1639 goto err_unmap_auxc; 1640 } 1641 1642 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1643 init_hca->rdmarc_base, 1644 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1645 dev->caps.num_qps, 1646 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1647 0, 0); 1648 if (err) { 1649 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1650 goto err_unmap_altc; 1651 } 1652 1653 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1654 init_hca->cqc_base, 1655 dev_cap->cqc_entry_sz, 1656 dev->caps.num_cqs, 1657 dev->caps.reserved_cqs, 0, 0); 1658 if (err) { 1659 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n"); 1660 goto err_unmap_rdmarc; 1661 } 1662 1663 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1664 init_hca->srqc_base, 1665 dev_cap->srq_entry_sz, 1666 dev->caps.num_srqs, 1667 dev->caps.reserved_srqs, 0, 0); 1668 if (err) { 1669 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n"); 1670 goto err_unmap_cq; 1671 } 1672 1673 /* 1674 * For flow steering device managed mode it is required to use 1675 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1676 * required, but for simplicity just map the whole multicast 1677 * group table now. The table isn't very big and it's a lot 1678 * easier than trying to track ref counts. 1679 */ 1680 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1681 init_hca->mc_base, 1682 mlx4_get_mgm_entry_size(dev), 1683 dev->caps.num_mgms + dev->caps.num_amgms, 1684 dev->caps.num_mgms + dev->caps.num_amgms, 1685 0, 0); 1686 if (err) { 1687 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n"); 1688 goto err_unmap_srq; 1689 } 1690 1691 return 0; 1692 1693err_unmap_srq: 1694 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1695 1696err_unmap_cq: 1697 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1698 1699err_unmap_rdmarc: 1700 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1701 1702err_unmap_altc: 1703 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1704 1705err_unmap_auxc: 1706 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1707 1708err_unmap_qp: 1709 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1710 1711err_unmap_dmpt: 1712 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1713 1714err_unmap_mtt: 1715 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1716 1717err_unmap_eq: 1718 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1719 1720err_unmap_cmpt: 1721 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1722 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1723 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1724 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1725 1726err_unmap_aux: 1727 unmap_flag = mlx4_UNMAP_ICM_AUX(dev); 1728 if (unmap_flag) 1729 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n"); 1730 1731err_free_aux: 1732 if (!unmap_flag) 1733 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1734 1735 return err; 1736} 1737 1738static void mlx4_free_icms(struct mlx4_dev *dev) 1739{ 1740 struct mlx4_priv *priv = mlx4_priv(dev); 1741 1742 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1743 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1744 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1745 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1746 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1747 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1748 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1749 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1750 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1751 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1752 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1753 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1754 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1755 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1756 1757 if (!mlx4_UNMAP_ICM_AUX(dev)) 1758 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1759 else 1760 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n"); 1761} 1762 1763static void mlx4_slave_exit(struct mlx4_dev *dev) 1764{ 1765 struct mlx4_priv *priv = mlx4_priv(dev); 1766 1767 mutex_lock(&priv->cmd.slave_cmd_mutex); 1768 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) 1769 mlx4_warn(dev, "Failed to close slave function.\n"); 1770 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1771} 1772 1773static int map_bf_area(struct mlx4_dev *dev) 1774{ 1775 struct mlx4_priv *priv = mlx4_priv(dev); 1776 resource_size_t bf_start; 1777 resource_size_t bf_len; 1778 int err = 0; 1779 1780 if (!dev->caps.bf_reg_size) 1781 return -ENXIO; 1782 1783 bf_start = pci_resource_start(dev->pdev, 2) + 1784 (dev->caps.num_uars << PAGE_SHIFT); 1785 bf_len = pci_resource_len(dev->pdev, 2) - 1786 (dev->caps.num_uars << PAGE_SHIFT); 1787 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1788 if (!priv->bf_mapping) 1789 err = -ENOMEM; 1790 1791 return err; 1792} 1793 1794static void unmap_bf_area(struct mlx4_dev *dev) 1795{ 1796 if (mlx4_priv(dev)->bf_mapping) 1797 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1798} 1799 1800s64 mlx4_read_clock(struct mlx4_dev *dev) 1801{ 1802 u32 clockhi, clocklo, clockhi1; 1803 s64 cycles; 1804 int i; 1805 struct mlx4_priv *priv = mlx4_priv(dev); 1806 1807 if (!priv->clock_mapping) 1808 return -ENOTSUPP; 1809 1810 for (i = 0; i < 10; i++) { 1811 clockhi = swab32(readl(priv->clock_mapping)); 1812 clocklo = swab32(readl(priv->clock_mapping + 4)); 1813 clockhi1 = swab32(readl(priv->clock_mapping)); 1814 if (clockhi == clockhi1) 1815 break; 1816 } 1817 1818 cycles = (u64) clockhi << 32 | (u64) clocklo; 1819 1820 return cycles & CORE_CLOCK_MASK; 1821} 1822EXPORT_SYMBOL_GPL(mlx4_read_clock); 1823 1824 1825static int map_internal_clock(struct mlx4_dev *dev) 1826{ 1827 struct mlx4_priv *priv = mlx4_priv(dev); 1828 1829 priv->clock_mapping = ioremap(pci_resource_start(dev->pdev, 1830 priv->fw.clock_bar) + 1831 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1832 1833 if (!priv->clock_mapping) 1834 return -ENOMEM; 1835 1836 return 0; 1837} 1838 1839 1840int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1841 struct mlx4_clock_params *params) 1842{ 1843 struct mlx4_priv *priv = mlx4_priv(dev); 1844 1845 if (mlx4_is_slave(dev)) 1846 return -ENOTSUPP; 1847 if (!params) 1848 return -EINVAL; 1849 1850 params->bar = priv->fw.clock_bar; 1851 params->offset = priv->fw.clock_offset; 1852 params->size = MLX4_CLOCK_SIZE; 1853 1854 return 0; 1855} 1856EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1857 1858static void unmap_internal_clock(struct mlx4_dev *dev) 1859{ 1860 struct mlx4_priv *priv = mlx4_priv(dev); 1861 1862 if (priv->clock_mapping) 1863 iounmap(priv->clock_mapping); 1864} 1865 1866static void mlx4_close_hca(struct mlx4_dev *dev) 1867{ 1868 unmap_internal_clock(dev); 1869 unmap_bf_area(dev); 1870 if (mlx4_is_slave(dev)) { 1871 mlx4_slave_exit(dev); 1872 } else { 1873 mlx4_CLOSE_HCA(dev, 0); 1874 mlx4_free_icms(dev); 1875 1876 if (!mlx4_UNMAP_FA(dev)) 1877 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 1878 else 1879 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n"); 1880 } 1881} 1882 1883static int mlx4_init_slave(struct mlx4_dev *dev) 1884{ 1885 struct mlx4_priv *priv = mlx4_priv(dev); 1886 u64 dma = (u64) priv->mfunc.vhcr_dma; 1887 int num_of_reset_retries = NUM_OF_RESET_RETRIES; 1888 int ret_from_reset = 0; 1889 u32 slave_read; 1890 u32 cmd_channel_ver; 1891 1892 mutex_lock(&priv->cmd.slave_cmd_mutex); 1893 priv->cmd.max_cmds = 1; 1894 mlx4_warn(dev, "Sending reset\n"); 1895 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 1896 MLX4_COMM_TIME); 1897 /* if we are in the middle of flr the slave will try 1898 * NUM_OF_RESET_RETRIES times before leaving.*/ 1899 if (ret_from_reset) { 1900 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 1901 msleep(SLEEP_TIME_IN_RESET); 1902 while (ret_from_reset && num_of_reset_retries) { 1903 mlx4_warn(dev, "slave is currently in the" 1904 "middle of FLR. retrying..." 1905 "(try num:%d)\n", 1906 (NUM_OF_RESET_RETRIES - 1907 num_of_reset_retries + 1)); 1908 ret_from_reset = 1909 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 1910 0, MLX4_COMM_TIME); 1911 num_of_reset_retries = num_of_reset_retries - 1; 1912 } 1913 } else 1914 goto err; 1915 } 1916 1917 /* check the driver version - the slave I/F revision 1918 * must match the master's */ 1919 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 1920 cmd_channel_ver = mlx4_comm_get_version(); 1921 1922 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 1923 MLX4_COMM_GET_IF_REV(slave_read)) { 1924 mlx4_err(dev, "slave driver version is not supported" 1925 " by the master\n"); 1926 goto err; 1927 } 1928 1929 mlx4_warn(dev, "Sending vhcr0\n"); 1930 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 1931 MLX4_COMM_TIME)) 1932 goto err; 1933 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 1934 MLX4_COMM_TIME)) 1935 goto err; 1936 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 1937 MLX4_COMM_TIME)) 1938 goto err; 1939 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) 1940 goto err; 1941 1942 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1943 return 0; 1944 1945err: 1946 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); 1947 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1948 return -EIO; 1949} 1950 1951static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 1952{ 1953 int i; 1954 1955 for (i = 1; i <= dev->caps.num_ports; i++) { 1956 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 1957 dev->caps.gid_table_len[i] = 1958 mlx4_get_slave_num_gids(dev, 0); 1959 else 1960 dev->caps.gid_table_len[i] = 1; 1961 dev->caps.pkey_table_len[i] = 1962 dev->phys_caps.pkey_phys_table_len[i] - 1; 1963 } 1964} 1965 1966static int choose_log_fs_mgm_entry_size(int qp_per_entry) 1967{ 1968 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 1969 1970 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 1971 i++) { 1972 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 1973 break; 1974 } 1975 1976 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 1977} 1978 1979static void choose_steering_mode(struct mlx4_dev *dev, 1980 struct mlx4_dev_cap *dev_cap) 1981{ 1982 int nvfs; 1983 1984 mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(dev->pdev), 0, &nvfs); 1985 if (high_rate_steer && !mlx4_is_mfunc(dev)) { 1986 dev->caps.flags &= ~(MLX4_DEV_CAP_FLAG_VEP_MC_STEER | 1987 MLX4_DEV_CAP_FLAG_VEP_UC_STEER); 1988 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_FS_EN; 1989 } 1990 1991 if (mlx4_log_num_mgm_entry_size == -1 && 1992 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 1993 (!mlx4_is_mfunc(dev) || 1994 (dev_cap->fs_max_num_qp_per_entry >= (nvfs + 1))) && 1995 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 1996 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 1997 dev->oper_log_mgm_entry_size = 1998 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 1999 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2000 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2001 } else { 2002 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2003 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2004 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2005 else { 2006 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2007 2008 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2009 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2010 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags " 2011 "set to use B0 steering. Falling back to A0 steering mode.\n"); 2012 } 2013 dev->oper_log_mgm_entry_size = 2014 mlx4_log_num_mgm_entry_size > 0 ? 2015 mlx4_log_num_mgm_entry_size : 2016 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2017 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2018 } 2019 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, " 2020 "log_num_mgm_entry_size = %d\n", 2021 mlx4_steering_mode_str(dev->caps.steering_mode), 2022 dev->oper_log_mgm_entry_size, mlx4_log_num_mgm_entry_size); 2023} 2024 2025static int mlx4_init_hca(struct mlx4_dev *dev) 2026{ 2027 struct mlx4_priv *priv = mlx4_priv(dev); 2028 struct mlx4_dev_cap *dev_cap = NULL; 2029 struct mlx4_adapter adapter; 2030 struct mlx4_mod_stat_cfg mlx4_cfg; 2031 struct mlx4_profile profile; 2032 struct mlx4_init_hca_param init_hca; 2033 u64 icm_size; 2034 int err; 2035 2036 if (!mlx4_is_slave(dev)) { 2037 err = mlx4_QUERY_FW(dev); 2038 if (err) { 2039 if (err == -EACCES) 2040 mlx4_info(dev, "non-primary physical function, skipping.\n"); 2041 else 2042 mlx4_err(dev, "QUERY_FW command failed, aborting.\n"); 2043 return err; 2044 } 2045 2046 err = mlx4_load_fw(dev); 2047 if (err) { 2048 mlx4_err(dev, "Failed to start FW, aborting.\n"); 2049 return err; 2050 } 2051 2052 mlx4_cfg.log_pg_sz_m = 1; 2053 mlx4_cfg.log_pg_sz = 0; 2054 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2055 if (err) 2056 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2057 2058 dev_cap = kzalloc(sizeof *dev_cap, GFP_KERNEL); 2059 if (!dev_cap) { 2060 mlx4_err(dev, "Failed to allocate memory for dev_cap\n"); 2061 err = -ENOMEM; 2062 goto err_stop_fw; 2063 } 2064 2065 err = mlx4_dev_cap(dev, dev_cap); 2066 if (err) { 2067 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 2068 goto err_stop_fw; 2069 } 2070 2071 choose_steering_mode(dev, dev_cap); 2072 2073 if (mlx4_is_master(dev)) 2074 mlx4_parav_master_pf_caps(dev); 2075 2076 process_mod_param_profile(&profile); 2077 if (dev->caps.steering_mode == 2078 MLX4_STEERING_MODE_DEVICE_MANAGED) 2079 profile.num_mcg = MLX4_FS_NUM_MCG; 2080 2081 icm_size = mlx4_make_profile(dev, &profile, dev_cap, 2082 &init_hca); 2083 if ((long long) icm_size < 0) { 2084 err = icm_size; 2085 goto err_stop_fw; 2086 } 2087 2088 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; 2089 2090 init_hca.log_uar_sz = ilog2(dev->caps.num_uars); 2091 init_hca.uar_page_sz = PAGE_SHIFT - 12; 2092 2093 err = mlx4_init_icm(dev, dev_cap, &init_hca, icm_size); 2094 if (err) 2095 goto err_stop_fw; 2096 2097 init_hca.mw_enable = 1; 2098 2099 err = mlx4_INIT_HCA(dev, &init_hca); 2100 if (err) { 2101 mlx4_err(dev, "INIT_HCA command failed, aborting.\n"); 2102 goto err_free_icm; 2103 } 2104 2105 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2106 err = mlx4_query_func(dev, dev_cap); 2107 if (err < 0) { 2108 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2109 goto err_stop_fw; 2110 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2111 dev->caps.num_eqs = dev_cap->max_eqs; 2112 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 2113 dev->caps.reserved_uars = dev_cap->reserved_uars; 2114 } 2115 } 2116 2117 /* 2118 * Read HCA frequency by QUERY_HCA command 2119 */ 2120 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2121 memset(&init_hca, 0, sizeof(init_hca)); 2122 err = mlx4_QUERY_HCA(dev, &init_hca); 2123 if (err) { 2124 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n"); 2125 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2126 } else { 2127 dev->caps.hca_core_clock = 2128 init_hca.hca_core_clock; 2129 } 2130 2131 /* In case we got HCA frequency 0 - disable timestamping 2132 * to avoid dividing by zero 2133 */ 2134 if (!dev->caps.hca_core_clock) { 2135 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2136 mlx4_err(dev, "HCA frequency is 0. Timestamping is not supported."); 2137 } else if (map_internal_clock(dev)) { 2138 /* Map internal clock, 2139 * in case of failure disable timestamping 2140 */ 2141 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2142 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n"); 2143 } 2144 } 2145 } else { 2146 err = mlx4_init_slave(dev); 2147 if (err) { 2148 mlx4_err(dev, "Failed to initialize slave\n"); 2149 return err; 2150 } 2151 2152 err = mlx4_slave_cap(dev); 2153 if (err) { 2154 mlx4_err(dev, "Failed to obtain slave caps\n"); 2155 goto err_close; 2156 } 2157 } 2158 2159 if (map_bf_area(dev)) 2160 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2161 2162 /* Only the master set the ports, all the rest got it from it.*/ 2163 if (!mlx4_is_slave(dev)) 2164 mlx4_set_port_mask(dev); 2165 2166 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2167 if (err) { 2168 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n"); 2169 goto unmap_bf; 2170 } 2171 2172 priv->eq_table.inta_pin = adapter.inta_pin; 2173 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); 2174 memcpy(dev->vsd, adapter.vsd, sizeof(dev->vsd)); 2175 dev->vsd_vendor_id = adapter.vsd_vendor_id; 2176 2177 if (!mlx4_is_slave(dev)) 2178 kfree(dev_cap); 2179 2180 return 0; 2181 2182unmap_bf: 2183 if (!mlx4_is_slave(dev)) 2184 unmap_internal_clock(dev); 2185 unmap_bf_area(dev); 2186 2187 if (mlx4_is_slave(dev)) { 2188 kfree(dev->caps.qp0_tunnel); 2189 kfree(dev->caps.qp0_proxy); 2190 kfree(dev->caps.qp1_tunnel); 2191 kfree(dev->caps.qp1_proxy); 2192 } 2193 2194err_close: 2195 if (mlx4_is_slave(dev)) 2196 mlx4_slave_exit(dev); 2197 else 2198 mlx4_CLOSE_HCA(dev, 0); 2199 2200err_free_icm: 2201 if (!mlx4_is_slave(dev)) 2202 mlx4_free_icms(dev); 2203 2204err_stop_fw: 2205 if (!mlx4_is_slave(dev)) { 2206 if (!mlx4_UNMAP_FA(dev)) 2207 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 2208 else 2209 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n"); 2210 kfree(dev_cap); 2211 } 2212 return err; 2213} 2214 2215static int mlx4_init_counters_table(struct mlx4_dev *dev) 2216{ 2217 struct mlx4_priv *priv = mlx4_priv(dev); 2218 int nent_pow2, port_indx, vf_index, num_counters; 2219 int res, index = 0; 2220 struct counter_index *new_counter_index; 2221 2222 2223 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2224 return -ENOENT; 2225 2226 if (!mlx4_is_slave(dev) && 2227 dev->caps.max_counters == dev->caps.max_extended_counters) { 2228 res = mlx4_cmd(dev, MLX4_IF_STATE_EXTENDED, 0, 0, 2229 MLX4_CMD_SET_IF_STAT, 2230 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2231 if (res) { 2232 mlx4_err(dev, "Failed to set extended counters (err=%d)\n", res); 2233 return res; 2234 } 2235 } 2236 2237 mutex_init(&priv->counters_table.mutex); 2238 2239 if (mlx4_is_slave(dev)) { 2240 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) { 2241 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]); 2242 if (dev->caps.def_counter_index[port_indx] != 0xFF) { 2243 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2244 if (!new_counter_index) 2245 return -ENOMEM; 2246 new_counter_index->index = dev->caps.def_counter_index[port_indx]; 2247 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port_indx]); 2248 } 2249 } 2250 mlx4_dbg(dev, "%s: slave allocated %d counters for %d ports\n", 2251 __func__, dev->caps.num_ports, dev->caps.num_ports); 2252 return 0; 2253 } 2254 2255 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2256 2257 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) { 2258 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]); 2259 /* allocating 2 counters per port for PFs */ 2260 /* For the PF, the ETH default counters are 0,2; */ 2261 /* and the RoCE default counters are 1,3 */ 2262 for (num_counters = 0; num_counters < 2; num_counters++, index++) { 2263 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2264 if (!new_counter_index) 2265 return -ENOMEM; 2266 new_counter_index->index = index; 2267 list_add_tail(&new_counter_index->list, 2268 &priv->counters_table.global_port_list[port_indx]); 2269 } 2270 } 2271 2272 if (mlx4_is_master(dev)) { 2273 for (vf_index = 0; vf_index < dev->num_vfs; vf_index++) { 2274 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) { 2275 INIT_LIST_HEAD(&priv->counters_table.vf_list[vf_index][port_indx]); 2276 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2277 if (!new_counter_index) 2278 return -ENOMEM; 2279 if (index < nent_pow2 - 2) { 2280 new_counter_index->index = index; 2281 index++; 2282 } else { 2283 new_counter_index->index = MLX4_SINK_COUNTER_INDEX; 2284 } 2285 2286 list_add_tail(&new_counter_index->list, 2287 &priv->counters_table.vf_list[vf_index][port_indx]); 2288 } 2289 } 2290 2291 res = mlx4_bitmap_init(&priv->counters_table.bitmap, 2292 nent_pow2, nent_pow2 - 1, 2293 index, 1); 2294 mlx4_dbg(dev, "%s: master allocated %d counters for %d VFs\n", 2295 __func__, index, dev->num_vfs); 2296 } else { 2297 res = mlx4_bitmap_init(&priv->counters_table.bitmap, 2298 nent_pow2, nent_pow2 - 1, 2299 index, 1); 2300 mlx4_dbg(dev, "%s: native allocated %d counters for %d ports\n", 2301 __func__, index, dev->caps.num_ports); 2302 } 2303 2304 return 0; 2305 2306} 2307 2308static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2309{ 2310 struct mlx4_priv *priv = mlx4_priv(dev); 2311 int i, j; 2312 struct counter_index *port, *tmp_port; 2313 struct counter_index *vf, *tmp_vf; 2314 2315 mutex_lock(&priv->counters_table.mutex); 2316 2317 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) { 2318 for (i = 0; i < dev->caps.num_ports; i++) { 2319 list_for_each_entry_safe(port, tmp_port, 2320 &priv->counters_table.global_port_list[i], 2321 list) { 2322 list_del(&port->list); 2323 kfree(port); 2324 } 2325 } 2326 if (!mlx4_is_slave(dev)) { 2327 for (i = 0; i < dev->num_vfs; i++) { 2328 for (j = 0; j < dev->caps.num_ports; j++) { 2329 list_for_each_entry_safe(vf, tmp_vf, 2330 &priv->counters_table.vf_list[i][j], 2331 list) { 2332 /* clear the counter statistic */ 2333 if (__mlx4_clear_if_stat(dev, vf->index)) 2334 mlx4_dbg(dev, "%s: reset counter %d failed\n", 2335 __func__, vf->index); 2336 list_del(&vf->list); 2337 kfree(vf); 2338 } 2339 } 2340 } 2341 mlx4_bitmap_cleanup(&priv->counters_table.bitmap); 2342 } 2343 } 2344 mutex_unlock(&priv->counters_table.mutex); 2345} 2346 2347int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave) 2348{ 2349 struct mlx4_priv *priv = mlx4_priv(dev); 2350 int i, first; 2351 struct counter_index *vf, *tmp_vf; 2352 2353 /* clean VF's counters for the next useg */ 2354 if (slave > 0 && slave <= dev->num_vfs) { 2355 mlx4_dbg(dev, "%s: free counters of slave(%d)\n" 2356 , __func__, slave); 2357 2358 mutex_lock(&priv->counters_table.mutex); 2359 for (i = 0; i < dev->caps.num_ports; i++) { 2360 first = 0; 2361 list_for_each_entry_safe(vf, tmp_vf, 2362 &priv->counters_table.vf_list[slave - 1][i], 2363 list) { 2364 /* clear the counter statistic */ 2365 if (__mlx4_clear_if_stat(dev, vf->index)) 2366 mlx4_dbg(dev, "%s: reset counter %d failed\n", 2367 __func__, vf->index); 2368 if (first++ && vf->index != MLX4_SINK_COUNTER_INDEX) { 2369 mlx4_dbg(dev, "%s: delete counter index %d for slave %d and port %d\n" 2370 , __func__, vf->index, slave, i + 1); 2371 mlx4_bitmap_free(&priv->counters_table.bitmap, vf->index, MLX4_USE_RR); 2372 list_del(&vf->list); 2373 kfree(vf); 2374 } else { 2375 mlx4_dbg(dev, "%s: can't delete default counter index %d for slave %d and port %d\n" 2376 , __func__, vf->index, slave, i + 1); 2377 } 2378 } 2379 } 2380 mutex_unlock(&priv->counters_table.mutex); 2381 } 2382 2383 return 0; 2384} 2385 2386int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, u32 *idx) 2387{ 2388 struct mlx4_priv *priv = mlx4_priv(dev); 2389 struct counter_index *new_counter_index; 2390 2391 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2392 return -ENOENT; 2393 2394 if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) || 2395 (port < 0) || (port > MLX4_MAX_PORTS)) { 2396 mlx4_dbg(dev, "%s: invalid slave(%d) or port(%d) index\n", 2397 __func__, slave, port); 2398 return -EINVAL; 2399 } 2400 2401 /* handle old guest request does not support request by port index */ 2402 if (port == 0) { 2403 *idx = MLX4_SINK_COUNTER_INDEX; 2404 mlx4_dbg(dev, "%s: allocated default counter index %d for slave %d port %d\n" 2405 , __func__, *idx, slave, port); 2406 return 0; 2407 } 2408 2409 mutex_lock(&priv->counters_table.mutex); 2410 2411 *idx = mlx4_bitmap_alloc(&priv->counters_table.bitmap); 2412 /* if no resources return the default counter of the slave and port */ 2413 if (*idx == -1) { 2414 if (slave == 0) { /* its the ethernet counter ?????? */ 2415 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next, 2416 struct counter_index, 2417 list); 2418 } else { 2419 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next, 2420 struct counter_index, 2421 list); 2422 } 2423 2424 *idx = new_counter_index->index; 2425 mlx4_dbg(dev, "%s: allocated defualt counter index %d for slave %d port %d\n" 2426 , __func__, *idx, slave, port); 2427 goto out; 2428 } 2429 2430 if (slave == 0) { /* native or master */ 2431 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2432 if (!new_counter_index) 2433 goto no_mem; 2434 new_counter_index->index = *idx; 2435 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]); 2436 } else { 2437 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2438 if (!new_counter_index) 2439 goto no_mem; 2440 new_counter_index->index = *idx; 2441 list_add_tail(&new_counter_index->list, &priv->counters_table.vf_list[slave - 1][port - 1]); 2442 } 2443 2444 mlx4_dbg(dev, "%s: allocated counter index %d for slave %d port %d\n" 2445 , __func__, *idx, slave, port); 2446out: 2447 mutex_unlock(&priv->counters_table.mutex); 2448 return 0; 2449 2450no_mem: 2451 mlx4_bitmap_free(&priv->counters_table.bitmap, *idx, MLX4_USE_RR); 2452 mutex_unlock(&priv->counters_table.mutex); 2453 *idx = MLX4_SINK_COUNTER_INDEX; 2454 mlx4_dbg(dev, "%s: failed err (%d)\n" 2455 , __func__, -ENOMEM); 2456 return -ENOMEM; 2457} 2458 2459int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx) 2460{ 2461 u64 out_param; 2462 int err; 2463 struct mlx4_priv *priv = mlx4_priv(dev); 2464 struct counter_index *new_counter_index, *c_index; 2465 2466 if (mlx4_is_mfunc(dev)) { 2467 err = mlx4_cmd_imm(dev, 0, &out_param, 2468 ((u32) port) << 8 | (u32) RES_COUNTER, 2469 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2470 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2471 if (!err) { 2472 *idx = get_param_l(&out_param); 2473 if (*idx == MLX4_SINK_COUNTER_INDEX) 2474 return -ENOSPC; 2475 2476 mutex_lock(&priv->counters_table.mutex); 2477 c_index = list_entry(priv->counters_table.global_port_list[port - 1].next, 2478 struct counter_index, 2479 list); 2480 mutex_unlock(&priv->counters_table.mutex); 2481 if (c_index->index == *idx) 2482 return -EEXIST; 2483 2484 if (mlx4_is_slave(dev)) { 2485 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL); 2486 if (!new_counter_index) { 2487 mlx4_counter_free(dev, port, *idx); 2488 return -ENOMEM; 2489 } 2490 new_counter_index->index = *idx; 2491 mutex_lock(&priv->counters_table.mutex); 2492 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]); 2493 mutex_unlock(&priv->counters_table.mutex); 2494 mlx4_dbg(dev, "%s: allocated counter index %d for port %d\n" 2495 , __func__, *idx, port); 2496 } 2497 } 2498 return err; 2499 } 2500 return __mlx4_counter_alloc(dev, 0, port, idx); 2501} 2502EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2503 2504void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx) 2505{ 2506 /* check if native or slave and deletes acordingly */ 2507 struct mlx4_priv *priv = mlx4_priv(dev); 2508 struct counter_index *pf, *tmp_pf; 2509 struct counter_index *vf, *tmp_vf; 2510 int first; 2511 2512 2513 if (idx == MLX4_SINK_COUNTER_INDEX) { 2514 mlx4_dbg(dev, "%s: try to delete default counter index %d for port %d\n" 2515 , __func__, idx, port); 2516 return; 2517 } 2518 2519 if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) || 2520 (port < 0) || (port > MLX4_MAX_PORTS)) { 2521 mlx4_warn(dev, "%s: deletion failed due to invalid slave(%d) or port(%d) index\n" 2522 , __func__, slave, idx); 2523 return; 2524 } 2525 2526 mutex_lock(&priv->counters_table.mutex); 2527 if (slave == 0) { 2528 first = 0; 2529 list_for_each_entry_safe(pf, tmp_pf, 2530 &priv->counters_table.global_port_list[port - 1], 2531 list) { 2532 /* the first 2 counters are reserved */ 2533 if (pf->index == idx) { 2534 /* clear the counter statistic */ 2535 if (__mlx4_clear_if_stat(dev, pf->index)) 2536 mlx4_dbg(dev, "%s: reset counter %d failed\n", 2537 __func__, pf->index); 2538 if (1 < first && idx != MLX4_SINK_COUNTER_INDEX) { 2539 list_del(&pf->list); 2540 kfree(pf); 2541 mlx4_dbg(dev, "%s: delete counter index %d for native device (%d) port %d\n" 2542 , __func__, idx, slave, port); 2543 mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR); 2544 goto out; 2545 } else { 2546 mlx4_dbg(dev, "%s: can't delete default counter index %d for native device (%d) port %d\n" 2547 , __func__, idx, slave, port); 2548 goto out; 2549 } 2550 } 2551 first++; 2552 } 2553 mlx4_dbg(dev, "%s: can't delete counter index %d for native device (%d) port %d\n" 2554 , __func__, idx, slave, port); 2555 } else { 2556 first = 0; 2557 list_for_each_entry_safe(vf, tmp_vf, 2558 &priv->counters_table.vf_list[slave - 1][port - 1], 2559 list) { 2560 /* the first element is reserved */ 2561 if (vf->index == idx) { 2562 /* clear the counter statistic */ 2563 if (__mlx4_clear_if_stat(dev, vf->index)) 2564 mlx4_dbg(dev, "%s: reset counter %d failed\n", 2565 __func__, vf->index); 2566 if (first) { 2567 list_del(&vf->list); 2568 kfree(vf); 2569 mlx4_dbg(dev, "%s: delete counter index %d for slave %d port %d\n", 2570 __func__, idx, slave, port); 2571 mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR); 2572 goto out; 2573 } else { 2574 mlx4_dbg(dev, "%s: can't delete default slave (%d) counter index %d for port %d\n" 2575 , __func__, slave, idx, port); 2576 goto out; 2577 } 2578 } 2579 first++; 2580 } 2581 mlx4_dbg(dev, "%s: can't delete slave (%d) counter index %d for port %d\n" 2582 , __func__, slave, idx, port); 2583 } 2584 2585out: 2586 mutex_unlock(&priv->counters_table.mutex); 2587} 2588 2589void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx) 2590{ 2591 u64 in_param = 0; 2592 struct mlx4_priv *priv = mlx4_priv(dev); 2593 struct counter_index *counter, *tmp_counter; 2594 int first = 0; 2595 2596 if (mlx4_is_mfunc(dev)) { 2597 set_param_l(&in_param, idx); 2598 mlx4_cmd(dev, in_param, 2599 ((u32) port) << 8 | (u32) RES_COUNTER, 2600 RES_OP_RESERVE, 2601 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2602 MLX4_CMD_WRAPPED); 2603 2604 if (mlx4_is_slave(dev) && idx != MLX4_SINK_COUNTER_INDEX) { 2605 mutex_lock(&priv->counters_table.mutex); 2606 list_for_each_entry_safe(counter, tmp_counter, 2607 &priv->counters_table.global_port_list[port - 1], 2608 list) { 2609 if (counter->index == idx && first++) { 2610 list_del(&counter->list); 2611 kfree(counter); 2612 mlx4_dbg(dev, "%s: delete counter index %d for port %d\n" 2613 , __func__, idx, port); 2614 mutex_unlock(&priv->counters_table.mutex); 2615 return; 2616 } 2617 } 2618 mutex_unlock(&priv->counters_table.mutex); 2619 } 2620 2621 return; 2622 } 2623 __mlx4_counter_free(dev, 0, port, idx); 2624} 2625EXPORT_SYMBOL_GPL(mlx4_counter_free); 2626 2627int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2628 u8 counter_index) 2629{ 2630 struct mlx4_cmd_mailbox *if_stat_mailbox = NULL; 2631 int err = 0; 2632 u32 if_stat_in_mod = (counter_index & 0xff) | (1 << 31); 2633 2634 if (counter_index == MLX4_SINK_COUNTER_INDEX) 2635 return -EINVAL; 2636 2637 if (mlx4_is_slave(dev)) 2638 return 0; 2639 2640 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2641 if (IS_ERR(if_stat_mailbox)) { 2642 err = PTR_ERR(if_stat_mailbox); 2643 return err; 2644 } 2645 2646 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2647 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2648 MLX4_CMD_NATIVE); 2649 2650 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2651 return err; 2652} 2653 2654u8 mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port) 2655{ 2656 struct mlx4_priv *priv = mlx4_priv(dev); 2657 struct counter_index *new_counter_index; 2658 2659 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) { 2660 mlx4_dbg(dev, "%s: return counter index %d for slave %d port (MLX4_PORT_TYPE_IB) %d\n", 2661 __func__, MLX4_SINK_COUNTER_INDEX, slave, port); 2662 return (u8)MLX4_SINK_COUNTER_INDEX; 2663 } 2664 2665 mutex_lock(&priv->counters_table.mutex); 2666 if (slave == 0) { 2667 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next, 2668 struct counter_index, 2669 list); 2670 } else { 2671 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next, 2672 struct counter_index, 2673 list); 2674 } 2675 mutex_unlock(&priv->counters_table.mutex); 2676 2677 mlx4_dbg(dev, "%s: return counter index %d for slave %d port %d\n", 2678 __func__, new_counter_index->index, slave, port); 2679 2680 2681 return (u8)new_counter_index->index; 2682} 2683 2684int mlx4_get_vport_ethtool_stats(struct mlx4_dev *dev, int port, 2685 struct mlx4_en_vport_stats *vport_stats, 2686 int reset) 2687{ 2688 struct mlx4_priv *priv = mlx4_priv(dev); 2689 struct mlx4_cmd_mailbox *if_stat_mailbox = NULL; 2690 union mlx4_counter *counter; 2691 int err = 0; 2692 u32 if_stat_in_mod; 2693 struct counter_index *vport, *tmp_vport; 2694 2695 if (!vport_stats) 2696 return -EINVAL; 2697 2698 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2699 if (IS_ERR(if_stat_mailbox)) { 2700 err = PTR_ERR(if_stat_mailbox); 2701 return err; 2702 } 2703 2704 mutex_lock(&priv->counters_table.mutex); 2705 list_for_each_entry_safe(vport, tmp_vport, 2706 &priv->counters_table.global_port_list[port - 1], 2707 list) { 2708 if (vport->index == MLX4_SINK_COUNTER_INDEX) 2709 continue; 2710 2711 memset(if_stat_mailbox->buf, 0, sizeof(union mlx4_counter)); 2712 if_stat_in_mod = (vport->index & 0xff) | ((reset & 1) << 31); 2713 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, 2714 if_stat_in_mod, 0, 2715 MLX4_CMD_QUERY_IF_STAT, 2716 MLX4_CMD_TIME_CLASS_C, 2717 MLX4_CMD_NATIVE); 2718 if (err) { 2719 mlx4_dbg(dev, "%s: failed to read statistics for counter index %d\n", 2720 __func__, vport->index); 2721 goto if_stat_out; 2722 } 2723 counter = (union mlx4_counter *)if_stat_mailbox->buf; 2724 if ((counter->control.cnt_mode & 0xf) == 1) { 2725 vport_stats->rx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastFrames); 2726 vport_stats->rx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxUnicastFrames); 2727 vport_stats->rx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxMulticastFrames); 2728 vport_stats->tx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastFrames); 2729 vport_stats->tx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxUnicastFrames); 2730 vport_stats->tx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxMulticastFrames); 2731 vport_stats->rx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastOctets); 2732 vport_stats->rx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxUnicastOctets); 2733 vport_stats->rx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxMulticastOctets); 2734 vport_stats->tx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastOctets); 2735 vport_stats->tx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxUnicastOctets); 2736 vport_stats->tx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxMulticastOctets); 2737 vport_stats->rx_errors += be64_to_cpu(counter->ext.counters[0].IfRxErrorFrames); 2738 vport_stats->rx_dropped += be64_to_cpu(counter->ext.counters[0].IfRxNoBufferFrames); 2739 vport_stats->tx_errors += be64_to_cpu(counter->ext.counters[0].IfTxDroppedFrames); 2740 } 2741 } 2742 2743if_stat_out: 2744 mutex_unlock(&priv->counters_table.mutex); 2745 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2746 2747 return err; 2748} 2749EXPORT_SYMBOL_GPL(mlx4_get_vport_ethtool_stats); 2750 2751static int mlx4_setup_hca(struct mlx4_dev *dev) 2752{ 2753 struct mlx4_priv *priv = mlx4_priv(dev); 2754 int err; 2755 int port; 2756 __be32 ib_port_default_caps; 2757 2758 err = mlx4_init_uar_table(dev); 2759 if (err) { 2760 mlx4_err(dev, "Failed to initialize " 2761 "user access region table (err=%d), aborting.\n", 2762 err); 2763 return err; 2764 } 2765 2766 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2767 if (err) { 2768 mlx4_err(dev, "Failed to allocate driver access region " 2769 "(err=%d), aborting.\n", err); 2770 goto err_uar_table_free; 2771 } 2772 2773 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2774 if (!priv->kar) { 2775 mlx4_err(dev, "Couldn't map kernel access region, " 2776 "aborting.\n"); 2777 err = -ENOMEM; 2778 goto err_uar_free; 2779 } 2780 2781 err = mlx4_init_pd_table(dev); 2782 if (err) { 2783 mlx4_err(dev, "Failed to initialize " 2784 "protection domain table (err=%d), aborting.\n", err); 2785 goto err_kar_unmap; 2786 } 2787 2788 err = mlx4_init_xrcd_table(dev); 2789 if (err) { 2790 mlx4_err(dev, "Failed to initialize " 2791 "reliable connection domain table (err=%d), " 2792 "aborting.\n", err); 2793 goto err_pd_table_free; 2794 } 2795 2796 err = mlx4_init_mr_table(dev); 2797 if (err) { 2798 mlx4_err(dev, "Failed to initialize " 2799 "memory region table (err=%d), aborting.\n", err); 2800 goto err_xrcd_table_free; 2801 } 2802 2803 if (!mlx4_is_slave(dev)) { 2804 err = mlx4_init_mcg_table(dev); 2805 if (err) { 2806 mlx4_err(dev, "Failed to initialize " 2807 "multicast group table (err=%d), aborting.\n", 2808 err); 2809 goto err_mr_table_free; 2810 } 2811 } 2812 2813 err = mlx4_init_eq_table(dev); 2814 if (err) { 2815 mlx4_err(dev, "Failed to initialize " 2816 "event queue table (err=%d), aborting.\n", err); 2817 goto err_mcg_table_free; 2818 } 2819 2820 err = mlx4_cmd_use_events(dev); 2821 if (err) { 2822 mlx4_err(dev, "Failed to switch to event-driven " 2823 "firmware commands (err=%d), aborting.\n", err); 2824 goto err_eq_table_free; 2825 } 2826 2827 err = mlx4_NOP(dev); 2828 if (err) { 2829 if (dev->flags & MLX4_FLAG_MSI_X) { 2830 mlx4_warn(dev, "NOP command failed to generate MSI-X " 2831 "interrupt IRQ %d).\n", 2832 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 2833 mlx4_warn(dev, "Trying again without MSI-X.\n"); 2834 } else { 2835 mlx4_err(dev, "NOP command failed to generate interrupt " 2836 "(IRQ %d), aborting.\n", 2837 priv->eq_table.eq[dev->caps.num_comp_vectors].irq); 2838 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2839 } 2840 2841 goto err_cmd_poll; 2842 } 2843 2844 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2845 2846 err = mlx4_init_cq_table(dev); 2847 if (err) { 2848 mlx4_err(dev, "Failed to initialize " 2849 "completion queue table (err=%d), aborting.\n", err); 2850 goto err_cmd_poll; 2851 } 2852 2853 err = mlx4_init_srq_table(dev); 2854 if (err) { 2855 mlx4_err(dev, "Failed to initialize " 2856 "shared receive queue table (err=%d), aborting.\n", 2857 err); 2858 goto err_cq_table_free; 2859 } 2860 2861 err = mlx4_init_qp_table(dev); 2862 if (err) { 2863 mlx4_err(dev, "Failed to initialize " 2864 "queue pair table (err=%d), aborting.\n", err); 2865 goto err_srq_table_free; 2866 } 2867 2868 err = mlx4_init_counters_table(dev); 2869 if (err && err != -ENOENT) { 2870 mlx4_err(dev, "Failed to initialize counters table (err=%d), " 2871 "aborting.\n", err); 2872 goto err_qp_table_free; 2873 } 2874 2875 if (!mlx4_is_slave(dev)) { 2876 for (port = 1; port <= dev->caps.num_ports; port++) { 2877 ib_port_default_caps = 0; 2878 err = mlx4_get_port_ib_caps(dev, port, 2879 &ib_port_default_caps); 2880 if (err) 2881 mlx4_warn(dev, "failed to get port %d default " 2882 "ib capabilities (%d). Continuing " 2883 "with caps = 0\n", port, err); 2884 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2885 2886 /* initialize per-slave default ib port capabilities */ 2887 if (mlx4_is_master(dev)) { 2888 int i; 2889 for (i = 0; i < dev->num_slaves; i++) { 2890 if (i == mlx4_master_func_num(dev)) 2891 continue; 2892 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2893 ib_port_default_caps; 2894 } 2895 } 2896 2897 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2898 2899 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2900 dev->caps.pkey_table_len[port] : -1); 2901 if (err) { 2902 mlx4_err(dev, "Failed to set port %d (err=%d), " 2903 "aborting\n", port, err); 2904 goto err_counters_table_free; 2905 } 2906 } 2907 } 2908 2909 return 0; 2910 2911err_counters_table_free: 2912 mlx4_cleanup_counters_table(dev); 2913 2914err_qp_table_free: 2915 mlx4_cleanup_qp_table(dev); 2916 2917err_srq_table_free: 2918 mlx4_cleanup_srq_table(dev); 2919 2920err_cq_table_free: 2921 mlx4_cleanup_cq_table(dev); 2922 2923err_cmd_poll: 2924 mlx4_cmd_use_polling(dev); 2925 2926err_eq_table_free: 2927 mlx4_cleanup_eq_table(dev); 2928 2929err_mcg_table_free: 2930 if (!mlx4_is_slave(dev)) 2931 mlx4_cleanup_mcg_table(dev); 2932 2933err_mr_table_free: 2934 mlx4_cleanup_mr_table(dev); 2935 2936err_xrcd_table_free: 2937 mlx4_cleanup_xrcd_table(dev); 2938 2939err_pd_table_free: 2940 mlx4_cleanup_pd_table(dev); 2941 2942err_kar_unmap: 2943 iounmap(priv->kar); 2944 2945err_uar_free: 2946 mlx4_uar_free(dev, &priv->driver_uar); 2947 2948err_uar_table_free: 2949 mlx4_cleanup_uar_table(dev); 2950 return err; 2951} 2952 2953static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2954{ 2955 struct mlx4_priv *priv = mlx4_priv(dev); 2956 struct msix_entry *entries; 2957 int err; 2958 int i; 2959 2960 if (msi_x) { 2961 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ; 2962 2963 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, 2964 nreq); 2965 2966 if (msi_x > 1 && !mlx4_is_mfunc(dev)) 2967 nreq = min_t(int, nreq, msi_x); 2968 2969 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); 2970 if (!entries) 2971 goto no_msi; 2972 2973 for (i = 0; i < nreq; ++i) 2974 entries[i].entry = i; 2975 2976 retry: 2977 err = pci_enable_msix(dev->pdev, entries, nreq); 2978 if (err) { 2979 /* Try again if at least 2 vectors are available */ 2980 if (err > 1) { 2981 mlx4_info(dev, "Requested %d vectors, " 2982 "but only %d MSI-X vectors available, " 2983 "trying again\n", nreq, err); 2984 nreq = err; 2985 goto retry; 2986 } 2987 kfree(entries); 2988 /* if error, or can't alloc even 1 IRQ */ 2989 if (err < 0) { 2990 mlx4_err(dev, "No IRQs left, device can't " 2991 "be started.\n"); 2992 goto no_irq; 2993 } 2994 goto no_msi; 2995 } 2996 2997 if (nreq < 2998 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) { 2999 /*Working in legacy mode , all EQ's shared*/ 3000 dev->caps.comp_pool = 0; 3001 dev->caps.num_comp_vectors = nreq - 1; 3002 } else { 3003 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; 3004 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; 3005 } 3006 for (i = 0; i < nreq; ++i) 3007 priv->eq_table.eq[i].irq = entries[i].vector; 3008 3009 dev->flags |= MLX4_FLAG_MSI_X; 3010 3011 kfree(entries); 3012 return; 3013 } 3014 3015no_msi: 3016 dev->caps.num_comp_vectors = 1; 3017 dev->caps.comp_pool = 0; 3018 3019 for (i = 0; i < 2; ++i) 3020 priv->eq_table.eq[i].irq = dev->pdev->irq; 3021 return; 3022no_irq: 3023 dev->caps.num_comp_vectors = 0; 3024 dev->caps.comp_pool = 0; 3025 return; 3026} 3027 3028static void 3029mlx4_init_hca_info(struct mlx4_dev *dev) 3030{ 3031 struct mlx4_hca_info *info = &mlx4_priv(dev)->hca_info; 3032 3033 info->dev = dev; 3034 3035 info->firmware_attr = (struct device_attribute)__ATTR(fw_ver, S_IRUGO, 3036 show_firmware_version, NULL); 3037 if (device_create_file(&dev->pdev->dev, &info->firmware_attr)) 3038 mlx4_err(dev, "Failed to add file firmware version"); 3039 3040 info->hca_attr = (struct device_attribute)__ATTR(hca, S_IRUGO, show_hca, 3041 NULL); 3042 if (device_create_file(&dev->pdev->dev, &info->hca_attr)) 3043 mlx4_err(dev, "Failed to add file hca type"); 3044 3045 info->board_attr = (struct device_attribute)__ATTR(board_id, S_IRUGO, 3046 show_board, NULL); 3047 if (device_create_file(&dev->pdev->dev, &info->board_attr)) 3048 mlx4_err(dev, "Failed to add file board id type"); 3049} 3050 3051static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 3052{ 3053 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 3054 int err = 0; 3055 3056 info->dev = dev; 3057 info->port = port; 3058 if (!mlx4_is_slave(dev)) { 3059 mlx4_init_mac_table(dev, &info->mac_table); 3060 mlx4_init_vlan_table(dev, &info->vlan_table); 3061 info->base_qpn = mlx4_get_base_qpn(dev, port); 3062 } 3063 3064 sprintf(info->dev_name, "mlx4_port%d", port); 3065 info->port_attr.attr.name = info->dev_name; 3066 if (mlx4_is_mfunc(dev)) 3067 info->port_attr.attr.mode = S_IRUGO; 3068 else { 3069 info->port_attr.attr.mode = S_IRUGO | S_IWUSR; 3070 info->port_attr.store = set_port_type; 3071 } 3072 info->port_attr.show = show_port_type; 3073 sysfs_attr_init(&info->port_attr.attr); 3074 3075 err = device_create_file(&dev->pdev->dev, &info->port_attr); 3076 if (err) { 3077 mlx4_err(dev, "Failed to create file for port %d\n", port); 3078 info->port = -1; 3079 } 3080 3081 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 3082 info->port_mtu_attr.attr.name = info->dev_mtu_name; 3083 if (mlx4_is_mfunc(dev)) 3084 info->port_mtu_attr.attr.mode = S_IRUGO; 3085 else { 3086 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; 3087 info->port_mtu_attr.store = set_port_ib_mtu; 3088 } 3089 info->port_mtu_attr.show = show_port_ib_mtu; 3090 sysfs_attr_init(&info->port_mtu_attr.attr); 3091 3092 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); 3093 if (err) { 3094 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 3095 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 3096 info->port = -1; 3097 } 3098 3099 return err; 3100} 3101 3102static void 3103mlx4_cleanup_hca_info(struct mlx4_hca_info *info) 3104{ 3105 device_remove_file(&info->dev->pdev->dev, &info->firmware_attr); 3106 device_remove_file(&info->dev->pdev->dev, &info->board_attr); 3107 device_remove_file(&info->dev->pdev->dev, &info->hca_attr); 3108} 3109 3110static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3111{ 3112 if (info->port < 0) 3113 return; 3114 3115 device_remove_file(&info->dev->pdev->dev, &info->port_attr); 3116 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); 3117} 3118 3119static int mlx4_init_steering(struct mlx4_dev *dev) 3120{ 3121 struct mlx4_priv *priv = mlx4_priv(dev); 3122 int num_entries = dev->caps.num_ports; 3123 int i, j; 3124 3125 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); 3126 if (!priv->steer) 3127 return -ENOMEM; 3128 3129 for (i = 0; i < num_entries; i++) 3130 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3131 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3132 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3133 } 3134 return 0; 3135} 3136 3137static void mlx4_clear_steering(struct mlx4_dev *dev) 3138{ 3139 struct mlx4_priv *priv = mlx4_priv(dev); 3140 struct mlx4_steer_index *entry, *tmp_entry; 3141 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3142 int num_entries = dev->caps.num_ports; 3143 int i, j; 3144 3145 for (i = 0; i < num_entries; i++) { 3146 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3147 list_for_each_entry_safe(pqp, tmp_pqp, 3148 &priv->steer[i].promisc_qps[j], 3149 list) { 3150 list_del(&pqp->list); 3151 kfree(pqp); 3152 } 3153 list_for_each_entry_safe(entry, tmp_entry, 3154 &priv->steer[i].steer_entries[j], 3155 list) { 3156 list_del(&entry->list); 3157 list_for_each_entry_safe(pqp, tmp_pqp, 3158 &entry->duplicates, 3159 list) { 3160 list_del(&pqp->list); 3161 kfree(pqp); 3162 } 3163 kfree(entry); 3164 } 3165 } 3166 } 3167 kfree(priv->steer); 3168} 3169 3170static int extended_func_num(struct pci_dev *pdev) 3171{ 3172 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3173} 3174 3175#define MLX4_OWNER_BASE 0x8069c 3176#define MLX4_OWNER_SIZE 4 3177 3178static int mlx4_get_ownership(struct mlx4_dev *dev) 3179{ 3180 void __iomem *owner; 3181 u32 ret; 3182 3183 if (pci_channel_offline(dev->pdev)) 3184 return -EIO; 3185 3186 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 3187 MLX4_OWNER_SIZE); 3188 if (!owner) { 3189 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3190 return -ENOMEM; 3191 } 3192 3193 ret = readl(owner); 3194 iounmap(owner); 3195 return (int) !!ret; 3196} 3197 3198static void mlx4_free_ownership(struct mlx4_dev *dev) 3199{ 3200 void __iomem *owner; 3201 3202 if (pci_channel_offline(dev->pdev)) 3203 return; 3204 3205 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, 3206 MLX4_OWNER_SIZE); 3207 if (!owner) { 3208 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3209 return; 3210 } 3211 writel(0, owner); 3212 msleep(1000); 3213 iounmap(owner); 3214} 3215 3216static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data) 3217{ 3218 struct mlx4_priv *priv; 3219 struct mlx4_dev *dev; 3220 int err; 3221 int port; 3222 int nvfs, prb_vf; 3223 3224 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3225 3226 err = pci_enable_device(pdev); 3227 if (err) { 3228 dev_err(&pdev->dev, "Cannot enable PCI device, " 3229 "aborting.\n"); 3230 return err; 3231 } 3232 3233 mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(pdev), 0, &nvfs); 3234 mlx4_get_val(probe_vf.dbdf2val.tbl, pci_physfn(pdev), 0, &prb_vf); 3235 if (nvfs > MLX4_MAX_NUM_VF) { 3236 dev_err(&pdev->dev, "There are more VF's (%d) than allowed(%d)\n", 3237 nvfs, MLX4_MAX_NUM_VF); 3238 return -EINVAL; 3239 } 3240 3241 if (nvfs < 0) { 3242 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3243 return -EINVAL; 3244 } 3245 /* 3246 * Check for BARs. 3247 */ 3248 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3249 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3250 dev_err(&pdev->dev, "Missing DCS, aborting." 3251 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%x)\n", 3252 pci_dev_data, pci_resource_flags(pdev, 0)); 3253 err = -ENODEV; 3254 goto err_disable_pdev; 3255 } 3256 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3257 dev_err(&pdev->dev, "Missing UAR, aborting.\n"); 3258 err = -ENODEV; 3259 goto err_disable_pdev; 3260 } 3261 3262 err = pci_request_regions(pdev, DRV_NAME); 3263 if (err) { 3264 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3265 goto err_disable_pdev; 3266 } 3267 3268 pci_set_master(pdev); 3269 3270 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 3271 if (err) { 3272 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); 3273 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3274 if (err) { 3275 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); 3276 goto err_release_regions; 3277 } 3278 } 3279 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 3280 if (err) { 3281 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " 3282 "consistent PCI DMA mask.\n"); 3283 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3284 if (err) { 3285 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " 3286 "aborting.\n"); 3287 goto err_release_regions; 3288 } 3289 } 3290 3291 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3292 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3293 3294 priv = kzalloc(sizeof *priv, GFP_KERNEL); 3295 if (!priv) { 3296 dev_err(&pdev->dev, "Device struct alloc failed, " 3297 "aborting.\n"); 3298 err = -ENOMEM; 3299 goto err_release_regions; 3300 } 3301 3302 dev = &priv->dev; 3303 dev->pdev = pdev; 3304 INIT_LIST_HEAD(&priv->dev_list); 3305 INIT_LIST_HEAD(&priv->ctx_list); 3306 spin_lock_init(&priv->ctx_lock); 3307 3308 mutex_init(&priv->port_mutex); 3309 3310 INIT_LIST_HEAD(&priv->pgdir_list); 3311 mutex_init(&priv->pgdir_mutex); 3312 3313 INIT_LIST_HEAD(&priv->bf_list); 3314 mutex_init(&priv->bf_mutex); 3315 3316 dev->rev_id = pdev->revision; 3317 dev->numa_node = dev_to_node(&pdev->dev); 3318 /* Detect if this device is a virtual function */ 3319 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3320 /* When acting as pf, we normally skip vfs unless explicitly 3321 * requested to probe them. */ 3322 if (nvfs && extended_func_num(pdev) > prb_vf) { 3323 mlx4_warn(dev, "Skipping virtual function:%d\n", 3324 extended_func_num(pdev)); 3325 err = -ENODEV; 3326 goto err_free_dev; 3327 } 3328 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3329 dev->flags |= MLX4_FLAG_SLAVE; 3330 } else { 3331 /* We reset the device and enable SRIOV only for physical 3332 * devices. Try to claim ownership on the device; 3333 * if already taken, skip -- do not allow multiple PFs */ 3334 err = mlx4_get_ownership(dev); 3335 if (err) { 3336 if (err < 0) 3337 goto err_free_dev; 3338 else { 3339 mlx4_warn(dev, "Multiple PFs not yet supported." 3340 " Skipping PF.\n"); 3341 err = -EINVAL; 3342 goto err_free_dev; 3343 } 3344 } 3345 3346 if (nvfs) { 3347 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", nvfs); 3348 err = pci_enable_sriov(pdev, nvfs); 3349 if (err) { 3350 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n", 3351 err); 3352 err = 0; 3353 } else { 3354 mlx4_warn(dev, "Running in master mode\n"); 3355 dev->flags |= MLX4_FLAG_SRIOV | 3356 MLX4_FLAG_MASTER; 3357 dev->num_vfs = nvfs; 3358 } 3359 } 3360 3361 atomic_set(&priv->opreq_count, 0); 3362 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3363 3364 /* 3365 * Now reset the HCA before we touch the PCI capabilities or 3366 * attempt a firmware command, since a boot ROM may have left 3367 * the HCA in an undefined state. 3368 */ 3369 err = mlx4_reset(dev); 3370 if (err) { 3371 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3372 goto err_sriov; 3373 } 3374 } 3375 3376slave_start: 3377 err = mlx4_cmd_init(dev); 3378 if (err) { 3379 mlx4_err(dev, "Failed to init command interface, aborting.\n"); 3380 goto err_sriov; 3381 } 3382 3383 /* In slave functions, the communication channel must be initialized 3384 * before posting commands. Also, init num_slaves before calling 3385 * mlx4_init_hca */ 3386 if (mlx4_is_mfunc(dev)) { 3387 if (mlx4_is_master(dev)) 3388 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3389 else { 3390 dev->num_slaves = 0; 3391 err = mlx4_multi_func_init(dev); 3392 if (err) { 3393 mlx4_err(dev, "Failed to init slave mfunc" 3394 " interface, aborting.\n"); 3395 goto err_cmd; 3396 } 3397 } 3398 } 3399 3400 err = mlx4_init_hca(dev); 3401 if (err) { 3402 if (err == -EACCES) { 3403 /* Not primary Physical function 3404 * Running in slave mode */ 3405 mlx4_cmd_cleanup(dev); 3406 dev->flags |= MLX4_FLAG_SLAVE; 3407 dev->flags &= ~MLX4_FLAG_MASTER; 3408 goto slave_start; 3409 } else 3410 goto err_mfunc; 3411 } 3412 3413 /* In master functions, the communication channel must be initialized 3414 * after obtaining its address from fw */ 3415 if (mlx4_is_master(dev)) { 3416 err = mlx4_multi_func_init(dev); 3417 if (err) { 3418 mlx4_err(dev, "Failed to init master mfunc" 3419 "interface, aborting.\n"); 3420 goto err_close; 3421 } 3422 } 3423 3424 err = mlx4_alloc_eq_table(dev); 3425 if (err) 3426 goto err_master_mfunc; 3427 3428 priv->msix_ctl.pool_bm = 0; 3429 mutex_init(&priv->msix_ctl.pool_lock); 3430 3431 mlx4_enable_msi_x(dev); 3432 3433 /* no MSIX and no shared IRQ */ 3434 if (!dev->caps.num_comp_vectors && !dev->caps.comp_pool) { 3435 err = -ENOSPC; 3436 goto err_free_eq; 3437 } 3438 3439 if ((mlx4_is_mfunc(dev)) && 3440 !(dev->flags & MLX4_FLAG_MSI_X)) { 3441 err = -ENOSYS; 3442 mlx4_err(dev, "INTx is not supported in multi-function mode." 3443 " aborting.\n"); 3444 goto err_free_eq; 3445 } 3446 3447 if (!mlx4_is_slave(dev)) { 3448 err = mlx4_init_steering(dev); 3449 if (err) 3450 goto err_free_eq; 3451 } 3452 3453 mlx4_init_quotas(dev); 3454 3455 err = mlx4_setup_hca(dev); 3456 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3457 !mlx4_is_mfunc(dev)) { 3458 dev->flags &= ~MLX4_FLAG_MSI_X; 3459 dev->caps.num_comp_vectors = 1; 3460 dev->caps.comp_pool = 0; 3461 pci_disable_msix(pdev); 3462 err = mlx4_setup_hca(dev); 3463 } 3464 3465 if (err) 3466 goto err_steer; 3467 3468 mlx4_init_hca_info(dev); 3469 3470 for (port = 1; port <= dev->caps.num_ports; port++) { 3471 err = mlx4_init_port_info(dev, port); 3472 if (err) 3473 goto err_port; 3474 } 3475 3476 err = mlx4_register_device(dev); 3477 if (err) 3478 goto err_port; 3479 3480 mlx4_request_modules(dev); 3481 3482 mlx4_sense_init(dev); 3483 mlx4_start_sense(dev); 3484 3485 priv->pci_dev_data = pci_dev_data; 3486 pci_set_drvdata(pdev, dev); 3487 3488 return 0; 3489 3490err_port: 3491 for (--port; port >= 1; --port) 3492 mlx4_cleanup_port_info(&priv->port[port]); 3493 3494 mlx4_cleanup_counters_table(dev); 3495 mlx4_cleanup_qp_table(dev); 3496 mlx4_cleanup_srq_table(dev); 3497 mlx4_cleanup_cq_table(dev); 3498 mlx4_cmd_use_polling(dev); 3499 mlx4_cleanup_eq_table(dev); 3500 mlx4_cleanup_mcg_table(dev); 3501 mlx4_cleanup_mr_table(dev); 3502 mlx4_cleanup_xrcd_table(dev); 3503 mlx4_cleanup_pd_table(dev); 3504 mlx4_cleanup_uar_table(dev); 3505 3506err_steer: 3507 if (!mlx4_is_slave(dev)) 3508 mlx4_clear_steering(dev); 3509 3510err_free_eq: 3511 mlx4_free_eq_table(dev); 3512 3513err_master_mfunc: 3514 if (mlx4_is_master(dev)) { 3515 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3516 mlx4_multi_func_cleanup(dev); 3517 } 3518 3519 if (mlx4_is_slave(dev)) { 3520 kfree(dev->caps.qp0_tunnel); 3521 kfree(dev->caps.qp0_proxy); 3522 kfree(dev->caps.qp1_tunnel); 3523 kfree(dev->caps.qp1_proxy); 3524 } 3525 3526err_close: 3527 if (dev->flags & MLX4_FLAG_MSI_X) 3528 pci_disable_msix(pdev); 3529 3530 mlx4_close_hca(dev); 3531 3532err_mfunc: 3533 if (mlx4_is_slave(dev)) 3534 mlx4_multi_func_cleanup(dev); 3535 3536err_cmd: 3537 mlx4_cmd_cleanup(dev); 3538 3539err_sriov: 3540 if (dev->flags & MLX4_FLAG_SRIOV) 3541 pci_disable_sriov(pdev); 3542 3543 if (!mlx4_is_slave(dev)) 3544 mlx4_free_ownership(dev); 3545 3546err_free_dev: 3547 kfree(priv); 3548 3549err_release_regions: 3550 pci_release_regions(pdev); 3551 3552err_disable_pdev: 3553 pci_disable_device(pdev); 3554 pci_set_drvdata(pdev, NULL); 3555 return err; 3556} 3557 3558static int __devinit mlx4_init_one(struct pci_dev *pdev, 3559 const struct pci_device_id *id) 3560{ 3561 device_set_desc(pdev->dev.bsddev, mlx4_version); 3562 return __mlx4_init_one(pdev, id->driver_data); 3563} 3564 3565static void mlx4_remove_one(struct pci_dev *pdev) 3566{ 3567 struct mlx4_dev *dev = pci_get_drvdata(pdev); 3568 struct mlx4_priv *priv = mlx4_priv(dev); 3569 int p; 3570 3571 if (dev) { 3572 /* in SRIOV it is not allowed to unload the pf's 3573 * driver while there are alive vf's */ 3574 if (mlx4_is_master(dev)) { 3575 if (mlx4_how_many_lives_vf(dev)) 3576 mlx4_err(dev, "Removing PF when there are assigned VF's !!!\n"); 3577 } 3578 mlx4_stop_sense(dev); 3579 mlx4_unregister_device(dev); 3580 3581 mlx4_cleanup_hca_info(&priv->hca_info); 3582 for (p = 1; p <= dev->caps.num_ports; p++) { 3583 mlx4_cleanup_port_info(&priv->port[p]); 3584 mlx4_CLOSE_PORT(dev, p); 3585 } 3586 3587 if (mlx4_is_master(dev)) 3588 mlx4_free_resource_tracker(dev, 3589 RES_TR_FREE_SLAVES_ONLY); 3590 3591 mlx4_cleanup_counters_table(dev); 3592 mlx4_cleanup_qp_table(dev); 3593 mlx4_cleanup_srq_table(dev); 3594 mlx4_cleanup_cq_table(dev); 3595 mlx4_cmd_use_polling(dev); 3596 mlx4_cleanup_eq_table(dev); 3597 mlx4_cleanup_mcg_table(dev); 3598 mlx4_cleanup_mr_table(dev); 3599 mlx4_cleanup_xrcd_table(dev); 3600 mlx4_cleanup_pd_table(dev); 3601 3602 if (mlx4_is_master(dev)) 3603 mlx4_free_resource_tracker(dev, 3604 RES_TR_FREE_STRUCTS_ONLY); 3605 3606 iounmap(priv->kar); 3607 mlx4_uar_free(dev, &priv->driver_uar); 3608 mlx4_cleanup_uar_table(dev); 3609 if (!mlx4_is_slave(dev)) 3610 mlx4_clear_steering(dev); 3611 mlx4_free_eq_table(dev); 3612 if (mlx4_is_master(dev)) 3613 mlx4_multi_func_cleanup(dev); 3614 mlx4_close_hca(dev); 3615 if (mlx4_is_slave(dev)) 3616 mlx4_multi_func_cleanup(dev); 3617 mlx4_cmd_cleanup(dev); 3618 3619 if (dev->flags & MLX4_FLAG_MSI_X) 3620 pci_disable_msix(pdev); 3621 if (dev->flags & MLX4_FLAG_SRIOV) { 3622 mlx4_warn(dev, "Disabling SR-IOV\n"); 3623 pci_disable_sriov(pdev); 3624 } 3625 3626 if (!mlx4_is_slave(dev)) 3627 mlx4_free_ownership(dev); 3628 3629 kfree(dev->caps.qp0_tunnel); 3630 kfree(dev->caps.qp0_proxy); 3631 kfree(dev->caps.qp1_tunnel); 3632 kfree(dev->caps.qp1_proxy); 3633 3634 kfree(priv); 3635 pci_release_regions(pdev); 3636 pci_disable_device(pdev); 3637 pci_set_drvdata(pdev, NULL); 3638 } 3639} 3640 3641static int restore_current_port_types(struct mlx4_dev *dev, 3642 enum mlx4_port_type *types, 3643 enum mlx4_port_type *poss_types) 3644{ 3645 struct mlx4_priv *priv = mlx4_priv(dev); 3646 int err, i; 3647 3648 mlx4_stop_sense(dev); 3649 mutex_lock(&priv->port_mutex); 3650 for (i = 0; i < dev->caps.num_ports; i++) 3651 dev->caps.possible_type[i + 1] = poss_types[i]; 3652 err = mlx4_change_port_types(dev, types); 3653 mlx4_start_sense(dev); 3654 mutex_unlock(&priv->port_mutex); 3655 return err; 3656} 3657 3658int mlx4_restart_one(struct pci_dev *pdev) 3659{ 3660 struct mlx4_dev *dev = pci_get_drvdata(pdev); 3661 struct mlx4_priv *priv = mlx4_priv(dev); 3662 enum mlx4_port_type curr_type[MLX4_MAX_PORTS]; 3663 enum mlx4_port_type poss_type[MLX4_MAX_PORTS]; 3664 int pci_dev_data, err, i; 3665 3666 pci_dev_data = priv->pci_dev_data; 3667 for (i = 0; i < dev->caps.num_ports; i++) { 3668 curr_type[i] = dev->caps.port_type[i + 1]; 3669 poss_type[i] = dev->caps.possible_type[i + 1]; 3670 } 3671 3672 mlx4_remove_one(pdev); 3673 err = __mlx4_init_one(pdev, pci_dev_data); 3674 if (err) 3675 return err; 3676 3677 dev = pci_get_drvdata(pdev); 3678 err = restore_current_port_types(dev, curr_type, poss_type); 3679 if (err) 3680 mlx4_err(dev, "mlx4_restart_one: could not restore original port types (%d)\n", 3681 err); 3682 return 0; 3683} 3684 3685static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { 3686 /* MT25408 "Hermon" SDR */ 3687 { PCI_VDEVICE(MELLANOX, 0x6340), 3688 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3689 /* MT25408 "Hermon" DDR */ 3690 { PCI_VDEVICE(MELLANOX, 0x634a), 3691 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3692 /* MT25408 "Hermon" QDR */ 3693 { PCI_VDEVICE(MELLANOX, 0x6354), 3694 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3695 /* MT25408 "Hermon" DDR PCIe gen2 */ 3696 { PCI_VDEVICE(MELLANOX, 0x6732), 3697 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3698 /* MT25408 "Hermon" QDR PCIe gen2 */ 3699 { PCI_VDEVICE(MELLANOX, 0x673c), 3700 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3701 /* MT25408 "Hermon" EN 10GigE */ 3702 { PCI_VDEVICE(MELLANOX, 0x6368), 3703 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3704 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ 3705 { PCI_VDEVICE(MELLANOX, 0x6750), 3706 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3707 /* MT25458 ConnectX EN 10GBASE-T 10GigE */ 3708 { PCI_VDEVICE(MELLANOX, 0x6372), 3709 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3710 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ 3711 { PCI_VDEVICE(MELLANOX, 0x675a), 3712 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3713 /* MT26468 ConnectX EN 10GigE PCIe gen2*/ 3714 { PCI_VDEVICE(MELLANOX, 0x6764), 3715 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3716 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ 3717 { PCI_VDEVICE(MELLANOX, 0x6746), 3718 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3719 /* MT26478 ConnectX2 40GigE PCIe gen2 */ 3720 { PCI_VDEVICE(MELLANOX, 0x676e), 3721 .driver_data = MLX4_PCI_DEV_FORCE_SENSE_PORT }, 3722 /* MT25400 Family [ConnectX-2 Virtual Function] */ 3723 { PCI_VDEVICE(MELLANOX, 0x1002), 3724 .driver_data = MLX4_PCI_DEV_IS_VF }, 3725 /* MT27500 Family [ConnectX-3] */ 3726 { PCI_VDEVICE(MELLANOX, 0x1003) }, 3727 /* MT27500 Family [ConnectX-3 Virtual Function] */ 3728 { PCI_VDEVICE(MELLANOX, 0x1004), 3729 .driver_data = MLX4_PCI_DEV_IS_VF }, 3730 { PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */ 3731 { PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */ 3732 { PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */ 3733 { PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */ 3734 { PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */ 3735 { PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */ 3736 { PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */ 3737 { PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */ 3738 { PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */ 3739 { PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */ 3740 { PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */ 3741 { PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */ 3742 { 0, } 3743}; 3744 3745MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 3746 3747static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 3748 pci_channel_state_t state) 3749{ 3750 mlx4_remove_one(pdev); 3751 3752 return state == pci_channel_io_perm_failure ? 3753 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 3754} 3755 3756static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 3757{ 3758 int ret = __mlx4_init_one(pdev, 0); 3759 3760 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 3761} 3762 3763static const struct pci_error_handlers mlx4_err_handler = { 3764 .error_detected = mlx4_pci_err_detected, 3765 .slot_reset = mlx4_pci_slot_reset, 3766}; 3767 3768static int suspend(struct pci_dev *pdev, pm_message_t state) 3769{ 3770 mlx4_remove_one(pdev); 3771 3772 return 0; 3773} 3774 3775static int resume(struct pci_dev *pdev) 3776{ 3777 return __mlx4_init_one(pdev, 0); 3778} 3779 3780static struct pci_driver mlx4_driver = { 3781 .name = DRV_NAME, 3782 .id_table = mlx4_pci_table, 3783 .probe = mlx4_init_one, 3784 .remove = __devexit_p(mlx4_remove_one), 3785 .suspend = suspend, 3786 .resume = resume, 3787 .err_handler = &mlx4_err_handler, 3788}; 3789 3790static int __init mlx4_verify_params(void) 3791{ 3792 int status; 3793 3794 status = update_defaults(&port_type_array); 3795 if (status == INVALID_STR) { 3796 if (mlx4_fill_dbdf2val_tbl(&port_type_array.dbdf2val)) 3797 return -1; 3798 } else if (status == INVALID_DATA) { 3799 return -1; 3800 } 3801 3802 status = update_defaults(&num_vfs); 3803 if (status == INVALID_STR) { 3804 if (mlx4_fill_dbdf2val_tbl(&num_vfs.dbdf2val)) 3805 return -1; 3806 } else if (status == INVALID_DATA) { 3807 return -1; 3808 } 3809 3810 status = update_defaults(&probe_vf); 3811 if (status == INVALID_STR) { 3812 if (mlx4_fill_dbdf2val_tbl(&probe_vf.dbdf2val)) 3813 return -1; 3814 } else if (status == INVALID_DATA) { 3815 return -1; 3816 } 3817 3818 if (msi_x < 0) { 3819 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x); 3820 return -1; 3821 } 3822 3823 if ((log_num_mac < 0) || (log_num_mac > 7)) { 3824 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac); 3825 return -1; 3826 } 3827 3828 if (log_num_vlan != 0) 3829 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 3830 MLX4_LOG_NUM_VLANS); 3831 3832 if (mlx4_set_4k_mtu != -1) 3833 pr_warning("mlx4_core: set_4k_mtu - obsolete module param\n"); 3834 3835 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) { 3836 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); 3837 return -1; 3838 } 3839 3840 if (mlx4_log_num_mgm_entry_size != -1 && 3841 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 3842 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { 3843 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not " 3844 "in legal range (-1 or %d..%d)\n", 3845 mlx4_log_num_mgm_entry_size, 3846 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 3847 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 3848 return -1; 3849 } 3850 3851 if (mod_param_profile.num_qp < 18 || mod_param_profile.num_qp > 23) { 3852 pr_warning("mlx4_core: bad log_num_qp: %d\n", 3853 mod_param_profile.num_qp); 3854 return -1; 3855 } 3856 3857 if (mod_param_profile.num_srq < 10) { 3858 pr_warning("mlx4_core: too low log_num_srq: %d\n", 3859 mod_param_profile.num_srq); 3860 return -1; 3861 } 3862 3863 if (mod_param_profile.num_cq < 10) { 3864 pr_warning("mlx4_core: too low log_num_cq: %d\n", 3865 mod_param_profile.num_cq); 3866 return -1; 3867 } 3868 3869 if (mod_param_profile.num_mpt < 10) { 3870 pr_warning("mlx4_core: too low log_num_mpt: %d\n", 3871 mod_param_profile.num_mpt); 3872 return -1; 3873 } 3874 3875 if (mod_param_profile.num_mtt_segs && 3876 mod_param_profile.num_mtt_segs < 15) { 3877 pr_warning("mlx4_core: too low log_num_mtt: %d\n", 3878 mod_param_profile.num_mtt_segs); 3879 return -1; 3880 } 3881 3882 if (mod_param_profile.num_mtt_segs > MLX4_MAX_LOG_NUM_MTT) { 3883 pr_warning("mlx4_core: too high log_num_mtt: %d\n", 3884 mod_param_profile.num_mtt_segs); 3885 return -1; 3886 } 3887 return 0; 3888} 3889 3890static int __init mlx4_init(void) 3891{ 3892 int ret; 3893 3894 if (mlx4_verify_params()) 3895 return -EINVAL; 3896 3897 mlx4_catas_init(); 3898 3899 mlx4_wq = create_singlethread_workqueue("mlx4"); 3900 if (!mlx4_wq) 3901 return -ENOMEM; 3902 3903 if (enable_sys_tune) 3904 sys_tune_init(); 3905 3906 ret = pci_register_driver(&mlx4_driver); 3907 if (ret < 0) 3908 goto err; 3909 3910 return 0; 3911 3912err: 3913 if (enable_sys_tune) 3914 sys_tune_fini(); 3915 3916 destroy_workqueue(mlx4_wq); 3917 3918 return ret; 3919} 3920 3921static void __exit mlx4_cleanup(void) 3922{ 3923 if (enable_sys_tune) 3924 sys_tune_fini(); 3925 3926 pci_unregister_driver(&mlx4_driver); 3927 destroy_workqueue(mlx4_wq); 3928} 3929 3930module_init_order(mlx4_init, SI_ORDER_MIDDLE); 3931module_exit(mlx4_cleanup); 3932 3933#include <sys/module.h> 3934static int 3935mlx4_evhand(module_t mod, int event, void *arg) 3936{ 3937 return (0); 3938} 3939 3940static moduledata_t mlx4_mod = { 3941 .name = "mlx4", 3942 .evhand = mlx4_evhand, 3943}; 3944MODULE_VERSION(mlx4, 1); 3945DECLARE_MODULE(mlx4, mlx4_mod, SI_SUB_OFED_PREINIT, SI_ORDER_ANY); 3946