1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#ifndef MLX4_FW_H 36#define MLX4_FW_H 37 38#include "mlx4.h" 39#include "icm.h" 40 41struct mlx4_mod_stat_cfg { 42 u8 log_pg_sz; 43 u8 log_pg_sz_m; 44}; 45 46struct mlx4_dev_cap { 47 int max_srq_sz; 48 int max_qp_sz; 49 int reserved_qps; 50 int max_qps; 51 int reserved_srqs; 52 int max_srqs; 53 int max_cq_sz; 54 int reserved_cqs; 55 int max_cqs; 56 int max_mpts; 57 int reserved_eqs; 58 int max_eqs; 59 int num_sys_eqs; 60 int reserved_mtts; 61 int max_mrw_sz; 62 int reserved_mrws; 63 int max_mtt_seg; 64 int max_requester_per_qp; 65 int max_responder_per_qp; 66 int max_rdma_global; 67 int local_ca_ack_delay; 68 int num_ports; 69 u32 max_msg_sz; 70 int ib_mtu[MLX4_MAX_PORTS + 1]; 71 int max_port_width[MLX4_MAX_PORTS + 1]; 72 int max_vl[MLX4_MAX_PORTS + 1]; 73 int max_gids[MLX4_MAX_PORTS + 1]; 74 int max_pkeys[MLX4_MAX_PORTS + 1]; 75 u64 def_mac[MLX4_MAX_PORTS + 1]; 76 u16 eth_mtu[MLX4_MAX_PORTS + 1]; 77 int trans_type[MLX4_MAX_PORTS + 1]; 78 int vendor_oui[MLX4_MAX_PORTS + 1]; 79 u16 wavelength[MLX4_MAX_PORTS + 1]; 80 u64 trans_code[MLX4_MAX_PORTS + 1]; 81 u16 stat_rate_support; 82 int fs_log_max_ucast_qp_range_size; 83 int fs_max_num_qp_per_entry; 84 u64 flags; 85 u64 flags2; 86 int reserved_uars; 87 int uar_size; 88 int min_page_sz; 89 int bf_reg_size; 90 int bf_regs_per_page; 91 int max_sq_sg; 92 int max_sq_desc_sz; 93 int max_rq_sg; 94 int max_rq_desc_sz; 95 int max_qp_per_mcg; 96 int reserved_mgms; 97 int max_mcgs; 98 int reserved_pds; 99 int max_pds; 100 int reserved_xrcds; 101 int max_xrcds; 102 int qpc_entry_sz; 103 int rdmarc_entry_sz; 104 int altc_entry_sz; 105 int aux_entry_sz; 106 int srq_entry_sz; 107 int cqc_entry_sz; 108 int eqc_entry_sz; 109 int dmpt_entry_sz; 110 int cmpt_entry_sz; 111 int mtt_entry_sz; 112 int resize_srq; 113 u32 bmme_flags; 114 u32 reserved_lkey; 115 u64 max_icm_sz; 116 int max_gso_sz; 117 int max_rss_tbl_sz; 118 u8 supported_port_types[MLX4_MAX_PORTS + 1]; 119 u8 suggested_type[MLX4_MAX_PORTS + 1]; 120 u8 default_sense[MLX4_MAX_PORTS + 1]; 121 u8 log_max_macs[MLX4_MAX_PORTS + 1]; 122 u8 log_max_vlans[MLX4_MAX_PORTS + 1]; 123 u32 max_basic_counters; 124 u32 sync_qp; 125 u8 timestamp_support; 126 u32 max_extended_counters; 127}; 128 129struct mlx4_func_cap { 130 u8 num_ports; 131 u8 flags; 132 u32 pf_context_behaviour; 133 int qp_quota; 134 int cq_quota; 135 int srq_quota; 136 int mpt_quota; 137 int mtt_quota; 138 int max_eq; 139 int reserved_eq; 140 int mcg_quota; 141 u32 qp0_tunnel_qpn; 142 u32 qp0_proxy_qpn; 143 u32 qp1_tunnel_qpn; 144 u32 qp1_proxy_qpn; 145 u8 physical_port; 146 u8 port_flags; 147 u8 def_counter_index; 148 u8 extra_flags; 149}; 150 151struct mlx4_func { 152 int bus; 153 int device; 154 int function; 155 int physical_function; 156 int rsvd_eqs; 157 int max_eq; 158 int rsvd_uars; 159}; 160 161struct mlx4_adapter { 162 u16 vsd_vendor_id; 163 char board_id[MLX4_BOARD_ID_LEN]; 164 char vsd[MLX4_VSD_LEN]; 165 u8 inta_pin; 166}; 167 168struct mlx4_init_hca_param { 169 u64 qpc_base; 170 u64 rdmarc_base; 171 u64 auxc_base; 172 u64 altc_base; 173 u64 srqc_base; 174 u64 cqc_base; 175 u64 eqc_base; 176 u64 mc_base; 177 u64 dmpt_base; 178 u64 cmpt_base; 179 u64 mtt_base; 180 u64 global_caps; 181 u16 log_mc_entry_sz; 182 u16 log_mc_hash_sz; 183 u16 hca_core_clock; 184 u8 log_num_qps; 185 u8 log_num_srqs; 186 u8 log_num_cqs; 187 u8 log_num_eqs; 188 u16 num_sys_eqs; 189 u8 log_rd_per_qp; 190 u8 log_mc_table_sz; 191 u8 log_mpt_sz; 192 u8 log_uar_sz; 193 u8 uar_page_sz; /* log pg sz in 4k chunks */ 194 u8 mw_enable; /* Enable memory windows */ 195 u8 fs_hash_enable_bits; 196 u8 steering_mode; /* for QUERY_HCA */ 197 u64 dev_cap_enabled; 198}; 199 200struct mlx4_init_ib_param { 201 int port_width; 202 int vl_cap; 203 int mtu_cap; 204 u16 gid_cap; 205 u16 pkey_cap; 206 int set_guid0; 207 u64 guid0; 208 int set_node_guid; 209 u64 node_guid; 210 int set_si_guid; 211 u64 si_guid; 212}; 213 214struct mlx4_set_ib_param { 215 int set_si_guid; 216 int reset_qkey_viol; 217 u64 si_guid; 218 u32 cap_mask; 219}; 220 221int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap); 222int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, 223 struct mlx4_func_cap *func_cap); 224int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 225 struct mlx4_vhcr *vhcr, 226 struct mlx4_cmd_mailbox *inbox, 227 struct mlx4_cmd_mailbox *outbox, 228 struct mlx4_cmd_info *cmd); 229int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm); 230int mlx4_UNMAP_FA(struct mlx4_dev *dev); 231int mlx4_RUN_FW(struct mlx4_dev *dev); 232int mlx4_QUERY_FW(struct mlx4_dev *dev); 233int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter); 234int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); 235int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); 236int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic); 237int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt); 238int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages); 239int mlx4_NOP(struct mlx4_dev *dev); 240int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg); 241int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave); 242void mlx4_opreq_action(struct work_struct *work); 243 244#endif /* MLX4_FW_H */ 245