1/*- 2 * Copyright (c) 2003-2009 RMI Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * $FreeBSD$ 29 * 30 * RMI_BSD 31 */ 32 33/* #define MAC_SPLIT_MODE */ 34 35#define MAC_SPACING 0x400 36#define XGMAC_SPACING 0x400 37 38/* PE-MCXMAC register and bit field definitions */ 39#define R_MAC_CONFIG_1 0x00 40#define O_MAC_CONFIG_1__srst 31 41#define O_MAC_CONFIG_1__simr 30 42#define O_MAC_CONFIG_1__hrrmc 18 43#define W_MAC_CONFIG_1__hrtmc 2 44#define O_MAC_CONFIG_1__hrrfn 16 45#define W_MAC_CONFIG_1__hrtfn 2 46#define O_MAC_CONFIG_1__intlb 8 47#define O_MAC_CONFIG_1__rxfc 5 48#define O_MAC_CONFIG_1__txfc 4 49#define O_MAC_CONFIG_1__srxen 3 50#define O_MAC_CONFIG_1__rxen 2 51#define O_MAC_CONFIG_1__stxen 1 52#define O_MAC_CONFIG_1__txen 0 53#define R_MAC_CONFIG_2 0x01 54#define O_MAC_CONFIG_2__prlen 12 55#define W_MAC_CONFIG_2__prlen 4 56#define O_MAC_CONFIG_2__speed 8 57#define W_MAC_CONFIG_2__speed 2 58#define O_MAC_CONFIG_2__hugen 5 59#define O_MAC_CONFIG_2__flchk 4 60#define O_MAC_CONFIG_2__crce 1 61#define O_MAC_CONFIG_2__fulld 0 62#define R_IPG_IFG 0x02 63#define O_IPG_IFG__ipgr1 24 64#define W_IPG_IFG__ipgr1 7 65#define O_IPG_IFG__ipgr2 16 66#define W_IPG_IFG__ipgr2 7 67#define O_IPG_IFG__mifg 8 68#define W_IPG_IFG__mifg 8 69#define O_IPG_IFG__ipgt 0 70#define W_IPG_IFG__ipgt 7 71#define R_HALF_DUPLEX 0x03 72#define O_HALF_DUPLEX__abebt 24 73#define W_HALF_DUPLEX__abebt 4 74#define O_HALF_DUPLEX__abebe 19 75#define O_HALF_DUPLEX__bpnb 18 76#define O_HALF_DUPLEX__nobo 17 77#define O_HALF_DUPLEX__edxsdfr 16 78#define O_HALF_DUPLEX__retry 12 79#define W_HALF_DUPLEX__retry 4 80#define O_HALF_DUPLEX__lcol 0 81#define W_HALF_DUPLEX__lcol 10 82#define R_MAXIMUM_FRAME_LENGTH 0x04 83#define O_MAXIMUM_FRAME_LENGTH__maxf 0 84#define W_MAXIMUM_FRAME_LENGTH__maxf 16 85#define R_TEST 0x07 86#define O_TEST__mbof 3 87#define O_TEST__rthdf 2 88#define O_TEST__tpause 1 89#define O_TEST__sstct 0 90#define R_MII_MGMT_CONFIG 0x08 91#define O_MII_MGMT_CONFIG__scinc 5 92#define O_MII_MGMT_CONFIG__spre 4 93#define O_MII_MGMT_CONFIG__clks 3 94#define W_MII_MGMT_CONFIG__clks 3 95#define R_MII_MGMT_COMMAND 0x09 96#define O_MII_MGMT_COMMAND__scan 1 97#define O_MII_MGMT_COMMAND__rstat 0 98#define R_MII_MGMT_ADDRESS 0x0A 99#define O_MII_MGMT_ADDRESS__fiad 8 100#define W_MII_MGMT_ADDRESS__fiad 5 101#define O_MII_MGMT_ADDRESS__fgad 5 102#define W_MII_MGMT_ADDRESS__fgad 0 103#define R_MII_MGMT_WRITE_DATA 0x0B 104#define O_MII_MGMT_WRITE_DATA__ctld 0 105#define W_MII_MGMT_WRITE_DATA__ctld 16 106#define R_MII_MGMT_STATUS 0x0C 107#define R_MII_MGMT_INDICATORS 0x0D 108#define O_MII_MGMT_INDICATORS__nvalid 2 109#define O_MII_MGMT_INDICATORS__scan 1 110#define O_MII_MGMT_INDICATORS__busy 0 111#define R_INTERFACE_CONTROL 0x0E 112#define O_INTERFACE_CONTROL__hrstint 31 113#define O_INTERFACE_CONTROL__tbimode 27 114#define O_INTERFACE_CONTROL__ghdmode 26 115#define O_INTERFACE_CONTROL__lhdmode 25 116#define O_INTERFACE_CONTROL__phymod 24 117#define O_INTERFACE_CONTROL__hrrmi 23 118#define O_INTERFACE_CONTROL__rspd 16 119#define O_INTERFACE_CONTROL__hr100 15 120#define O_INTERFACE_CONTROL__frcq 10 121#define O_INTERFACE_CONTROL__nocfr 9 122#define O_INTERFACE_CONTROL__dlfct 8 123#define O_INTERFACE_CONTROL__enjab 0 124#define R_INTERFACE_STATUS 0x0F 125#define O_INTERFACE_STATUS__xsdfr 9 126#define O_INTERFACE_STATUS__ssrr 8 127#define W_INTERFACE_STATUS__ssrr 5 128#define O_INTERFACE_STATUS__miilf 3 129#define O_INTERFACE_STATUS__locar 2 130#define O_INTERFACE_STATUS__sqerr 1 131#define O_INTERFACE_STATUS__jabber 0 132#define R_STATION_ADDRESS_LS 0x10 133#define R_STATION_ADDRESS_MS 0x11 134 135/* A-XGMAC register and bit field definitions */ 136#define R_XGMAC_CONFIG_0 0x00 137#define O_XGMAC_CONFIG_0__hstmacrst 31 138#define O_XGMAC_CONFIG_0__hstrstrctl 23 139#define O_XGMAC_CONFIG_0__hstrstrfn 22 140#define O_XGMAC_CONFIG_0__hstrsttctl 18 141#define O_XGMAC_CONFIG_0__hstrsttfn 17 142#define O_XGMAC_CONFIG_0__hstrstmiim 16 143#define O_XGMAC_CONFIG_0__hstloopback 8 144#define R_XGMAC_CONFIG_1 0x01 145#define O_XGMAC_CONFIG_1__hsttctlen 31 146#define O_XGMAC_CONFIG_1__hsttfen 30 147#define O_XGMAC_CONFIG_1__hstrctlen 29 148#define O_XGMAC_CONFIG_1__hstrfen 28 149#define O_XGMAC_CONFIG_1__tfen 26 150#define O_XGMAC_CONFIG_1__rfen 24 151#define O_XGMAC_CONFIG_1__hstrctlshrtp 12 152#define O_XGMAC_CONFIG_1__hstdlyfcstx 10 153#define W_XGMAC_CONFIG_1__hstdlyfcstx 2 154#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8 155#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2 156#define O_XGMAC_CONFIG_1__hstppen 7 157#define O_XGMAC_CONFIG_1__hstbytswp 6 158#define O_XGMAC_CONFIG_1__hstdrplt64 5 159#define O_XGMAC_CONFIG_1__hstprmscrx 4 160#define O_XGMAC_CONFIG_1__hstlenchk 3 161#define O_XGMAC_CONFIG_1__hstgenfcs 2 162#define O_XGMAC_CONFIG_1__hstpadmode 0 163#define W_XGMAC_CONFIG_1__hstpadmode 2 164#define R_XGMAC_CONFIG_2 0x02 165#define O_XGMAC_CONFIG_2__hsttctlfrcp 31 166#define O_XGMAC_CONFIG_2__hstmlnkflth 27 167#define O_XGMAC_CONFIG_2__hstalnkflth 26 168#define O_XGMAC_CONFIG_2__rflnkflt 24 169#define W_XGMAC_CONFIG_2__rflnkflt 2 170#define O_XGMAC_CONFIG_2__hstipgextmod 16 171#define W_XGMAC_CONFIG_2__hstipgextmod 5 172#define O_XGMAC_CONFIG_2__hstrctlfrcp 15 173#define O_XGMAC_CONFIG_2__hstipgexten 5 174#define O_XGMAC_CONFIG_2__hstmipgext 0 175#define W_XGMAC_CONFIG_2__hstmipgext 5 176#define R_XGMAC_CONFIG_3 0x03 177#define O_XGMAC_CONFIG_3__hstfltrfrm 31 178#define W_XGMAC_CONFIG_3__hstfltrfrm 16 179#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15 180#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16 181#define R_XGMAC_STATION_ADDRESS_LS 0x04 182#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0 183#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32 184#define R_XGMAC_STATION_ADDRESS_MS 0x05 185#define R_XGMAC_MAX_FRAME_LEN 0x08 186#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16 187#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14 188#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0 189#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16 190#define R_XGMAC_REV_LEVEL 0x0B 191#define O_XGMAC_REV_LEVEL__revlvl 0 192#define W_XGMAC_REV_LEVEL__revlvl 15 193#define R_XGMAC_MIIM_COMMAND 0x10 194#define O_XGMAC_MIIM_COMMAND__hstldcmd 3 195#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0 196#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3 197#define R_XGMAC_MIIM_FILED 0x11 198#define O_XGMAC_MIIM_FILED__hststfield 30 199#define W_XGMAC_MIIM_FILED__hststfield 2 200#define O_XGMAC_MIIM_FILED__hstopfield 28 201#define W_XGMAC_MIIM_FILED__hstopfield 2 202#define O_XGMAC_MIIM_FILED__hstphyadx 23 203#define W_XGMAC_MIIM_FILED__hstphyadx 5 204#define O_XGMAC_MIIM_FILED__hstregadx 18 205#define W_XGMAC_MIIM_FILED__hstregadx 5 206#define O_XGMAC_MIIM_FILED__hsttafield 16 207#define W_XGMAC_MIIM_FILED__hsttafield 2 208#define O_XGMAC_MIIM_FILED__miimrddat 0 209#define W_XGMAC_MIIM_FILED__miimrddat 16 210#define R_XGMAC_MIIM_CONFIG 0x12 211#define O_XGMAC_MIIM_CONFIG__hstnopram 7 212#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0 213#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7 214#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13 215#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0 216#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32 217#define R_XGMAC_MIIM_INDICATOR 0x14 218#define O_XGMAC_MIIM_INDICATOR__miimphylf 4 219#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3 220#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2 221#define O_XGMAC_MIIM_INDICATOR__miimmon 1 222#define O_XGMAC_MIIM_INDICATOR__miimbusy 0 223 224/* GMAC stats registers */ 225#define R_RBYT 0x27 226#define R_RPKT 0x28 227#define R_RFCS 0x29 228#define R_RMCA 0x2A 229#define R_RBCA 0x2B 230#define R_RXCF 0x2C 231#define R_RXPF 0x2D 232#define R_RXUO 0x2E 233#define R_RALN 0x2F 234#define R_RFLR 0x30 235#define R_RCDE 0x31 236#define R_RCSE 0x32 237#define R_RUND 0x33 238#define R_ROVR 0x34 239#define R_TBYT 0x38 240#define R_TPKT 0x39 241#define R_TMCA 0x3A 242#define R_TBCA 0x3B 243#define R_TXPF 0x3C 244#define R_TDFR 0x3D 245#define R_TEDF 0x3E 246#define R_TSCL 0x3F 247#define R_TMCL 0x40 248#define R_TLCL 0x41 249#define R_TXCL 0x42 250#define R_TNCL 0x43 251#define R_TJBR 0x46 252#define R_TFCS 0x47 253#define R_TXCF 0x48 254#define R_TOVR 0x49 255#define R_TUND 0x4A 256#define R_TFRG 0x4B 257 258/* Glue logic register and bit field definitions */ 259#define R_MAC_ADDR0 0x50 260#define R_MAC_ADDR1 0x52 261#define R_MAC_ADDR2 0x54 262#define R_MAC_ADDR3 0x56 263#define R_MAC_ADDR_MASK2 0x58 264#define R_MAC_ADDR_MASK3 0x5A 265#define R_MAC_FILTER_CONFIG 0x5C 266#define O_MAC_FILTER_CONFIG__BROADCAST_EN 10 267#define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9 268#define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8 269#define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7 270#define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6 271#define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5 272#define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4 273#define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3 274#define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2 275#define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1 276#define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0 277#define R_HASH_TABLE_VECTOR 0x30 278#define R_TX_CONTROL 0x0A0 279#define O_TX_CONTROL__Tx15Halt 31 280#define O_TX_CONTROL__Tx14Halt 30 281#define O_TX_CONTROL__Tx13Halt 29 282#define O_TX_CONTROL__Tx12Halt 28 283#define O_TX_CONTROL__Tx11Halt 27 284#define O_TX_CONTROL__Tx10Halt 26 285#define O_TX_CONTROL__Tx9Halt 25 286#define O_TX_CONTROL__Tx8Halt 24 287#define O_TX_CONTROL__Tx7Halt 23 288#define O_TX_CONTROL__Tx6Halt 22 289#define O_TX_CONTROL__Tx5Halt 21 290#define O_TX_CONTROL__Tx4Halt 20 291#define O_TX_CONTROL__Tx3Halt 19 292#define O_TX_CONTROL__Tx2Halt 18 293#define O_TX_CONTROL__Tx1Halt 17 294#define O_TX_CONTROL__Tx0Halt 16 295#define O_TX_CONTROL__TxIdle 15 296#define O_TX_CONTROL__TxEnable 14 297#define O_TX_CONTROL__TxThreshold 0 298#define W_TX_CONTROL__TxThreshold 14 299#define R_RX_CONTROL 0x0A1 300#define O_RX_CONTROL__RGMII 10 301#define O_RX_CONTROL__SoftReset 2 302#define O_RX_CONTROL__RxHalt 1 303#define O_RX_CONTROL__RxEnable 0 304#define R_DESC_PACK_CTRL 0x0A2 305#define O_DESC_PACK_CTRL__ByteOffset 17 306#define W_DESC_PACK_CTRL__ByteOffset 3 307#define O_DESC_PACK_CTRL__PrePadEnable 16 308#define O_DESC_PACK_CTRL__MaxEntry 14 309#define W_DESC_PACK_CTRL__MaxEntry 2 310#define O_DESC_PACK_CTRL__RegularSize 0 311#define W_DESC_PACK_CTRL__RegularSize 14 312#define R_STATCTRL 0x0A3 313#define O_STATCTRL__OverFlowEn 4 314#define O_STATCTRL__GIG 3 315#define O_STATCTRL__Sten 2 316#define O_STATCTRL__ClrCnt 1 317#define O_STATCTRL__AutoZ 0 318#define R_L2ALLOCCTRL 0x0A4 319#define O_L2ALLOCCTRL__TxL2Allocate 9 320#define W_L2ALLOCCTRL__TxL2Allocate 9 321#define O_L2ALLOCCTRL__RxL2Allocate 0 322#define W_L2ALLOCCTRL__RxL2Allocate 9 323#define R_INTMASK 0x0A5 324#define O_INTMASK__Spi4TxError 28 325#define O_INTMASK__Spi4RxError 27 326#define O_INTMASK__RGMIIHalfDupCollision 27 327#define O_INTMASK__Abort 26 328#define O_INTMASK__Underrun 25 329#define O_INTMASK__DiscardPacket 24 330#define O_INTMASK__AsyncFifoFull 23 331#define O_INTMASK__TagFull 22 332#define O_INTMASK__Class3Full 21 333#define O_INTMASK__C3EarlyFull 20 334#define O_INTMASK__Class2Full 19 335#define O_INTMASK__C2EarlyFull 18 336#define O_INTMASK__Class1Full 17 337#define O_INTMASK__C1EarlyFull 16 338#define O_INTMASK__Class0Full 15 339#define O_INTMASK__C0EarlyFull 14 340#define O_INTMASK__RxDataFull 13 341#define O_INTMASK__RxEarlyFull 12 342#define O_INTMASK__RFreeEmpty 9 343#define O_INTMASK__RFEarlyEmpty 8 344#define O_INTMASK__P2PSpillEcc 7 345#define O_INTMASK__FreeDescFull 5 346#define O_INTMASK__FreeEarlyFull 4 347#define O_INTMASK__TxFetchError 3 348#define O_INTMASK__StatCarry 2 349#define O_INTMASK__MDInt 1 350#define O_INTMASK__TxIllegal 0 351#define R_INTREG 0x0A6 352#define O_INTREG__Spi4TxError 28 353#define O_INTREG__Spi4RxError 27 354#define O_INTREG__RGMIIHalfDupCollision 27 355#define O_INTREG__Abort 26 356#define O_INTREG__Underrun 25 357#define O_INTREG__DiscardPacket 24 358#define O_INTREG__AsyncFifoFull 23 359#define O_INTREG__TagFull 22 360#define O_INTREG__Class3Full 21 361#define O_INTREG__C3EarlyFull 20 362#define O_INTREG__Class2Full 19 363#define O_INTREG__C2EarlyFull 18 364#define O_INTREG__Class1Full 17 365#define O_INTREG__C1EarlyFull 16 366#define O_INTREG__Class0Full 15 367#define O_INTREG__C0EarlyFull 14 368#define O_INTREG__RxDataFull 13 369#define O_INTREG__RxEarlyFull 12 370#define O_INTREG__RFreeEmpty 9 371#define O_INTREG__RFEarlyEmpty 8 372#define O_INTREG__P2PSpillEcc 7 373#define O_INTREG__FreeDescFull 5 374#define O_INTREG__FreeEarlyFull 4 375#define O_INTREG__TxFetchError 3 376#define O_INTREG__StatCarry 2 377#define O_INTREG__MDInt 1 378#define O_INTREG__TxIllegal 0 379#define R_TXRETRY 0x0A7 380#define O_TXRETRY__CollisionRetry 6 381#define O_TXRETRY__BusErrorRetry 5 382#define O_TXRETRY__UnderRunRetry 4 383#define O_TXRETRY__Retries 0 384#define W_TXRETRY__Retries 4 385#define R_CORECONTROL 0x0A8 386#define O_CORECONTROL__ErrorThread 4 387#define W_CORECONTROL__ErrorThread 7 388#define O_CORECONTROL__Shutdown 2 389#define O_CORECONTROL__Speed 0 390#define W_CORECONTROL__Speed 2 391#define R_BYTEOFFSET0 0x0A9 392#define R_BYTEOFFSET1 0x0AA 393#define R_L2TYPE_0 0x0F0 394#define O_L2TYPE__ExtraHdrProtoSize 26 395#define W_L2TYPE__ExtraHdrProtoSize 5 396#define O_L2TYPE__ExtraHdrProtoOffset 20 397#define W_L2TYPE__ExtraHdrProtoOffset 6 398#define O_L2TYPE__ExtraHeaderSize 14 399#define W_L2TYPE__ExtraHeaderSize 6 400#define O_L2TYPE__ProtoOffset 8 401#define W_L2TYPE__ProtoOffset 6 402#define O_L2TYPE__L2HdrOffset 2 403#define W_L2TYPE__L2HdrOffset 6 404#define O_L2TYPE__L2Proto 0 405#define W_L2TYPE__L2Proto 2 406#define R_L2TYPE_1 0xF0 407#define R_L2TYPE_2 0xF0 408#define R_L2TYPE_3 0xF0 409#define R_PARSERCONFIGREG 0x100 410#define O_PARSERCONFIGREG__CRCHashPoly 8 411#define W_PARSERCONFIGREG__CRCHashPoly 7 412#define O_PARSERCONFIGREG__PrePadOffset 4 413#define W_PARSERCONFIGREG__PrePadOffset 4 414#define O_PARSERCONFIGREG__UseCAM 2 415#define O_PARSERCONFIGREG__UseHASH 1 416#define O_PARSERCONFIGREG__UseProto 0 417#define R_L3CTABLE 0x140 418#define O_L3CTABLE__Offset0 25 419#define W_L3CTABLE__Offset0 7 420#define O_L3CTABLE__Len0 21 421#define W_L3CTABLE__Len0 4 422#define O_L3CTABLE__Offset1 14 423#define W_L3CTABLE__Offset1 7 424#define O_L3CTABLE__Len1 10 425#define W_L3CTABLE__Len1 4 426#define O_L3CTABLE__Offset2 4 427#define W_L3CTABLE__Offset2 6 428#define O_L3CTABLE__Len2 0 429#define W_L3CTABLE__Len2 4 430#define O_L3CTABLE__L3HdrOffset 26 431#define W_L3CTABLE__L3HdrOffset 6 432#define O_L3CTABLE__L4ProtoOffset 20 433#define W_L3CTABLE__L4ProtoOffset 6 434#define O_L3CTABLE__IPChksumCompute 19 435#define O_L3CTABLE__L4Classify 18 436#define O_L3CTABLE__L2Proto 16 437#define W_L3CTABLE__L2Proto 2 438#define O_L3CTABLE__L3ProtoKey 0 439#define W_L3CTABLE__L3ProtoKey 16 440#define R_L4CTABLE 0x160 441#define O_L4CTABLE__Offset0 21 442#define W_L4CTABLE__Offset0 6 443#define O_L4CTABLE__Len0 17 444#define W_L4CTABLE__Len0 4 445#define O_L4CTABLE__Offset1 11 446#define W_L4CTABLE__Offset1 6 447#define O_L4CTABLE__Len1 7 448#define W_L4CTABLE__Len1 4 449#define O_L4CTABLE__TCPChksumEnable 0 450#define R_CAM4X128TABLE 0x172 451#define O_CAM4X128TABLE__ClassId 7 452#define W_CAM4X128TABLE__ClassId 2 453#define O_CAM4X128TABLE__BucketId 1 454#define W_CAM4X128TABLE__BucketId 6 455#define O_CAM4X128TABLE__UseBucket 0 456#define R_CAM4X128KEY 0x180 457#define R_TRANSLATETABLE 0x1A0 458#define R_DMACR0 0x200 459#define O_DMACR0__Data0WrMaxCr 27 460#define W_DMACR0__Data0WrMaxCr 3 461#define O_DMACR0__Data0RdMaxCr 24 462#define W_DMACR0__Data0RdMaxCr 3 463#define O_DMACR0__Data1WrMaxCr 21 464#define W_DMACR0__Data1WrMaxCr 3 465#define O_DMACR0__Data1RdMaxCr 18 466#define W_DMACR0__Data1RdMaxCr 3 467#define O_DMACR0__Data2WrMaxCr 15 468#define W_DMACR0__Data2WrMaxCr 3 469#define O_DMACR0__Data2RdMaxCr 12 470#define W_DMACR0__Data2RdMaxCr 3 471#define O_DMACR0__Data3WrMaxCr 9 472#define W_DMACR0__Data3WrMaxCr 3 473#define O_DMACR0__Data3RdMaxCr 6 474#define W_DMACR0__Data3RdMaxCr 3 475#define O_DMACR0__Data4WrMaxCr 3 476#define W_DMACR0__Data4WrMaxCr 3 477#define O_DMACR0__Data4RdMaxCr 0 478#define W_DMACR0__Data4RdMaxCr 3 479#define R_DMACR1 0x201 480#define O_DMACR1__Data5WrMaxCr 27 481#define W_DMACR1__Data5WrMaxCr 3 482#define O_DMACR1__Data5RdMaxCr 24 483#define W_DMACR1__Data5RdMaxCr 3 484#define O_DMACR1__Data6WrMaxCr 21 485#define W_DMACR1__Data6WrMaxCr 3 486#define O_DMACR1__Data6RdMaxCr 18 487#define W_DMACR1__Data6RdMaxCr 3 488#define O_DMACR1__Data7WrMaxCr 15 489#define W_DMACR1__Data7WrMaxCr 3 490#define O_DMACR1__Data7RdMaxCr 12 491#define W_DMACR1__Data7RdMaxCr 3 492#define O_DMACR1__Data8WrMaxCr 9 493#define W_DMACR1__Data8WrMaxCr 3 494#define O_DMACR1__Data8RdMaxCr 6 495#define W_DMACR1__Data8RdMaxCr 3 496#define O_DMACR1__Data9WrMaxCr 3 497#define W_DMACR1__Data9WrMaxCr 3 498#define O_DMACR1__Data9RdMaxCr 0 499#define W_DMACR1__Data9RdMaxCr 3 500#define R_DMACR2 0x202 501#define O_DMACR2__Data10WrMaxCr 27 502#define W_DMACR2__Data10WrMaxCr 3 503#define O_DMACR2__Data10RdMaxCr 24 504#define W_DMACR2__Data10RdMaxCr 3 505#define O_DMACR2__Data11WrMaxCr 21 506#define W_DMACR2__Data11WrMaxCr 3 507#define O_DMACR2__Data11RdMaxCr 18 508#define W_DMACR2__Data11RdMaxCr 3 509#define O_DMACR2__Data12WrMaxCr 15 510#define W_DMACR2__Data12WrMaxCr 3 511#define O_DMACR2__Data12RdMaxCr 12 512#define W_DMACR2__Data12RdMaxCr 3 513#define O_DMACR2__Data13WrMaxCr 9 514#define W_DMACR2__Data13WrMaxCr 3 515#define O_DMACR2__Data13RdMaxCr 6 516#define W_DMACR2__Data13RdMaxCr 3 517#define O_DMACR2__Data14WrMaxCr 3 518#define W_DMACR2__Data14WrMaxCr 3 519#define O_DMACR2__Data14RdMaxCr 0 520#define W_DMACR2__Data14RdMaxCr 3 521#define R_DMACR3 0x203 522#define O_DMACR3__Data15WrMaxCr 27 523#define W_DMACR3__Data15WrMaxCr 3 524#define O_DMACR3__Data15RdMaxCr 24 525#define W_DMACR3__Data15RdMaxCr 3 526#define O_DMACR3__SpClassWrMaxCr 21 527#define W_DMACR3__SpClassWrMaxCr 3 528#define O_DMACR3__SpClassRdMaxCr 18 529#define W_DMACR3__SpClassRdMaxCr 3 530#define O_DMACR3__JumFrInWrMaxCr 15 531#define W_DMACR3__JumFrInWrMaxCr 3 532#define O_DMACR3__JumFrInRdMaxCr 12 533#define W_DMACR3__JumFrInRdMaxCr 3 534#define O_DMACR3__RegFrInWrMaxCr 9 535#define W_DMACR3__RegFrInWrMaxCr 3 536#define O_DMACR3__RegFrInRdMaxCr 6 537#define W_DMACR3__RegFrInRdMaxCr 3 538#define O_DMACR3__FrOutWrMaxCr 3 539#define W_DMACR3__FrOutWrMaxCr 3 540#define O_DMACR3__FrOutRdMaxCr 0 541#define W_DMACR3__FrOutRdMaxCr 3 542#define R_REG_FRIN_SPILL_MEM_START_0 0x204 543#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0 544#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32 545#define R_REG_FRIN_SPILL_MEM_START_1 0x205 546#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0 547#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3 548#define R_REG_FRIN_SPILL_MEM_SIZE 0x206 549#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0 550#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32 551#define R_FROUT_SPILL_MEM_START_0 0x207 552#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0 553#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32 554#define R_FROUT_SPILL_MEM_START_1 0x208 555#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0 556#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3 557#define R_FROUT_SPILL_MEM_SIZE 0x209 558#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0 559#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32 560#define R_CLASS0_SPILL_MEM_START_0 0x20A 561#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0 562#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32 563#define R_CLASS0_SPILL_MEM_START_1 0x20B 564#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0 565#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3 566#define R_CLASS0_SPILL_MEM_SIZE 0x20C 567#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0 568#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32 569#define R_JUMFRIN_SPILL_MEM_START_0 0x20D 570#define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0 571#define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32 572#define R_JUMFRIN_SPILL_MEM_START_1 0x20E 573#define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0 574#define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3 575#define R_JUMFRIN_SPILL_MEM_SIZE 0x20F 576#define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0 577#define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32 578#define R_CLASS1_SPILL_MEM_START_0 0x210 579#define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0 580#define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32 581#define R_CLASS1_SPILL_MEM_START_1 0x211 582#define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0 583#define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3 584#define R_CLASS1_SPILL_MEM_SIZE 0x212 585#define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0 586#define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32 587#define R_CLASS2_SPILL_MEM_START_0 0x213 588#define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0 589#define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32 590#define R_CLASS2_SPILL_MEM_START_1 0x214 591#define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0 592#define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3 593#define R_CLASS2_SPILL_MEM_SIZE 0x215 594#define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0 595#define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32 596#define R_CLASS3_SPILL_MEM_START_0 0x216 597#define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0 598#define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32 599#define R_CLASS3_SPILL_MEM_START_1 0x217 600#define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0 601#define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3 602#define R_CLASS3_SPILL_MEM_SIZE 0x218 603#define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0 604#define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32 605#define R_REG_FRIN1_SPILL_MEM_START_0 0x219 606#define R_REG_FRIN1_SPILL_MEM_START_1 0x21a 607#define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b 608#define R_SPIHNGY0 0x219 609#define O_SPIHNGY0__EG_HNGY_THRESH_0 24 610#define W_SPIHNGY0__EG_HNGY_THRESH_0 7 611#define O_SPIHNGY0__EG_HNGY_THRESH_1 16 612#define W_SPIHNGY0__EG_HNGY_THRESH_1 7 613#define O_SPIHNGY0__EG_HNGY_THRESH_2 8 614#define W_SPIHNGY0__EG_HNGY_THRESH_2 7 615#define O_SPIHNGY0__EG_HNGY_THRESH_3 0 616#define W_SPIHNGY0__EG_HNGY_THRESH_3 7 617#define R_SPIHNGY1 0x21A 618#define O_SPIHNGY1__EG_HNGY_THRESH_4 24 619#define W_SPIHNGY1__EG_HNGY_THRESH_4 7 620#define O_SPIHNGY1__EG_HNGY_THRESH_5 16 621#define W_SPIHNGY1__EG_HNGY_THRESH_5 7 622#define O_SPIHNGY1__EG_HNGY_THRESH_6 8 623#define W_SPIHNGY1__EG_HNGY_THRESH_6 7 624#define O_SPIHNGY1__EG_HNGY_THRESH_7 0 625#define W_SPIHNGY1__EG_HNGY_THRESH_7 7 626#define R_SPIHNGY2 0x21B 627#define O_SPIHNGY2__EG_HNGY_THRESH_8 24 628#define W_SPIHNGY2__EG_HNGY_THRESH_8 7 629#define O_SPIHNGY2__EG_HNGY_THRESH_9 16 630#define W_SPIHNGY2__EG_HNGY_THRESH_9 7 631#define O_SPIHNGY2__EG_HNGY_THRESH_10 8 632#define W_SPIHNGY2__EG_HNGY_THRESH_10 7 633#define O_SPIHNGY2__EG_HNGY_THRESH_11 0 634#define W_SPIHNGY2__EG_HNGY_THRESH_11 7 635#define R_SPIHNGY3 0x21C 636#define O_SPIHNGY3__EG_HNGY_THRESH_12 24 637#define W_SPIHNGY3__EG_HNGY_THRESH_12 7 638#define O_SPIHNGY3__EG_HNGY_THRESH_13 16 639#define W_SPIHNGY3__EG_HNGY_THRESH_13 7 640#define O_SPIHNGY3__EG_HNGY_THRESH_14 8 641#define W_SPIHNGY3__EG_HNGY_THRESH_14 7 642#define O_SPIHNGY3__EG_HNGY_THRESH_15 0 643#define W_SPIHNGY3__EG_HNGY_THRESH_15 7 644#define R_SPISTRV0 0x21D 645#define O_SPISTRV0__EG_STRV_THRESH_0 24 646#define W_SPISTRV0__EG_STRV_THRESH_0 7 647#define O_SPISTRV0__EG_STRV_THRESH_1 16 648#define W_SPISTRV0__EG_STRV_THRESH_1 7 649#define O_SPISTRV0__EG_STRV_THRESH_2 8 650#define W_SPISTRV0__EG_STRV_THRESH_2 7 651#define O_SPISTRV0__EG_STRV_THRESH_3 0 652#define W_SPISTRV0__EG_STRV_THRESH_3 7 653#define R_SPISTRV1 0x21E 654#define O_SPISTRV1__EG_STRV_THRESH_4 24 655#define W_SPISTRV1__EG_STRV_THRESH_4 7 656#define O_SPISTRV1__EG_STRV_THRESH_5 16 657#define W_SPISTRV1__EG_STRV_THRESH_5 7 658#define O_SPISTRV1__EG_STRV_THRESH_6 8 659#define W_SPISTRV1__EG_STRV_THRESH_6 7 660#define O_SPISTRV1__EG_STRV_THRESH_7 0 661#define W_SPISTRV1__EG_STRV_THRESH_7 7 662#define R_SPISTRV2 0x21F 663#define O_SPISTRV2__EG_STRV_THRESH_8 24 664#define W_SPISTRV2__EG_STRV_THRESH_8 7 665#define O_SPISTRV2__EG_STRV_THRESH_9 16 666#define W_SPISTRV2__EG_STRV_THRESH_9 7 667#define O_SPISTRV2__EG_STRV_THRESH_10 8 668#define W_SPISTRV2__EG_STRV_THRESH_10 7 669#define O_SPISTRV2__EG_STRV_THRESH_11 0 670#define W_SPISTRV2__EG_STRV_THRESH_11 7 671#define R_SPISTRV3 0x220 672#define O_SPISTRV3__EG_STRV_THRESH_12 24 673#define W_SPISTRV3__EG_STRV_THRESH_12 7 674#define O_SPISTRV3__EG_STRV_THRESH_13 16 675#define W_SPISTRV3__EG_STRV_THRESH_13 7 676#define O_SPISTRV3__EG_STRV_THRESH_14 8 677#define W_SPISTRV3__EG_STRV_THRESH_14 7 678#define O_SPISTRV3__EG_STRV_THRESH_15 0 679#define W_SPISTRV3__EG_STRV_THRESH_15 7 680#define R_TXDATAFIFO0 0x221 681#define O_TXDATAFIFO0__Tx0DataFifoStart 24 682#define W_TXDATAFIFO0__Tx0DataFifoStart 7 683#define O_TXDATAFIFO0__Tx0DataFifoSize 16 684#define W_TXDATAFIFO0__Tx0DataFifoSize 7 685#define O_TXDATAFIFO0__Tx1DataFifoStart 8 686#define W_TXDATAFIFO0__Tx1DataFifoStart 7 687#define O_TXDATAFIFO0__Tx1DataFifoSize 0 688#define W_TXDATAFIFO0__Tx1DataFifoSize 7 689#define R_TXDATAFIFO1 0x222 690#define O_TXDATAFIFO1__Tx2DataFifoStart 24 691#define W_TXDATAFIFO1__Tx2DataFifoStart 7 692#define O_TXDATAFIFO1__Tx2DataFifoSize 16 693#define W_TXDATAFIFO1__Tx2DataFifoSize 7 694#define O_TXDATAFIFO1__Tx3DataFifoStart 8 695#define W_TXDATAFIFO1__Tx3DataFifoStart 7 696#define O_TXDATAFIFO1__Tx3DataFifoSize 0 697#define W_TXDATAFIFO1__Tx3DataFifoSize 7 698#define R_TXDATAFIFO2 0x223 699#define O_TXDATAFIFO2__Tx4DataFifoStart 24 700#define W_TXDATAFIFO2__Tx4DataFifoStart 7 701#define O_TXDATAFIFO2__Tx4DataFifoSize 16 702#define W_TXDATAFIFO2__Tx4DataFifoSize 7 703#define O_TXDATAFIFO2__Tx5DataFifoStart 8 704#define W_TXDATAFIFO2__Tx5DataFifoStart 7 705#define O_TXDATAFIFO2__Tx5DataFifoSize 0 706#define W_TXDATAFIFO2__Tx5DataFifoSize 7 707#define R_TXDATAFIFO3 0x224 708#define O_TXDATAFIFO3__Tx6DataFifoStart 24 709#define W_TXDATAFIFO3__Tx6DataFifoStart 7 710#define O_TXDATAFIFO3__Tx6DataFifoSize 16 711#define W_TXDATAFIFO3__Tx6DataFifoSize 7 712#define O_TXDATAFIFO3__Tx7DataFifoStart 8 713#define W_TXDATAFIFO3__Tx7DataFifoStart 7 714#define O_TXDATAFIFO3__Tx7DataFifoSize 0 715#define W_TXDATAFIFO3__Tx7DataFifoSize 7 716#define R_TXDATAFIFO4 0x225 717#define O_TXDATAFIFO4__Tx8DataFifoStart 24 718#define W_TXDATAFIFO4__Tx8DataFifoStart 7 719#define O_TXDATAFIFO4__Tx8DataFifoSize 16 720#define W_TXDATAFIFO4__Tx8DataFifoSize 7 721#define O_TXDATAFIFO4__Tx9DataFifoStart 8 722#define W_TXDATAFIFO4__Tx9DataFifoStart 7 723#define O_TXDATAFIFO4__Tx9DataFifoSize 0 724#define W_TXDATAFIFO4__Tx9DataFifoSize 7 725#define R_TXDATAFIFO5 0x226 726#define O_TXDATAFIFO5__Tx10DataFifoStart 24 727#define W_TXDATAFIFO5__Tx10DataFifoStart 7 728#define O_TXDATAFIFO5__Tx10DataFifoSize 16 729#define W_TXDATAFIFO5__Tx10DataFifoSize 7 730#define O_TXDATAFIFO5__Tx11DataFifoStart 8 731#define W_TXDATAFIFO5__Tx11DataFifoStart 7 732#define O_TXDATAFIFO5__Tx11DataFifoSize 0 733#define W_TXDATAFIFO5__Tx11DataFifoSize 7 734#define R_TXDATAFIFO6 0x227 735#define O_TXDATAFIFO6__Tx12DataFifoStart 24 736#define W_TXDATAFIFO6__Tx12DataFifoStart 7 737#define O_TXDATAFIFO6__Tx12DataFifoSize 16 738#define W_TXDATAFIFO6__Tx12DataFifoSize 7 739#define O_TXDATAFIFO6__Tx13DataFifoStart 8 740#define W_TXDATAFIFO6__Tx13DataFifoStart 7 741#define O_TXDATAFIFO6__Tx13DataFifoSize 0 742#define W_TXDATAFIFO6__Tx13DataFifoSize 7 743#define R_TXDATAFIFO7 0x228 744#define O_TXDATAFIFO7__Tx14DataFifoStart 24 745#define W_TXDATAFIFO7__Tx14DataFifoStart 7 746#define O_TXDATAFIFO7__Tx14DataFifoSize 16 747#define W_TXDATAFIFO7__Tx14DataFifoSize 7 748#define O_TXDATAFIFO7__Tx15DataFifoStart 8 749#define W_TXDATAFIFO7__Tx15DataFifoStart 7 750#define O_TXDATAFIFO7__Tx15DataFifoSize 0 751#define W_TXDATAFIFO7__Tx15DataFifoSize 7 752#define R_RXDATAFIFO0 0x229 753#define O_RXDATAFIFO0__Rx0DataFifoStart 24 754#define W_RXDATAFIFO0__Rx0DataFifoStart 7 755#define O_RXDATAFIFO0__Rx0DataFifoSize 16 756#define W_RXDATAFIFO0__Rx0DataFifoSize 7 757#define O_RXDATAFIFO0__Rx1DataFifoStart 8 758#define W_RXDATAFIFO0__Rx1DataFifoStart 7 759#define O_RXDATAFIFO0__Rx1DataFifoSize 0 760#define W_RXDATAFIFO0__Rx1DataFifoSize 7 761#define R_RXDATAFIFO1 0x22A 762#define O_RXDATAFIFO1__Rx2DataFifoStart 24 763#define W_RXDATAFIFO1__Rx2DataFifoStart 7 764#define O_RXDATAFIFO1__Rx2DataFifoSize 16 765#define W_RXDATAFIFO1__Rx2DataFifoSize 7 766#define O_RXDATAFIFO1__Rx3DataFifoStart 8 767#define W_RXDATAFIFO1__Rx3DataFifoStart 7 768#define O_RXDATAFIFO1__Rx3DataFifoSize 0 769#define W_RXDATAFIFO1__Rx3DataFifoSize 7 770#define R_RXDATAFIFO2 0x22B 771#define O_RXDATAFIFO2__Rx4DataFifoStart 24 772#define W_RXDATAFIFO2__Rx4DataFifoStart 7 773#define O_RXDATAFIFO2__Rx4DataFifoSize 16 774#define W_RXDATAFIFO2__Rx4DataFifoSize 7 775#define O_RXDATAFIFO2__Rx5DataFifoStart 8 776#define W_RXDATAFIFO2__Rx5DataFifoStart 7 777#define O_RXDATAFIFO2__Rx5DataFifoSize 0 778#define W_RXDATAFIFO2__Rx5DataFifoSize 7 779#define R_RXDATAFIFO3 0x22C 780#define O_RXDATAFIFO3__Rx6DataFifoStart 24 781#define W_RXDATAFIFO3__Rx6DataFifoStart 7 782#define O_RXDATAFIFO3__Rx6DataFifoSize 16 783#define W_RXDATAFIFO3__Rx6DataFifoSize 7 784#define O_RXDATAFIFO3__Rx7DataFifoStart 8 785#define W_RXDATAFIFO3__Rx7DataFifoStart 7 786#define O_RXDATAFIFO3__Rx7DataFifoSize 0 787#define W_RXDATAFIFO3__Rx7DataFifoSize 7 788#define R_RXDATAFIFO4 0x22D 789#define O_RXDATAFIFO4__Rx8DataFifoStart 24 790#define W_RXDATAFIFO4__Rx8DataFifoStart 7 791#define O_RXDATAFIFO4__Rx8DataFifoSize 16 792#define W_RXDATAFIFO4__Rx8DataFifoSize 7 793#define O_RXDATAFIFO4__Rx9DataFifoStart 8 794#define W_RXDATAFIFO4__Rx9DataFifoStart 7 795#define O_RXDATAFIFO4__Rx9DataFifoSize 0 796#define W_RXDATAFIFO4__Rx9DataFifoSize 7 797#define R_RXDATAFIFO5 0x22E 798#define O_RXDATAFIFO5__Rx10DataFifoStart 24 799#define W_RXDATAFIFO5__Rx10DataFifoStart 7 800#define O_RXDATAFIFO5__Rx10DataFifoSize 16 801#define W_RXDATAFIFO5__Rx10DataFifoSize 7 802#define O_RXDATAFIFO5__Rx11DataFifoStart 8 803#define W_RXDATAFIFO5__Rx11DataFifoStart 7 804#define O_RXDATAFIFO5__Rx11DataFifoSize 0 805#define W_RXDATAFIFO5__Rx11DataFifoSize 7 806#define R_RXDATAFIFO6 0x22F 807#define O_RXDATAFIFO6__Rx12DataFifoStart 24 808#define W_RXDATAFIFO6__Rx12DataFifoStart 7 809#define O_RXDATAFIFO6__Rx12DataFifoSize 16 810#define W_RXDATAFIFO6__Rx12DataFifoSize 7 811#define O_RXDATAFIFO6__Rx13DataFifoStart 8 812#define W_RXDATAFIFO6__Rx13DataFifoStart 7 813#define O_RXDATAFIFO6__Rx13DataFifoSize 0 814#define W_RXDATAFIFO6__Rx13DataFifoSize 7 815#define R_RXDATAFIFO7 0x230 816#define O_RXDATAFIFO7__Rx14DataFifoStart 24 817#define W_RXDATAFIFO7__Rx14DataFifoStart 7 818#define O_RXDATAFIFO7__Rx14DataFifoSize 16 819#define W_RXDATAFIFO7__Rx14DataFifoSize 7 820#define O_RXDATAFIFO7__Rx15DataFifoStart 8 821#define W_RXDATAFIFO7__Rx15DataFifoStart 7 822#define O_RXDATAFIFO7__Rx15DataFifoSize 0 823#define W_RXDATAFIFO7__Rx15DataFifoSize 7 824#define R_XGMACPADCALIBRATION 0x231 825#define R_FREEQCARVE 0x233 826#define R_SPI4STATICDELAY0 0x240 827#define O_SPI4STATICDELAY0__DataLine7 28 828#define W_SPI4STATICDELAY0__DataLine7 4 829#define O_SPI4STATICDELAY0__DataLine6 24 830#define W_SPI4STATICDELAY0__DataLine6 4 831#define O_SPI4STATICDELAY0__DataLine5 20 832#define W_SPI4STATICDELAY0__DataLine5 4 833#define O_SPI4STATICDELAY0__DataLine4 16 834#define W_SPI4STATICDELAY0__DataLine4 4 835#define O_SPI4STATICDELAY0__DataLine3 12 836#define W_SPI4STATICDELAY0__DataLine3 4 837#define O_SPI4STATICDELAY0__DataLine2 8 838#define W_SPI4STATICDELAY0__DataLine2 4 839#define O_SPI4STATICDELAY0__DataLine1 4 840#define W_SPI4STATICDELAY0__DataLine1 4 841#define O_SPI4STATICDELAY0__DataLine0 0 842#define W_SPI4STATICDELAY0__DataLine0 4 843#define R_SPI4STATICDELAY1 0x241 844#define O_SPI4STATICDELAY1__DataLine15 28 845#define W_SPI4STATICDELAY1__DataLine15 4 846#define O_SPI4STATICDELAY1__DataLine14 24 847#define W_SPI4STATICDELAY1__DataLine14 4 848#define O_SPI4STATICDELAY1__DataLine13 20 849#define W_SPI4STATICDELAY1__DataLine13 4 850#define O_SPI4STATICDELAY1__DataLine12 16 851#define W_SPI4STATICDELAY1__DataLine12 4 852#define O_SPI4STATICDELAY1__DataLine11 12 853#define W_SPI4STATICDELAY1__DataLine11 4 854#define O_SPI4STATICDELAY1__DataLine10 8 855#define W_SPI4STATICDELAY1__DataLine10 4 856#define O_SPI4STATICDELAY1__DataLine9 4 857#define W_SPI4STATICDELAY1__DataLine9 4 858#define O_SPI4STATICDELAY1__DataLine8 0 859#define W_SPI4STATICDELAY1__DataLine8 4 860#define R_SPI4STATICDELAY2 0x242 861#define O_SPI4STATICDELAY0__TxStat1 8 862#define W_SPI4STATICDELAY0__TxStat1 4 863#define O_SPI4STATICDELAY0__TxStat0 4 864#define W_SPI4STATICDELAY0__TxStat0 4 865#define O_SPI4STATICDELAY0__RxControl 0 866#define W_SPI4STATICDELAY0__RxControl 4 867#define R_SPI4CONTROL 0x243 868#define O_SPI4CONTROL__StaticDelay 2 869#define O_SPI4CONTROL__LVDS_LVTTL 1 870#define O_SPI4CONTROL__SPI4Enable 0 871#define R_CLASSWATERMARKS 0x244 872#define O_CLASSWATERMARKS__Class0Watermark 24 873#define W_CLASSWATERMARKS__Class0Watermark 5 874#define O_CLASSWATERMARKS__Class1Watermark 16 875#define W_CLASSWATERMARKS__Class1Watermark 5 876#define O_CLASSWATERMARKS__Class3Watermark 0 877#define W_CLASSWATERMARKS__Class3Watermark 5 878#define R_RXWATERMARKS1 0x245 879#define O_RXWATERMARKS__Rx0DataWatermark 24 880#define W_RXWATERMARKS__Rx0DataWatermark 7 881#define O_RXWATERMARKS__Rx1DataWatermark 16 882#define W_RXWATERMARKS__Rx1DataWatermark 7 883#define O_RXWATERMARKS__Rx3DataWatermark 0 884#define W_RXWATERMARKS__Rx3DataWatermark 7 885#define R_RXWATERMARKS2 0x246 886#define O_RXWATERMARKS__Rx4DataWatermark 24 887#define W_RXWATERMARKS__Rx4DataWatermark 7 888#define O_RXWATERMARKS__Rx5DataWatermark 16 889#define W_RXWATERMARKS__Rx5DataWatermark 7 890#define O_RXWATERMARKS__Rx6DataWatermark 8 891#define W_RXWATERMARKS__Rx6DataWatermark 7 892#define O_RXWATERMARKS__Rx7DataWatermark 0 893#define W_RXWATERMARKS__Rx7DataWatermark 7 894#define R_RXWATERMARKS3 0x247 895#define O_RXWATERMARKS__Rx8DataWatermark 24 896#define W_RXWATERMARKS__Rx8DataWatermark 7 897#define O_RXWATERMARKS__Rx9DataWatermark 16 898#define W_RXWATERMARKS__Rx9DataWatermark 7 899#define O_RXWATERMARKS__Rx10DataWatermark 8 900#define W_RXWATERMARKS__Rx10DataWatermark 7 901#define O_RXWATERMARKS__Rx11DataWatermark 0 902#define W_RXWATERMARKS__Rx11DataWatermark 7 903#define R_RXWATERMARKS4 0x248 904#define O_RXWATERMARKS__Rx12DataWatermark 24 905#define W_RXWATERMARKS__Rx12DataWatermark 7 906#define O_RXWATERMARKS__Rx13DataWatermark 16 907#define W_RXWATERMARKS__Rx13DataWatermark 7 908#define O_RXWATERMARKS__Rx14DataWatermark 8 909#define W_RXWATERMARKS__Rx14DataWatermark 7 910#define O_RXWATERMARKS__Rx15DataWatermark 0 911#define W_RXWATERMARKS__Rx15DataWatermark 7 912#define R_FREEWATERMARKS 0x249 913#define O_FREEWATERMARKS__FreeOutWatermark 16 914#define W_FREEWATERMARKS__FreeOutWatermark 16 915#define O_FREEWATERMARKS__JumFrWatermark 8 916#define W_FREEWATERMARKS__JumFrWatermark 7 917#define O_FREEWATERMARKS__RegFrWatermark 0 918#define W_FREEWATERMARKS__RegFrWatermark 7 919#define R_EGRESSFIFOCARVINGSLOTS 0x24a 920 921#define CTRL_RES0 0 922#define CTRL_RES1 1 923#define CTRL_REG_FREE 2 924#define CTRL_JUMBO_FREE 3 925#define CTRL_CONT 4 926#define CTRL_EOP 5 927#define CTRL_START 6 928#define CTRL_SNGL 7 929 930#define CTRL_B0_NOT_EOP 0 931#define CTRL_B0_EOP 1 932 933#define R_ROUND_ROBIN_TABLE 0 934#define R_PDE_CLASS_0 0x300 935#define R_PDE_CLASS_1 0x302 936#define R_PDE_CLASS_2 0x304 937#define R_PDE_CLASS_3 0x306 938 939#define R_MSG_TX_THRESHOLD 0x308 940 941#define R_GMAC_JFR0_BUCKET_SIZE 0x320 942#define R_GMAC_RFR0_BUCKET_SIZE 0x321 943#define R_GMAC_TX0_BUCKET_SIZE 0x322 944#define R_GMAC_TX1_BUCKET_SIZE 0x323 945#define R_GMAC_TX2_BUCKET_SIZE 0x324 946#define R_GMAC_TX3_BUCKET_SIZE 0x325 947#define R_GMAC_JFR1_BUCKET_SIZE 0x326 948#define R_GMAC_RFR1_BUCKET_SIZE 0x327 949 950#define R_XGS_TX0_BUCKET_SIZE 0x320 951#define R_XGS_TX1_BUCKET_SIZE 0x321 952#define R_XGS_TX2_BUCKET_SIZE 0x322 953#define R_XGS_TX3_BUCKET_SIZE 0x323 954#define R_XGS_TX4_BUCKET_SIZE 0x324 955#define R_XGS_TX5_BUCKET_SIZE 0x325 956#define R_XGS_TX6_BUCKET_SIZE 0x326 957#define R_XGS_TX7_BUCKET_SIZE 0x327 958#define R_XGS_TX8_BUCKET_SIZE 0x328 959#define R_XGS_TX9_BUCKET_SIZE 0x329 960#define R_XGS_TX10_BUCKET_SIZE 0x32A 961#define R_XGS_TX11_BUCKET_SIZE 0x32B 962#define R_XGS_TX12_BUCKET_SIZE 0x32C 963#define R_XGS_TX13_BUCKET_SIZE 0x32D 964#define R_XGS_TX14_BUCKET_SIZE 0x32E 965#define R_XGS_TX15_BUCKET_SIZE 0x32F 966#define R_XGS_JFR_BUCKET_SIZE 0x330 967#define R_XGS_RFR_BUCKET_SIZE 0x331 968 969#define R_CC_CPU0_0 0x380 970#define R_CC_CPU1_0 0x388 971#define R_CC_CPU2_0 0x390 972#define R_CC_CPU3_0 0x398 973#define R_CC_CPU4_0 0x3a0 974#define R_CC_CPU5_0 0x3a8 975#define R_CC_CPU6_0 0x3b0 976#define R_CC_CPU7_0 0x3b8 977 978#define XLR_GMAC_BLK_SZ (XLR_IO_GMAC_1_OFFSET - \ 979 XLR_IO_GMAC_0_OFFSET) 980 981/* Constants used for configuring the devices */ 982 983#define RGE_TX_THRESHOLD 1024 984#define RGE_TX_Q_SIZE 1024 985 986#define MAC_B2B_IPG 88 987 988#define NLGE_PREPAD_LEN 32 989 990/* frame sizes need to be cacheline aligned */ 991#define MAX_FRAME_SIZE (1536 + NLGE_PREPAD_LEN) 992#define MAX_FRAME_SIZE_JUMBO 9216 993#define RGE_TX_THRESHOLD_BYTES ETHER_MAX_LEN 994 995#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES 996#define MAC_PREPAD 0 997#define BYTE_OFFSET 2 998#define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE + BYTE_OFFSET + \ 999 MAC_PREPAD + MAC_SKB_BACK_PTR_SIZE + SMP_CACHE_BYTES) 1000#define MAC_CRC_LEN 4 1001#define MAX_NUM_MSGRNG_STN_CC 128 1002#define MAX_MSG_SND_ATTEMPTS 100 /* 13 stns x 4 entry msg/stn + 1003 headroom */ 1004 1005#define MAC_FRIN_TO_BE_SENT_THRESHOLD 16 1006 1007#define MAX_NUM_DESC_SPILL 1024 1008#define MAX_FRIN_SPILL (MAX_NUM_DESC_SPILL << 2) 1009#define MAX_FROUT_SPILL (MAX_NUM_DESC_SPILL << 2) 1010#define MAX_CLASS_0_SPILL (MAX_NUM_DESC_SPILL << 2) 1011#define MAX_CLASS_1_SPILL (MAX_NUM_DESC_SPILL << 2) 1012#define MAX_CLASS_2_SPILL (MAX_NUM_DESC_SPILL << 2) 1013#define MAX_CLASS_3_SPILL (MAX_NUM_DESC_SPILL << 2) 1014 1015#define XLR_MAX_CORE 8 1016 1017#define XLR_MAX_NLNA 3 1018#define XLR_MAX_MACS 8 1019#define XLR_MAX_TX_FRAGS 14 1020#define MAX_P2D_DESC_PER_PORT 512 1021 1022#define PHY_STATUS_RETRIES 25000 1023 1024/* Structs representing hardware data structures */ 1025struct size_1_desc { 1026 uint64_t entry0; 1027}; 1028 1029struct size_2_desc { 1030 uint64_t entry0; 1031 uint64_t entry1; 1032}; 1033 1034struct size_3_desc { 1035 uint64_t entry0; 1036 uint64_t entry1; 1037 uint64_t entry2; 1038}; 1039 1040struct size_4_desc { 1041 uint64_t entry0; 1042 uint64_t entry1; 1043 uint64_t entry2; 1044 uint64_t entry3; 1045}; 1046 1047struct fr_desc { 1048 struct size_1_desc d1; 1049}; 1050 1051union rx_tx_desc { 1052 struct size_2_desc d2; 1053 /* struct size_3_desc d3; */ 1054 /* struct size_4_desc d4; */ 1055}; 1056 1057 1058extern unsigned char xlr_base_mac_addr[]; 1059 1060/* Driver data structures and enums */ 1061 1062typedef enum { 1063 xlr_mac_speed_10, xlr_mac_speed_100, 1064 xlr_mac_speed_1000, xlr_mac_speed_rsvd 1065} xlr_mac_speed_t; 1066 1067typedef enum { 1068 xlr_mac_duplex_auto, xlr_mac_duplex_half, 1069 xlr_mac_duplex_full 1070} xlr_mac_duplex_t; 1071 1072typedef enum { 1073 xlr_mac_link_down, 1074 xlr_mac_link_up, 1075} xlr_mac_link_t; 1076 1077typedef enum { 1078 xlr_mac_fc_auto, xlr_mac_fc_disabled, xlr_mac_fc_frame, 1079 xlr_mac_fc_collision, xlr_mac_fc_carrier 1080} xlr_mac_fc_t; 1081 1082enum { 1083 SGMII_SPEED_10 = 0x00000000, 1084 SGMII_SPEED_100 = 0x02000000, 1085 SGMII_SPEED_1000 = 0x04000000, 1086}; 1087 1088struct nlge_softc; 1089 1090/* 1091 * A data-structure to hold a set of related ports. The "sense" in which they 1092 * are related is defined by the user of this data-structure. 1093 * 1094 * One example: a set of ports that are controlled thru a single MDIO line. 1095 */ 1096struct nlge_port_set { 1097 struct nlge_softc **port_vec; 1098 uint32_t vec_sz; 1099}; 1100 1101/* 1102 * nlna_softc has Network Accelerator (NA) attributes that are necessary to 1103 * configure the h/w registers of this block. All the commmon configuration 1104 * for a set of GMAC ports controlled by an NA is done from here. 1105 */ 1106struct nlna_softc { 1107 device_t nlna_dev; 1108 1109 uint32_t num_ports; 1110 int na_type; 1111 int mac_type; 1112 xlr_reg_t *base; 1113 1114 struct fr_desc *frin_spill; 1115 struct fr_desc *frout_spill; 1116 union rx_tx_desc *class_0_spill; 1117 union rx_tx_desc *class_1_spill; 1118 union rx_tx_desc *class_2_spill; 1119 union rx_tx_desc *class_3_spill; 1120 uint32_t rfrbucket; 1121 uint32_t station_id; 1122 1123 struct nlge_softc *child_sc[XLR_MAX_MACS]; 1124 1125 /* 1126 * Set of ports controlled/configured by the MII line 1127 * of this network accelerator. 1128 */ 1129 struct nlge_port_set mdio_set; 1130 struct nlge_softc *mdio_sc[XLR_MAX_MACS]; 1131}; 1132 1133struct nlge_softc { 1134 struct ifnet *nlge_if; /* should be first member - cf. 1135 mii.c:miibus_attach() */ 1136 struct mii_data nlge_mii; 1137 struct nlge_port_set *mdio_pset; 1138 device_t nlge_dev; 1139 device_t mii_bus; 1140 xlr_reg_t *base; 1141 xlr_reg_t *mii_base; 1142 xlr_reg_t *pcs_addr; 1143 xlr_reg_t *serdes_addr; 1144 int port_type; 1145 int if_flags; 1146 xlr_mac_speed_t speed; 1147 xlr_mac_duplex_t duplex; 1148 xlr_mac_link_t link; 1149 xlr_mac_fc_t flow_ctrl; 1150 uint32_t id; 1151 uint32_t instance; 1152 uint32_t phy_addr; 1153 uint32_t tx_bucket_id; 1154 uint8_t dev_addr[ETHER_ADDR_LEN]; 1155 struct mtx sc_lock; 1156}; 1157 1158 1159struct nlge_tx_desc { 1160 uint64_t frag[XLR_MAX_TX_FRAGS + 2]; 1161}; 1162 1163#define MAX_TX_RING_SIZE (XLR_MAX_MACS * MAX_P2D_DESC_PER_PORT *\ 1164 sizeof(struct p2d_tx_desc)) 1165 1166#define NLGE_WRITE(base, off, val) xlr_write_reg(base, off, val) 1167#define NLGE_READ(base, off) xlr_read_reg(base, off) 1168#define NLGE_UPDATE(base, off, val, mask) \ 1169 do { \ 1170 uint32_t rd_val, wrt_val; \ 1171 rd_val = NLGE_READ(base, off); \ 1172 wrt_val = (rd_val & ~mask) | (val & mask); \ 1173 NLGE_WRITE(base, off, wrt_val); \ 1174 } while (0) 1175 1176#define NLGE_LOCK_INIT(_sc, _name) \ 1177 mtx_init(&(_sc)->sc_lock, _name, MTX_NETWORK_LOCK, MTX_DEF) 1178#define NLGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) 1179#define NLGE_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) 1180#define NLGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) 1181#define NLGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED) 1182 1183