1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD 29 * $FreeBSD$ 30 */ 31 32#ifndef __NLM_FMNV2_H__ 33#define __NLM_FMNV2_H__ 34 35/** 36* @file_name fmn.h 37* @author Netlogic Microsystems 38* @brief HAL for Fast message network V2 39*/ 40 41/* FMN configuration registers */ 42#define CMS_OUTPUTQ_CONFIG(i) ((i)*2) 43#define CMS_MAX_OUTPUTQ 1024 44#define CMS_OUTPUTQ_CREDIT_CFG (0x2000/4) 45#define CMS_MSG_CONFIG (0x2008/4) 46#define CMS_MSG_ERR (0x2010/4) 47#define CMS_TRACE_CONFIG (0x2018/4) 48#define CMS_TRACE_BASE_ADDR (0x2020/4) 49#define CMS_TRACE_LIMIT_ADDR (0x2028/4) 50#define CMS_TRACE_CURRENT_ADDR (0x2030/4) 51#define CMS_MSG_ENDIAN_SWAP (0x2038/4) 52 53#define CMS_CPU_PUSHQ(node, core, thread, vc) \ 54 (((node)<<10) | ((core)<<4) | ((thread)<<2) | ((vc)<<0)) 55#define CMS_POPQ(node, queue) (((node)<<10) | (queue)) 56#define CMS_IO_PUSHQ(node, queue) (((node)<<10) | (queue)) 57 58#define CMS_POPQ_QID(i) (128+(i)) 59 60/* FMN Level Interrupt Type */ 61#define CMS_LVL_INTR_DISABLE 0 62#define CMS_LVL_LOW_WATERMARK 1 63#define CMS_LVL_HI_WATERMARK 2 64 65/* FMN Level interrupt trigger values */ 66#define CMS_QUEUE_NON_EMPTY 0 67#define CMS_QUEUE_QUARTER_FULL 1 68#define CMS_QUEUE_HALF_FULL 2 69#define CMS_QUEUE_THREE_QUARTER_FULL 3 70#define CMS_QUEUE_FULL 4 71 72/* FMN Timer Interrupt Type */ 73#define CMS_TIMER_INTR_DISABLE 0 74#define CMS_TIMER_CONSUMER 1 75#define CMS_TIMER_PRODUCER 1 76 77/* FMN timer interrupt trigger values */ 78#define CMS_TWO_POW_EIGHT_CYCLES 0 79#define CMS_TWO_POW_TEN_CYCLES 1 80#define CMS_TWO_POW_TWELVE_CYCLES 2 81#define CMS_TWO_POW_FOURTEEN_CYCLES 3 82#define CMS_TWO_POW_SIXTEEN_CYCLES 4 83#define CMS_TWO_POW_EIGHTTEEN_CYCLES 5 84#define CMS_TWO_POW_TWENTY_CYCLES 6 85#define CMS_TWO_POW_TWENTYTWO_CYCLES 7 86 87#define CMS_QUEUE_ENA 1ULL 88#define CMS_QUEUE_DIS 0 89#define CMS_SPILL_ENA 1ULL 90#define CMS_SPILL_DIS 0 91 92#define CMS_MAX_VCPU_VC 4 93 94/* Each XLP chip can hold upto 32K messages on the chip itself */ 95#define CMS_ON_CHIP_MESG_SPACE (32*1024) 96#define CMS_MAX_ONCHIP_SEGMENTS 1024 97#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64 98 99/* FMN Network error */ 100#define CMS_ILLEGAL_DST_ERROR 0x100 101#define CMS_BIU_TIMEOUT_ERROR 0x080 102#define CMS_BIU_ERROR 0x040 103#define CMS_SPILL_FILL_UNCORRECT_ECC_ERROR 0x020 104#define CMS_SPILL_FILL_CORRECT_ECC_ERROR 0x010 105#define CMS_SPILL_UNCORRECT_ECC_ERROR 0x008 106#define CMS_SPILL_CORRECT_ECC_ERROR 0x004 107#define CMS_OUTPUTQ_UNCORRECT_ECC_ERROR 0x002 108#define CMS_OUTPUTQ_CORRECT_ECC_ERROR 0x001 109 110/* worst case, a single entry message consists of a 4 byte header 111 * and an 8-byte entry = 12 bytes in total 112 */ 113#define CMS_SINGLE_ENTRY_MSG_SIZE 12 114/* total spill memory needed for one FMN queue */ 115#define CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs) \ 116 ((spilltotmsgs) * (CMS_SINGLE_ENTRY_MSG_SIZE)) 117 118/* FMN Src station id's */ 119#define CMS_CPU0_SRC_STID (0 << 4) 120#define CMS_CPU1_SRC_STID (1 << 4) 121#define CMS_CPU2_SRC_STID (2 << 4) 122#define CMS_CPU3_SRC_STID (3 << 4) 123#define CMS_CPU4_SRC_STID (4 << 4) 124#define CMS_CPU5_SRC_STID (5 << 4) 125#define CMS_CPU6_SRC_STID (6 << 4) 126#define CMS_CPU7_SRC_STID (7 << 4) 127#define CMS_PCIE0_SRC_STID 256 128#define CMS_PCIE1_SRC_STID 258 129#define CMS_PCIE2_SRC_STID 260 130#define CMS_PCIE3_SRC_STID 262 131#define CMS_DTE_SRC_STID 264 132#define CMS_RSA_ECC_SRC_STID 272 133#define CMS_CRYPTO_SRC_STID 281 134#define CMS_CMP_SRC_STID 298 135#define CMS_POE_SRC_STID 384 136#define CMS_NAE_SRC_STID 476 137 138/* POPQ related defines */ 139#define CMS_POPQID_START 128 140#define CMS_POPQID_END 255 141 142#define CMS_INT_RCVD 0x800000000000000ULL 143 144#define nlm_read_cms_reg(b, r) nlm_read_reg64_xkphys(b,r) 145#define nlm_write_cms_reg(b, r, v) nlm_write_reg64_xkphys(b,r,v) 146#define nlm_get_cms_pcibase(node) \ 147 nlm_pcicfg_base(XLP_IO_CMS_OFFSET(node)) 148#define nlm_get_cms_regbase(node) \ 149 nlm_xkphys_map_pcibar0(nlm_get_cms_pcibase(node)) 150 151#define XLP_CMS_ON_CHIP_PER_QUEUE_SPACE(node) \ 152 ((XLP_CMS_ON_CHIP_MESG_SPACE)/ \ 153 (nlm_read_reg(nlm_pcibase_cms(node), \ 154 XLP_PCI_DEVINFO_REG0)) 155/* total spill memory needed */ 156#define XLP_CMS_TOTAL_SPILL_MEM(node, spilltotmsgs) \ 157 ((XLP_CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs)) * \ 158 (nlm_read_reg(nlm_pcibase_cms(node), \ 159 XLP_PCI_DEVINFO_REG0)) 160#define CMS_TOTAL_QUEUE_SIZE(node, spilltotmsgs) \ 161 ((spilltotmsgs) + (CMS_ON_CHIP_PER_QUEUE_SPACE(node))) 162 163enum fmn_swcode { 164 FMN_SWCODE_CPU0=1, 165 FMN_SWCODE_CPU1, 166 FMN_SWCODE_CPU2, 167 FMN_SWCODE_CPU3, 168 FMN_SWCODE_CPU4, 169 FMN_SWCODE_CPU5, 170 FMN_SWCODE_CPU6, 171 FMN_SWCODE_CPU7, 172 FMN_SWCODE_CPU8, 173 FMN_SWCODE_CPU9, 174 FMN_SWCODE_CPU10, 175 FMN_SWCODE_CPU11, 176 FMN_SWCODE_CPU12, 177 FMN_SWCODE_CPU13, 178 FMN_SWCODE_CPU14, 179 FMN_SWCODE_CPU15, 180 FMN_SWCODE_CPU16, 181 FMN_SWCODE_CPU17, 182 FMN_SWCODE_CPU18, 183 FMN_SWCODE_CPU19, 184 FMN_SWCODE_CPU20, 185 FMN_SWCODE_CPU21, 186 FMN_SWCODE_CPU22, 187 FMN_SWCODE_CPU23, 188 FMN_SWCODE_CPU24, 189 FMN_SWCODE_CPU25, 190 FMN_SWCODE_CPU26, 191 FMN_SWCODE_CPU27, 192 FMN_SWCODE_CPU28, 193 FMN_SWCODE_CPU29, 194 FMN_SWCODE_CPU30, 195 FMN_SWCODE_CPU31, 196 FMN_SWCODE_CPU32, 197 FMN_SWCODE_PCIE0, 198 FMN_SWCODE_PCIE1, 199 FMN_SWCODE_PCIE2, 200 FMN_SWCODE_PCIE3, 201 FMN_SWCODE_DTE, 202 FMN_SWCODE_CRYPTO, 203 FMN_SWCODE_RSA, 204 FMN_SWCODE_CMP, 205 FMN_SWCODE_POE, 206 FMN_SWCODE_NAE, 207}; 208 209extern uint64_t nlm_cms_spill_total_messages; 210extern uint32_t nlm_cms_total_stations; 211 212extern uint64_t cms_base_addr(int node); 213extern int nlm_cms_verify_credit_config (int spill_en, int tot_credit); 214extern int nlm_cms_get_oc_space(int qsize, int max_queues, int qid, int *ocbase, int *ocstart, int *ocend); 215extern void nlm_cms_setup_credits (uint64_t base, int destid, int srcid, int credit); 216extern int nlm_cms_config_onchip_queue (uint64_t base, uint64_t cms_spill_base, int qid, int spill_en); 217extern void nlm_cms_default_setup(int node, uint64_t spill_base, int spill_en, int popq_en); 218extern uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid); 219extern void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val); 220extern void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type, int intr_val); 221extern void nlm_cms_level_intr(int node, int sub_type, int intr_val); 222extern void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type, int intr_val); 223extern void nlm_cms_timer_intr(int node, int en, int sub_type, int intr_val); 224extern int nlm_cms_outputq_intr_check(uint64_t base, int qid); 225extern void nlm_cms_outputq_clr_intr(uint64_t base, int qid); 226extern void nlm_cms_illegal_dst_error_intr(uint64_t base, int en); 227extern void nlm_cms_timeout_error_intr(uint64_t base, int en); 228extern void nlm_cms_biu_error_resp_intr(uint64_t base, int en); 229extern void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en); 230extern void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en); 231extern void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en); 232extern void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en); 233extern uint64_t nlm_cms_network_error_status(uint64_t base); 234extern int nlm_cms_get_net_error_code(uint64_t err); 235extern int nlm_cms_get_net_error_syndrome(uint64_t err); 236extern int nlm_cms_get_net_error_ramindex(uint64_t err); 237extern int nlm_cms_get_net_error_outputq(uint64_t err); 238extern void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base, uint64_t trace_limit, int match_dstid_en, int dst_id, int match_srcid_en, int src_id, int wrap); 239extern void nlm_cms_endian_byte_swap (uint64_t base, int en); 240extern uint8_t xlp_msg_send(uint8_t vc, uint8_t size); 241extern int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base, 242 int nsegs); 243extern int nlm_cms_alloc_onchip_q(uint64_t base, int qid, int nsegs); 244 245#endif 246