1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/cons.h> 38#include <sys/kdb.h> 39#include <sys/reboot.h> 40 41#include <vm/vm.h> 42#include <vm/vm_page.h> 43 44#include <net/ethernet.h> 45 46#include <machine/clock.h> 47#include <machine/cpu.h> 48#include <machine/cpuregs.h> 49#include <machine/hwfunc.h> 50#include <machine/md_var.h> 51#include <machine/trap.h> 52#include <machine/vmparam.h> 53 54#include <mips/atheros/ar71xxreg.h> 55#include <mips/atheros/ar71xx_cpudef.h> 56#include <mips/atheros/ar71xx_chip.h> 57#include <mips/atheros/ar91xxreg.h> 58#include <mips/atheros/ar91xx_chip.h> 59 60#include <mips/sentry5/s5reg.h> 61 62static void 63ar91xx_chip_detect_mem_size(void) 64{ 65} 66 67static void 68ar91xx_chip_detect_sys_frequency(void) 69{ 70 uint32_t pll; 71 uint32_t freq; 72 uint32_t div; 73 74 u_ar71xx_refclk = AR91XX_BASE_FREQ; 75 76 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG); 77 78 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); 79 freq = div * AR91XX_BASE_FREQ; 80 u_ar71xx_cpu_freq = freq; 81 82 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; 83 u_ar71xx_ddr_freq = freq / div; 84 85 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; 86 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; 87 u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div; 88 u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div; 89} 90 91static void 92ar91xx_chip_device_stop(uint32_t mask) 93{ 94 uint32_t reg; 95 96 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); 97 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask); 98} 99 100static void 101ar91xx_chip_device_start(uint32_t mask) 102{ 103 uint32_t reg; 104 105 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); 106 ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask); 107} 108 109static int 110ar91xx_chip_device_stopped(uint32_t mask) 111{ 112 uint32_t reg; 113 114 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); 115 return ((reg & mask) == mask); 116} 117 118static void 119ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) 120{ 121 122 switch (unit) { 123 case 0: 124 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG, 125 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, 126 AR91XX_ETH0_PLL_SHIFT); 127 break; 128 case 1: 129 ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG, 130 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, 131 AR91XX_ETH1_PLL_SHIFT); 132 break; 133 default: 134 printf("%s: invalid PLL set for arge unit: %d\n", 135 __func__, unit); 136 return; 137 } 138} 139 140static void 141ar91xx_chip_ddr_flush_ge(int unit) 142{ 143 144 switch (unit) { 145 case 0: 146 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); 147 break; 148 case 1: 149 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); 150 break; 151 default: 152 printf("%s: invalid DDR flush for arge unit: %d\n", 153 __func__, unit); 154 return; 155 } 156} 157 158static void 159ar91xx_chip_ddr_flush_ip2(void) 160{ 161 162 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC); 163} 164 165 166static uint32_t 167ar91xx_chip_get_eth_pll(unsigned int mac, int speed) 168{ 169 uint32_t pll; 170 171 switch(speed) { 172 case 10: 173 pll = AR91XX_PLL_VAL_10; 174 break; 175 case 100: 176 pll = AR91XX_PLL_VAL_100; 177 break; 178 case 1000: 179 pll = AR91XX_PLL_VAL_1000; 180 break; 181 default: 182 printf("%s%d: invalid speed %d\n", __func__, mac, speed); 183 pll = 0; 184 } 185 186 return (pll); 187} 188 189static void 190ar91xx_chip_init_usb_peripheral(void) 191{ 192 193 ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE); 194 DELAY(100); 195 196 ar71xx_device_start(RST_RESET_USB_HOST); 197 DELAY(100); 198 199 ar71xx_device_start(RST_RESET_USB_PHY); 200 DELAY(100); 201 202 /* Wireless */ 203 ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC); 204 DELAY(1000); 205 206 ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC); 207 DELAY(1000); 208} 209 210struct ar71xx_cpu_def ar91xx_chip_def = { 211 &ar91xx_chip_detect_mem_size, 212 &ar91xx_chip_detect_sys_frequency, 213 &ar91xx_chip_device_stop, 214 &ar91xx_chip_device_start, 215 &ar91xx_chip_device_stopped, 216 &ar91xx_chip_set_pll_ge, 217 &ar71xx_chip_set_mii_speed, 218 &ar71xx_chip_set_mii_if, 219 &ar91xx_chip_ddr_flush_ge, 220 &ar91xx_chip_get_eth_pll, 221 &ar91xx_chip_ddr_flush_ip2, 222 &ar91xx_chip_init_usb_peripheral, 223}; 224