1/* $FreeBSD: stable/10/sys/dev/usb/controller/xhci.c 360335 2020-04-26 08:38:10Z hselasky $ */ 2/*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36/* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43#ifdef USB_GLOBAL_INCLUDE_FILE 44#include USB_GLOBAL_INCLUDE_FILE 45#else 46#include <sys/stdint.h> 47#include <sys/stddef.h> 48#include <sys/param.h> 49#include <sys/queue.h> 50#include <sys/types.h> 51#include <sys/systm.h> 52#include <sys/kernel.h> 53#include <sys/bus.h> 54#include <sys/module.h> 55#include <sys/lock.h> 56#include <sys/mutex.h> 57#include <sys/condvar.h> 58#include <sys/sysctl.h> 59#include <sys/sx.h> 60#include <sys/unistd.h> 61#include <sys/callout.h> 62#include <sys/malloc.h> 63#include <sys/priv.h> 64 65#include <dev/usb/usb.h> 66#include <dev/usb/usbdi.h> 67 68#define USB_DEBUG_VAR xhcidebug 69 70#include <dev/usb/usb_core.h> 71#include <dev/usb/usb_debug.h> 72#include <dev/usb/usb_busdma.h> 73#include <dev/usb/usb_process.h> 74#include <dev/usb/usb_transfer.h> 75#include <dev/usb/usb_device.h> 76#include <dev/usb/usb_hub.h> 77#include <dev/usb/usb_util.h> 78 79#include <dev/usb/usb_controller.h> 80#include <dev/usb/usb_bus.h> 81#endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83#include <dev/usb/controller/xhci.h> 84#include <dev/usb/controller/xhcireg.h> 85 86#define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92static int xhcistreams; 93SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 96 97#ifdef USB_DEBUG 98static int xhcidebug; 99static int xhciroute; 100static int xhcipolling; 101static int xhcidma32; 102static int xhcictlstep; 103 104SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 105 &xhcidebug, 0, "Debug level"); 106TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 107SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 108 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 109TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 110SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 111 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 112TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 113SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 114 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 115TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32); 116SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, 117 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); 118TUNABLE_INT("hw.usb.xhci.ctlstep", &xhcictlstep); 119#else 120#define xhciroute 0 121#define xhcidma32 0 122#define xhcictlstep 0 123#endif 124 125#define XHCI_INTR_ENDPT 1 126 127struct xhci_std_temp { 128 struct xhci_softc *sc; 129 struct usb_page_cache *pc; 130 struct xhci_td *td; 131 struct xhci_td *td_next; 132 uint32_t len; 133 uint32_t offset; 134 uint32_t max_packet_size; 135 uint32_t average; 136 uint16_t isoc_delta; 137 uint16_t isoc_frame; 138 uint8_t shortpkt; 139 uint8_t multishort; 140 uint8_t last_frame; 141 uint8_t trb_type; 142 uint8_t direction; 143 uint8_t tbc; 144 uint8_t tlbpc; 145 uint8_t step_td; 146 uint8_t do_isoc_sync; 147}; 148 149static void xhci_do_poll(struct usb_bus *); 150static void xhci_device_done(struct usb_xfer *, usb_error_t); 151static void xhci_root_intr(struct xhci_softc *); 152static void xhci_free_device_ext(struct usb_device *); 153static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 154 struct usb_endpoint_descriptor *); 155static usb_proc_callback_t xhci_configure_msg; 156static usb_error_t xhci_configure_device(struct usb_device *); 157static usb_error_t xhci_configure_endpoint(struct usb_device *, 158 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 159 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 160 uint8_t); 161static usb_error_t xhci_configure_mask(struct usb_device *, 162 uint32_t, uint8_t); 163static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 164 uint64_t, uint8_t); 165static void xhci_endpoint_doorbell(struct usb_xfer *); 166static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 167static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 168static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 169#ifdef USB_DEBUG 170static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 171#endif 172 173extern struct usb_bus_methods xhci_bus_methods; 174 175#ifdef USB_DEBUG 176static void 177xhci_dump_trb(struct xhci_trb *trb) 178{ 179 DPRINTFN(5, "trb = %p\n", trb); 180 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 181 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 182 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 183} 184 185static void 186xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 187{ 188 DPRINTFN(5, "pep = %p\n", pep); 189 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 190 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 191 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 192 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 193 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 194 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 195 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 196} 197 198static void 199xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 200{ 201 DPRINTFN(5, "psl = %p\n", psl); 202 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 203 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 204 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 205 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 206} 207#endif 208 209uint8_t 210xhci_use_polling(void) 211{ 212#ifdef USB_DEBUG 213 return (xhcipolling != 0); 214#else 215 return (0); 216#endif 217} 218 219static void 220xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 221{ 222 struct xhci_softc *sc = XHCI_BUS2SC(bus); 223 uint16_t i; 224 225 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 226 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 227 228 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 229 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 230 231 for (i = 0; i != sc->sc_noscratch; i++) { 232 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 233 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 234 } 235} 236 237static void 238xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 239{ 240 if (sc->sc_ctx_is_64_byte) { 241 uint32_t offset; 242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 243 /* all contexts are initially 32-bytes */ 244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 245 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 246 } 247 *ptr = htole32(val); 248} 249 250static uint32_t 251xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 252{ 253 if (sc->sc_ctx_is_64_byte) { 254 uint32_t offset; 255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 256 /* all contexts are initially 32-bytes */ 257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 258 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 259 } 260 return (le32toh(*ptr)); 261} 262 263static void 264xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 265{ 266 if (sc->sc_ctx_is_64_byte) { 267 uint32_t offset; 268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 269 /* all contexts are initially 32-bytes */ 270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 272 } 273 *ptr = htole64(val); 274} 275 276#ifdef USB_DEBUG 277static uint64_t 278xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 279{ 280 if (sc->sc_ctx_is_64_byte) { 281 uint32_t offset; 282 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 283 /* all contexts are initially 32-bytes */ 284 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 285 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 286 } 287 return (le64toh(*ptr)); 288} 289#endif 290 291static int 292xhci_reset_command_queue_locked(struct xhci_softc *sc) 293{ 294 struct usb_page_search buf_res; 295 struct xhci_hw_root *phwr; 296 uint64_t addr; 297 uint32_t temp; 298 299 DPRINTF("\n"); 300 301 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 302 if (temp & XHCI_CRCR_LO_CRR) { 303 DPRINTF("Command ring running\n"); 304 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 305 306 /* 307 * Try to abort the last command as per section 308 * 4.6.1.2 "Aborting a Command" of the XHCI 309 * specification: 310 */ 311 312 /* stop and cancel */ 313 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 314 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 315 316 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 317 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 318 319 /* wait 250ms */ 320 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 321 322 /* check if command ring is still running */ 323 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 324 if (temp & XHCI_CRCR_LO_CRR) { 325 DPRINTF("Comand ring still running\n"); 326 return (USB_ERR_IOERROR); 327 } 328 } 329 330 /* reset command ring */ 331 sc->sc_command_ccs = 1; 332 sc->sc_command_idx = 0; 333 334 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 335 336 /* set up command ring control base address */ 337 addr = buf_res.physaddr; 338 phwr = buf_res.buffer; 339 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 340 341 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 342 343 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 344 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 345 346 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 347 348 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 349 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 350 351 return (0); 352} 353 354usb_error_t 355xhci_start_controller(struct xhci_softc *sc) 356{ 357 struct usb_page_search buf_res; 358 struct xhci_hw_root *phwr; 359 struct xhci_dev_ctx_addr *pdctxa; 360 usb_error_t err; 361 uint64_t addr; 362 uint32_t temp; 363 uint16_t i; 364 365 DPRINTF("\n"); 366 367 sc->sc_event_ccs = 1; 368 sc->sc_event_idx = 0; 369 sc->sc_command_ccs = 1; 370 sc->sc_command_idx = 0; 371 372 err = xhci_reset_controller(sc); 373 if (err) 374 return (err); 375 376 /* set up number of device slots */ 377 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 378 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 379 380 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 381 382 temp = XREAD4(sc, oper, XHCI_USBSTS); 383 384 /* clear interrupts */ 385 XWRITE4(sc, oper, XHCI_USBSTS, temp); 386 /* disable all device notifications */ 387 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 388 389 /* set up device context base address */ 390 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 391 pdctxa = buf_res.buffer; 392 memset(pdctxa, 0, sizeof(*pdctxa)); 393 394 addr = buf_res.physaddr; 395 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 396 397 /* slot 0 points to the table of scratchpad pointers */ 398 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 399 400 for (i = 0; i != sc->sc_noscratch; i++) { 401 struct usb_page_search buf_scp; 402 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 403 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 404 } 405 406 addr = buf_res.physaddr; 407 408 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 409 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 410 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 411 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 412 413 /* set up event table size */ 414 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 415 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 416 417 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 418 419 /* set up interrupt rate */ 420 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 421 422 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 423 424 phwr = buf_res.buffer; 425 addr = buf_res.physaddr; 426 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 427 428 /* reset hardware root structure */ 429 memset(phwr, 0, sizeof(*phwr)); 430 431 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 432 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 433 434 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 435 436 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 437 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 438 439 addr = buf_res.physaddr; 440 441 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 442 443 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 444 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 445 446 /* set up interrupter registers */ 447 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 448 temp |= XHCI_IMAN_INTR_ENA; 449 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 450 451 /* set up command ring control base address */ 452 addr = buf_res.physaddr; 453 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 454 455 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 456 457 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 458 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 459 460 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 461 462 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 463 464 /* Go! */ 465 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 466 XHCI_CMD_INTE | XHCI_CMD_HSEE); 467 468 for (i = 0; i != 100; i++) { 469 usb_pause_mtx(NULL, hz / 100); 470 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 471 if (!temp) 472 break; 473 } 474 if (temp) { 475 XWRITE4(sc, oper, XHCI_USBCMD, 0); 476 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 477 return (USB_ERR_IOERROR); 478 } 479 480 /* catch any lost interrupts */ 481 xhci_do_poll(&sc->sc_bus); 482 483 if (sc->sc_port_route != NULL) { 484 /* Route all ports to the XHCI by default */ 485 sc->sc_port_route(sc->sc_bus.parent, 486 ~xhciroute, xhciroute); 487 } 488 return (0); 489} 490 491usb_error_t 492xhci_halt_controller(struct xhci_softc *sc) 493{ 494 uint32_t temp; 495 uint16_t i; 496 497 DPRINTF("\n"); 498 499 sc->sc_capa_off = 0; 500 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 501 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 502 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 503 504 /* Halt controller */ 505 XWRITE4(sc, oper, XHCI_USBCMD, 0); 506 507 for (i = 0; i != 100; i++) { 508 usb_pause_mtx(NULL, hz / 100); 509 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 510 if (temp) 511 break; 512 } 513 514 if (!temp) { 515 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 516 return (USB_ERR_IOERROR); 517 } 518 return (0); 519} 520 521usb_error_t 522xhci_reset_controller(struct xhci_softc *sc) 523{ 524 uint32_t temp = 0; 525 uint16_t i; 526 527 DPRINTF("\n"); 528 529 /* Reset controller */ 530 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 531 532 for (i = 0; i != 100; i++) { 533 usb_pause_mtx(NULL, hz / 100); 534 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 535 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 536 if (!temp) 537 break; 538 } 539 540 if (temp) { 541 device_printf(sc->sc_bus.parent, "Controller " 542 "reset timeout.\n"); 543 return (USB_ERR_IOERROR); 544 } 545 return (0); 546} 547 548usb_error_t 549xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 550{ 551 uint32_t temp; 552 553 DPRINTF("\n"); 554 555 /* initialize some bus fields */ 556 sc->sc_bus.parent = self; 557 558 /* set the bus revision */ 559 sc->sc_bus.usbrev = USB_REV_3_0; 560 561 /* set up the bus struct */ 562 sc->sc_bus.methods = &xhci_bus_methods; 563 564 /* set up devices array */ 565 sc->sc_bus.devices = sc->sc_devices; 566 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 567 568 /* set default cycle state in case of early interrupts */ 569 sc->sc_event_ccs = 1; 570 sc->sc_command_ccs = 1; 571 572 /* set up bus space offsets */ 573 sc->sc_capa_off = 0; 574 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 575 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 576 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 577 578 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 579 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 580 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 581 582 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 583 584 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 585 device_printf(sc->sc_bus.parent, "Controller does " 586 "not support 4K page size.\n"); 587 return (ENXIO); 588 } 589 590 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 591 592 DPRINTF("HCS0 = 0x%08x\n", temp); 593 594 /* set up context size */ 595 if (XHCI_HCS0_CSZ(temp)) { 596 sc->sc_ctx_is_64_byte = 1; 597 } else { 598 sc->sc_ctx_is_64_byte = 0; 599 } 600 601 /* get DMA bits */ 602 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 603 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 604 605 device_printf(self, "%d bytes context size, %d-bit DMA\n", 606 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 607 608 /* enable 64Kbyte control endpoint quirk */ 609 sc->sc_bus.control_ep_quirk = 1; 610 611 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 612 613 /* get number of device slots */ 614 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 615 616 if (sc->sc_noport == 0) { 617 device_printf(sc->sc_bus.parent, "Invalid number " 618 "of ports: %u\n", sc->sc_noport); 619 return (ENXIO); 620 } 621 622 sc->sc_noport = sc->sc_noport; 623 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 624 625 DPRINTF("Max slots: %u\n", sc->sc_noslot); 626 627 if (sc->sc_noslot > XHCI_MAX_DEVICES) 628 sc->sc_noslot = XHCI_MAX_DEVICES; 629 630 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 631 632 DPRINTF("HCS2=0x%08x\n", temp); 633 634 /* get number of scratchpads */ 635 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 636 637 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 638 device_printf(sc->sc_bus.parent, "XHCI request " 639 "too many scratchpads\n"); 640 return (ENOMEM); 641 } 642 643 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 644 645 /* get event table size */ 646 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 647 if (sc->sc_erst_max > XHCI_MAX_RSEG) 648 sc->sc_erst_max = XHCI_MAX_RSEG; 649 650 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 651 652 /* get maximum exit latency */ 653 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 654 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 655 656 /* Check if we should use the default IMOD value. */ 657 if (sc->sc_imod_default == 0) 658 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 659 660 /* get all DMA memory */ 661 if (usb_bus_mem_alloc_all(&sc->sc_bus, 662 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 663 return (ENOMEM); 664 } 665 666 /* set up command queue mutex and condition varible */ 667 cv_init(&sc->sc_cmd_cv, "CMDQ"); 668 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 669 670 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 671 sc->sc_config_msg[0].bus = &sc->sc_bus; 672 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 673 sc->sc_config_msg[1].bus = &sc->sc_bus; 674 675 return (0); 676} 677 678void 679xhci_uninit(struct xhci_softc *sc) 680{ 681 /* 682 * NOTE: At this point the control transfer process is gone 683 * and "xhci_configure_msg" is no longer called. Consequently 684 * waiting for the configuration messages to complete is not 685 * needed. 686 */ 687 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 688 689 cv_destroy(&sc->sc_cmd_cv); 690 sx_destroy(&sc->sc_cmd_sx); 691} 692 693static void 694xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 695{ 696 struct xhci_softc *sc = XHCI_BUS2SC(bus); 697 698 switch (state) { 699 case USB_HW_POWER_SUSPEND: 700 DPRINTF("Stopping the XHCI\n"); 701 xhci_halt_controller(sc); 702 xhci_reset_controller(sc); 703 break; 704 case USB_HW_POWER_SHUTDOWN: 705 DPRINTF("Stopping the XHCI\n"); 706 xhci_halt_controller(sc); 707 xhci_reset_controller(sc); 708 break; 709 case USB_HW_POWER_RESUME: 710 DPRINTF("Starting the XHCI\n"); 711 xhci_start_controller(sc); 712 break; 713 default: 714 break; 715 } 716} 717 718static usb_error_t 719xhci_generic_done_sub(struct usb_xfer *xfer) 720{ 721 struct xhci_td *td; 722 struct xhci_td *td_alt_next; 723 uint32_t len; 724 uint8_t status; 725 726 td = xfer->td_transfer_cache; 727 td_alt_next = td->alt_next; 728 729 if (xfer->aframes != xfer->nframes) 730 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 731 732 while (1) { 733 734 usb_pc_cpu_invalidate(td->page_cache); 735 736 status = td->status; 737 len = td->remainder; 738 739 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 740 xfer, (unsigned int)xfer->aframes, 741 (unsigned int)xfer->nframes, 742 (unsigned int)len, (unsigned int)td->len, 743 (unsigned int)status); 744 745 /* 746 * Verify the status length and 747 * add the length to "frlengths[]": 748 */ 749 if (len > td->len) { 750 /* should not happen */ 751 DPRINTF("Invalid status length, " 752 "0x%04x/0x%04x bytes\n", len, td->len); 753 status = XHCI_TRB_ERROR_LENGTH; 754 } else if (xfer->aframes != xfer->nframes) { 755 xfer->frlengths[xfer->aframes] += td->len - len; 756 } 757 /* Check for last transfer */ 758 if (((void *)td) == xfer->td_transfer_last) { 759 td = NULL; 760 break; 761 } 762 /* Check for transfer error */ 763 if (status != XHCI_TRB_ERROR_SHORT_PKT && 764 status != XHCI_TRB_ERROR_SUCCESS) { 765 /* the transfer is finished */ 766 td = NULL; 767 break; 768 } 769 /* Check for short transfer */ 770 if (len > 0) { 771 if (xfer->flags_int.short_frames_ok || 772 xfer->flags_int.isochronous_xfr || 773 xfer->flags_int.control_xfr) { 774 /* follow alt next */ 775 td = td->alt_next; 776 } else { 777 /* the transfer is finished */ 778 td = NULL; 779 } 780 break; 781 } 782 td = td->obj_next; 783 784 if (td->alt_next != td_alt_next) { 785 /* this USB frame is complete */ 786 break; 787 } 788 } 789 790 /* update transfer cache */ 791 792 xfer->td_transfer_cache = td; 793 794 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 795 (status != XHCI_TRB_ERROR_SHORT_PKT && 796 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 797 USB_ERR_NORMAL_COMPLETION); 798} 799 800static void 801xhci_generic_done(struct usb_xfer *xfer) 802{ 803 usb_error_t err = 0; 804 805 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 806 xfer, xfer->endpoint); 807 808 /* reset scanner */ 809 810 xfer->td_transfer_cache = xfer->td_transfer_first; 811 812 if (xfer->flags_int.control_xfr) { 813 814 if (xfer->flags_int.control_hdr) 815 err = xhci_generic_done_sub(xfer); 816 817 xfer->aframes = 1; 818 819 if (xfer->td_transfer_cache == NULL) 820 goto done; 821 } 822 823 while (xfer->aframes != xfer->nframes) { 824 825 err = xhci_generic_done_sub(xfer); 826 xfer->aframes++; 827 828 if (xfer->td_transfer_cache == NULL) 829 goto done; 830 } 831 832 if (xfer->flags_int.control_xfr && 833 !xfer->flags_int.control_act) 834 err = xhci_generic_done_sub(xfer); 835done: 836 /* transfer is complete */ 837 xhci_device_done(xfer, err); 838} 839 840static void 841xhci_activate_transfer(struct usb_xfer *xfer) 842{ 843 struct xhci_td *td; 844 845 td = xfer->td_transfer_cache; 846 847 usb_pc_cpu_invalidate(td->page_cache); 848 849 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 850 851 /* activate the transfer */ 852 853 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 854 usb_pc_cpu_flush(td->page_cache); 855 856 xhci_endpoint_doorbell(xfer); 857 } 858} 859 860static void 861xhci_skip_transfer(struct usb_xfer *xfer) 862{ 863 struct xhci_td *td; 864 struct xhci_td *td_last; 865 866 td = xfer->td_transfer_cache; 867 td_last = xfer->td_transfer_last; 868 869 td = td->alt_next; 870 871 usb_pc_cpu_invalidate(td->page_cache); 872 873 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 874 875 usb_pc_cpu_invalidate(td_last->page_cache); 876 877 /* copy LINK TRB to current waiting location */ 878 879 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 880 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 881 usb_pc_cpu_flush(td->page_cache); 882 883 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 884 usb_pc_cpu_flush(td->page_cache); 885 886 xhci_endpoint_doorbell(xfer); 887 } 888} 889 890/*------------------------------------------------------------------------* 891 * xhci_check_transfer 892 *------------------------------------------------------------------------*/ 893static void 894xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 895{ 896 struct xhci_endpoint_ext *pepext; 897 int64_t offset; 898 uint64_t td_event; 899 uint32_t temp; 900 uint32_t remainder; 901 uint16_t stream_id = 0; 902 uint16_t i; 903 uint8_t status; 904 uint8_t halted; 905 uint8_t epno; 906 uint8_t index; 907 908 /* decode TRB */ 909 td_event = le64toh(trb->qwTrb0); 910 temp = le32toh(trb->dwTrb2); 911 912 remainder = XHCI_TRB_2_REM_GET(temp); 913 status = XHCI_TRB_2_ERROR_GET(temp); 914 915 temp = le32toh(trb->dwTrb3); 916 epno = XHCI_TRB_3_EP_GET(temp); 917 index = XHCI_TRB_3_SLOT_GET(temp); 918 919 /* check if error means halted */ 920 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 921 status != XHCI_TRB_ERROR_SUCCESS); 922 923 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 924 index, epno, remainder, status); 925 926 if (index > sc->sc_noslot) { 927 DPRINTF("Invalid slot.\n"); 928 return; 929 } 930 931 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 932 DPRINTF("Invalid endpoint.\n"); 933 return; 934 } 935 936 pepext = &sc->sc_hw.devs[index].endp[epno]; 937 938 /* try to find the USB transfer that generated the event */ 939 for (i = 0;; i++) { 940 struct usb_xfer *xfer; 941 struct xhci_td *td; 942 943 if (i == (XHCI_MAX_TRANSFERS - 1)) { 944 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 945 stream_id == (XHCI_MAX_STREAMS - 1)) 946 break; 947 stream_id++; 948 i = 0; 949 DPRINTFN(5, "stream_id=%u\n", stream_id); 950 } 951 952 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 953 if (xfer == NULL) 954 continue; 955 956 td = xfer->td_transfer_cache; 957 958 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 959 (long long)td_event, 960 (long long)td->td_self, 961 (long long)td->td_self + sizeof(td->td_trb)); 962 963 /* 964 * NOTE: Some XHCI implementations might not trigger 965 * an event on the last LINK TRB so we need to 966 * consider both the last and second last event 967 * address as conditions for a successful transfer. 968 * 969 * NOTE: We assume that the XHCI will only trigger one 970 * event per chain of TRBs. 971 */ 972 973 offset = td_event - td->td_self; 974 975 if (offset >= 0 && 976 offset < (int64_t)sizeof(td->td_trb)) { 977 978 usb_pc_cpu_invalidate(td->page_cache); 979 980 /* compute rest of remainder, if any */ 981 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 982 temp = le32toh(td->td_trb[i].dwTrb2); 983 remainder += XHCI_TRB_2_BYTES_GET(temp); 984 } 985 986 DPRINTFN(5, "New remainder: %u\n", remainder); 987 988 /* clear isochronous transfer errors */ 989 if (xfer->flags_int.isochronous_xfr) { 990 if (halted) { 991 halted = 0; 992 status = XHCI_TRB_ERROR_SUCCESS; 993 remainder = td->len; 994 } 995 } 996 997 /* "td->remainder" is verified later */ 998 td->remainder = remainder; 999 td->status = status; 1000 1001 usb_pc_cpu_flush(td->page_cache); 1002 1003 /* 1004 * 1) Last transfer descriptor makes the 1005 * transfer done 1006 */ 1007 if (((void *)td) == xfer->td_transfer_last) { 1008 DPRINTF("TD is last\n"); 1009 xhci_generic_done(xfer); 1010 break; 1011 } 1012 1013 /* 1014 * 2) Any kind of error makes the transfer 1015 * done 1016 */ 1017 if (halted) { 1018 DPRINTF("TD has I/O error\n"); 1019 xhci_generic_done(xfer); 1020 break; 1021 } 1022 1023 /* 1024 * 3) If there is no alternate next transfer, 1025 * a short packet also makes the transfer done 1026 */ 1027 if (td->remainder > 0) { 1028 if (td->alt_next == NULL) { 1029 DPRINTF( 1030 "short TD has no alternate next\n"); 1031 xhci_generic_done(xfer); 1032 break; 1033 } 1034 DPRINTF("TD has short pkt\n"); 1035 if (xfer->flags_int.short_frames_ok || 1036 xfer->flags_int.isochronous_xfr || 1037 xfer->flags_int.control_xfr) { 1038 /* follow the alt next */ 1039 xfer->td_transfer_cache = td->alt_next; 1040 xhci_activate_transfer(xfer); 1041 break; 1042 } 1043 xhci_skip_transfer(xfer); 1044 xhci_generic_done(xfer); 1045 break; 1046 } 1047 1048 /* 1049 * 4) Transfer complete - go to next TD 1050 */ 1051 DPRINTF("Following next TD\n"); 1052 xfer->td_transfer_cache = td->obj_next; 1053 xhci_activate_transfer(xfer); 1054 break; /* there should only be one match */ 1055 } 1056 } 1057} 1058 1059static int 1060xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1061{ 1062 if (sc->sc_cmd_addr == trb->qwTrb0) { 1063 DPRINTF("Received command event\n"); 1064 sc->sc_cmd_result[0] = trb->dwTrb2; 1065 sc->sc_cmd_result[1] = trb->dwTrb3; 1066 cv_signal(&sc->sc_cmd_cv); 1067 return (1); /* command match */ 1068 } 1069 return (0); 1070} 1071 1072static int 1073xhci_interrupt_poll(struct xhci_softc *sc) 1074{ 1075 struct usb_page_search buf_res; 1076 struct xhci_hw_root *phwr; 1077 uint64_t addr; 1078 uint32_t temp; 1079 int retval = 0; 1080 uint16_t i; 1081 uint8_t event; 1082 uint8_t j; 1083 uint8_t k; 1084 uint8_t t; 1085 1086 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1087 1088 phwr = buf_res.buffer; 1089 1090 /* Receive any events */ 1091 1092 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1093 1094 i = sc->sc_event_idx; 1095 j = sc->sc_event_ccs; 1096 t = 2; 1097 1098 while (1) { 1099 1100 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1101 1102 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1103 1104 if (j != k) 1105 break; 1106 1107 event = XHCI_TRB_3_TYPE_GET(temp); 1108 1109 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1110 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1111 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1112 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1113 1114 switch (event) { 1115 case XHCI_TRB_EVENT_TRANSFER: 1116 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1117 break; 1118 case XHCI_TRB_EVENT_CMD_COMPLETE: 1119 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1120 break; 1121 default: 1122 DPRINTF("Unhandled event = %u\n", event); 1123 break; 1124 } 1125 1126 i++; 1127 1128 if (i == XHCI_MAX_EVENTS) { 1129 i = 0; 1130 j ^= 1; 1131 1132 /* check for timeout */ 1133 if (!--t) 1134 break; 1135 } 1136 } 1137 1138 sc->sc_event_idx = i; 1139 sc->sc_event_ccs = j; 1140 1141 /* 1142 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1143 * latched. That means to activate the register we need to 1144 * write both the low and high double word of the 64-bit 1145 * register. 1146 */ 1147 1148 addr = buf_res.physaddr; 1149 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1150 1151 /* try to clear busy bit */ 1152 addr |= XHCI_ERDP_LO_BUSY; 1153 1154 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1155 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1156 1157 return (retval); 1158} 1159 1160static usb_error_t 1161xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1162 uint16_t timeout_ms) 1163{ 1164 struct usb_page_search buf_res; 1165 struct xhci_hw_root *phwr; 1166 uint64_t addr; 1167 uint32_t temp; 1168 uint8_t i; 1169 uint8_t j; 1170 uint8_t timeout = 0; 1171 int err; 1172 1173 XHCI_CMD_ASSERT_LOCKED(sc); 1174 1175 /* get hardware root structure */ 1176 1177 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1178 1179 phwr = buf_res.buffer; 1180 1181 /* Queue command */ 1182 1183 USB_BUS_LOCK(&sc->sc_bus); 1184retry: 1185 i = sc->sc_command_idx; 1186 j = sc->sc_command_ccs; 1187 1188 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1189 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1190 (long long)le64toh(trb->qwTrb0), 1191 (long)le32toh(trb->dwTrb2), 1192 (long)le32toh(trb->dwTrb3)); 1193 1194 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1195 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1196 1197 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1198 1199 temp = trb->dwTrb3; 1200 1201 if (j) 1202 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1203 else 1204 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1205 1206 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1207 1208 phwr->hwr_commands[i].dwTrb3 = temp; 1209 1210 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1211 1212 addr = buf_res.physaddr; 1213 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1214 1215 sc->sc_cmd_addr = htole64(addr); 1216 1217 i++; 1218 1219 if (i == (XHCI_MAX_COMMANDS - 1)) { 1220 1221 if (j) { 1222 temp = htole32(XHCI_TRB_3_TC_BIT | 1223 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1224 XHCI_TRB_3_CYCLE_BIT); 1225 } else { 1226 temp = htole32(XHCI_TRB_3_TC_BIT | 1227 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1228 } 1229 1230 phwr->hwr_commands[i].dwTrb3 = temp; 1231 1232 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1233 1234 i = 0; 1235 j ^= 1; 1236 } 1237 1238 sc->sc_command_idx = i; 1239 sc->sc_command_ccs = j; 1240 1241 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1242 1243 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1244 USB_MS_TO_TICKS(timeout_ms)); 1245 1246 /* 1247 * In some error cases event interrupts are not generated. 1248 * Poll one time to see if the command has completed. 1249 */ 1250 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1251 DPRINTF("Command was completed when polling\n"); 1252 err = 0; 1253 } 1254 if (err != 0) { 1255 DPRINTF("Command timeout!\n"); 1256 /* 1257 * After some weeks of continuous operation, it has 1258 * been observed that the ASMedia Technology, ASM1042 1259 * SuperSpeed USB Host Controller can suddenly stop 1260 * accepting commands via the command queue. Try to 1261 * first reset the command queue. If that fails do a 1262 * host controller reset. 1263 */ 1264 if (timeout == 0 && 1265 xhci_reset_command_queue_locked(sc) == 0) { 1266 temp = le32toh(trb->dwTrb3); 1267 1268 /* 1269 * Avoid infinite XHCI reset loops if the set 1270 * address command fails to respond due to a 1271 * non-enumerating device: 1272 */ 1273 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1274 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1275 DPRINTF("Set address timeout\n"); 1276 } else { 1277 timeout = 1; 1278 goto retry; 1279 } 1280 } else { 1281 DPRINTF("Controller reset!\n"); 1282 usb_bus_reset_async_locked(&sc->sc_bus); 1283 } 1284 err = USB_ERR_TIMEOUT; 1285 trb->dwTrb2 = 0; 1286 trb->dwTrb3 = 0; 1287 } else { 1288 temp = le32toh(sc->sc_cmd_result[0]); 1289 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1290 err = USB_ERR_IOERROR; 1291 1292 trb->dwTrb2 = sc->sc_cmd_result[0]; 1293 trb->dwTrb3 = sc->sc_cmd_result[1]; 1294 } 1295 1296 USB_BUS_UNLOCK(&sc->sc_bus); 1297 1298 return (err); 1299} 1300 1301#if 0 1302static usb_error_t 1303xhci_cmd_nop(struct xhci_softc *sc) 1304{ 1305 struct xhci_trb trb; 1306 uint32_t temp; 1307 1308 DPRINTF("\n"); 1309 1310 trb.qwTrb0 = 0; 1311 trb.dwTrb2 = 0; 1312 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1313 1314 trb.dwTrb3 = htole32(temp); 1315 1316 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1317} 1318#endif 1319 1320static usb_error_t 1321xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1322{ 1323 struct xhci_trb trb; 1324 uint32_t temp; 1325 usb_error_t err; 1326 1327 DPRINTF("\n"); 1328 1329 trb.qwTrb0 = 0; 1330 trb.dwTrb2 = 0; 1331 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1332 1333 err = xhci_do_command(sc, &trb, 100 /* ms */); 1334 if (err) 1335 goto done; 1336 1337 temp = le32toh(trb.dwTrb3); 1338 1339 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1340 1341done: 1342 return (err); 1343} 1344 1345static usb_error_t 1346xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1347{ 1348 struct xhci_trb trb; 1349 uint32_t temp; 1350 1351 DPRINTF("\n"); 1352 1353 trb.qwTrb0 = 0; 1354 trb.dwTrb2 = 0; 1355 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1356 XHCI_TRB_3_SLOT_SET(slot_id); 1357 1358 trb.dwTrb3 = htole32(temp); 1359 1360 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1361} 1362 1363static usb_error_t 1364xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1365 uint8_t bsr, uint8_t slot_id) 1366{ 1367 struct xhci_trb trb; 1368 uint32_t temp; 1369 1370 DPRINTF("\n"); 1371 1372 trb.qwTrb0 = htole64(input_ctx); 1373 trb.dwTrb2 = 0; 1374 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1375 XHCI_TRB_3_SLOT_SET(slot_id); 1376 1377 if (bsr) 1378 temp |= XHCI_TRB_3_BSR_BIT; 1379 1380 trb.dwTrb3 = htole32(temp); 1381 1382 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1383} 1384 1385static usb_error_t 1386xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1387{ 1388 struct usb_page_search buf_inp; 1389 struct usb_page_search buf_dev; 1390 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1391 struct xhci_hw_dev *hdev; 1392 struct xhci_dev_ctx *pdev; 1393 struct xhci_endpoint_ext *pepext; 1394 uint32_t temp; 1395 uint16_t mps; 1396 usb_error_t err; 1397 uint8_t index; 1398 1399 /* the root HUB case is not handled here */ 1400 if (udev->parent_hub == NULL) 1401 return (USB_ERR_INVAL); 1402 1403 index = udev->controller_slot_id; 1404 1405 hdev = &sc->sc_hw.devs[index]; 1406 1407 if (mtx != NULL) 1408 mtx_unlock(mtx); 1409 1410 XHCI_CMD_LOCK(sc); 1411 1412 switch (hdev->state) { 1413 case XHCI_ST_DEFAULT: 1414 case XHCI_ST_ENABLED: 1415 1416 hdev->state = XHCI_ST_ENABLED; 1417 1418 /* set configure mask to slot and EP0 */ 1419 xhci_configure_mask(udev, 3, 0); 1420 1421 /* configure input slot context structure */ 1422 err = xhci_configure_device(udev); 1423 1424 if (err != 0) { 1425 DPRINTF("Could not configure device\n"); 1426 break; 1427 } 1428 1429 /* configure input endpoint context structure */ 1430 switch (udev->speed) { 1431 case USB_SPEED_LOW: 1432 case USB_SPEED_FULL: 1433 mps = 8; 1434 break; 1435 case USB_SPEED_HIGH: 1436 mps = 64; 1437 break; 1438 default: 1439 mps = 512; 1440 break; 1441 } 1442 1443 pepext = xhci_get_endpoint_ext(udev, 1444 &udev->ctrl_ep_desc); 1445 1446 /* ensure the control endpoint is setup again */ 1447 USB_BUS_LOCK(udev->bus); 1448 pepext->trb_halted = 1; 1449 pepext->trb_running = 0; 1450 USB_BUS_UNLOCK(udev->bus); 1451 1452 err = xhci_configure_endpoint(udev, 1453 &udev->ctrl_ep_desc, pepext, 1454 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1455 1456 if (err != 0) { 1457 DPRINTF("Could not configure default endpoint\n"); 1458 break; 1459 } 1460 1461 /* execute set address command */ 1462 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1463 1464 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1465 (address == 0), index); 1466 1467 if (err != 0) { 1468 temp = le32toh(sc->sc_cmd_result[0]); 1469 if (address == 0 && sc->sc_port_route != NULL && 1470 XHCI_TRB_2_ERROR_GET(temp) == 1471 XHCI_TRB_ERROR_PARAMETER) { 1472 /* LynxPoint XHCI - ports are not switchable */ 1473 /* Un-route all ports from the XHCI */ 1474 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1475 } 1476 DPRINTF("Could not set address " 1477 "for slot %u.\n", index); 1478 if (address != 0) 1479 break; 1480 } 1481 1482 /* update device address to new value */ 1483 1484 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1485 pdev = buf_dev.buffer; 1486 usb_pc_cpu_invalidate(&hdev->device_pc); 1487 1488 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1489 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1490 1491 /* update device state to new value */ 1492 1493 if (address != 0) 1494 hdev->state = XHCI_ST_ADDRESSED; 1495 else 1496 hdev->state = XHCI_ST_DEFAULT; 1497 break; 1498 1499 default: 1500 DPRINTF("Wrong state for set address.\n"); 1501 err = USB_ERR_IOERROR; 1502 break; 1503 } 1504 XHCI_CMD_UNLOCK(sc); 1505 1506 if (mtx != NULL) 1507 mtx_lock(mtx); 1508 1509 return (err); 1510} 1511 1512static usb_error_t 1513xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1514 uint8_t deconfigure, uint8_t slot_id) 1515{ 1516 struct xhci_trb trb; 1517 uint32_t temp; 1518 1519 DPRINTF("\n"); 1520 1521 trb.qwTrb0 = htole64(input_ctx); 1522 trb.dwTrb2 = 0; 1523 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1524 XHCI_TRB_3_SLOT_SET(slot_id); 1525 1526 if (deconfigure) 1527 temp |= XHCI_TRB_3_DCEP_BIT; 1528 1529 trb.dwTrb3 = htole32(temp); 1530 1531 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1532} 1533 1534static usb_error_t 1535xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1536 uint8_t slot_id) 1537{ 1538 struct xhci_trb trb; 1539 uint32_t temp; 1540 1541 DPRINTF("\n"); 1542 1543 trb.qwTrb0 = htole64(input_ctx); 1544 trb.dwTrb2 = 0; 1545 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1546 XHCI_TRB_3_SLOT_SET(slot_id); 1547 trb.dwTrb3 = htole32(temp); 1548 1549 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1550} 1551 1552static usb_error_t 1553xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1554 uint8_t ep_id, uint8_t slot_id) 1555{ 1556 struct xhci_trb trb; 1557 uint32_t temp; 1558 1559 DPRINTF("\n"); 1560 1561 trb.qwTrb0 = 0; 1562 trb.dwTrb2 = 0; 1563 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1564 XHCI_TRB_3_SLOT_SET(slot_id) | 1565 XHCI_TRB_3_EP_SET(ep_id); 1566 1567 if (preserve) 1568 temp |= XHCI_TRB_3_PRSV_BIT; 1569 1570 trb.dwTrb3 = htole32(temp); 1571 1572 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1573} 1574 1575static usb_error_t 1576xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1577 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1578{ 1579 struct xhci_trb trb; 1580 uint32_t temp; 1581 1582 DPRINTF("\n"); 1583 1584 trb.qwTrb0 = htole64(dequeue_ptr); 1585 1586 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1587 trb.dwTrb2 = htole32(temp); 1588 1589 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1590 XHCI_TRB_3_SLOT_SET(slot_id) | 1591 XHCI_TRB_3_EP_SET(ep_id); 1592 trb.dwTrb3 = htole32(temp); 1593 1594 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1595} 1596 1597static usb_error_t 1598xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1599 uint8_t ep_id, uint8_t slot_id) 1600{ 1601 struct xhci_trb trb; 1602 uint32_t temp; 1603 1604 DPRINTF("\n"); 1605 1606 trb.qwTrb0 = 0; 1607 trb.dwTrb2 = 0; 1608 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1609 XHCI_TRB_3_SLOT_SET(slot_id) | 1610 XHCI_TRB_3_EP_SET(ep_id); 1611 1612 if (suspend) 1613 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1614 1615 trb.dwTrb3 = htole32(temp); 1616 1617 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1618} 1619 1620static usb_error_t 1621xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1622{ 1623 struct xhci_trb trb; 1624 uint32_t temp; 1625 1626 DPRINTF("\n"); 1627 1628 trb.qwTrb0 = 0; 1629 trb.dwTrb2 = 0; 1630 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1631 XHCI_TRB_3_SLOT_SET(slot_id); 1632 1633 trb.dwTrb3 = htole32(temp); 1634 1635 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1636} 1637 1638/*------------------------------------------------------------------------* 1639 * xhci_interrupt - XHCI interrupt handler 1640 *------------------------------------------------------------------------*/ 1641void 1642xhci_interrupt(struct xhci_softc *sc) 1643{ 1644 uint32_t status; 1645 uint32_t temp; 1646 1647 USB_BUS_LOCK(&sc->sc_bus); 1648 1649 status = XREAD4(sc, oper, XHCI_USBSTS); 1650 1651 /* acknowledge interrupts, if any */ 1652 if (status != 0) { 1653 XWRITE4(sc, oper, XHCI_USBSTS, status); 1654 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1655 } 1656 1657 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1658 1659 /* force clearing of pending interrupts */ 1660 if (temp & XHCI_IMAN_INTR_PEND) 1661 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1662 1663 /* check for event(s) */ 1664 xhci_interrupt_poll(sc); 1665 1666 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1667 XHCI_STS_HSE | XHCI_STS_HCE)) { 1668 1669 if (status & XHCI_STS_PCD) { 1670 xhci_root_intr(sc); 1671 } 1672 1673 if (status & XHCI_STS_HCH) { 1674 printf("%s: host controller halted\n", 1675 __FUNCTION__); 1676 } 1677 1678 if (status & XHCI_STS_HSE) { 1679 printf("%s: host system error\n", 1680 __FUNCTION__); 1681 } 1682 1683 if (status & XHCI_STS_HCE) { 1684 printf("%s: host controller error\n", 1685 __FUNCTION__); 1686 } 1687 } 1688 USB_BUS_UNLOCK(&sc->sc_bus); 1689} 1690 1691/*------------------------------------------------------------------------* 1692 * xhci_timeout - XHCI timeout handler 1693 *------------------------------------------------------------------------*/ 1694static void 1695xhci_timeout(void *arg) 1696{ 1697 struct usb_xfer *xfer = arg; 1698 1699 DPRINTF("xfer=%p\n", xfer); 1700 1701 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1702 1703 /* transfer is transferred */ 1704 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1705} 1706 1707static void 1708xhci_do_poll(struct usb_bus *bus) 1709{ 1710 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1711 1712 USB_BUS_LOCK(&sc->sc_bus); 1713 xhci_interrupt_poll(sc); 1714 USB_BUS_UNLOCK(&sc->sc_bus); 1715} 1716 1717static void 1718xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1719{ 1720 struct usb_page_search buf_res; 1721 struct xhci_td *td; 1722 struct xhci_td *td_next; 1723 struct xhci_td *td_alt_next; 1724 struct xhci_td *td_first; 1725 uint32_t buf_offset; 1726 uint32_t average; 1727 uint32_t len_old; 1728 uint32_t npkt_off; 1729 uint32_t dword; 1730 uint8_t shortpkt_old; 1731 uint8_t precompute; 1732 uint8_t x; 1733 1734 td_alt_next = NULL; 1735 buf_offset = 0; 1736 shortpkt_old = temp->shortpkt; 1737 len_old = temp->len; 1738 npkt_off = 0; 1739 precompute = 1; 1740 1741restart: 1742 1743 td = temp->td; 1744 td_next = td_first = temp->td_next; 1745 1746 while (1) { 1747 1748 if (temp->len == 0) { 1749 1750 if (temp->shortpkt) 1751 break; 1752 1753 /* send a Zero Length Packet, ZLP, last */ 1754 1755 temp->shortpkt = 1; 1756 average = 0; 1757 1758 } else { 1759 1760 average = temp->average; 1761 1762 if (temp->len < average) { 1763 if (temp->len % temp->max_packet_size) { 1764 temp->shortpkt = 1; 1765 } 1766 average = temp->len; 1767 } 1768 } 1769 1770 if (td_next == NULL) 1771 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1772 1773 /* get next TD */ 1774 1775 td = td_next; 1776 td_next = td->obj_next; 1777 1778 /* check if we are pre-computing */ 1779 1780 if (precompute) { 1781 1782 /* update remaining length */ 1783 1784 temp->len -= average; 1785 1786 continue; 1787 } 1788 /* fill out current TD */ 1789 1790 td->len = average; 1791 td->remainder = 0; 1792 td->status = 0; 1793 1794 /* update remaining length */ 1795 1796 temp->len -= average; 1797 1798 /* reset TRB index */ 1799 1800 x = 0; 1801 1802 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1803 /* immediate data */ 1804 1805 if (average > 8) 1806 average = 8; 1807 1808 td->td_trb[0].qwTrb0 = 0; 1809 1810 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1811 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1812 average); 1813 1814 dword = XHCI_TRB_2_BYTES_SET(8) | 1815 XHCI_TRB_2_TDSZ_SET(0) | 1816 XHCI_TRB_2_IRQ_SET(0); 1817 1818 td->td_trb[0].dwTrb2 = htole32(dword); 1819 1820 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1821 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1822 1823 /* check wLength */ 1824 if (td->td_trb[0].qwTrb0 & 1825 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1826 if (td->td_trb[0].qwTrb0 & 1827 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1828 dword |= XHCI_TRB_3_TRT_IN; 1829 else 1830 dword |= XHCI_TRB_3_TRT_OUT; 1831 } 1832 1833 td->td_trb[0].dwTrb3 = htole32(dword); 1834#ifdef USB_DEBUG 1835 xhci_dump_trb(&td->td_trb[x]); 1836#endif 1837 x++; 1838 1839 } else do { 1840 1841 uint32_t npkt; 1842 1843 /* fill out buffer pointers */ 1844 1845 if (average == 0) { 1846 memset(&buf_res, 0, sizeof(buf_res)); 1847 } else { 1848 usbd_get_page(temp->pc, temp->offset + 1849 buf_offset, &buf_res); 1850 1851 /* get length to end of page */ 1852 if (buf_res.length > average) 1853 buf_res.length = average; 1854 1855 /* check for maximum length */ 1856 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1857 buf_res.length = XHCI_TD_PAGE_SIZE; 1858 1859 npkt_off += buf_res.length; 1860 } 1861 1862 /* set up npkt */ 1863 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1864 temp->max_packet_size; 1865 1866 if (npkt == 0) 1867 npkt = 1; 1868 else if (npkt > 31) 1869 npkt = 31; 1870 1871 /* fill out TRB's */ 1872 td->td_trb[x].qwTrb0 = 1873 htole64((uint64_t)buf_res.physaddr); 1874 1875 dword = 1876 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1877 XHCI_TRB_2_TDSZ_SET(npkt) | 1878 XHCI_TRB_2_IRQ_SET(0); 1879 1880 td->td_trb[x].dwTrb2 = htole32(dword); 1881 1882 switch (temp->trb_type) { 1883 case XHCI_TRB_TYPE_ISOCH: 1884 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1885 XHCI_TRB_3_TBC_SET(temp->tbc) | 1886 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1887 if (td != td_first) { 1888 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1889 } else if (temp->do_isoc_sync != 0) { 1890 temp->do_isoc_sync = 0; 1891 /* wait until "isoc_frame" */ 1892 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1893 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1894 } else { 1895 /* start data transfer at next interval */ 1896 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1897 XHCI_TRB_3_ISO_SIA_BIT; 1898 } 1899 if (temp->direction == UE_DIR_IN) 1900 dword |= XHCI_TRB_3_ISP_BIT; 1901 break; 1902 case XHCI_TRB_TYPE_DATA_STAGE: 1903 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1904 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1905 if (temp->direction == UE_DIR_IN) 1906 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1907 /* 1908 * Section 3.2.9 in the XHCI 1909 * specification about control 1910 * transfers says that we should use a 1911 * normal-TRB if there are more TRBs 1912 * extending the data-stage 1913 * TRB. Update the "trb_type". 1914 */ 1915 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1916 break; 1917 case XHCI_TRB_TYPE_STATUS_STAGE: 1918 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1919 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1920 if (temp->direction == UE_DIR_IN) 1921 dword |= XHCI_TRB_3_DIR_IN; 1922 break; 1923 default: /* XHCI_TRB_TYPE_NORMAL */ 1924 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1925 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1926 if (temp->direction == UE_DIR_IN) 1927 dword |= XHCI_TRB_3_ISP_BIT; 1928 break; 1929 } 1930 td->td_trb[x].dwTrb3 = htole32(dword); 1931 1932 average -= buf_res.length; 1933 buf_offset += buf_res.length; 1934#ifdef USB_DEBUG 1935 xhci_dump_trb(&td->td_trb[x]); 1936#endif 1937 x++; 1938 1939 } while (average != 0); 1940 1941 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1942 1943 /* store number of data TRB's */ 1944 1945 td->ntrb = x; 1946 1947 DPRINTF("NTRB=%u\n", x); 1948 1949 /* fill out link TRB */ 1950 1951 if (td_next != NULL) { 1952 /* link the current TD with the next one */ 1953 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1954 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1955 } else { 1956 /* this field will get updated later */ 1957 DPRINTF("NOLINK\n"); 1958 } 1959 1960 dword = XHCI_TRB_2_IRQ_SET(0); 1961 1962 td->td_trb[x].dwTrb2 = htole32(dword); 1963 1964 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1965 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1966 /* 1967 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1968 * frame only receives a single short packet event 1969 * by setting the CHAIN bit in the LINK field. In 1970 * addition some XHCI controllers have problems 1971 * sending a ZLP unless the CHAIN-BIT is set in 1972 * the LINK TRB. 1973 */ 1974 XHCI_TRB_3_CHAIN_BIT; 1975 1976 td->td_trb[x].dwTrb3 = htole32(dword); 1977 1978 td->alt_next = td_alt_next; 1979#ifdef USB_DEBUG 1980 xhci_dump_trb(&td->td_trb[x]); 1981#endif 1982 usb_pc_cpu_flush(td->page_cache); 1983 } 1984 1985 if (precompute) { 1986 precompute = 0; 1987 1988 /* set up alt next pointer, if any */ 1989 if (temp->last_frame) { 1990 td_alt_next = NULL; 1991 } else { 1992 /* we use this field internally */ 1993 td_alt_next = td_next; 1994 } 1995 1996 /* restore */ 1997 temp->shortpkt = shortpkt_old; 1998 temp->len = len_old; 1999 goto restart; 2000 } 2001 2002 /* 2003 * Remove cycle bit from the first TRB if we are 2004 * stepping them: 2005 */ 2006 if (temp->step_td != 0) { 2007 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2008 usb_pc_cpu_flush(td_first->page_cache); 2009 } 2010 2011 /* clear TD SIZE to zero, hence this is the last TRB */ 2012 /* remove chain bit because this is the last data TRB in the chain */ 2013 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 2014 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2015 /* remove CHAIN-BIT from last LINK TRB */ 2016 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2017 2018 usb_pc_cpu_flush(td->page_cache); 2019 2020 temp->td = td; 2021 temp->td_next = td_next; 2022} 2023 2024static void 2025xhci_setup_generic_chain(struct usb_xfer *xfer) 2026{ 2027 struct xhci_std_temp temp; 2028 struct xhci_td *td; 2029 uint32_t x; 2030 uint32_t y; 2031 uint8_t mult; 2032 2033 temp.do_isoc_sync = 0; 2034 temp.step_td = 0; 2035 temp.tbc = 0; 2036 temp.tlbpc = 0; 2037 temp.average = xfer->max_hc_frame_size; 2038 temp.max_packet_size = xfer->max_packet_size; 2039 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 2040 temp.pc = NULL; 2041 temp.last_frame = 0; 2042 temp.offset = 0; 2043 temp.multishort = xfer->flags_int.isochronous_xfr || 2044 xfer->flags_int.control_xfr || 2045 xfer->flags_int.short_frames_ok; 2046 2047 /* toggle the DMA set we are using */ 2048 xfer->flags_int.curr_dma_set ^= 1; 2049 2050 /* get next DMA set */ 2051 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2052 2053 temp.td = NULL; 2054 temp.td_next = td; 2055 2056 xfer->td_transfer_first = td; 2057 xfer->td_transfer_cache = td; 2058 2059 if (xfer->flags_int.isochronous_xfr) { 2060 uint8_t shift; 2061 2062 /* compute multiplier for ISOCHRONOUS transfers */ 2063 mult = xfer->endpoint->ecomp ? 2064 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2065 : 0; 2066 /* check for USB 2.0 multiplier */ 2067 if (mult == 0) { 2068 mult = (xfer->endpoint->edesc-> 2069 wMaxPacketSize[1] >> 3) & 3; 2070 } 2071 /* range check */ 2072 if (mult > 2) 2073 mult = 3; 2074 else 2075 mult++; 2076 2077 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2078 2079 DPRINTF("MFINDEX=0x%08x\n", x); 2080 2081 switch (usbd_get_speed(xfer->xroot->udev)) { 2082 case USB_SPEED_FULL: 2083 shift = 3; 2084 temp.isoc_delta = 8; /* 1ms */ 2085 x += temp.isoc_delta - 1; 2086 x &= ~(temp.isoc_delta - 1); 2087 break; 2088 default: 2089 shift = usbd_xfer_get_fps_shift(xfer); 2090 temp.isoc_delta = 1U << shift; 2091 x += temp.isoc_delta - 1; 2092 x &= ~(temp.isoc_delta - 1); 2093 /* simple frame load balancing */ 2094 x += xfer->endpoint->usb_uframe; 2095 break; 2096 } 2097 2098 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2099 2100 if ((xfer->endpoint->is_synced == 0) || 2101 (y < (xfer->nframes << shift)) || 2102 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2103 /* 2104 * If there is data underflow or the pipe 2105 * queue is empty we schedule the transfer a 2106 * few frames ahead of the current frame 2107 * position. Else two isochronous transfers 2108 * might overlap. 2109 */ 2110 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2111 xfer->endpoint->is_synced = 1; 2112 temp.do_isoc_sync = 1; 2113 2114 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2115 } 2116 2117 /* compute isochronous completion time */ 2118 2119 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2120 2121 xfer->isoc_time_complete = 2122 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2123 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2124 2125 x = 0; 2126 temp.isoc_frame = xfer->endpoint->isoc_next; 2127 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2128 2129 xfer->endpoint->isoc_next += xfer->nframes << shift; 2130 2131 } else if (xfer->flags_int.control_xfr) { 2132 2133 /* check if we should prepend a setup message */ 2134 2135 if (xfer->flags_int.control_hdr) { 2136 2137 temp.len = xfer->frlengths[0]; 2138 temp.pc = xfer->frbuffers + 0; 2139 temp.shortpkt = temp.len ? 1 : 0; 2140 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2141 temp.direction = 0; 2142 2143 /* check for last frame */ 2144 if (xfer->nframes == 1) { 2145 /* no STATUS stage yet, SETUP is last */ 2146 if (xfer->flags_int.control_act) 2147 temp.last_frame = 1; 2148 } 2149 2150 xhci_setup_generic_chain_sub(&temp); 2151 } 2152 x = 1; 2153 mult = 1; 2154 temp.isoc_delta = 0; 2155 temp.isoc_frame = 0; 2156 temp.trb_type = xfer->flags_int.control_did_data ? 2157 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2158 } else { 2159 x = 0; 2160 mult = 1; 2161 temp.isoc_delta = 0; 2162 temp.isoc_frame = 0; 2163 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2164 } 2165 2166 if (x != xfer->nframes) { 2167 /* set up page_cache pointer */ 2168 temp.pc = xfer->frbuffers + x; 2169 /* set endpoint direction */ 2170 temp.direction = UE_GET_DIR(xfer->endpointno); 2171 } 2172 2173 while (x != xfer->nframes) { 2174 2175 /* DATA0 / DATA1 message */ 2176 2177 temp.len = xfer->frlengths[x]; 2178 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2179 x != 0 && temp.multishort == 0); 2180 2181 x++; 2182 2183 if (x == xfer->nframes) { 2184 if (xfer->flags_int.control_xfr) { 2185 /* no STATUS stage yet, DATA is last */ 2186 if (xfer->flags_int.control_act) 2187 temp.last_frame = 1; 2188 } else { 2189 temp.last_frame = 1; 2190 } 2191 } 2192 if (temp.len == 0) { 2193 2194 /* make sure that we send an USB packet */ 2195 2196 temp.shortpkt = 0; 2197 2198 temp.tbc = 0; 2199 temp.tlbpc = mult - 1; 2200 2201 } else if (xfer->flags_int.isochronous_xfr) { 2202 2203 uint8_t tdpc; 2204 2205 /* 2206 * Isochronous transfers don't have short 2207 * packet termination: 2208 */ 2209 2210 temp.shortpkt = 1; 2211 2212 /* isochronous transfers have a transfer limit */ 2213 2214 if (temp.len > xfer->max_frame_size) 2215 temp.len = xfer->max_frame_size; 2216 2217 /* compute TD packet count */ 2218 tdpc = (temp.len + xfer->max_packet_size - 1) / 2219 xfer->max_packet_size; 2220 2221 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2222 temp.tlbpc = (tdpc % mult); 2223 2224 if (temp.tlbpc == 0) 2225 temp.tlbpc = mult - 1; 2226 else 2227 temp.tlbpc--; 2228 } else { 2229 2230 /* regular data transfer */ 2231 2232 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2233 } 2234 2235 xhci_setup_generic_chain_sub(&temp); 2236 2237 if (xfer->flags_int.isochronous_xfr) { 2238 temp.offset += xfer->frlengths[x - 1]; 2239 temp.isoc_frame += temp.isoc_delta; 2240 } else { 2241 /* get next Page Cache pointer */ 2242 temp.pc = xfer->frbuffers + x; 2243 } 2244 } 2245 2246 /* check if we should append a status stage */ 2247 2248 if (xfer->flags_int.control_xfr && 2249 !xfer->flags_int.control_act) { 2250 2251 /* 2252 * Send a DATA1 message and invert the current 2253 * endpoint direction. 2254 */ 2255 if (xhcictlstep || temp.sc->sc_ctlstep) { 2256 /* 2257 * Some XHCI controllers will not delay the 2258 * status stage until the next SOF. Force this 2259 * behaviour to avoid failed control 2260 * transfers. 2261 */ 2262 temp.step_td = (xfer->nframes != 0); 2263 } else { 2264 temp.step_td = 0; 2265 } 2266 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2267 temp.len = 0; 2268 temp.pc = NULL; 2269 temp.shortpkt = 0; 2270 temp.last_frame = 1; 2271 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2272 2273 xhci_setup_generic_chain_sub(&temp); 2274 } 2275 2276 td = temp.td; 2277 2278 /* must have at least one frame! */ 2279 2280 xfer->td_transfer_last = td; 2281 2282 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2283} 2284 2285static void 2286xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2287{ 2288 struct usb_page_search buf_res; 2289 struct xhci_dev_ctx_addr *pdctxa; 2290 2291 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2292 2293 pdctxa = buf_res.buffer; 2294 2295 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2296 2297 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2298 2299 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2300} 2301 2302static usb_error_t 2303xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2304{ 2305 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2306 struct usb_page_search buf_inp; 2307 struct xhci_input_dev_ctx *pinp; 2308 uint32_t temp; 2309 uint8_t index; 2310 uint8_t x; 2311 2312 index = udev->controller_slot_id; 2313 2314 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2315 2316 pinp = buf_inp.buffer; 2317 2318 if (drop) { 2319 mask &= XHCI_INCTX_NON_CTRL_MASK; 2320 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2321 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2322 } else { 2323 /* 2324 * Some hardware requires that we drop the endpoint 2325 * context before adding it again: 2326 */ 2327 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2328 mask & XHCI_INCTX_NON_CTRL_MASK); 2329 2330 /* Add new endpoint context */ 2331 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2332 2333 /* find most significant set bit */ 2334 for (x = 31; x != 1; x--) { 2335 if (mask & (1 << x)) 2336 break; 2337 } 2338 2339 /* adjust */ 2340 x--; 2341 2342 /* figure out the maximum number of contexts */ 2343 if (x > sc->sc_hw.devs[index].context_num) 2344 sc->sc_hw.devs[index].context_num = x; 2345 else 2346 x = sc->sc_hw.devs[index].context_num; 2347 2348 /* update number of contexts */ 2349 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2350 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2351 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2352 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2353 } 2354 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2355 return (0); 2356} 2357 2358static usb_error_t 2359xhci_configure_endpoint(struct usb_device *udev, 2360 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2361 uint16_t interval, uint8_t max_packet_count, 2362 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2363 uint16_t max_frame_size, uint8_t ep_mode) 2364{ 2365 struct usb_page_search buf_inp; 2366 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2367 struct xhci_input_dev_ctx *pinp; 2368 uint64_t ring_addr = pepext->physaddr; 2369 uint32_t temp; 2370 uint8_t index; 2371 uint8_t epno; 2372 uint8_t type; 2373 2374 index = udev->controller_slot_id; 2375 2376 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2377 2378 pinp = buf_inp.buffer; 2379 2380 epno = edesc->bEndpointAddress; 2381 type = edesc->bmAttributes & UE_XFERTYPE; 2382 2383 if (type == UE_CONTROL) 2384 epno |= UE_DIR_IN; 2385 2386 epno = XHCI_EPNO2EPID(epno); 2387 2388 if (epno == 0) 2389 return (USB_ERR_NO_PIPE); /* invalid */ 2390 2391 if (max_packet_count == 0) 2392 return (USB_ERR_BAD_BUFSIZE); 2393 2394 max_packet_count--; 2395 2396 if (mult == 0) 2397 return (USB_ERR_BAD_BUFSIZE); 2398 2399 /* store endpoint mode */ 2400 pepext->trb_ep_mode = ep_mode; 2401 /* store bMaxPacketSize for control endpoints */ 2402 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2403 usb_pc_cpu_flush(pepext->page_cache); 2404 2405 if (ep_mode == USB_EP_MODE_STREAMS) { 2406 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2407 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2408 XHCI_EPCTX_0_LSA_SET(1); 2409 2410 ring_addr += sizeof(struct xhci_trb) * 2411 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2412 } else { 2413 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2414 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2415 XHCI_EPCTX_0_LSA_SET(0); 2416 2417 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2418 } 2419 2420 switch (udev->speed) { 2421 case USB_SPEED_FULL: 2422 case USB_SPEED_LOW: 2423 /* 1ms -> 125us */ 2424 fps_shift += 3; 2425 break; 2426 default: 2427 break; 2428 } 2429 2430 switch (type) { 2431 case UE_INTERRUPT: 2432 if (fps_shift > 3) 2433 fps_shift--; 2434 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2435 break; 2436 case UE_ISOCHRONOUS: 2437 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2438 2439 switch (udev->speed) { 2440 case USB_SPEED_SUPER: 2441 if (mult > 3) 2442 mult = 3; 2443 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2444 max_packet_count /= mult; 2445 break; 2446 default: 2447 break; 2448 } 2449 break; 2450 default: 2451 break; 2452 } 2453 2454 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2455 2456 temp = 2457 XHCI_EPCTX_1_HID_SET(0) | 2458 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2459 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2460 2461 /* 2462 * Always enable the "three strikes and you are gone" feature 2463 * except for ISOCHRONOUS endpoints. This is suggested by 2464 * section 4.3.3 in the XHCI specification about device slot 2465 * initialisation. 2466 */ 2467 if (type != UE_ISOCHRONOUS) 2468 temp |= XHCI_EPCTX_1_CERR_SET(3); 2469 2470 switch (type) { 2471 case UE_CONTROL: 2472 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2473 break; 2474 case UE_ISOCHRONOUS: 2475 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2476 break; 2477 case UE_BULK: 2478 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2479 break; 2480 default: 2481 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2482 break; 2483 } 2484 2485 /* check for IN direction */ 2486 if (epno & 1) 2487 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2488 2489 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2490 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2491 2492 switch (edesc->bmAttributes & UE_XFERTYPE) { 2493 case UE_INTERRUPT: 2494 case UE_ISOCHRONOUS: 2495 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2496 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2497 max_frame_size)); 2498 break; 2499 case UE_CONTROL: 2500 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2501 break; 2502 default: 2503 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2504 break; 2505 } 2506 2507 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2508 2509#ifdef USB_DEBUG 2510 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2511#endif 2512 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2513 2514 return (0); /* success */ 2515} 2516 2517static usb_error_t 2518xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2519{ 2520 struct xhci_endpoint_ext *pepext; 2521 struct usb_endpoint_ss_comp_descriptor *ecomp; 2522 usb_stream_t x; 2523 2524 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2525 xfer->endpoint->edesc); 2526 2527 ecomp = xfer->endpoint->ecomp; 2528 2529 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2530 uint64_t temp; 2531 2532 /* halt any transfers */ 2533 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2534 2535 /* compute start of TRB ring for stream "x" */ 2536 temp = pepext->physaddr + 2537 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2538 XHCI_SCTX_0_SCT_SEC_TR_RING; 2539 2540 /* make tree structure */ 2541 pepext->trb[(XHCI_MAX_TRANSFERS * 2542 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2543 2544 /* reserved fields */ 2545 pepext->trb[(XHCI_MAX_TRANSFERS * 2546 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2547 pepext->trb[(XHCI_MAX_TRANSFERS * 2548 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2549 } 2550 usb_pc_cpu_flush(pepext->page_cache); 2551 2552 return (xhci_configure_endpoint(xfer->xroot->udev, 2553 xfer->endpoint->edesc, pepext, 2554 xfer->interval, xfer->max_packet_count, 2555 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2556 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2557 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2558} 2559 2560static usb_error_t 2561xhci_configure_device(struct usb_device *udev) 2562{ 2563 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2564 struct usb_page_search buf_inp; 2565 struct usb_page_cache *pcinp; 2566 struct xhci_input_dev_ctx *pinp; 2567 struct usb_device *hubdev; 2568 uint32_t temp; 2569 uint32_t route; 2570 uint32_t rh_port; 2571 uint8_t is_hub; 2572 uint8_t index; 2573 uint8_t depth; 2574 2575 index = udev->controller_slot_id; 2576 2577 DPRINTF("index=%u\n", index); 2578 2579 pcinp = &sc->sc_hw.devs[index].input_pc; 2580 2581 usbd_get_page(pcinp, 0, &buf_inp); 2582 2583 pinp = buf_inp.buffer; 2584 2585 rh_port = 0; 2586 route = 0; 2587 2588 /* figure out route string and root HUB port number */ 2589 2590 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2591 2592 if (hubdev->parent_hub == NULL) 2593 break; 2594 2595 depth = hubdev->parent_hub->depth; 2596 2597 /* 2598 * NOTE: HS/FS/LS devices and the SS root HUB can have 2599 * more than 15 ports 2600 */ 2601 2602 rh_port = hubdev->port_no; 2603 2604 if (depth == 0) 2605 break; 2606 2607 if (rh_port > 15) 2608 rh_port = 15; 2609 2610 if (depth < 6) 2611 route |= rh_port << (4 * (depth - 1)); 2612 } 2613 2614 DPRINTF("Route=0x%08x\n", route); 2615 2616 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2617 XHCI_SCTX_0_CTX_NUM_SET( 2618 sc->sc_hw.devs[index].context_num + 1); 2619 2620 switch (udev->speed) { 2621 case USB_SPEED_LOW: 2622 temp |= XHCI_SCTX_0_SPEED_SET(2); 2623 if (udev->parent_hs_hub != NULL && 2624 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2625 UDPROTO_HSHUBMTT) { 2626 DPRINTF("Device inherits MTT\n"); 2627 temp |= XHCI_SCTX_0_MTT_SET(1); 2628 } 2629 break; 2630 case USB_SPEED_HIGH: 2631 temp |= XHCI_SCTX_0_SPEED_SET(3); 2632 if (sc->sc_hw.devs[index].nports != 0 && 2633 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2634 DPRINTF("HUB supports MTT\n"); 2635 temp |= XHCI_SCTX_0_MTT_SET(1); 2636 } 2637 break; 2638 case USB_SPEED_FULL: 2639 temp |= XHCI_SCTX_0_SPEED_SET(1); 2640 if (udev->parent_hs_hub != NULL && 2641 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2642 UDPROTO_HSHUBMTT) { 2643 DPRINTF("Device inherits MTT\n"); 2644 temp |= XHCI_SCTX_0_MTT_SET(1); 2645 } 2646 break; 2647 default: 2648 temp |= XHCI_SCTX_0_SPEED_SET(4); 2649 break; 2650 } 2651 2652 is_hub = sc->sc_hw.devs[index].nports != 0 && 2653 (udev->speed == USB_SPEED_SUPER || 2654 udev->speed == USB_SPEED_HIGH); 2655 2656 if (is_hub) 2657 temp |= XHCI_SCTX_0_HUB_SET(1); 2658 2659 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2660 2661 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2662 2663 if (is_hub) { 2664 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2665 sc->sc_hw.devs[index].nports); 2666 } 2667 2668 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2669 2670 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2671 2672 if (is_hub) { 2673 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2674 sc->sc_hw.devs[index].tt); 2675 } 2676 2677 hubdev = udev->parent_hs_hub; 2678 2679 /* check if we should activate the transaction translator */ 2680 switch (udev->speed) { 2681 case USB_SPEED_FULL: 2682 case USB_SPEED_LOW: 2683 if (hubdev != NULL) { 2684 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2685 hubdev->controller_slot_id); 2686 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2687 udev->hs_port_no); 2688 } 2689 break; 2690 default: 2691 break; 2692 } 2693 2694 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2695 2696 /* 2697 * These fields should be initialized to zero, according to 2698 * XHCI section 6.2.2 - slot context: 2699 */ 2700 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2701 XHCI_SCTX_3_SLOT_STATE_SET(0); 2702 2703 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2704 2705#ifdef USB_DEBUG 2706 xhci_dump_device(sc, &pinp->ctx_slot); 2707#endif 2708 usb_pc_cpu_flush(pcinp); 2709 2710 return (0); /* success */ 2711} 2712 2713static usb_error_t 2714xhci_alloc_device_ext(struct usb_device *udev) 2715{ 2716 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2717 struct usb_page_search buf_dev; 2718 struct usb_page_search buf_ep; 2719 struct xhci_trb *trb; 2720 struct usb_page_cache *pc; 2721 struct usb_page *pg; 2722 uint64_t addr; 2723 uint8_t index; 2724 uint8_t i; 2725 2726 index = udev->controller_slot_id; 2727 2728 pc = &sc->sc_hw.devs[index].device_pc; 2729 pg = &sc->sc_hw.devs[index].device_pg; 2730 2731 /* need to initialize the page cache */ 2732 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2733 2734 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2735 (2 * sizeof(struct xhci_dev_ctx)) : 2736 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2737 goto error; 2738 2739 usbd_get_page(pc, 0, &buf_dev); 2740 2741 pc = &sc->sc_hw.devs[index].input_pc; 2742 pg = &sc->sc_hw.devs[index].input_pg; 2743 2744 /* need to initialize the page cache */ 2745 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2746 2747 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2748 (2 * sizeof(struct xhci_input_dev_ctx)) : 2749 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2750 goto error; 2751 } 2752 2753 /* initialize all endpoint LINK TRBs */ 2754 2755 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2756 2757 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2758 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2759 2760 /* need to initialize the page cache */ 2761 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2762 2763 if (usb_pc_alloc_mem(pc, pg, 2764 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2765 goto error; 2766 } 2767 2768 /* lookup endpoint TRB ring */ 2769 usbd_get_page(pc, 0, &buf_ep); 2770 2771 /* get TRB pointer */ 2772 trb = buf_ep.buffer; 2773 trb += XHCI_MAX_TRANSFERS - 1; 2774 2775 /* get TRB start address */ 2776 addr = buf_ep.physaddr; 2777 2778 /* create LINK TRB */ 2779 trb->qwTrb0 = htole64(addr); 2780 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2781 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2782 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2783 2784 usb_pc_cpu_flush(pc); 2785 } 2786 2787 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2788 2789 return (0); 2790 2791error: 2792 xhci_free_device_ext(udev); 2793 2794 return (USB_ERR_NOMEM); 2795} 2796 2797static void 2798xhci_free_device_ext(struct usb_device *udev) 2799{ 2800 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2801 uint8_t index; 2802 uint8_t i; 2803 2804 index = udev->controller_slot_id; 2805 xhci_set_slot_pointer(sc, index, 0); 2806 2807 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2808 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2809 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2810 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2811} 2812 2813static struct xhci_endpoint_ext * 2814xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2815{ 2816 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2817 struct xhci_endpoint_ext *pepext; 2818 struct usb_page_cache *pc; 2819 struct usb_page_search buf_ep; 2820 uint8_t epno; 2821 uint8_t index; 2822 2823 epno = edesc->bEndpointAddress; 2824 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2825 epno |= UE_DIR_IN; 2826 2827 epno = XHCI_EPNO2EPID(epno); 2828 2829 index = udev->controller_slot_id; 2830 2831 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2832 2833 usbd_get_page(pc, 0, &buf_ep); 2834 2835 pepext = &sc->sc_hw.devs[index].endp[epno]; 2836 pepext->page_cache = pc; 2837 pepext->trb = buf_ep.buffer; 2838 pepext->physaddr = buf_ep.physaddr; 2839 2840 return (pepext); 2841} 2842 2843static void 2844xhci_endpoint_doorbell(struct usb_xfer *xfer) 2845{ 2846 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2847 uint8_t epno; 2848 uint8_t index; 2849 2850 epno = xfer->endpointno; 2851 if (xfer->flags_int.control_xfr) 2852 epno |= UE_DIR_IN; 2853 2854 epno = XHCI_EPNO2EPID(epno); 2855 index = xfer->xroot->udev->controller_slot_id; 2856 2857 if (xfer->xroot->udev->flags.self_suspended == 0) { 2858 XWRITE4(sc, door, XHCI_DOORBELL(index), 2859 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2860 } 2861} 2862 2863static void 2864xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2865{ 2866 struct xhci_endpoint_ext *pepext; 2867 2868 if (xfer->flags_int.bandwidth_reclaimed) { 2869 xfer->flags_int.bandwidth_reclaimed = 0; 2870 2871 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2872 xfer->endpoint->edesc); 2873 2874 pepext->trb_used[xfer->stream_id]--; 2875 2876 pepext->xfer[xfer->qh_pos] = NULL; 2877 2878 if (error && pepext->trb_running != 0) { 2879 pepext->trb_halted = 1; 2880 pepext->trb_running = 0; 2881 } 2882 } 2883} 2884 2885static usb_error_t 2886xhci_transfer_insert(struct usb_xfer *xfer) 2887{ 2888 struct xhci_td *td_first; 2889 struct xhci_td *td_last; 2890 struct xhci_trb *trb_link; 2891 struct xhci_endpoint_ext *pepext; 2892 uint64_t addr; 2893 usb_stream_t id; 2894 uint8_t i; 2895 uint8_t inext; 2896 uint8_t trb_limit; 2897 2898 DPRINTFN(8, "\n"); 2899 2900 id = xfer->stream_id; 2901 2902 /* check if already inserted */ 2903 if (xfer->flags_int.bandwidth_reclaimed) { 2904 DPRINTFN(8, "Already in schedule\n"); 2905 return (0); 2906 } 2907 2908 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2909 xfer->endpoint->edesc); 2910 2911 td_first = xfer->td_transfer_first; 2912 td_last = xfer->td_transfer_last; 2913 addr = pepext->physaddr; 2914 2915 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2916 case UE_CONTROL: 2917 case UE_INTERRUPT: 2918 /* single buffered */ 2919 trb_limit = 1; 2920 break; 2921 default: 2922 /* multi buffered */ 2923 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2924 break; 2925 } 2926 2927 if (pepext->trb_used[id] >= trb_limit) { 2928 DPRINTFN(8, "Too many TDs queued.\n"); 2929 return (USB_ERR_NOMEM); 2930 } 2931 2932 /* check if bMaxPacketSize changed */ 2933 if (xfer->flags_int.control_xfr != 0 && 2934 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 2935 2936 DPRINTFN(8, "Reconfigure control endpoint\n"); 2937 2938 /* force driver to reconfigure endpoint */ 2939 pepext->trb_halted = 1; 2940 pepext->trb_running = 0; 2941 } 2942 2943 /* check for stopped condition, after putting transfer on interrupt queue */ 2944 if (pepext->trb_running == 0) { 2945 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2946 2947 DPRINTFN(8, "Not running\n"); 2948 2949 /* start configuration */ 2950 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2951 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2952 return (0); 2953 } 2954 2955 pepext->trb_used[id]++; 2956 2957 /* get current TRB index */ 2958 i = pepext->trb_index[id]; 2959 2960 /* get next TRB index */ 2961 inext = (i + 1); 2962 2963 /* the last entry of the ring is a hardcoded link TRB */ 2964 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2965 inext = 0; 2966 2967 /* store next TRB index, before stream ID offset is added */ 2968 pepext->trb_index[id] = inext; 2969 2970 /* offset for stream */ 2971 i += id * XHCI_MAX_TRANSFERS; 2972 inext += id * XHCI_MAX_TRANSFERS; 2973 2974 /* compute terminating return address */ 2975 addr += (inext * sizeof(struct xhci_trb)); 2976 2977 /* compute link TRB pointer */ 2978 trb_link = td_last->td_trb + td_last->ntrb; 2979 2980 /* update next pointer of last link TRB */ 2981 trb_link->qwTrb0 = htole64(addr); 2982 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2983 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2984 XHCI_TRB_3_CYCLE_BIT | 2985 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2986 2987#ifdef USB_DEBUG 2988 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2989#endif 2990 usb_pc_cpu_flush(td_last->page_cache); 2991 2992 /* write ahead chain end marker */ 2993 2994 pepext->trb[inext].qwTrb0 = 0; 2995 pepext->trb[inext].dwTrb2 = 0; 2996 pepext->trb[inext].dwTrb3 = 0; 2997 2998 /* update next pointer of link TRB */ 2999 3000 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 3001 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 3002 3003#ifdef USB_DEBUG 3004 xhci_dump_trb(&pepext->trb[i]); 3005#endif 3006 usb_pc_cpu_flush(pepext->page_cache); 3007 3008 /* toggle cycle bit which activates the transfer chain */ 3009 3010 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 3011 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3012 3013 usb_pc_cpu_flush(pepext->page_cache); 3014 3015 DPRINTF("qh_pos = %u\n", i); 3016 3017 pepext->xfer[i] = xfer; 3018 3019 xfer->qh_pos = i; 3020 3021 xfer->flags_int.bandwidth_reclaimed = 1; 3022 3023 xhci_endpoint_doorbell(xfer); 3024 3025 return (0); 3026} 3027 3028static void 3029xhci_root_intr(struct xhci_softc *sc) 3030{ 3031 uint16_t i; 3032 3033 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3034 3035 /* clear any old interrupt data */ 3036 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3037 3038 for (i = 1; i <= sc->sc_noport; i++) { 3039 /* pick out CHANGE bits from the status register */ 3040 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3041 XHCI_PS_CSC | XHCI_PS_PEC | 3042 XHCI_PS_OCC | XHCI_PS_WRC | 3043 XHCI_PS_PRC | XHCI_PS_PLC | 3044 XHCI_PS_CEC)) { 3045 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3046 DPRINTF("port %d changed\n", i); 3047 } 3048 } 3049 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3050 sizeof(sc->sc_hub_idata)); 3051} 3052 3053/*------------------------------------------------------------------------* 3054 * xhci_device_done - XHCI done handler 3055 * 3056 * NOTE: This function can be called two times in a row on 3057 * the same USB transfer. From close and from interrupt. 3058 *------------------------------------------------------------------------*/ 3059static void 3060xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3061{ 3062 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3063 xfer, xfer->endpoint, error); 3064 3065 /* remove transfer from HW queue */ 3066 xhci_transfer_remove(xfer, error); 3067 3068 /* dequeue transfer and start next transfer */ 3069 usbd_transfer_done(xfer, error); 3070} 3071 3072/*------------------------------------------------------------------------* 3073 * XHCI data transfer support (generic type) 3074 *------------------------------------------------------------------------*/ 3075static void 3076xhci_device_generic_open(struct usb_xfer *xfer) 3077{ 3078 if (xfer->flags_int.isochronous_xfr) { 3079 switch (xfer->xroot->udev->speed) { 3080 case USB_SPEED_FULL: 3081 break; 3082 default: 3083 usb_hs_bandwidth_alloc(xfer); 3084 break; 3085 } 3086 } 3087} 3088 3089static void 3090xhci_device_generic_close(struct usb_xfer *xfer) 3091{ 3092 DPRINTF("\n"); 3093 3094 xhci_device_done(xfer, USB_ERR_CANCELLED); 3095 3096 if (xfer->flags_int.isochronous_xfr) { 3097 switch (xfer->xroot->udev->speed) { 3098 case USB_SPEED_FULL: 3099 break; 3100 default: 3101 usb_hs_bandwidth_free(xfer); 3102 break; 3103 } 3104 } 3105} 3106 3107static void 3108xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3109 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3110{ 3111 struct usb_xfer *xfer; 3112 3113 /* check if there is a current transfer */ 3114 xfer = ep->endpoint_q[stream_id].curr; 3115 if (xfer == NULL) 3116 return; 3117 3118 /* 3119 * Check if the current transfer is started and then pickup 3120 * the next one, if any. Else wait for next start event due to 3121 * block on failure feature. 3122 */ 3123 if (!xfer->flags_int.bandwidth_reclaimed) 3124 return; 3125 3126 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3127 if (xfer == NULL) { 3128 /* 3129 * In case of enter we have to consider that the 3130 * transfer is queued by the USB core after the enter 3131 * method is called. 3132 */ 3133 xfer = enter_xfer; 3134 3135 if (xfer == NULL) 3136 return; 3137 } 3138 3139 /* try to multi buffer */ 3140 xhci_transfer_insert(xfer); 3141} 3142 3143static void 3144xhci_device_generic_enter(struct usb_xfer *xfer) 3145{ 3146 DPRINTF("\n"); 3147 3148 /* set up TD's and QH */ 3149 xhci_setup_generic_chain(xfer); 3150 3151 xhci_device_generic_multi_enter(xfer->endpoint, 3152 xfer->stream_id, xfer); 3153} 3154 3155static void 3156xhci_device_generic_start(struct usb_xfer *xfer) 3157{ 3158 DPRINTF("\n"); 3159 3160 /* try to insert xfer on HW queue */ 3161 xhci_transfer_insert(xfer); 3162 3163 /* try to multi buffer */ 3164 xhci_device_generic_multi_enter(xfer->endpoint, 3165 xfer->stream_id, NULL); 3166 3167 /* add transfer last on interrupt queue */ 3168 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3169 3170 /* start timeout, if any */ 3171 if (xfer->timeout != 0) 3172 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3173} 3174 3175struct usb_pipe_methods xhci_device_generic_methods = 3176{ 3177 .open = xhci_device_generic_open, 3178 .close = xhci_device_generic_close, 3179 .enter = xhci_device_generic_enter, 3180 .start = xhci_device_generic_start, 3181}; 3182 3183/*------------------------------------------------------------------------* 3184 * xhci root HUB support 3185 *------------------------------------------------------------------------* 3186 * Simulate a hardware HUB by handling all the necessary requests. 3187 *------------------------------------------------------------------------*/ 3188 3189#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3190 3191static const 3192struct usb_device_descriptor xhci_devd = 3193{ 3194 .bLength = sizeof(xhci_devd), 3195 .bDescriptorType = UDESC_DEVICE, /* type */ 3196 HSETW(.bcdUSB, 0x0300), /* USB version */ 3197 .bDeviceClass = UDCLASS_HUB, /* class */ 3198 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3199 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3200 .bMaxPacketSize = 9, /* max packet size */ 3201 HSETW(.idVendor, 0x0000), /* vendor */ 3202 HSETW(.idProduct, 0x0000), /* product */ 3203 HSETW(.bcdDevice, 0x0100), /* device version */ 3204 .iManufacturer = 1, 3205 .iProduct = 2, 3206 .iSerialNumber = 0, 3207 .bNumConfigurations = 1, /* # of configurations */ 3208}; 3209 3210static const 3211struct xhci_bos_desc xhci_bosd = { 3212 .bosd = { 3213 .bLength = sizeof(xhci_bosd.bosd), 3214 .bDescriptorType = UDESC_BOS, 3215 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3216 .bNumDeviceCaps = 3, 3217 }, 3218 .usb2extd = { 3219 .bLength = sizeof(xhci_bosd.usb2extd), 3220 .bDescriptorType = 1, 3221 .bDevCapabilityType = 2, 3222 .bmAttributes[0] = 2, 3223 }, 3224 .usbdcd = { 3225 .bLength = sizeof(xhci_bosd.usbdcd), 3226 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3227 .bDevCapabilityType = 3, 3228 .bmAttributes = 0, /* XXX */ 3229 HSETW(.wSpeedsSupported, 0x000C), 3230 .bFunctionalitySupport = 8, 3231 .bU1DevExitLat = 255, /* dummy - not used */ 3232 .wU2DevExitLat = { 0x00, 0x08 }, 3233 }, 3234 .cidd = { 3235 .bLength = sizeof(xhci_bosd.cidd), 3236 .bDescriptorType = 1, 3237 .bDevCapabilityType = 4, 3238 .bReserved = 0, 3239 .bContainerID = 0, /* XXX */ 3240 }, 3241}; 3242 3243static const 3244struct xhci_config_desc xhci_confd = { 3245 .confd = { 3246 .bLength = sizeof(xhci_confd.confd), 3247 .bDescriptorType = UDESC_CONFIG, 3248 .wTotalLength[0] = sizeof(xhci_confd), 3249 .bNumInterface = 1, 3250 .bConfigurationValue = 1, 3251 .iConfiguration = 0, 3252 .bmAttributes = UC_SELF_POWERED, 3253 .bMaxPower = 0 /* max power */ 3254 }, 3255 .ifcd = { 3256 .bLength = sizeof(xhci_confd.ifcd), 3257 .bDescriptorType = UDESC_INTERFACE, 3258 .bNumEndpoints = 1, 3259 .bInterfaceClass = UICLASS_HUB, 3260 .bInterfaceSubClass = UISUBCLASS_HUB, 3261 .bInterfaceProtocol = 0, 3262 }, 3263 .endpd = { 3264 .bLength = sizeof(xhci_confd.endpd), 3265 .bDescriptorType = UDESC_ENDPOINT, 3266 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3267 .bmAttributes = UE_INTERRUPT, 3268 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3269 .bInterval = 255, 3270 }, 3271 .endpcd = { 3272 .bLength = sizeof(xhci_confd.endpcd), 3273 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3274 .bMaxBurst = 0, 3275 .bmAttributes = 0, 3276 }, 3277}; 3278 3279static const 3280struct usb_hub_ss_descriptor xhci_hubd = { 3281 .bLength = sizeof(xhci_hubd), 3282 .bDescriptorType = UDESC_SS_HUB, 3283}; 3284 3285static usb_error_t 3286xhci_roothub_exec(struct usb_device *udev, 3287 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3288{ 3289 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3290 const char *str_ptr; 3291 const void *ptr; 3292 uint32_t port; 3293 uint32_t v; 3294 uint16_t len; 3295 uint16_t i; 3296 uint16_t value; 3297 uint16_t index; 3298 uint8_t j; 3299 usb_error_t err; 3300 3301 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3302 3303 /* buffer reset */ 3304 ptr = (const void *)&sc->sc_hub_desc; 3305 len = 0; 3306 err = 0; 3307 3308 value = UGETW(req->wValue); 3309 index = UGETW(req->wIndex); 3310 3311 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3312 "wValue=0x%04x wIndex=0x%04x\n", 3313 req->bmRequestType, req->bRequest, 3314 UGETW(req->wLength), value, index); 3315 3316#define C(x,y) ((x) | ((y) << 8)) 3317 switch (C(req->bRequest, req->bmRequestType)) { 3318 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3319 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3320 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3321 /* 3322 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3323 * for the integrated root hub. 3324 */ 3325 break; 3326 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3327 len = 1; 3328 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3329 break; 3330 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3331 switch (value >> 8) { 3332 case UDESC_DEVICE: 3333 if ((value & 0xff) != 0) { 3334 err = USB_ERR_IOERROR; 3335 goto done; 3336 } 3337 len = sizeof(xhci_devd); 3338 ptr = (const void *)&xhci_devd; 3339 break; 3340 3341 case UDESC_BOS: 3342 if ((value & 0xff) != 0) { 3343 err = USB_ERR_IOERROR; 3344 goto done; 3345 } 3346 len = sizeof(xhci_bosd); 3347 ptr = (const void *)&xhci_bosd; 3348 break; 3349 3350 case UDESC_CONFIG: 3351 if ((value & 0xff) != 0) { 3352 err = USB_ERR_IOERROR; 3353 goto done; 3354 } 3355 len = sizeof(xhci_confd); 3356 ptr = (const void *)&xhci_confd; 3357 break; 3358 3359 case UDESC_STRING: 3360 switch (value & 0xff) { 3361 case 0: /* Language table */ 3362 str_ptr = "\001"; 3363 break; 3364 3365 case 1: /* Vendor */ 3366 str_ptr = sc->sc_vendor; 3367 break; 3368 3369 case 2: /* Product */ 3370 str_ptr = "XHCI root HUB"; 3371 break; 3372 3373 default: 3374 str_ptr = ""; 3375 break; 3376 } 3377 3378 len = usb_make_str_desc( 3379 sc->sc_hub_desc.temp, 3380 sizeof(sc->sc_hub_desc.temp), 3381 str_ptr); 3382 break; 3383 3384 default: 3385 err = USB_ERR_IOERROR; 3386 goto done; 3387 } 3388 break; 3389 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3390 len = 1; 3391 sc->sc_hub_desc.temp[0] = 0; 3392 break; 3393 case C(UR_GET_STATUS, UT_READ_DEVICE): 3394 len = 2; 3395 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3396 break; 3397 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3398 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3399 len = 2; 3400 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3401 break; 3402 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3403 if (value >= XHCI_MAX_DEVICES) { 3404 err = USB_ERR_IOERROR; 3405 goto done; 3406 } 3407 break; 3408 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3409 if (value != 0 && value != 1) { 3410 err = USB_ERR_IOERROR; 3411 goto done; 3412 } 3413 sc->sc_conf = value; 3414 break; 3415 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3416 break; 3417 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3418 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3419 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3420 err = USB_ERR_IOERROR; 3421 goto done; 3422 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3423 break; 3424 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3425 break; 3426 /* Hub requests */ 3427 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3428 break; 3429 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3430 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3431 3432 if ((index < 1) || 3433 (index > sc->sc_noport)) { 3434 err = USB_ERR_IOERROR; 3435 goto done; 3436 } 3437 port = XHCI_PORTSC(index); 3438 3439 v = XREAD4(sc, oper, port); 3440 i = XHCI_PS_PLS_GET(v); 3441 v &= ~XHCI_PS_CLEAR; 3442 3443 switch (value) { 3444 case UHF_C_BH_PORT_RESET: 3445 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3446 break; 3447 case UHF_C_PORT_CONFIG_ERROR: 3448 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3449 break; 3450 case UHF_C_PORT_SUSPEND: 3451 case UHF_C_PORT_LINK_STATE: 3452 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3453 break; 3454 case UHF_C_PORT_CONNECTION: 3455 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3456 break; 3457 case UHF_C_PORT_ENABLE: 3458 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3459 break; 3460 case UHF_C_PORT_OVER_CURRENT: 3461 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3462 break; 3463 case UHF_C_PORT_RESET: 3464 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3465 break; 3466 case UHF_PORT_ENABLE: 3467 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3468 break; 3469 case UHF_PORT_POWER: 3470 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3471 break; 3472 case UHF_PORT_INDICATOR: 3473 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3474 break; 3475 case UHF_PORT_SUSPEND: 3476 3477 /* U3 -> U15 */ 3478 if (i == 3) { 3479 XWRITE4(sc, oper, port, v | 3480 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3481 } 3482 3483 /* wait 20ms for resume sequence to complete */ 3484 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3485 3486 /* U0 */ 3487 XWRITE4(sc, oper, port, v | 3488 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3489 break; 3490 default: 3491 err = USB_ERR_IOERROR; 3492 goto done; 3493 } 3494 break; 3495 3496 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3497 if ((value & 0xff) != 0) { 3498 err = USB_ERR_IOERROR; 3499 goto done; 3500 } 3501 3502 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3503 3504 sc->sc_hub_desc.hubd = xhci_hubd; 3505 3506 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3507 3508 if (XHCI_HCS0_PPC(v)) 3509 i = UHD_PWR_INDIVIDUAL; 3510 else 3511 i = UHD_PWR_GANGED; 3512 3513 if (XHCI_HCS0_PIND(v)) 3514 i |= UHD_PORT_IND; 3515 3516 i |= UHD_OC_INDIVIDUAL; 3517 3518 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3519 3520 /* see XHCI section 5.4.9: */ 3521 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3522 3523 for (j = 1; j <= sc->sc_noport; j++) { 3524 3525 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3526 if (v & XHCI_PS_DR) { 3527 sc->sc_hub_desc.hubd. 3528 DeviceRemovable[j / 8] |= 1U << (j % 8); 3529 } 3530 } 3531 len = sc->sc_hub_desc.hubd.bLength; 3532 break; 3533 3534 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3535 len = 16; 3536 memset(sc->sc_hub_desc.temp, 0, 16); 3537 break; 3538 3539 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3540 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3541 3542 if ((index < 1) || 3543 (index > sc->sc_noport)) { 3544 err = USB_ERR_IOERROR; 3545 goto done; 3546 } 3547 3548 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3549 3550 DPRINTFN(9, "port status=0x%08x\n", v); 3551 3552 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3553 3554 switch (XHCI_PS_SPEED_GET(v)) { 3555 case 3: 3556 i |= UPS_HIGH_SPEED; 3557 break; 3558 case 2: 3559 i |= UPS_LOW_SPEED; 3560 break; 3561 case 1: 3562 /* FULL speed */ 3563 break; 3564 default: 3565 i |= UPS_OTHER_SPEED; 3566 break; 3567 } 3568 3569 if (v & XHCI_PS_CCS) 3570 i |= UPS_CURRENT_CONNECT_STATUS; 3571 if (v & XHCI_PS_PED) 3572 i |= UPS_PORT_ENABLED; 3573 if (v & XHCI_PS_OCA) 3574 i |= UPS_OVERCURRENT_INDICATOR; 3575 if (v & XHCI_PS_PR) 3576 i |= UPS_RESET; 3577#if 0 3578 if (v & XHCI_PS_PP) 3579 /* XXX undefined */ 3580#endif 3581 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3582 3583 i = 0; 3584 if (v & XHCI_PS_CSC) 3585 i |= UPS_C_CONNECT_STATUS; 3586 if (v & XHCI_PS_PEC) 3587 i |= UPS_C_PORT_ENABLED; 3588 if (v & XHCI_PS_OCC) 3589 i |= UPS_C_OVERCURRENT_INDICATOR; 3590 if (v & XHCI_PS_WRC) 3591 i |= UPS_C_BH_PORT_RESET; 3592 if (v & XHCI_PS_PRC) 3593 i |= UPS_C_PORT_RESET; 3594 if (v & XHCI_PS_PLC) 3595 i |= UPS_C_PORT_LINK_STATE; 3596 if (v & XHCI_PS_CEC) 3597 i |= UPS_C_PORT_CONFIG_ERROR; 3598 3599 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3600 len = sizeof(sc->sc_hub_desc.ps); 3601 break; 3602 3603 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3604 err = USB_ERR_IOERROR; 3605 goto done; 3606 3607 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3608 break; 3609 3610 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3611 3612 i = index >> 8; 3613 index &= 0x00FF; 3614 3615 if ((index < 1) || 3616 (index > sc->sc_noport)) { 3617 err = USB_ERR_IOERROR; 3618 goto done; 3619 } 3620 3621 port = XHCI_PORTSC(index); 3622 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3623 3624 switch (value) { 3625 case UHF_PORT_U1_TIMEOUT: 3626 if (XHCI_PS_SPEED_GET(v) != 4) { 3627 err = USB_ERR_IOERROR; 3628 goto done; 3629 } 3630 port = XHCI_PORTPMSC(index); 3631 v = XREAD4(sc, oper, port); 3632 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3633 v |= XHCI_PM3_U1TO_SET(i); 3634 XWRITE4(sc, oper, port, v); 3635 break; 3636 case UHF_PORT_U2_TIMEOUT: 3637 if (XHCI_PS_SPEED_GET(v) != 4) { 3638 err = USB_ERR_IOERROR; 3639 goto done; 3640 } 3641 port = XHCI_PORTPMSC(index); 3642 v = XREAD4(sc, oper, port); 3643 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3644 v |= XHCI_PM3_U2TO_SET(i); 3645 XWRITE4(sc, oper, port, v); 3646 break; 3647 case UHF_BH_PORT_RESET: 3648 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3649 break; 3650 case UHF_PORT_LINK_STATE: 3651 XWRITE4(sc, oper, port, v | 3652 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3653 /* 4ms settle time */ 3654 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3655 break; 3656 case UHF_PORT_ENABLE: 3657 DPRINTFN(3, "set port enable %d\n", index); 3658 break; 3659 case UHF_PORT_SUSPEND: 3660 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3661 j = XHCI_PS_SPEED_GET(v); 3662 if ((j < 1) || (j > 3)) { 3663 /* non-supported speed */ 3664 err = USB_ERR_IOERROR; 3665 goto done; 3666 } 3667 XWRITE4(sc, oper, port, v | 3668 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3669 break; 3670 case UHF_PORT_RESET: 3671 DPRINTFN(6, "reset port %d\n", index); 3672 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3673 break; 3674 case UHF_PORT_POWER: 3675 DPRINTFN(3, "set port power %d\n", index); 3676 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3677 break; 3678 case UHF_PORT_TEST: 3679 DPRINTFN(3, "set port test %d\n", index); 3680 break; 3681 case UHF_PORT_INDICATOR: 3682 DPRINTFN(3, "set port indicator %d\n", index); 3683 3684 v &= ~XHCI_PS_PIC_SET(3); 3685 v |= XHCI_PS_PIC_SET(1); 3686 3687 XWRITE4(sc, oper, port, v); 3688 break; 3689 default: 3690 err = USB_ERR_IOERROR; 3691 goto done; 3692 } 3693 break; 3694 3695 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3696 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3697 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3698 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3699 break; 3700 default: 3701 err = USB_ERR_IOERROR; 3702 goto done; 3703 } 3704done: 3705 *plength = len; 3706 *pptr = ptr; 3707 return (err); 3708} 3709 3710static void 3711xhci_xfer_setup(struct usb_setup_params *parm) 3712{ 3713 struct usb_page_search page_info; 3714 struct usb_page_cache *pc; 3715 struct xhci_softc *sc; 3716 struct usb_xfer *xfer; 3717 void *last_obj; 3718 uint32_t ntd; 3719 uint32_t n; 3720 3721 sc = XHCI_BUS2SC(parm->udev->bus); 3722 xfer = parm->curr_xfer; 3723 3724 /* 3725 * The proof for the "ntd" formula is illustrated like this: 3726 * 3727 * +------------------------------------+ 3728 * | | 3729 * | |remainder -> | 3730 * | +-----+---+ | 3731 * | | xxx | x | frm 0 | 3732 * | +-----+---++ | 3733 * | | xxx | xx | frm 1 | 3734 * | +-----+----+ | 3735 * | ... | 3736 * +------------------------------------+ 3737 * 3738 * "xxx" means a completely full USB transfer descriptor 3739 * 3740 * "x" and "xx" means a short USB packet 3741 * 3742 * For the remainder of an USB transfer modulo 3743 * "max_data_length" we need two USB transfer descriptors. 3744 * One to transfer the remaining data and one to finalise with 3745 * a zero length packet in case the "force_short_xfer" flag is 3746 * set. We only need two USB transfer descriptors in the case 3747 * where the transfer length of the first one is a factor of 3748 * "max_frame_size". The rest of the needed USB transfer 3749 * descriptors is given by the buffer size divided by the 3750 * maximum data payload. 3751 */ 3752 parm->hc_max_packet_size = 0x400; 3753 parm->hc_max_packet_count = 16 * 3; 3754 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3755 3756 xfer->flags_int.bdma_enable = 1; 3757 3758 usbd_transfer_setup_sub(parm); 3759 3760 if (xfer->flags_int.isochronous_xfr) { 3761 ntd = ((1 * xfer->nframes) 3762 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3763 } else if (xfer->flags_int.control_xfr) { 3764 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3765 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3766 } else { 3767 ntd = ((2 * xfer->nframes) 3768 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3769 } 3770 3771alloc_dma_set: 3772 3773 if (parm->err) 3774 return; 3775 3776 /* 3777 * Allocate queue heads and transfer descriptors 3778 */ 3779 last_obj = NULL; 3780 3781 if (usbd_transfer_setup_sub_malloc( 3782 parm, &pc, sizeof(struct xhci_td), 3783 XHCI_TD_ALIGN, ntd)) { 3784 parm->err = USB_ERR_NOMEM; 3785 return; 3786 } 3787 if (parm->buf) { 3788 for (n = 0; n != ntd; n++) { 3789 struct xhci_td *td; 3790 3791 usbd_get_page(pc + n, 0, &page_info); 3792 3793 td = page_info.buffer; 3794 3795 /* init TD */ 3796 td->td_self = page_info.physaddr; 3797 td->obj_next = last_obj; 3798 td->page_cache = pc + n; 3799 3800 last_obj = td; 3801 3802 usb_pc_cpu_flush(pc + n); 3803 } 3804 } 3805 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3806 3807 if (!xfer->flags_int.curr_dma_set) { 3808 xfer->flags_int.curr_dma_set = 1; 3809 goto alloc_dma_set; 3810 } 3811} 3812 3813static usb_error_t 3814xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3815{ 3816 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3817 struct usb_page_search buf_inp; 3818 struct usb_device *udev; 3819 struct xhci_endpoint_ext *pepext; 3820 struct usb_endpoint_descriptor *edesc; 3821 struct usb_page_cache *pcinp; 3822 usb_error_t err; 3823 usb_stream_t stream_id; 3824 uint32_t mask; 3825 uint8_t index; 3826 uint8_t epno; 3827 3828 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3829 xfer->endpoint->edesc); 3830 3831 udev = xfer->xroot->udev; 3832 index = udev->controller_slot_id; 3833 3834 pcinp = &sc->sc_hw.devs[index].input_pc; 3835 3836 usbd_get_page(pcinp, 0, &buf_inp); 3837 3838 edesc = xfer->endpoint->edesc; 3839 3840 epno = edesc->bEndpointAddress; 3841 stream_id = xfer->stream_id; 3842 3843 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3844 epno |= UE_DIR_IN; 3845 3846 epno = XHCI_EPNO2EPID(epno); 3847 3848 if (epno == 0) 3849 return (USB_ERR_NO_PIPE); /* invalid */ 3850 3851 XHCI_CMD_LOCK(sc); 3852 3853 /* configure endpoint */ 3854 3855 err = xhci_configure_endpoint_by_xfer(xfer); 3856 3857 if (err != 0) { 3858 XHCI_CMD_UNLOCK(sc); 3859 return (err); 3860 } 3861 3862 /* 3863 * Get the endpoint into the stopped state according to the 3864 * endpoint context state diagram in the XHCI specification: 3865 */ 3866 3867 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3868 3869 if (err != 0) 3870 DPRINTF("Could not stop endpoint %u\n", epno); 3871 3872 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3873 3874 if (err != 0) 3875 DPRINTF("Could not reset endpoint %u\n", epno); 3876 3877 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3878 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3879 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3880 stream_id, epno, index); 3881 3882 if (err != 0) 3883 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3884 3885 /* 3886 * Get the endpoint into the running state according to the 3887 * endpoint context state diagram in the XHCI specification: 3888 */ 3889 3890 mask = (1U << epno); 3891 xhci_configure_mask(udev, mask | 1U, 0); 3892 3893 if (!(sc->sc_hw.devs[index].ep_configured & mask)) { 3894 sc->sc_hw.devs[index].ep_configured |= mask; 3895 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3896 } else { 3897 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3898 } 3899 3900 if (err != 0) { 3901 DPRINTF("Could not configure " 3902 "endpoint %u at slot %u.\n", epno, index); 3903 } 3904 XHCI_CMD_UNLOCK(sc); 3905 3906 return (0); 3907} 3908 3909static void 3910xhci_xfer_unsetup(struct usb_xfer *xfer) 3911{ 3912 return; 3913} 3914 3915static void 3916xhci_start_dma_delay(struct usb_xfer *xfer) 3917{ 3918 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3919 3920 /* put transfer on interrupt queue (again) */ 3921 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3922 3923 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3924 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3925} 3926 3927static void 3928xhci_configure_msg(struct usb_proc_msg *pm) 3929{ 3930 struct xhci_softc *sc; 3931 struct xhci_endpoint_ext *pepext; 3932 struct usb_xfer *xfer; 3933 3934 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3935 3936restart: 3937 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3938 3939 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3940 xfer->endpoint->edesc); 3941 3942 if ((pepext->trb_halted != 0) || 3943 (pepext->trb_running == 0)) { 3944 3945 uint16_t i; 3946 3947 /* clear halted and running */ 3948 pepext->trb_halted = 0; 3949 pepext->trb_running = 0; 3950 3951 /* nuke remaining buffered transfers */ 3952 3953 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3954 XHCI_MAX_STREAMS); i++) { 3955 /* 3956 * NOTE: We need to use the timeout 3957 * error code here else existing 3958 * isochronous clients can get 3959 * confused: 3960 */ 3961 if (pepext->xfer[i] != NULL) { 3962 xhci_device_done(pepext->xfer[i], 3963 USB_ERR_TIMEOUT); 3964 } 3965 } 3966 3967 /* 3968 * NOTE: The USB transfer cannot vanish in 3969 * this state! 3970 */ 3971 3972 USB_BUS_UNLOCK(&sc->sc_bus); 3973 3974 xhci_configure_reset_endpoint(xfer); 3975 3976 USB_BUS_LOCK(&sc->sc_bus); 3977 3978 /* check if halted is still cleared */ 3979 if (pepext->trb_halted == 0) { 3980 pepext->trb_running = 1; 3981 memset(pepext->trb_index, 0, 3982 sizeof(pepext->trb_index)); 3983 } 3984 goto restart; 3985 } 3986 3987 if (xfer->flags_int.did_dma_delay) { 3988 3989 /* remove transfer from interrupt queue (again) */ 3990 usbd_transfer_dequeue(xfer); 3991 3992 /* we are finally done */ 3993 usb_dma_delay_done_cb(xfer); 3994 3995 /* queue changed - restart */ 3996 goto restart; 3997 } 3998 } 3999 4000 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4001 4002 /* try to insert xfer on HW queue */ 4003 xhci_transfer_insert(xfer); 4004 4005 /* try to multi buffer */ 4006 xhci_device_generic_multi_enter(xfer->endpoint, 4007 xfer->stream_id, NULL); 4008 } 4009} 4010 4011static void 4012xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4013 struct usb_endpoint *ep) 4014{ 4015 struct xhci_endpoint_ext *pepext; 4016 4017 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 4018 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 4019 4020 if (udev->parent_hub == NULL) { 4021 /* root HUB has special endpoint handling */ 4022 return; 4023 } 4024 4025 ep->methods = &xhci_device_generic_methods; 4026 4027 pepext = xhci_get_endpoint_ext(udev, edesc); 4028 4029 USB_BUS_LOCK(udev->bus); 4030 pepext->trb_halted = 1; 4031 pepext->trb_running = 0; 4032 USB_BUS_UNLOCK(udev->bus); 4033} 4034 4035static void 4036xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4037{ 4038 4039} 4040 4041static void 4042xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4043{ 4044 struct xhci_endpoint_ext *pepext; 4045 4046 DPRINTF("\n"); 4047 4048 if (udev->flags.usb_mode != USB_MODE_HOST) { 4049 /* not supported */ 4050 return; 4051 } 4052 if (udev->parent_hub == NULL) { 4053 /* root HUB has special endpoint handling */ 4054 return; 4055 } 4056 4057 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4058 4059 USB_BUS_LOCK(udev->bus); 4060 pepext->trb_halted = 1; 4061 pepext->trb_running = 0; 4062 USB_BUS_UNLOCK(udev->bus); 4063} 4064 4065static usb_error_t 4066xhci_device_init(struct usb_device *udev) 4067{ 4068 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4069 usb_error_t err; 4070 uint8_t temp; 4071 4072 /* no init for root HUB */ 4073 if (udev->parent_hub == NULL) 4074 return (0); 4075 4076 XHCI_CMD_LOCK(sc); 4077 4078 /* set invalid default */ 4079 4080 udev->controller_slot_id = sc->sc_noslot + 1; 4081 4082 /* try to get a new slot ID from the XHCI */ 4083 4084 err = xhci_cmd_enable_slot(sc, &temp); 4085 4086 if (err) { 4087 XHCI_CMD_UNLOCK(sc); 4088 return (err); 4089 } 4090 4091 if (temp > sc->sc_noslot) { 4092 XHCI_CMD_UNLOCK(sc); 4093 return (USB_ERR_BAD_ADDRESS); 4094 } 4095 4096 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4097 DPRINTF("slot %u already allocated.\n", temp); 4098 XHCI_CMD_UNLOCK(sc); 4099 return (USB_ERR_BAD_ADDRESS); 4100 } 4101 4102 /* store slot ID for later reference */ 4103 4104 udev->controller_slot_id = temp; 4105 4106 /* reset data structure */ 4107 4108 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4109 4110 /* set mark slot allocated */ 4111 4112 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4113 4114 err = xhci_alloc_device_ext(udev); 4115 4116 XHCI_CMD_UNLOCK(sc); 4117 4118 /* get device into default state */ 4119 4120 if (err == 0) 4121 err = xhci_set_address(udev, NULL, 0); 4122 4123 return (err); 4124} 4125 4126static void 4127xhci_device_uninit(struct usb_device *udev) 4128{ 4129 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4130 uint8_t index; 4131 4132 /* no init for root HUB */ 4133 if (udev->parent_hub == NULL) 4134 return; 4135 4136 XHCI_CMD_LOCK(sc); 4137 4138 index = udev->controller_slot_id; 4139 4140 if (index <= sc->sc_noslot) { 4141 xhci_cmd_disable_slot(sc, index); 4142 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4143 4144 /* free device extension */ 4145 xhci_free_device_ext(udev); 4146 } 4147 4148 XHCI_CMD_UNLOCK(sc); 4149} 4150 4151static void 4152xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4153{ 4154 /* 4155 * Wait until the hardware has finished any possible use of 4156 * the transfer descriptor(s) 4157 */ 4158 *pus = 2048; /* microseconds */ 4159} 4160 4161static void 4162xhci_device_resume(struct usb_device *udev) 4163{ 4164 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4165 uint8_t index; 4166 uint8_t n; 4167 uint8_t p; 4168 4169 DPRINTF("\n"); 4170 4171 /* check for root HUB */ 4172 if (udev->parent_hub == NULL) 4173 return; 4174 4175 index = udev->controller_slot_id; 4176 4177 XHCI_CMD_LOCK(sc); 4178 4179 /* blindly resume all endpoints */ 4180 4181 USB_BUS_LOCK(udev->bus); 4182 4183 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4184 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4185 XWRITE4(sc, door, XHCI_DOORBELL(index), 4186 n | XHCI_DB_SID_SET(p)); 4187 } 4188 } 4189 4190 USB_BUS_UNLOCK(udev->bus); 4191 4192 XHCI_CMD_UNLOCK(sc); 4193} 4194 4195static void 4196xhci_device_suspend(struct usb_device *udev) 4197{ 4198 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4199 uint8_t index; 4200 uint8_t n; 4201 usb_error_t err; 4202 4203 DPRINTF("\n"); 4204 4205 /* check for root HUB */ 4206 if (udev->parent_hub == NULL) 4207 return; 4208 4209 index = udev->controller_slot_id; 4210 4211 XHCI_CMD_LOCK(sc); 4212 4213 /* blindly suspend all endpoints */ 4214 4215 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4216 err = xhci_cmd_stop_ep(sc, 1, n, index); 4217 if (err != 0) { 4218 DPRINTF("Failed to suspend endpoint " 4219 "%u on slot %u (ignored).\n", n, index); 4220 } 4221 } 4222 4223 XHCI_CMD_UNLOCK(sc); 4224} 4225 4226static void 4227xhci_set_hw_power(struct usb_bus *bus) 4228{ 4229 DPRINTF("\n"); 4230} 4231 4232static void 4233xhci_device_state_change(struct usb_device *udev) 4234{ 4235 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4236 struct usb_page_search buf_inp; 4237 usb_error_t err; 4238 uint8_t index; 4239 4240 /* check for root HUB */ 4241 if (udev->parent_hub == NULL) 4242 return; 4243 4244 index = udev->controller_slot_id; 4245 4246 DPRINTF("\n"); 4247 4248 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4249 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4250 &sc->sc_hw.devs[index].tt); 4251 if (err != 0) 4252 sc->sc_hw.devs[index].nports = 0; 4253 } 4254 4255 XHCI_CMD_LOCK(sc); 4256 4257 switch (usb_get_device_state(udev)) { 4258 case USB_STATE_POWERED: 4259 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4260 break; 4261 4262 /* set default state */ 4263 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4264 sc->sc_hw.devs[index].ep_configured = 3U; 4265 4266 /* reset number of contexts */ 4267 sc->sc_hw.devs[index].context_num = 0; 4268 4269 err = xhci_cmd_reset_dev(sc, index); 4270 4271 if (err != 0) { 4272 DPRINTF("Device reset failed " 4273 "for slot %u.\n", index); 4274 } 4275 break; 4276 4277 case USB_STATE_ADDRESSED: 4278 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4279 break; 4280 4281 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4282 sc->sc_hw.devs[index].ep_configured = 3U; 4283 4284 /* set configure mask to slot only */ 4285 xhci_configure_mask(udev, 1, 0); 4286 4287 /* deconfigure all endpoints, except EP0 */ 4288 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4289 4290 if (err) { 4291 DPRINTF("Failed to deconfigure " 4292 "slot %u.\n", index); 4293 } 4294 break; 4295 4296 case USB_STATE_CONFIGURED: 4297 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { 4298 /* deconfigure all endpoints, except EP0 */ 4299 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4300 4301 if (err) { 4302 DPRINTF("Failed to deconfigure " 4303 "slot %u.\n", index); 4304 } 4305 } 4306 4307 /* set configured state */ 4308 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4309 sc->sc_hw.devs[index].ep_configured = 3U; 4310 4311 /* reset number of contexts */ 4312 sc->sc_hw.devs[index].context_num = 0; 4313 4314 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4315 4316 xhci_configure_mask(udev, 3, 0); 4317 4318 err = xhci_configure_device(udev); 4319 if (err != 0) { 4320 DPRINTF("Could not configure device " 4321 "at slot %u.\n", index); 4322 } 4323 4324 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4325 if (err != 0) { 4326 DPRINTF("Could not evaluate device " 4327 "context at slot %u.\n", index); 4328 } 4329 break; 4330 4331 default: 4332 break; 4333 } 4334 XHCI_CMD_UNLOCK(sc); 4335} 4336 4337static usb_error_t 4338xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4339 uint8_t ep_mode) 4340{ 4341 switch (ep_mode) { 4342 case USB_EP_MODE_DEFAULT: 4343 return (0); 4344 case USB_EP_MODE_STREAMS: 4345 if (xhcistreams == 0 || 4346 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4347 udev->speed != USB_SPEED_SUPER) 4348 return (USB_ERR_INVAL); 4349 return (0); 4350 default: 4351 return (USB_ERR_INVAL); 4352 } 4353} 4354 4355struct usb_bus_methods xhci_bus_methods = { 4356 .endpoint_init = xhci_ep_init, 4357 .endpoint_uninit = xhci_ep_uninit, 4358 .xfer_setup = xhci_xfer_setup, 4359 .xfer_unsetup = xhci_xfer_unsetup, 4360 .get_dma_delay = xhci_get_dma_delay, 4361 .device_init = xhci_device_init, 4362 .device_uninit = xhci_device_uninit, 4363 .device_resume = xhci_device_resume, 4364 .device_suspend = xhci_device_suspend, 4365 .set_hw_power = xhci_set_hw_power, 4366 .roothub_exec = xhci_roothub_exec, 4367 .xfer_poll = xhci_do_poll, 4368 .start_dma_delay = xhci_start_dma_delay, 4369 .set_address = xhci_set_address, 4370 .clear_stall = xhci_ep_clear_stall, 4371 .device_state_change = xhci_device_state_change, 4372 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4373 .set_endpoint_mode = xhci_set_endpoint_mode, 4374}; 4375