1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/dev/uart/uart_dev_lpc.c 338809 2018-09-19 19:54:13Z mav $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35#include <machine/fdt.h> 36 37#include <dev/uart/uart.h> 38#include <dev/uart/uart_cpu.h> 39#include <dev/uart/uart_cpu_fdt.h> 40#include <dev/uart/uart_bus.h> 41 42#include <dev/ic/ns16550.h> 43#include <arm/lpc/lpcreg.h> 44 45#include "uart_if.h" 46 47#define DEFAULT_RCLK (13 * 1000 * 1000) 48 49static bus_space_handle_t bsh_clkpwr; 50 51#define lpc_ns8250_get_clkreg(_bas, _reg) \ 52 bus_space_read_4(fdtbus_bs_tag, bsh_clkpwr, (_reg)) 53#define lpc_ns8250_set_clkreg(_bas, _reg, _val) \ 54 bus_space_write_4(fdtbus_bs_tag, bsh_clkpwr, (_reg), (_val)) 55 56/* 57 * Clear pending interrupts. THRE is cleared by reading IIR. Data 58 * that may have been received gets lost here. 59 */ 60static void 61lpc_ns8250_clrint(struct uart_bas *bas) 62{ 63 uint8_t iir, lsr; 64 65 iir = uart_getreg(bas, REG_IIR); 66 while ((iir & IIR_NOPEND) == 0) { 67 iir &= IIR_IMASK; 68 if (iir == IIR_RLS) { 69 lsr = uart_getreg(bas, REG_LSR); 70 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 71 (void)uart_getreg(bas, REG_DATA); 72 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 73 (void)uart_getreg(bas, REG_DATA); 74 else if (iir == IIR_MLSC) 75 (void)uart_getreg(bas, REG_MSR); 76 uart_barrier(bas); 77 iir = uart_getreg(bas, REG_IIR); 78 } 79} 80 81static int 82lpc_ns8250_delay(struct uart_bas *bas) 83{ 84 uint32_t uclk; 85 int x, y; 86 87 uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK); 88 89 x = (uclk >> 8) & 0xff; 90 y = uclk & 0xff; 91 92 return (16000000 / (bas->rclk * x / y)); 93} 94 95static void 96lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y) 97{ 98 99 switch (baudrate) { 100 case 2400: 101 *x = 1; 102 *y = 255; 103 return; 104 case 4800: 105 *x = 1; 106 *y = 169; 107 return; 108 case 9600: 109 *x = 3; 110 *y = 254; 111 return; 112 case 19200: 113 *x = 3; 114 *y = 127; 115 return; 116 case 38400: 117 *x = 6; 118 *y = 127; 119 return; 120 case 57600: 121 *x = 9; 122 *y = 127; 123 return; 124 default: 125 case 115200: 126 *x = 19; 127 *y = 134; 128 return; 129 case 230400: 130 *x = 19; 131 *y = 67; 132 return; 133 case 460800: 134 *x = 38; 135 *y = 67; 136 return; 137 } 138} 139 140static int 141lpc_ns8250_drain(struct uart_bas *bas, int what) 142{ 143 int delay, limit; 144 145 delay = lpc_ns8250_delay(bas); 146 147 if (what & UART_DRAIN_TRANSMITTER) { 148 /* 149 * Pick an arbitrary high limit to avoid getting stuck in 150 * an infinite loop when the hardware is broken. Make the 151 * limit high enough to handle large FIFOs. 152 */ 153 limit = 10*1024; 154 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 155 DELAY(delay); 156 if (limit == 0) { 157 /* printf("lpc_ns8250: transmitter appears stuck... "); */ 158 return (EIO); 159 } 160 } 161 162 if (what & UART_DRAIN_RECEIVER) { 163 /* 164 * Pick an arbitrary high limit to avoid getting stuck in 165 * an infinite loop when the hardware is broken. Make the 166 * limit high enough to handle large FIFOs and integrated 167 * UARTs. The HP rx2600 for example has 3 UARTs on the 168 * management board that tend to get a lot of data send 169 * to it when the UART is first activated. 170 */ 171 limit=10*4096; 172 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 173 (void)uart_getreg(bas, REG_DATA); 174 uart_barrier(bas); 175 DELAY(delay << 2); 176 } 177 if (limit == 0) { 178 /* printf("lpc_ns8250: receiver appears broken... "); */ 179 return (EIO); 180 } 181 } 182 183 return (0); 184} 185 186/* 187 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 188 * drained. WARNING: this function clobbers the FIFO setting! 189 */ 190static void 191lpc_ns8250_flush(struct uart_bas *bas, int what) 192{ 193 uint8_t fcr; 194 195 fcr = FCR_ENABLE; 196 if (what & UART_FLUSH_TRANSMITTER) 197 fcr |= FCR_XMT_RST; 198 if (what & UART_FLUSH_RECEIVER) 199 fcr |= FCR_RCV_RST; 200 uart_setreg(bas, REG_FCR, fcr); 201 uart_barrier(bas); 202} 203 204static int 205lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 206 int parity) 207{ 208 int xdiv, ydiv; 209 uint8_t lcr; 210 211 lcr = 0; 212 if (databits >= 8) 213 lcr |= LCR_8BITS; 214 else if (databits == 7) 215 lcr |= LCR_7BITS; 216 else if (databits == 6) 217 lcr |= LCR_6BITS; 218 else 219 lcr |= LCR_5BITS; 220 if (stopbits > 1) 221 lcr |= LCR_STOPB; 222 lcr |= parity << 3; 223 224 /* Set baudrate. */ 225 if (baudrate > 0) { 226 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 227 uart_barrier(bas); 228 uart_setreg(bas, REG_DLL, 0x00); 229 uart_setreg(bas, REG_DLH, 0x00); 230 uart_barrier(bas); 231 232 lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv); 233 lpc_ns8250_set_clkreg(bas, 234 LPC_CLKPWR_UART_U5CLK, 235 LPC_CLKPWR_UART_UCLK_X(xdiv) | 236 LPC_CLKPWR_UART_UCLK_Y(ydiv)); 237 } 238 239 /* Set LCR and clear DLAB. */ 240 uart_setreg(bas, REG_LCR, lcr); 241 uart_barrier(bas); 242 return (0); 243} 244 245/* 246 * Low-level UART interface. 247 */ 248static int lpc_ns8250_probe(struct uart_bas *bas); 249static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int); 250static void lpc_ns8250_term(struct uart_bas *bas); 251static void lpc_ns8250_putc(struct uart_bas *bas, int); 252static int lpc_ns8250_rxready(struct uart_bas *bas); 253static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *); 254 255static struct uart_ops uart_lpc_ns8250_ops = { 256 .probe = lpc_ns8250_probe, 257 .init = lpc_ns8250_init, 258 .term = lpc_ns8250_term, 259 .putc = lpc_ns8250_putc, 260 .rxready = lpc_ns8250_rxready, 261 .getc = lpc_ns8250_getc, 262}; 263 264static int 265lpc_ns8250_probe(struct uart_bas *bas) 266{ 267#if 0 268 u_char val; 269 270 /* Check known 0 bits that don't depend on DLAB. */ 271 val = uart_getreg(bas, REG_IIR); 272 if (val & 0x30) 273 return (ENXIO); 274 /* 275 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 276 * chip, but otherwise doesn't seem to have a function. In 277 * other words, uart(4) works regardless. Ignore that bit so 278 * the probe succeeds. 279 */ 280 val = uart_getreg(bas, REG_MCR); 281 if (val & 0xa0) 282 return (ENXIO); 283#endif 284 return (0); 285} 286 287static void 288lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 289 int parity) 290{ 291 u_char ier; 292 u_long clkmode; 293 294 /* Enable UART clock */ 295 bus_space_map(fdtbus_bs_tag, LPC_CLKPWR_PHYS_BASE, LPC_CLKPWR_SIZE, 0, 296 &bsh_clkpwr); 297 clkmode = lpc_ns8250_get_clkreg(bas, LPC_UART_CLKMODE); 298 lpc_ns8250_set_clkreg(bas, LPC_UART_CLKMODE, clkmode | 299 LPC_UART_CLKMODE_UART5(1)); 300 301#if 0 302 /* Work around H/W bug */ 303 uart_setreg(bas, REG_DATA, 0x00); 304#endif 305 if (bas->rclk == 0) 306 bas->rclk = DEFAULT_RCLK; 307 lpc_ns8250_param(bas, baudrate, databits, stopbits, parity); 308 309 /* Disable all interrupt sources. */ 310 /* 311 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 312 * UARTs split the receive time-out interrupt bit out separately as 313 * 0x10. This gets handled by ier_mask and ier_rxbits below. 314 */ 315 ier = uart_getreg(bas, REG_IER) & 0xe0; 316 uart_setreg(bas, REG_IER, ier); 317 uart_barrier(bas); 318 319 /* Disable the FIFO (if present). */ 320 uart_setreg(bas, REG_FCR, 0); 321 uart_barrier(bas); 322 323 /* Set RTS & DTR. */ 324 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 325 uart_barrier(bas); 326 327 lpc_ns8250_clrint(bas); 328} 329 330static void 331lpc_ns8250_term(struct uart_bas *bas) 332{ 333 334 /* Clear RTS & DTR. */ 335 uart_setreg(bas, REG_MCR, MCR_IE); 336 uart_barrier(bas); 337} 338 339static void 340lpc_ns8250_putc(struct uart_bas *bas, int c) 341{ 342 int limit; 343 344 limit = 250000; 345 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 346 DELAY(4); 347 uart_setreg(bas, REG_DATA, c); 348 uart_barrier(bas); 349} 350 351static int 352lpc_ns8250_rxready(struct uart_bas *bas) 353{ 354 355 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 356} 357 358static int 359lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 360{ 361 int c; 362 363 uart_lock(hwmtx); 364 365 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 366 uart_unlock(hwmtx); 367 DELAY(4); 368 uart_lock(hwmtx); 369 } 370 371 c = uart_getreg(bas, REG_DATA); 372 373 uart_unlock(hwmtx); 374 375 return (c); 376} 377 378/* 379 * High-level UART interface. 380 */ 381struct lpc_ns8250_softc { 382 struct uart_softc base; 383 uint8_t fcr; 384 uint8_t ier; 385 uint8_t mcr; 386 387 uint8_t ier_mask; 388 uint8_t ier_rxbits; 389}; 390 391static int lpc_ns8250_bus_attach(struct uart_softc *); 392static int lpc_ns8250_bus_detach(struct uart_softc *); 393static int lpc_ns8250_bus_flush(struct uart_softc *, int); 394static int lpc_ns8250_bus_getsig(struct uart_softc *); 395static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 396static int lpc_ns8250_bus_ipend(struct uart_softc *); 397static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int); 398static int lpc_ns8250_bus_probe(struct uart_softc *); 399static int lpc_ns8250_bus_receive(struct uart_softc *); 400static int lpc_ns8250_bus_setsig(struct uart_softc *, int); 401static int lpc_ns8250_bus_transmit(struct uart_softc *); 402static void lpc_ns8250_bus_grab(struct uart_softc *); 403static void lpc_ns8250_bus_ungrab(struct uart_softc *); 404 405static kobj_method_t lpc_ns8250_methods[] = { 406 KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach), 407 KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach), 408 KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush), 409 KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig), 410 KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl), 411 KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend), 412 KOBJMETHOD(uart_param, lpc_ns8250_bus_param), 413 KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe), 414 KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive), 415 KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig), 416 KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit), 417 KOBJMETHOD(uart_grab, lpc_ns8250_bus_grab), 418 KOBJMETHOD(uart_ungrab, lpc_ns8250_bus_ungrab), 419 { 0, 0 } 420}; 421 422static struct uart_class uart_lpc_class = { 423 "lpc_ns8250", 424 lpc_ns8250_methods, 425 sizeof(struct lpc_ns8250_softc), 426 .uc_ops = &uart_lpc_ns8250_ops, 427 .uc_range = 8, 428 .uc_rclk = DEFAULT_RCLK 429}; 430 431static struct ofw_compat_data compat_data[] = { 432 {"lpc,uart", (uintptr_t)&uart_lpc_class}, 433 {NULL, (uintptr_t)NULL}, 434}; 435UART_FDT_CLASS_AND_DEVICE(compat_data); 436 437#define SIGCHG(c, i, s, d) \ 438 if (c) { \ 439 i |= (i & s) ? s : s | d; \ 440 } else { \ 441 i = (i & s) ? (i & ~s) | d : i; \ 442 } 443 444static int 445lpc_ns8250_bus_attach(struct uart_softc *sc) 446{ 447 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 448 struct uart_bas *bas; 449 unsigned int ivar; 450 451 bas = &sc->sc_bas; 452 453 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR); 454 lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA; 455 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 456 &ivar)) { 457 if (UART_FLAGS_FCR_RX_LOW(ivar)) 458 lpc_ns8250->fcr |= FCR_RX_LOW; 459 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 460 lpc_ns8250->fcr |= FCR_RX_MEDL; 461 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 462 lpc_ns8250->fcr |= FCR_RX_HIGH; 463 else 464 lpc_ns8250->fcr |= FCR_RX_MEDH; 465 } else 466 lpc_ns8250->fcr |= FCR_RX_HIGH; 467 468 /* Get IER mask */ 469 ivar = 0xf0; 470 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 471 &ivar); 472 lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff); 473 474 /* Get IER RX interrupt bits */ 475 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 476 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 477 &ivar); 478 lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 479 480 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr); 481 uart_barrier(bas); 482 lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 483 484 if (lpc_ns8250->mcr & MCR_DTR) 485 sc->sc_hwsig |= SER_DTR; 486 if (lpc_ns8250->mcr & MCR_RTS) 487 sc->sc_hwsig |= SER_RTS; 488 lpc_ns8250_bus_getsig(sc); 489 490 lpc_ns8250_clrint(bas); 491 lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; 492 lpc_ns8250->ier |= lpc_ns8250->ier_rxbits; 493 uart_setreg(bas, REG_IER, lpc_ns8250->ier); 494 uart_barrier(bas); 495 496 return (0); 497} 498 499static int 500lpc_ns8250_bus_detach(struct uart_softc *sc) 501{ 502 struct lpc_ns8250_softc *lpc_ns8250; 503 struct uart_bas *bas; 504 u_char ier; 505 506 lpc_ns8250 = (struct lpc_ns8250_softc *)sc; 507 bas = &sc->sc_bas; 508 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; 509 uart_setreg(bas, REG_IER, ier); 510 uart_barrier(bas); 511 lpc_ns8250_clrint(bas); 512 return (0); 513} 514 515static int 516lpc_ns8250_bus_flush(struct uart_softc *sc, int what) 517{ 518 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 519 struct uart_bas *bas; 520 int error; 521 522 bas = &sc->sc_bas; 523 uart_lock(sc->sc_hwmtx); 524 if (sc->sc_rxfifosz > 1) { 525 lpc_ns8250_flush(bas, what); 526 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr); 527 uart_barrier(bas); 528 error = 0; 529 } else 530 error = lpc_ns8250_drain(bas, what); 531 uart_unlock(sc->sc_hwmtx); 532 return (error); 533} 534 535static int 536lpc_ns8250_bus_getsig(struct uart_softc *sc) 537{ 538 uint32_t new, old, sig; 539 uint8_t msr; 540 541 do { 542 old = sc->sc_hwsig; 543 sig = old; 544 uart_lock(sc->sc_hwmtx); 545 msr = uart_getreg(&sc->sc_bas, REG_MSR); 546 uart_unlock(sc->sc_hwmtx); 547 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 548 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 549 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 550 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 551 new = sig & ~SER_MASK_DELTA; 552 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 553 return (sig); 554} 555 556static int 557lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 558{ 559 struct uart_bas *bas; 560 int baudrate, divisor, error; 561 uint8_t efr, lcr; 562 563 bas = &sc->sc_bas; 564 error = 0; 565 uart_lock(sc->sc_hwmtx); 566 switch (request) { 567 case UART_IOCTL_BREAK: 568 lcr = uart_getreg(bas, REG_LCR); 569 if (data) 570 lcr |= LCR_SBREAK; 571 else 572 lcr &= ~LCR_SBREAK; 573 uart_setreg(bas, REG_LCR, lcr); 574 uart_barrier(bas); 575 break; 576 case UART_IOCTL_IFLOW: 577 lcr = uart_getreg(bas, REG_LCR); 578 uart_barrier(bas); 579 uart_setreg(bas, REG_LCR, 0xbf); 580 uart_barrier(bas); 581 efr = uart_getreg(bas, REG_EFR); 582 if (data) 583 efr |= EFR_RTS; 584 else 585 efr &= ~EFR_RTS; 586 uart_setreg(bas, REG_EFR, efr); 587 uart_barrier(bas); 588 uart_setreg(bas, REG_LCR, lcr); 589 uart_barrier(bas); 590 break; 591 case UART_IOCTL_OFLOW: 592 lcr = uart_getreg(bas, REG_LCR); 593 uart_barrier(bas); 594 uart_setreg(bas, REG_LCR, 0xbf); 595 uart_barrier(bas); 596 efr = uart_getreg(bas, REG_EFR); 597 if (data) 598 efr |= EFR_CTS; 599 else 600 efr &= ~EFR_CTS; 601 uart_setreg(bas, REG_EFR, efr); 602 uart_barrier(bas); 603 uart_setreg(bas, REG_LCR, lcr); 604 uart_barrier(bas); 605 break; 606 case UART_IOCTL_BAUD: 607 lcr = uart_getreg(bas, REG_LCR); 608 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 609 uart_barrier(bas); 610 divisor = uart_getreg(bas, REG_DLL) | 611 (uart_getreg(bas, REG_DLH) << 8); 612 uart_barrier(bas); 613 uart_setreg(bas, REG_LCR, lcr); 614 uart_barrier(bas); 615 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 616 if (baudrate > 0) 617 *(int*)data = baudrate; 618 else 619 error = ENXIO; 620 break; 621 default: 622 error = EINVAL; 623 break; 624 } 625 uart_unlock(sc->sc_hwmtx); 626 return (error); 627} 628 629static int 630lpc_ns8250_bus_ipend(struct uart_softc *sc) 631{ 632 struct uart_bas *bas; 633 struct lpc_ns8250_softc *lpc_ns8250; 634 int ipend; 635 uint8_t iir, lsr; 636 637 lpc_ns8250 = (struct lpc_ns8250_softc *)sc; 638 bas = &sc->sc_bas; 639 uart_lock(sc->sc_hwmtx); 640 iir = uart_getreg(bas, REG_IIR); 641 if (iir & IIR_NOPEND) { 642 uart_unlock(sc->sc_hwmtx); 643 return (0); 644 } 645 ipend = 0; 646 if (iir & IIR_RXRDY) { 647 lsr = uart_getreg(bas, REG_LSR); 648 if (lsr & LSR_OE) 649 ipend |= SER_INT_OVERRUN; 650 if (lsr & LSR_BI) 651 ipend |= SER_INT_BREAK; 652 if (lsr & LSR_RXRDY) 653 ipend |= SER_INT_RXREADY; 654 } else { 655 if (iir & IIR_TXRDY) { 656 ipend |= SER_INT_TXIDLE; 657 uart_setreg(bas, REG_IER, lpc_ns8250->ier); 658 } else 659 ipend |= SER_INT_SIGCHG; 660 } 661 if (ipend == 0) 662 lpc_ns8250_clrint(bas); 663 uart_unlock(sc->sc_hwmtx); 664 return (ipend); 665} 666 667static int 668lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 669 int stopbits, int parity) 670{ 671 struct uart_bas *bas; 672 int error; 673 674 bas = &sc->sc_bas; 675 uart_lock(sc->sc_hwmtx); 676 error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity); 677 uart_unlock(sc->sc_hwmtx); 678 return (error); 679} 680 681static int 682lpc_ns8250_bus_probe(struct uart_softc *sc) 683{ 684 struct lpc_ns8250_softc *lpc_ns8250; 685 struct uart_bas *bas; 686 int count, delay, error, limit; 687 uint8_t lsr, mcr, ier; 688 689 lpc_ns8250 = (struct lpc_ns8250_softc *)sc; 690 bas = &sc->sc_bas; 691 692 error = lpc_ns8250_probe(bas); 693 if (error) 694 return (error); 695 696 mcr = MCR_IE; 697 if (sc->sc_sysdev == NULL) { 698 /* By using lpc_ns8250_init() we also set DTR and RTS. */ 699 lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 700 } else 701 mcr |= MCR_DTR | MCR_RTS; 702 703 error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 704 if (error) 705 return (error); 706 707 /* 708 * Set loopback mode. This avoids having garbage on the wire and 709 * also allows us send and receive data. We set DTR and RTS to 710 * avoid the possibility that automatic flow-control prevents 711 * any data from being sent. 712 */ 713 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 714 uart_barrier(bas); 715 716 /* 717 * Enable FIFOs. And check that the UART has them. If not, we're 718 * done. Since this is the first time we enable the FIFOs, we reset 719 * them. 720 */ 721 uart_setreg(bas, REG_FCR, FCR_ENABLE); 722 uart_barrier(bas); 723 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 724 /* 725 * NS16450 or INS8250. We don't bother to differentiate 726 * between them. They're too old to be interesting. 727 */ 728 uart_setreg(bas, REG_MCR, mcr); 729 uart_barrier(bas); 730 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 731 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 732 return (0); 733 } 734 735 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 736 uart_barrier(bas); 737 738 count = 0; 739 delay = lpc_ns8250_delay(bas); 740 741 /* We have FIFOs. Drain the transmitter and receiver. */ 742 error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 743 if (error) { 744 uart_setreg(bas, REG_MCR, mcr); 745 uart_setreg(bas, REG_FCR, 0); 746 uart_barrier(bas); 747 goto done; 748 } 749 750 /* 751 * We should have a sufficiently clean "pipe" to determine the 752 * size of the FIFOs. We send as much characters as is reasonable 753 * and wait for the overflow bit in the LSR register to be 754 * asserted, counting the characters as we send them. Based on 755 * that count we know the FIFO size. 756 */ 757 do { 758 uart_setreg(bas, REG_DATA, 0); 759 uart_barrier(bas); 760 count++; 761 762 limit = 30; 763 lsr = 0; 764 /* 765 * LSR bits are cleared upon read, so we must accumulate 766 * them to be able to test LSR_OE below. 767 */ 768 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 769 --limit) 770 DELAY(delay); 771 if (limit == 0) { 772 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; 773 uart_setreg(bas, REG_IER, ier); 774 uart_setreg(bas, REG_MCR, mcr); 775 uart_setreg(bas, REG_FCR, 0); 776 uart_barrier(bas); 777 count = 0; 778 goto done; 779 } 780 } while ((lsr & LSR_OE) == 0 && count < 130); 781 count--; 782 783 uart_setreg(bas, REG_MCR, mcr); 784 785 /* Reset FIFOs. */ 786 lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 787 788done: 789 sc->sc_rxfifosz = 64; 790 device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs"); 791 792 /* 793 * Force the Tx FIFO size to 16 bytes for now. We don't program the 794 * Tx trigger. Also, we assume that all data has been sent when the 795 * interrupt happens. 796 */ 797 sc->sc_txfifosz = 16; 798 799#if 0 800 /* 801 * XXX there are some issues related to hardware flow control and 802 * it's likely that uart(4) is the cause. This basicly needs more 803 * investigation, but we avoid using for hardware flow control 804 * until then. 805 */ 806 /* 16650s or higher have automatic flow control. */ 807 if (sc->sc_rxfifosz > 16) { 808 sc->sc_hwiflow = 1; 809 sc->sc_hwoflow = 1; 810 } 811#endif 812 return (0); 813} 814 815static int 816lpc_ns8250_bus_receive(struct uart_softc *sc) 817{ 818 struct uart_bas *bas; 819 int xc; 820 uint8_t lsr; 821 822 bas = &sc->sc_bas; 823 uart_lock(sc->sc_hwmtx); 824 lsr = uart_getreg(bas, REG_LSR); 825 while (lsr & LSR_RXRDY) { 826 if (uart_rx_full(sc)) { 827 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 828 break; 829 } 830 xc = uart_getreg(bas, REG_DATA); 831 if (lsr & LSR_FE) 832 xc |= UART_STAT_FRAMERR; 833 if (lsr & LSR_PE) 834 xc |= UART_STAT_PARERR; 835 uart_rx_put(sc, xc); 836 lsr = uart_getreg(bas, REG_LSR); 837 } 838 /* Discard everything left in the Rx FIFO. */ 839 while (lsr & LSR_RXRDY) { 840 (void)uart_getreg(bas, REG_DATA); 841 uart_barrier(bas); 842 lsr = uart_getreg(bas, REG_LSR); 843 } 844 uart_unlock(sc->sc_hwmtx); 845 return (0); 846} 847 848static int 849lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig) 850{ 851 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 852 struct uart_bas *bas; 853 uint32_t new, old; 854 855 bas = &sc->sc_bas; 856 do { 857 old = sc->sc_hwsig; 858 new = old; 859 if (sig & SER_DDTR) { 860 SIGCHG(sig & SER_DTR, new, SER_DTR, 861 SER_DDTR); 862 } 863 if (sig & SER_DRTS) { 864 SIGCHG(sig & SER_RTS, new, SER_RTS, 865 SER_DRTS); 866 } 867 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 868 uart_lock(sc->sc_hwmtx); 869 lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 870 if (new & SER_DTR) 871 lpc_ns8250->mcr |= MCR_DTR; 872 if (new & SER_RTS) 873 lpc_ns8250->mcr |= MCR_RTS; 874 uart_setreg(bas, REG_MCR, lpc_ns8250->mcr); 875 uart_barrier(bas); 876 uart_unlock(sc->sc_hwmtx); 877 return (0); 878} 879 880static int 881lpc_ns8250_bus_transmit(struct uart_softc *sc) 882{ 883 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 884 struct uart_bas *bas; 885 int i; 886 887 bas = &sc->sc_bas; 888 uart_lock(sc->sc_hwmtx); 889 if (sc->sc_txdatasz > 1) { 890 if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) 891 lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 892 } else { 893 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 894 DELAY(4); 895 } 896 uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY); 897 uart_barrier(bas); 898 for (i = 0; i < sc->sc_txdatasz; i++) { 899 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 900 uart_barrier(bas); 901 } 902 sc->sc_txbusy = 1; 903 uart_unlock(sc->sc_hwmtx); 904 return (0); 905} 906 907void 908lpc_ns8250_bus_grab(struct uart_softc *sc) 909{ 910 struct uart_bas *bas = &sc->sc_bas; 911 912 /* 913 * turn off all interrupts to enter polling mode. Leave the 914 * saved mask alone. We'll restore whatever it was in ungrab. 915 * All pending interupt signals are reset when IER is set to 0. 916 */ 917 uart_lock(sc->sc_hwmtx); 918 uart_setreg(bas, REG_IER, 0); 919 uart_barrier(bas); 920 uart_unlock(sc->sc_hwmtx); 921} 922 923void 924lpc_ns8250_bus_ungrab(struct uart_softc *sc) 925{ 926 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; 927 struct uart_bas *bas = &sc->sc_bas; 928 929 /* 930 * Restore previous interrupt mask 931 */ 932 uart_lock(sc->sc_hwmtx); 933 uart_setreg(bas, REG_IER, lpc_ns8250->ier); 934 uart_barrier(bas); 935 uart_unlock(sc->sc_hwmtx); 936} 937