1/*- 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include "opt_ddb.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/conf.h> 39#include <sys/kdb.h> 40#include <machine/bus.h> 41#include <machine/fdt.h> 42 43#include <dev/uart/uart.h> 44#include <dev/uart/uart_cpu.h> 45#include <dev/uart/uart_cpu_fdt.h> 46#include <dev/uart/uart_bus.h> 47#include <dev/uart/uart_dev_imx.h> 48#include "uart_if.h" 49 50#include <arm/freescale/imx/imx_ccmvar.h> 51 52/* 53 * The hardare FIFOs are 32 bytes. We want an interrupt when there are 24 bytes 54 * available to read or space for 24 more bytes to write. While 8 bytes of 55 * slack before over/underrun might seem excessive, the hardware can run at 56 * 5mbps, which means 2uS per char, so at full speed 8 bytes provides only 16uS 57 * to get into the interrupt handler and service the fifo. 58 */ 59#define IMX_FIFOSZ 32 60#define IMX_RXFIFO_LEVEL 24 61#define IMX_TXFIFO_LEVEL 24 62 63/* 64 * Low-level UART interface. 65 */ 66static int imx_uart_probe(struct uart_bas *bas); 67static void imx_uart_init(struct uart_bas *bas, int, int, int, int); 68static void imx_uart_term(struct uart_bas *bas); 69static void imx_uart_putc(struct uart_bas *bas, int); 70static int imx_uart_rxready(struct uart_bas *bas); 71static int imx_uart_getc(struct uart_bas *bas, struct mtx *); 72 73static struct uart_ops uart_imx_uart_ops = { 74 .probe = imx_uart_probe, 75 .init = imx_uart_init, 76 .term = imx_uart_term, 77 .putc = imx_uart_putc, 78 .rxready = imx_uart_rxready, 79 .getc = imx_uart_getc, 80}; 81 82#if 0 /* Handy when debugging. */ 83static void 84dumpregs(struct uart_bas *bas, const char * msg) 85{ 86 87 if (!bootverbose) 88 return; 89 printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x " 90 "UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n", 91 msg, bas->bsh, 92 GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)), 93 GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)), 94 GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2))); 95} 96#endif 97 98static int 99imx_uart_probe(struct uart_bas *bas) 100{ 101 102 return (0); 103} 104 105static u_int 106imx_uart_getbaud(struct uart_bas *bas) 107{ 108 uint32_t rate, ubir, ubmr; 109 u_int baud, blo, bhi, i; 110 static const u_int predivs[] = {6, 5, 4, 3, 2, 1, 7, 1}; 111 static const u_int std_rates[] = { 112 9600, 14400, 19200, 38400, 57600, 115200, 230400, 460800, 921600 113 }; 114 115 /* 116 * Get the baud rate the hardware is programmed for, then search the 117 * table of standard baud rates for a number that's within 3% of the 118 * actual rate the hardware is programmed for. It's more comforting to 119 * see that your console is running at 115200 than 114942. Note that 120 * here we cannot make a simplifying assumption that the predivider and 121 * numerator are 1 (like we do when setting the baud rate), because we 122 * don't know what u-boot might have set up. 123 */ 124 i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >> 125 IMXUART_UFCR_RFDIV_SHIFT; 126 rate = imx_ccm_uart_hz() / predivs[i]; 127 ubir = GETREG(bas, REG(UBIR)) + 1; 128 ubmr = GETREG(bas, REG(UBMR)) + 1; 129 baud = ((rate / 16 ) * ubir) / ubmr; 130 131 blo = (baud * 100) / 103; 132 bhi = (baud * 100) / 97; 133 for (i = 0; i < nitems(std_rates); i++) { 134 rate = std_rates[i]; 135 if (rate >= blo && rate <= bhi) { 136 baud = rate; 137 break; 138 } 139 } 140 141 return (baud); 142} 143 144static void 145imx_uart_init(struct uart_bas *bas, int baudrate, int databits, 146 int stopbits, int parity) 147{ 148 uint32_t baseclk, reg; 149 150 /* Enable the device and the RX/TX channels. */ 151 SET(bas, REG(UCR1), FLD(UCR1, UARTEN)); 152 SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN)); 153 154 if (databits == 7) 155 DIS(bas, UCR2, WS); 156 else 157 ENA(bas, UCR2, WS); 158 159 if (stopbits == 2) 160 ENA(bas, UCR2, STPB); 161 else 162 DIS(bas, UCR2, STPB); 163 164 switch (parity) { 165 case UART_PARITY_ODD: 166 DIS(bas, UCR2, PROE); 167 ENA(bas, UCR2, PREN); 168 break; 169 case UART_PARITY_EVEN: 170 ENA(bas, UCR2, PROE); 171 ENA(bas, UCR2, PREN); 172 break; 173 case UART_PARITY_MARK: 174 case UART_PARITY_SPACE: 175 /* FALLTHROUGH: Hardware doesn't support mark/space. */ 176 case UART_PARITY_NONE: 177 default: 178 DIS(bas, UCR2, PREN); 179 break; 180 } 181 182 /* 183 * The hardware has an extremely flexible baud clock: it allows setting 184 * both the numerator and denominator of the divider, as well as a 185 * separate pre-divider. We simplify the problem of coming up with a 186 * workable pair of numbers by assuming a pre-divider and numerator of 187 * one because our base clock is so fast we can reach virtually any 188 * reasonable speed with a simple divisor. The numerator value actually 189 * includes the 16x over-sampling (so a value of 16 means divide by 1); 190 * the register value is the numerator-1, so we have a hard-coded 15. 191 * Note that a quirk of the hardware requires that both UBIR and UBMR be 192 * set back to back in order for the change to take effect. 193 */ 194 if (baudrate > 0) { 195 baseclk = imx_ccm_uart_hz(); 196 reg = GETREG(bas, REG(UFCR)); 197 reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1; 198 SETREG(bas, REG(UFCR), reg); 199 SETREG(bas, REG(UBIR), 15); 200 SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1); 201 } 202 203 /* 204 * Program the tx lowater and rx hiwater levels at which fifo-service 205 * interrupts are signaled. The tx value is interpetted as "when there 206 * are only this many bytes remaining" (not "this many free"). 207 */ 208 reg = GETREG(bas, REG(UFCR)); 209 reg &= ~(IMXUART_UFCR_TXTL_MASK | IMXUART_UFCR_RXTL_MASK); 210 reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT; 211 reg |= IMX_RXFIFO_LEVEL << IMXUART_UFCR_RXTL_SHIFT; 212 SETREG(bas, REG(UFCR), reg); 213} 214 215static void 216imx_uart_term(struct uart_bas *bas) 217{ 218 219} 220 221static void 222imx_uart_putc(struct uart_bas *bas, int c) 223{ 224 225 while (!(IS(bas, USR1, TRDY))) 226 ; 227 SETREG(bas, REG(UTXD), c); 228} 229 230static int 231imx_uart_rxready(struct uart_bas *bas) 232{ 233 234 return ((IS(bas, USR2, RDR)) ? 1 : 0); 235} 236 237static int 238imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx) 239{ 240 int c; 241 242 uart_lock(hwmtx); 243 while (!(IS(bas, USR2, RDR))) 244 ; 245 246 c = GETREG(bas, REG(URXD)); 247 uart_unlock(hwmtx); 248#if defined(KDB) 249 if (c & FLD(URXD, BRK)) { 250 if (kdb_break()) 251 return (0); 252 } 253#endif 254 return (c & 0xff); 255} 256 257/* 258 * High-level UART interface. 259 */ 260struct imx_uart_softc { 261 struct uart_softc base; 262}; 263 264static int imx_uart_bus_attach(struct uart_softc *); 265static int imx_uart_bus_detach(struct uart_softc *); 266static int imx_uart_bus_flush(struct uart_softc *, int); 267static int imx_uart_bus_getsig(struct uart_softc *); 268static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t); 269static int imx_uart_bus_ipend(struct uart_softc *); 270static int imx_uart_bus_param(struct uart_softc *, int, int, int, int); 271static int imx_uart_bus_probe(struct uart_softc *); 272static int imx_uart_bus_receive(struct uart_softc *); 273static int imx_uart_bus_setsig(struct uart_softc *, int); 274static int imx_uart_bus_transmit(struct uart_softc *); 275static void imx_uart_bus_grab(struct uart_softc *); 276static void imx_uart_bus_ungrab(struct uart_softc *); 277 278static kobj_method_t imx_uart_methods[] = { 279 KOBJMETHOD(uart_attach, imx_uart_bus_attach), 280 KOBJMETHOD(uart_detach, imx_uart_bus_detach), 281 KOBJMETHOD(uart_flush, imx_uart_bus_flush), 282 KOBJMETHOD(uart_getsig, imx_uart_bus_getsig), 283 KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl), 284 KOBJMETHOD(uart_ipend, imx_uart_bus_ipend), 285 KOBJMETHOD(uart_param, imx_uart_bus_param), 286 KOBJMETHOD(uart_probe, imx_uart_bus_probe), 287 KOBJMETHOD(uart_receive, imx_uart_bus_receive), 288 KOBJMETHOD(uart_setsig, imx_uart_bus_setsig), 289 KOBJMETHOD(uart_transmit, imx_uart_bus_transmit), 290 KOBJMETHOD(uart_grab, imx_uart_bus_grab), 291 KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab), 292 { 0, 0 } 293}; 294 295static struct uart_class uart_imx_class = { 296 "imx", 297 imx_uart_methods, 298 sizeof(struct imx_uart_softc), 299 .uc_ops = &uart_imx_uart_ops, 300 .uc_range = 0x100, 301 .uc_rclk = 24000000 /* TODO: get value from CCM */ 302}; 303 304static struct ofw_compat_data compat_data[] = { 305 {"fsl,imx6q-uart", (uintptr_t)&uart_imx_class}, 306 {"fsl,imx53-uart", (uintptr_t)&uart_imx_class}, 307 {"fsl,imx51-uart", (uintptr_t)&uart_imx_class}, 308 {"fsl,imx31-uart", (uintptr_t)&uart_imx_class}, 309 {"fsl,imx27-uart", (uintptr_t)&uart_imx_class}, 310 {"fsl,imx25-uart", (uintptr_t)&uart_imx_class}, 311 {"fsl,imx21-uart", (uintptr_t)&uart_imx_class}, 312 {NULL, (uintptr_t)NULL}, 313}; 314UART_FDT_CLASS_AND_DEVICE(compat_data); 315 316#define SIGCHG(c, i, s, d) \ 317 if (c) { \ 318 i |= (i & s) ? s : s | d; \ 319 } else { \ 320 i = (i & s) ? (i & ~s) | d : i; \ 321 } 322 323static int 324imx_uart_bus_attach(struct uart_softc *sc) 325{ 326 struct uart_bas *bas; 327 struct uart_devinfo *di; 328 329 bas = &sc->sc_bas; 330 if (sc->sc_sysdev != NULL) { 331 di = sc->sc_sysdev; 332 imx_uart_init(bas, di->baudrate, di->databits, di->stopbits, 333 di->parity); 334 } else { 335 imx_uart_init(bas, 115200, 8, 1, 0); 336 } 337 338 (void)imx_uart_bus_getsig(sc); 339 340 /* Clear all pending interrupts. */ 341 SETREG(bas, REG(USR1), 0xffff); 342 SETREG(bas, REG(USR2), 0xffff); 343 344 DIS(bas, UCR4, DREN); 345 ENA(bas, UCR1, RRDYEN); 346 DIS(bas, UCR1, IDEN); 347 DIS(bas, UCR3, RXDSEN); 348 ENA(bas, UCR2, ATEN); 349 DIS(bas, UCR1, TXMPTYEN); 350 DIS(bas, UCR1, TRDYEN); 351 DIS(bas, UCR4, TCEN); 352 DIS(bas, UCR4, OREN); 353 ENA(bas, UCR4, BKEN); 354 DIS(bas, UCR4, WKEN); 355 DIS(bas, UCR1, ADEN); 356 DIS(bas, UCR3, ACIEN); 357 DIS(bas, UCR2, ESCI); 358 DIS(bas, UCR4, ENIRI); 359 DIS(bas, UCR3, AIRINTEN); 360 DIS(bas, UCR3, AWAKEN); 361 DIS(bas, UCR3, FRAERREN); 362 DIS(bas, UCR3, PARERREN); 363 DIS(bas, UCR1, RTSDEN); 364 DIS(bas, UCR2, RTSEN); 365 DIS(bas, UCR3, DTREN); 366 DIS(bas, UCR3, RI); 367 DIS(bas, UCR3, DCD); 368 DIS(bas, UCR3, DTRDEN); 369 ENA(bas, UCR2, IRTS); 370 ENA(bas, UCR3, RXDMUXSEL); 371 372 return (0); 373} 374 375static int 376imx_uart_bus_detach(struct uart_softc *sc) 377{ 378 379 SETREG(&sc->sc_bas, REG(UCR4), 0); 380 381 return (0); 382} 383 384static int 385imx_uart_bus_flush(struct uart_softc *sc, int what) 386{ 387 388 /* TODO */ 389 return (0); 390} 391 392static int 393imx_uart_bus_getsig(struct uart_softc *sc) 394{ 395 uint32_t new, old, sig; 396 uint8_t bes; 397 398 do { 399 old = sc->sc_hwsig; 400 sig = old; 401 uart_lock(sc->sc_hwmtx); 402 bes = GETREG(&sc->sc_bas, REG(USR2)); 403 uart_unlock(sc->sc_hwmtx); 404 /* XXX: chip can show delta */ 405 SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD); 406 new = sig & ~SER_MASK_DELTA; 407 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 408 409 return (sig); 410} 411 412static int 413imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 414{ 415 struct uart_bas *bas; 416 int error; 417 418 bas = &sc->sc_bas; 419 error = 0; 420 uart_lock(sc->sc_hwmtx); 421 switch (request) { 422 case UART_IOCTL_BREAK: 423 /* TODO */ 424 break; 425 case UART_IOCTL_BAUD: 426 *(u_int*)data = imx_uart_getbaud(bas); 427 break; 428 default: 429 error = EINVAL; 430 break; 431 } 432 uart_unlock(sc->sc_hwmtx); 433 434 return (error); 435} 436 437static int 438imx_uart_bus_ipend(struct uart_softc *sc) 439{ 440 struct uart_bas *bas; 441 int ipend; 442 uint32_t usr1, usr2; 443 uint32_t ucr1, ucr2, ucr4; 444 445 bas = &sc->sc_bas; 446 ipend = 0; 447 448 uart_lock(sc->sc_hwmtx); 449 450 /* Read pending interrupts */ 451 usr1 = GETREG(bas, REG(USR1)); 452 usr2 = GETREG(bas, REG(USR2)); 453 /* ACK interrupts */ 454 SETREG(bas, REG(USR1), usr1); 455 SETREG(bas, REG(USR2), usr2); 456 457 ucr1 = GETREG(bas, REG(UCR1)); 458 ucr2 = GETREG(bas, REG(UCR2)); 459 ucr4 = GETREG(bas, REG(UCR4)); 460 461 /* If we have reached tx low-water, we can tx some more now. */ 462 if ((usr1 & FLD(USR1, TRDY)) && (ucr1 & FLD(UCR1, TRDYEN))) { 463 DIS(bas, UCR1, TRDYEN); 464 ipend |= SER_INT_TXIDLE; 465 } 466 467 /* 468 * If we have reached the rx high-water, or if there are bytes in the rx 469 * fifo and no new data has arrived for 8 character periods (aging 470 * timer), we have input data to process. 471 */ 472 if (((usr1 & FLD(USR1, RRDY)) && (ucr1 & FLD(UCR1, RRDYEN))) || 473 ((usr1 & FLD(USR1, AGTIM)) && (ucr2 & FLD(UCR2, ATEN)))) { 474 DIS(bas, UCR1, RRDYEN); 475 DIS(bas, UCR2, ATEN); 476 ipend |= SER_INT_RXREADY; 477 } 478 479 /* A break can come in at any time, it never gets disabled. */ 480 if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN))) 481 ipend |= SER_INT_BREAK; 482 483 uart_unlock(sc->sc_hwmtx); 484 485 return (ipend); 486} 487 488static int 489imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, 490 int stopbits, int parity) 491{ 492 493 uart_lock(sc->sc_hwmtx); 494 imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity); 495 uart_unlock(sc->sc_hwmtx); 496 return (0); 497} 498 499static int 500imx_uart_bus_probe(struct uart_softc *sc) 501{ 502 int error; 503 504 error = imx_uart_probe(&sc->sc_bas); 505 if (error) 506 return (error); 507 508 /* 509 * On input we can read up to the full fifo size at once. On output, we 510 * want to write only as much as the programmed tx low water level, 511 * because that's all we can be certain we have room for in the fifo 512 * when we get a tx-ready interrupt. 513 */ 514 sc->sc_rxfifosz = IMX_FIFOSZ; 515 sc->sc_txfifosz = IMX_TXFIFO_LEVEL; 516 517 device_set_desc(sc->sc_dev, "Freescale i.MX UART"); 518 return (0); 519} 520 521static int 522imx_uart_bus_receive(struct uart_softc *sc) 523{ 524 struct uart_bas *bas; 525 int xc, out; 526 527 bas = &sc->sc_bas; 528 uart_lock(sc->sc_hwmtx); 529 530 /* 531 * Empty the rx fifo. We get the RRDY interrupt when IMX_RXFIFO_LEVEL 532 * (the rx high-water level) is reached, but we set sc_rxfifosz to the 533 * full hardware fifo size, so we can safely process however much is 534 * there, not just the highwater size. 535 */ 536 while (IS(bas, USR2, RDR)) { 537 if (uart_rx_full(sc)) { 538 /* No space left in input buffer */ 539 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 540 break; 541 } 542 xc = GETREG(bas, REG(URXD)); 543 out = xc & 0x000000ff; 544 if (xc & FLD(URXD, FRMERR)) 545 out |= UART_STAT_FRAMERR; 546 if (xc & FLD(URXD, PRERR)) 547 out |= UART_STAT_PARERR; 548 if (xc & FLD(URXD, OVRRUN)) 549 out |= UART_STAT_OVERRUN; 550 if (xc & FLD(URXD, BRK)) 551 out |= UART_STAT_BREAK; 552 553 uart_rx_put(sc, out); 554 } 555 ENA(bas, UCR1, RRDYEN); 556 ENA(bas, UCR2, ATEN); 557 558 uart_unlock(sc->sc_hwmtx); 559 return (0); 560} 561 562static int 563imx_uart_bus_setsig(struct uart_softc *sc, int sig) 564{ 565 566 return (0); 567} 568 569static int 570imx_uart_bus_transmit(struct uart_softc *sc) 571{ 572 struct uart_bas *bas = &sc->sc_bas; 573 int i; 574 575 bas = &sc->sc_bas; 576 uart_lock(sc->sc_hwmtx); 577 578 /* 579 * Fill the tx fifo. The uart core puts at most IMX_TXFIFO_LEVEL bytes 580 * into the txbuf (because that's what sc_txfifosz is set to), and 581 * because we got the TRDY (low-water reached) interrupt we know at 582 * least that much space is available in the fifo. 583 */ 584 for (i = 0; i < sc->sc_txdatasz; i++) { 585 SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff); 586 } 587 sc->sc_txbusy = 1; 588 ENA(bas, UCR1, TRDYEN); 589 590 uart_unlock(sc->sc_hwmtx); 591 592 return (0); 593} 594 595static void 596imx_uart_bus_grab(struct uart_softc *sc) 597{ 598 struct uart_bas *bas = &sc->sc_bas; 599 600 bas = &sc->sc_bas; 601 uart_lock(sc->sc_hwmtx); 602 DIS(bas, UCR1, RRDYEN); 603 DIS(bas, UCR2, ATEN); 604 uart_unlock(sc->sc_hwmtx); 605} 606 607static void 608imx_uart_bus_ungrab(struct uart_softc *sc) 609{ 610 struct uart_bas *bas = &sc->sc_bas; 611 612 bas = &sc->sc_bas; 613 uart_lock(sc->sc_hwmtx); 614 ENA(bas, UCR1, RRDYEN); 615 ENA(bas, UCR2, ATEN); 616 uart_unlock(sc->sc_hwmtx); 617} 618