1/*- 2 * Copyright (c) 2008 Benno Rice. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD$"); 27 28/* 29 * Driver for SMSC LAN91C111, may work for older variants. 30 */ 31 32#ifdef HAVE_KERNEL_OPTION_HEADERS 33#include "opt_device_polling.h" 34#endif 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/errno.h> 39#include <sys/kernel.h> 40#include <sys/sockio.h> 41#include <sys/malloc.h> 42#include <sys/mbuf.h> 43#include <sys/queue.h> 44#include <sys/socket.h> 45#include <sys/syslog.h> 46#include <sys/taskqueue.h> 47 48#include <sys/module.h> 49#include <sys/bus.h> 50 51#include <machine/bus.h> 52#include <machine/resource.h> 53#include <sys/rman.h> 54 55#include <net/ethernet.h> 56#include <net/if.h> 57#include <net/if_arp.h> 58#include <net/if_dl.h> 59#include <net/if_types.h> 60#include <net/if_mib.h> 61#include <net/if_media.h> 62 63#ifdef INET 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/in_var.h> 67#include <netinet/ip.h> 68#endif 69 70#include <net/bpf.h> 71#include <net/bpfdesc.h> 72 73#include <dev/smc/if_smcreg.h> 74#include <dev/smc/if_smcvar.h> 75 76#include <dev/mii/mii.h> 77#include <dev/mii/mii_bitbang.h> 78#include <dev/mii/miivar.h> 79 80#define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 81#define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 82#define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 83 84#define SMC_INTR_PRIORITY 0 85#define SMC_RX_PRIORITY 5 86#define SMC_TX_PRIORITY 10 87 88devclass_t smc_devclass; 89 90static const char *smc_chip_ids[16] = { 91 NULL, NULL, NULL, 92 /* 3 */ "SMSC LAN91C90 or LAN91C92", 93 /* 4 */ "SMSC LAN91C94", 94 /* 5 */ "SMSC LAN91C95", 95 /* 6 */ "SMSC LAN91C96", 96 /* 7 */ "SMSC LAN91C100", 97 /* 8 */ "SMSC LAN91C100FD", 98 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 99 NULL, NULL, NULL, 100 NULL, NULL, NULL 101}; 102 103static void smc_init(void *); 104static void smc_start(struct ifnet *); 105static void smc_stop(struct smc_softc *); 106static int smc_ioctl(struct ifnet *, u_long, caddr_t); 107 108static void smc_init_locked(struct smc_softc *); 109static void smc_start_locked(struct ifnet *); 110static void smc_reset(struct smc_softc *); 111static int smc_mii_ifmedia_upd(struct ifnet *); 112static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 113static void smc_mii_tick(void *); 114static void smc_mii_mediachg(struct smc_softc *); 115static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 116 117static void smc_task_intr(void *, int); 118static void smc_task_rx(void *, int); 119static void smc_task_tx(void *, int); 120 121static driver_filter_t smc_intr; 122static timeout_t smc_watchdog; 123#ifdef DEVICE_POLLING 124static poll_handler_t smc_poll; 125#endif 126 127/* 128 * MII bit-bang glue 129 */ 130static uint32_t smc_mii_bitbang_read(device_t); 131static void smc_mii_bitbang_write(device_t, uint32_t); 132 133static const struct mii_bitbang_ops smc_mii_bitbang_ops = { 134 smc_mii_bitbang_read, 135 smc_mii_bitbang_write, 136 { 137 MGMT_MDO, /* MII_BIT_MDO */ 138 MGMT_MDI, /* MII_BIT_MDI */ 139 MGMT_MCLK, /* MII_BIT_MDC */ 140 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */ 141 0, /* MII_BIT_DIR_PHY_HOST */ 142 } 143}; 144 145static __inline void 146smc_select_bank(struct smc_softc *sc, uint16_t bank) 147{ 148 149 bus_barrier(sc->smc_reg, BSR, 2, 150 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 151 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 152 bus_barrier(sc->smc_reg, BSR, 2, 153 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 154} 155 156/* Never call this when not in bank 2. */ 157static __inline void 158smc_mmu_wait(struct smc_softc *sc) 159{ 160 161 KASSERT((bus_read_2(sc->smc_reg, BSR) & 162 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 163 device_get_nameunit(sc->smc_dev))); 164 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 165 ; 166} 167 168static __inline uint8_t 169smc_read_1(struct smc_softc *sc, bus_size_t offset) 170{ 171 172 return (bus_read_1(sc->smc_reg, offset)); 173} 174 175static __inline void 176smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val) 177{ 178 179 bus_write_1(sc->smc_reg, offset, val); 180} 181 182static __inline uint16_t 183smc_read_2(struct smc_softc *sc, bus_size_t offset) 184{ 185 186 return (bus_read_2(sc->smc_reg, offset)); 187} 188 189static __inline void 190smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val) 191{ 192 193 bus_write_2(sc->smc_reg, offset, val); 194} 195 196static __inline void 197smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 198 bus_size_t count) 199{ 200 201 bus_read_multi_2(sc->smc_reg, offset, datap, count); 202} 203 204static __inline void 205smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 206 bus_size_t count) 207{ 208 209 bus_write_multi_2(sc->smc_reg, offset, datap, count); 210} 211 212static __inline void 213smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length, 214 int flags) 215{ 216 217 bus_barrier(sc->smc_reg, offset, length, flags); 218} 219 220int 221smc_probe(device_t dev) 222{ 223 int rid, type, error; 224 uint16_t val; 225 struct smc_softc *sc; 226 struct resource *reg; 227 228 sc = device_get_softc(dev); 229 rid = 0; 230 type = SYS_RES_IOPORT; 231 error = 0; 232 233 if (sc->smc_usemem) 234 type = SYS_RES_MEMORY; 235 236 reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE); 237 if (reg == NULL) { 238 if (bootverbose) 239 device_printf(dev, 240 "could not allocate I/O resource for probe\n"); 241 return (ENXIO); 242 } 243 244 /* Check for the identification value in the BSR. */ 245 val = bus_read_2(reg, BSR); 246 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 247 if (bootverbose) 248 device_printf(dev, "identification value not in BSR\n"); 249 error = ENXIO; 250 goto done; 251 } 252 253 /* 254 * Try switching banks and make sure we still get the identification 255 * value. 256 */ 257 bus_write_2(reg, BSR, 0); 258 val = bus_read_2(reg, BSR); 259 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 260 if (bootverbose) 261 device_printf(dev, 262 "identification value not in BSR after write\n"); 263 error = ENXIO; 264 goto done; 265 } 266 267#if 0 268 /* Check the BAR. */ 269 bus_write_2(reg, BSR, 1); 270 val = bus_read_2(reg, BAR); 271 val = BAR_ADDRESS(val); 272 if (rman_get_start(reg) != val) { 273 if (bootverbose) 274 device_printf(dev, "BAR address %x does not match " 275 "I/O resource address %lx\n", val, 276 rman_get_start(reg)); 277 error = ENXIO; 278 goto done; 279 } 280#endif 281 282 /* Compare REV against known chip revisions. */ 283 bus_write_2(reg, BSR, 3); 284 val = bus_read_2(reg, REV); 285 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 286 if (smc_chip_ids[val] == NULL) { 287 if (bootverbose) 288 device_printf(dev, "Unknown chip revision: %d\n", val); 289 error = ENXIO; 290 goto done; 291 } 292 293 device_set_desc(dev, smc_chip_ids[val]); 294 295done: 296 bus_release_resource(dev, type, rid, reg); 297 return (error); 298} 299 300int 301smc_attach(device_t dev) 302{ 303 int type, error; 304 uint16_t val; 305 u_char eaddr[ETHER_ADDR_LEN]; 306 struct smc_softc *sc; 307 struct ifnet *ifp; 308 309 sc = device_get_softc(dev); 310 error = 0; 311 312 sc->smc_dev = dev; 313 314 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 315 if (ifp == NULL) { 316 error = ENOSPC; 317 goto done; 318 } 319 320 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 321 322 /* Set up watchdog callout. */ 323 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 324 325 type = SYS_RES_IOPORT; 326 if (sc->smc_usemem) 327 type = SYS_RES_MEMORY; 328 329 sc->smc_reg_rid = 0; 330 sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0, 331 16, RF_ACTIVE); 332 if (sc->smc_reg == NULL) { 333 error = ENXIO; 334 goto done; 335 } 336 337 sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0, 338 ~0, 1, RF_ACTIVE | RF_SHAREABLE); 339 if (sc->smc_irq == NULL) { 340 error = ENXIO; 341 goto done; 342 } 343 344 SMC_LOCK(sc); 345 smc_reset(sc); 346 SMC_UNLOCK(sc); 347 348 smc_select_bank(sc, 3); 349 val = smc_read_2(sc, REV); 350 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 351 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 352 if (bootverbose) 353 device_printf(dev, "revision %x\n", sc->smc_rev); 354 355 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 356 CALLOUT_RETURNUNLOCKED); 357 if (sc->smc_chip >= REV_CHIP_91110FD) { 358 (void)mii_attach(dev, &sc->smc_miibus, ifp, 359 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 360 MII_PHY_ANY, MII_OFFSET_ANY, 0); 361 if (sc->smc_miibus != NULL) { 362 sc->smc_mii_tick = smc_mii_tick; 363 sc->smc_mii_mediachg = smc_mii_mediachg; 364 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 365 } 366 } 367 368 smc_select_bank(sc, 1); 369 eaddr[0] = smc_read_1(sc, IAR0); 370 eaddr[1] = smc_read_1(sc, IAR1); 371 eaddr[2] = smc_read_1(sc, IAR2); 372 eaddr[3] = smc_read_1(sc, IAR3); 373 eaddr[4] = smc_read_1(sc, IAR4); 374 eaddr[5] = smc_read_1(sc, IAR5); 375 376 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 377 ifp->if_softc = sc; 378 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 379 ifp->if_init = smc_init; 380 ifp->if_ioctl = smc_ioctl; 381 ifp->if_start = smc_start; 382 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 383 IFQ_SET_READY(&ifp->if_snd); 384 385 ifp->if_capabilities = ifp->if_capenable = 0; 386 387#ifdef DEVICE_POLLING 388 ifp->if_capabilities |= IFCAP_POLLING; 389#endif 390 391 ether_ifattach(ifp, eaddr); 392 393 /* Set up taskqueue */ 394 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 395 TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 396 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 397 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 398 taskqueue_thread_enqueue, &sc->smc_tq); 399 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 400 device_get_nameunit(sc->smc_dev)); 401 402 /* Mask all interrupts. */ 403 sc->smc_mask = 0; 404 smc_write_1(sc, MSK, 0); 405 406 /* Wire up interrupt */ 407 error = bus_setup_intr(dev, sc->smc_irq, 408 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 409 if (error != 0) 410 goto done; 411 412done: 413 if (error != 0) 414 smc_detach(dev); 415 return (error); 416} 417 418int 419smc_detach(device_t dev) 420{ 421 int type; 422 struct smc_softc *sc; 423 424 sc = device_get_softc(dev); 425 SMC_LOCK(sc); 426 smc_stop(sc); 427 SMC_UNLOCK(sc); 428 429 if (sc->smc_ifp != NULL) { 430 ether_ifdetach(sc->smc_ifp); 431 } 432 433 callout_drain(&sc->smc_watchdog); 434 callout_drain(&sc->smc_mii_tick_ch); 435 436#ifdef DEVICE_POLLING 437 if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 438 ether_poll_deregister(sc->smc_ifp); 439#endif 440 441 if (sc->smc_ih != NULL) 442 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 443 444 if (sc->smc_tq != NULL) { 445 taskqueue_drain(sc->smc_tq, &sc->smc_intr); 446 taskqueue_drain(sc->smc_tq, &sc->smc_rx); 447 taskqueue_drain(sc->smc_tq, &sc->smc_tx); 448 taskqueue_free(sc->smc_tq); 449 sc->smc_tq = NULL; 450 } 451 452 if (sc->smc_ifp != NULL) { 453 if_free(sc->smc_ifp); 454 } 455 456 if (sc->smc_miibus != NULL) { 457 device_delete_child(sc->smc_dev, sc->smc_miibus); 458 bus_generic_detach(sc->smc_dev); 459 } 460 461 if (sc->smc_reg != NULL) { 462 type = SYS_RES_IOPORT; 463 if (sc->smc_usemem) 464 type = SYS_RES_MEMORY; 465 466 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 467 sc->smc_reg); 468 } 469 470 if (sc->smc_irq != NULL) 471 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 472 sc->smc_irq); 473 474 if (mtx_initialized(&sc->smc_mtx)) 475 mtx_destroy(&sc->smc_mtx); 476 477 return (0); 478} 479 480static void 481smc_start(struct ifnet *ifp) 482{ 483 struct smc_softc *sc; 484 485 sc = ifp->if_softc; 486 SMC_LOCK(sc); 487 smc_start_locked(ifp); 488 SMC_UNLOCK(sc); 489} 490 491static void 492smc_start_locked(struct ifnet *ifp) 493{ 494 struct smc_softc *sc; 495 struct mbuf *m; 496 u_int len, npages, spin_count; 497 498 sc = ifp->if_softc; 499 SMC_ASSERT_LOCKED(sc); 500 501 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 502 return; 503 if (IFQ_IS_EMPTY(&ifp->if_snd)) 504 return; 505 506 /* 507 * Grab the next packet. If it's too big, drop it. 508 */ 509 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 510 len = m_length(m, NULL); 511 len += (len & 1); 512 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 513 if_printf(ifp, "large packet discarded\n"); 514 ++ifp->if_oerrors; 515 m_freem(m); 516 return; /* XXX readcheck? */ 517 } 518 519 /* 520 * Flag that we're busy. 521 */ 522 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 523 sc->smc_pending = m; 524 525 /* 526 * Work out how many 256 byte "pages" we need. We have to include the 527 * control data for the packet in this calculation. 528 */ 529 npages = (len * PKT_CTRL_DATA_LEN) >> 8; 530 if (npages == 0) 531 npages = 1; 532 533 /* 534 * Request memory. 535 */ 536 smc_select_bank(sc, 2); 537 smc_mmu_wait(sc); 538 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 539 540 /* 541 * Spin briefly to see if the allocation succeeds. 542 */ 543 spin_count = TX_ALLOC_WAIT_TIME; 544 do { 545 if (smc_read_1(sc, IST) & ALLOC_INT) { 546 smc_write_1(sc, ACK, ALLOC_INT); 547 break; 548 } 549 } while (--spin_count); 550 551 /* 552 * If the allocation is taking too long, unmask the alloc interrupt 553 * and wait. 554 */ 555 if (spin_count == 0) { 556 sc->smc_mask |= ALLOC_INT; 557 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 558 smc_write_1(sc, MSK, sc->smc_mask); 559 return; 560 } 561 562 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 563} 564 565static void 566smc_task_tx(void *context, int pending) 567{ 568 struct ifnet *ifp; 569 struct smc_softc *sc; 570 struct mbuf *m, *m0; 571 u_int packet, len; 572 int last_len; 573 uint8_t *data; 574 575 (void)pending; 576 ifp = (struct ifnet *)context; 577 sc = ifp->if_softc; 578 579 SMC_LOCK(sc); 580 581 if (sc->smc_pending == NULL) { 582 SMC_UNLOCK(sc); 583 goto next_packet; 584 } 585 586 m = m0 = sc->smc_pending; 587 sc->smc_pending = NULL; 588 smc_select_bank(sc, 2); 589 590 /* 591 * Check the allocation result. 592 */ 593 packet = smc_read_1(sc, ARR); 594 595 /* 596 * If the allocation failed, requeue the packet and retry. 597 */ 598 if (packet & ARR_FAILED) { 599 IFQ_DRV_PREPEND(&ifp->if_snd, m); 600 ++ifp->if_oerrors; 601 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 602 smc_start_locked(ifp); 603 SMC_UNLOCK(sc); 604 return; 605 } 606 607 /* 608 * Tell the device to write to our packet number. 609 */ 610 smc_write_1(sc, PNR, packet); 611 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 612 613 /* 614 * Tell the device how long the packet is (including control data). 615 */ 616 len = m_length(m, 0); 617 len += PKT_CTRL_DATA_LEN; 618 smc_write_2(sc, DATA0, 0); 619 smc_write_2(sc, DATA0, len); 620 621 /* 622 * Push the data out to the device. 623 */ 624 data = NULL; 625 last_len = 0; 626 for (; m != NULL; m = m->m_next) { 627 data = mtod(m, uint8_t *); 628 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 629 last_len = m->m_len; 630 } 631 632 /* 633 * Push out the control byte and and the odd byte if needed. 634 */ 635 if ((len & 1) != 0 && data != NULL) 636 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); 637 else 638 smc_write_2(sc, DATA0, 0); 639 640 /* 641 * Unmask the TX empty interrupt. 642 */ 643 sc->smc_mask |= TX_EMPTY_INT; 644 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 645 smc_write_1(sc, MSK, sc->smc_mask); 646 647 /* 648 * Enqueue the packet. 649 */ 650 smc_mmu_wait(sc); 651 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 652 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 653 654 /* 655 * Finish up. 656 */ 657 ifp->if_opackets++; 658 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 659 SMC_UNLOCK(sc); 660 BPF_MTAP(ifp, m0); 661 m_freem(m0); 662 663next_packet: 664 /* 665 * See if there's anything else to do. 666 */ 667 smc_start(ifp); 668} 669 670static void 671smc_task_rx(void *context, int pending) 672{ 673 u_int packet, status, len; 674 uint8_t *data; 675 struct ifnet *ifp; 676 struct smc_softc *sc; 677 struct mbuf *m, *mhead, *mtail; 678 679 (void)pending; 680 ifp = (struct ifnet *)context; 681 sc = ifp->if_softc; 682 mhead = mtail = NULL; 683 684 SMC_LOCK(sc); 685 686 packet = smc_read_1(sc, FIFO_RX); 687 while ((packet & FIFO_EMPTY) == 0) { 688 /* 689 * Grab an mbuf and attach a cluster. 690 */ 691 MGETHDR(m, M_NOWAIT, MT_DATA); 692 if (m == NULL) { 693 break; 694 } 695 MCLGET(m, M_NOWAIT); 696 if ((m->m_flags & M_EXT) == 0) { 697 m_freem(m); 698 break; 699 } 700 701 /* 702 * Point to the start of the packet. 703 */ 704 smc_select_bank(sc, 2); 705 smc_write_1(sc, PNR, packet); 706 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 707 708 /* 709 * Grab status and packet length. 710 */ 711 status = smc_read_2(sc, DATA0); 712 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 713 len -= 6; 714 if (status & RX_ODDFRM) 715 len += 1; 716 717 /* 718 * Check for errors. 719 */ 720 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 721 smc_mmu_wait(sc); 722 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 723 ifp->if_ierrors++; 724 m_freem(m); 725 break; 726 } 727 728 /* 729 * Set the mbuf up the way we want it. 730 */ 731 m->m_pkthdr.rcvif = ifp; 732 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 733 m_adj(m, ETHER_ALIGN); 734 735 /* 736 * Pull the packet out of the device. Make sure we're in the 737 * right bank first as things may have changed while we were 738 * allocating our mbuf. 739 */ 740 smc_select_bank(sc, 2); 741 smc_write_1(sc, PNR, packet); 742 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 743 data = mtod(m, uint8_t *); 744 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 745 if (len & 1) { 746 data += len & ~1; 747 *data = smc_read_1(sc, DATA0); 748 } 749 750 /* 751 * Tell the device we're done. 752 */ 753 smc_mmu_wait(sc); 754 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 755 if (m == NULL) { 756 break; 757 } 758 759 if (mhead == NULL) { 760 mhead = mtail = m; 761 m->m_next = NULL; 762 } else { 763 mtail->m_next = m; 764 mtail = m; 765 } 766 packet = smc_read_1(sc, FIFO_RX); 767 } 768 769 sc->smc_mask |= RCV_INT; 770 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 771 smc_write_1(sc, MSK, sc->smc_mask); 772 773 SMC_UNLOCK(sc); 774 775 while (mhead != NULL) { 776 m = mhead; 777 mhead = mhead->m_next; 778 m->m_next = NULL; 779 ifp->if_ipackets++; 780 (*ifp->if_input)(ifp, m); 781 } 782} 783 784#ifdef DEVICE_POLLING 785static void 786smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 787{ 788 struct smc_softc *sc; 789 790 sc = ifp->if_softc; 791 792 SMC_LOCK(sc); 793 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 794 SMC_UNLOCK(sc); 795 return; 796 } 797 SMC_UNLOCK(sc); 798 799 if (cmd == POLL_AND_CHECK_STATUS) 800 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 801} 802#endif 803 804static int 805smc_intr(void *context) 806{ 807 struct smc_softc *sc; 808 809 sc = (struct smc_softc *)context; 810 /* 811 * Block interrupts in order to let smc_task_intr to kick in 812 */ 813 smc_write_1(sc, MSK, 0); 814 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 815 return (FILTER_HANDLED); 816} 817 818static void 819smc_task_intr(void *context, int pending) 820{ 821 struct smc_softc *sc; 822 struct ifnet *ifp; 823 u_int status, packet, counter, tcr; 824 825 (void)pending; 826 ifp = (struct ifnet *)context; 827 sc = ifp->if_softc; 828 829 SMC_LOCK(sc); 830 831 smc_select_bank(sc, 2); 832 833 /* 834 * Find out what interrupts are flagged. 835 */ 836 status = smc_read_1(sc, IST) & sc->smc_mask; 837 838 /* 839 * Transmit error 840 */ 841 if (status & TX_INT) { 842 /* 843 * Kill off the packet if there is one and re-enable transmit. 844 */ 845 packet = smc_read_1(sc, FIFO_TX); 846 if ((packet & FIFO_EMPTY) == 0) { 847 smc_write_1(sc, PNR, packet); 848 smc_write_2(sc, PTR, 0 | PTR_READ | 849 PTR_AUTO_INCR); 850 tcr = smc_read_2(sc, DATA0); 851 if ((tcr & EPHSR_TX_SUC) == 0) 852 device_printf(sc->smc_dev, 853 "bad packet\n"); 854 smc_mmu_wait(sc); 855 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 856 857 smc_select_bank(sc, 0); 858 tcr = smc_read_2(sc, TCR); 859 tcr |= TCR_TXENA | TCR_PAD_EN; 860 smc_write_2(sc, TCR, tcr); 861 smc_select_bank(sc, 2); 862 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 863 } 864 865 /* 866 * Ack the interrupt. 867 */ 868 smc_write_1(sc, ACK, TX_INT); 869 } 870 871 /* 872 * Receive 873 */ 874 if (status & RCV_INT) { 875 smc_write_1(sc, ACK, RCV_INT); 876 sc->smc_mask &= ~RCV_INT; 877 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx); 878 } 879 880 /* 881 * Allocation 882 */ 883 if (status & ALLOC_INT) { 884 smc_write_1(sc, ACK, ALLOC_INT); 885 sc->smc_mask &= ~ALLOC_INT; 886 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 887 } 888 889 /* 890 * Receive overrun 891 */ 892 if (status & RX_OVRN_INT) { 893 smc_write_1(sc, ACK, RX_OVRN_INT); 894 ifp->if_ierrors++; 895 } 896 897 /* 898 * Transmit empty 899 */ 900 if (status & TX_EMPTY_INT) { 901 smc_write_1(sc, ACK, TX_EMPTY_INT); 902 sc->smc_mask &= ~TX_EMPTY_INT; 903 callout_stop(&sc->smc_watchdog); 904 905 /* 906 * Update collision stats. 907 */ 908 smc_select_bank(sc, 0); 909 counter = smc_read_2(sc, ECR); 910 smc_select_bank(sc, 2); 911 ifp->if_collisions += 912 (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT; 913 ifp->if_collisions += 914 (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT; 915 916 /* 917 * See if there are any packets to transmit. 918 */ 919 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 920 } 921 922 /* 923 * Update the interrupt mask. 924 */ 925 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 926 smc_write_1(sc, MSK, sc->smc_mask); 927 928 SMC_UNLOCK(sc); 929} 930 931static uint32_t 932smc_mii_bitbang_read(device_t dev) 933{ 934 struct smc_softc *sc; 935 uint32_t val; 936 937 sc = device_get_softc(dev); 938 939 SMC_ASSERT_LOCKED(sc); 940 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 941 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)", 942 device_get_nameunit(sc->smc_dev), 943 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 944 945 val = smc_read_2(sc, MGMT); 946 smc_barrier(sc, MGMT, 2, 947 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 948 949 return (val); 950} 951 952static void 953smc_mii_bitbang_write(device_t dev, uint32_t val) 954{ 955 struct smc_softc *sc; 956 957 sc = device_get_softc(dev); 958 959 SMC_ASSERT_LOCKED(sc); 960 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 961 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)", 962 device_get_nameunit(sc->smc_dev), 963 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 964 965 smc_write_2(sc, MGMT, val); 966 smc_barrier(sc, MGMT, 2, 967 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 968} 969 970int 971smc_miibus_readreg(device_t dev, int phy, int reg) 972{ 973 struct smc_softc *sc; 974 int val; 975 976 sc = device_get_softc(dev); 977 978 SMC_LOCK(sc); 979 980 smc_select_bank(sc, 3); 981 982 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg); 983 984 SMC_UNLOCK(sc); 985 return (val); 986} 987 988int 989smc_miibus_writereg(device_t dev, int phy, int reg, int data) 990{ 991 struct smc_softc *sc; 992 993 sc = device_get_softc(dev); 994 995 SMC_LOCK(sc); 996 997 smc_select_bank(sc, 3); 998 999 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data); 1000 1001 SMC_UNLOCK(sc); 1002 return (0); 1003} 1004 1005void 1006smc_miibus_statchg(device_t dev) 1007{ 1008 struct smc_softc *sc; 1009 struct mii_data *mii; 1010 uint16_t tcr; 1011 1012 sc = device_get_softc(dev); 1013 mii = device_get_softc(sc->smc_miibus); 1014 1015 SMC_LOCK(sc); 1016 1017 smc_select_bank(sc, 0); 1018 tcr = smc_read_2(sc, TCR); 1019 1020 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1021 tcr |= TCR_SWFDUP; 1022 else 1023 tcr &= ~TCR_SWFDUP; 1024 1025 smc_write_2(sc, TCR, tcr); 1026 1027 SMC_UNLOCK(sc); 1028} 1029 1030static int 1031smc_mii_ifmedia_upd(struct ifnet *ifp) 1032{ 1033 struct smc_softc *sc; 1034 struct mii_data *mii; 1035 1036 sc = ifp->if_softc; 1037 if (sc->smc_miibus == NULL) 1038 return (ENXIO); 1039 1040 mii = device_get_softc(sc->smc_miibus); 1041 return (mii_mediachg(mii)); 1042} 1043 1044static void 1045smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1046{ 1047 struct smc_softc *sc; 1048 struct mii_data *mii; 1049 1050 sc = ifp->if_softc; 1051 if (sc->smc_miibus == NULL) 1052 return; 1053 1054 mii = device_get_softc(sc->smc_miibus); 1055 mii_pollstat(mii); 1056 ifmr->ifm_active = mii->mii_media_active; 1057 ifmr->ifm_status = mii->mii_media_status; 1058} 1059 1060static void 1061smc_mii_tick(void *context) 1062{ 1063 struct smc_softc *sc; 1064 1065 sc = (struct smc_softc *)context; 1066 1067 if (sc->smc_miibus == NULL) 1068 return; 1069 1070 SMC_UNLOCK(sc); 1071 1072 mii_tick(device_get_softc(sc->smc_miibus)); 1073 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1074} 1075 1076static void 1077smc_mii_mediachg(struct smc_softc *sc) 1078{ 1079 1080 if (sc->smc_miibus == NULL) 1081 return; 1082 mii_mediachg(device_get_softc(sc->smc_miibus)); 1083} 1084 1085static int 1086smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1087{ 1088 struct mii_data *mii; 1089 1090 if (sc->smc_miibus == NULL) 1091 return (EINVAL); 1092 1093 mii = device_get_softc(sc->smc_miibus); 1094 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1095} 1096 1097static void 1098smc_reset(struct smc_softc *sc) 1099{ 1100 u_int ctr; 1101 1102 SMC_ASSERT_LOCKED(sc); 1103 1104 smc_select_bank(sc, 2); 1105 1106 /* 1107 * Mask all interrupts. 1108 */ 1109 smc_write_1(sc, MSK, 0); 1110 1111 /* 1112 * Tell the device to reset. 1113 */ 1114 smc_select_bank(sc, 0); 1115 smc_write_2(sc, RCR, RCR_SOFT_RST); 1116 1117 /* 1118 * Set up the configuration register. 1119 */ 1120 smc_select_bank(sc, 1); 1121 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1122 DELAY(1); 1123 1124 /* 1125 * Turn off transmit and receive. 1126 */ 1127 smc_select_bank(sc, 0); 1128 smc_write_2(sc, TCR, 0); 1129 smc_write_2(sc, RCR, 0); 1130 1131 /* 1132 * Set up the control register. 1133 */ 1134 smc_select_bank(sc, 1); 1135 ctr = smc_read_2(sc, CTR); 1136 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; 1137 smc_write_2(sc, CTR, ctr); 1138 1139 /* 1140 * Reset the MMU. 1141 */ 1142 smc_select_bank(sc, 2); 1143 smc_mmu_wait(sc); 1144 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1145} 1146 1147static void 1148smc_enable(struct smc_softc *sc) 1149{ 1150 struct ifnet *ifp; 1151 1152 SMC_ASSERT_LOCKED(sc); 1153 ifp = sc->smc_ifp; 1154 1155 /* 1156 * Set up the receive/PHY control register. 1157 */ 1158 smc_select_bank(sc, 0); 1159 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1160 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1161 1162 /* 1163 * Set up the transmit and receive control registers. 1164 */ 1165 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1166 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1167 1168 /* 1169 * Set up the interrupt mask. 1170 */ 1171 smc_select_bank(sc, 2); 1172 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1173 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1174 smc_write_1(sc, MSK, sc->smc_mask); 1175} 1176 1177static void 1178smc_stop(struct smc_softc *sc) 1179{ 1180 1181 SMC_ASSERT_LOCKED(sc); 1182 1183 /* 1184 * Turn off callouts. 1185 */ 1186 callout_stop(&sc->smc_watchdog); 1187 callout_stop(&sc->smc_mii_tick_ch); 1188 1189 /* 1190 * Mask all interrupts. 1191 */ 1192 smc_select_bank(sc, 2); 1193 sc->smc_mask = 0; 1194 smc_write_1(sc, MSK, 0); 1195#ifdef DEVICE_POLLING 1196 ether_poll_deregister(sc->smc_ifp); 1197 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 1198 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING_NOCOUNT; 1199#endif 1200 1201 /* 1202 * Disable transmit and receive. 1203 */ 1204 smc_select_bank(sc, 0); 1205 smc_write_2(sc, TCR, 0); 1206 smc_write_2(sc, RCR, 0); 1207 1208 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1209} 1210 1211static void 1212smc_watchdog(void *arg) 1213{ 1214 struct smc_softc *sc; 1215 1216 sc = (struct smc_softc *)arg; 1217 device_printf(sc->smc_dev, "watchdog timeout\n"); 1218 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 1219} 1220 1221static void 1222smc_init(void *context) 1223{ 1224 struct smc_softc *sc; 1225 1226 sc = (struct smc_softc *)context; 1227 SMC_LOCK(sc); 1228 smc_init_locked(sc); 1229 SMC_UNLOCK(sc); 1230} 1231 1232static void 1233smc_init_locked(struct smc_softc *sc) 1234{ 1235 struct ifnet *ifp; 1236 1237 SMC_ASSERT_LOCKED(sc); 1238 ifp = sc->smc_ifp; 1239 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1240 return; 1241 1242 smc_reset(sc); 1243 smc_enable(sc); 1244 1245 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1246 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1247 1248 smc_start_locked(ifp); 1249 1250 if (sc->smc_mii_tick != NULL) 1251 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1252 1253#ifdef DEVICE_POLLING 1254 SMC_UNLOCK(sc); 1255 ether_poll_register(smc_poll, ifp); 1256 SMC_LOCK(sc); 1257 ifp->if_capenable |= IFCAP_POLLING; 1258 ifp->if_capenable |= IFCAP_POLLING_NOCOUNT; 1259#endif 1260} 1261 1262static int 1263smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1264{ 1265 struct smc_softc *sc; 1266 int error; 1267 1268 sc = ifp->if_softc; 1269 error = 0; 1270 1271 switch (cmd) { 1272 case SIOCSIFFLAGS: 1273 if ((ifp->if_flags & IFF_UP) == 0 && 1274 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1275 SMC_LOCK(sc); 1276 smc_stop(sc); 1277 SMC_UNLOCK(sc); 1278 } else { 1279 smc_init(sc); 1280 if (sc->smc_mii_mediachg != NULL) 1281 sc->smc_mii_mediachg(sc); 1282 } 1283 break; 1284 1285 case SIOCADDMULTI: 1286 case SIOCDELMULTI: 1287 /* XXX 1288 SMC_LOCK(sc); 1289 smc_setmcast(sc); 1290 SMC_UNLOCK(sc); 1291 */ 1292 error = EINVAL; 1293 break; 1294 1295 case SIOCGIFMEDIA: 1296 case SIOCSIFMEDIA: 1297 if (sc->smc_mii_mediaioctl == NULL) { 1298 error = EINVAL; 1299 break; 1300 } 1301 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1302 break; 1303 1304 default: 1305 error = ether_ioctl(ifp, cmd, data); 1306 break; 1307 } 1308 1309 return (error); 1310} 1311