1/*-
2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/10/sys/dev/sfxge/common/hunt_nic.c 342480 2018-12-26 09:33:26Z arybchik $");
33
34#include "efx.h"
35#include "efx_impl.h"
36#if EFSYS_OPT_MON_MCDI
37#include "mcdi_mon.h"
38#endif
39
40#if EFSYS_OPT_HUNTINGTON
41
42#include "ef10_tlv_layout.h"
43
44static	__checkReturn	efx_rc_t
45hunt_nic_get_required_pcie_bandwidth(
46	__in		efx_nic_t *enp,
47	__out		uint32_t *bandwidth_mbpsp)
48{
49	uint32_t port_modes;
50	uint32_t max_port_mode;
51	uint32_t bandwidth;
52	efx_rc_t rc;
53
54	/*
55	 * On Huntington, the firmware may not give us the current port mode, so
56	 * we need to go by the set of available port modes and assume the most
57	 * capable mode is in use.
58	 */
59
60	if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
61		/* No port mode info available */
62		bandwidth = 0;
63		goto out;
64	}
65
66	if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
67		/*
68		 * This needs the full PCIe bandwidth (and could use
69		 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
70		 */
71		if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
72			    EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
73			goto fail1;
74	} else {
75		if (port_modes & (1 << TLV_PORT_MODE_40G)) {
76			max_port_mode = TLV_PORT_MODE_40G;
77		} else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
78			max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
79		} else {
80			/* Assume two 10G ports */
81			max_port_mode = TLV_PORT_MODE_10G_10G;
82		}
83
84		if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
85							    &bandwidth)) != 0)
86			goto fail2;
87	}
88
89out:
90	*bandwidth_mbpsp = bandwidth;
91
92	return (0);
93
94fail2:
95	EFSYS_PROBE(fail2);
96fail1:
97	EFSYS_PROBE1(fail1, efx_rc_t, rc);
98
99	return (rc);
100}
101
102	__checkReturn	efx_rc_t
103hunt_board_cfg(
104	__in		efx_nic_t *enp)
105{
106	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
107	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
108	uint8_t mac_addr[6];
109	uint32_t board_type = 0;
110	ef10_link_state_t els;
111	efx_port_t *epp = &(enp->en_port);
112	uint32_t port;
113	uint32_t pf;
114	uint32_t vf;
115	uint32_t mask;
116	uint32_t flags;
117	uint32_t sysclk, dpcpu_clk;
118	uint32_t base, nvec;
119	uint32_t bandwidth;
120	efx_rc_t rc;
121
122	if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
123		goto fail1;
124
125	/*
126	 * NOTE: The MCDI protocol numbers ports from zero.
127	 * The common code MCDI interface numbers ports from one.
128	 */
129	emip->emi_port = port + 1;
130
131	if ((rc = ef10_external_port_mapping(enp, port,
132		    &encp->enc_external_port)) != 0)
133		goto fail2;
134
135	/*
136	 * Get PCIe function number from firmware (used for
137	 * per-function privilege and dynamic config info).
138	 *  - PCIe PF: pf = PF number, vf = 0xffff.
139	 *  - PCIe VF: pf = parent PF, vf = VF number.
140	 */
141	if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
142		goto fail3;
143
144	encp->enc_pf = pf;
145	encp->enc_vf = vf;
146
147	/* MAC address for this function */
148	if (EFX_PCI_FUNCTION_IS_PF(encp)) {
149		rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
150		if ((rc == 0) && (mac_addr[0] & 0x02)) {
151			/*
152			 * If the static config does not include a global MAC
153			 * address pool then the board may return a locally
154			 * administered MAC address (this should only happen on
155			 * incorrectly programmed boards).
156			 */
157			rc = EINVAL;
158		}
159	} else {
160		rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
161	}
162	if (rc != 0)
163		goto fail4;
164
165	EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
166
167	/* Board configuration */
168	rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
169	if (rc != 0) {
170		/* Unprivileged functions may not be able to read board cfg */
171		if (rc == EACCES)
172			board_type = 0;
173		else
174			goto fail5;
175	}
176
177	encp->enc_board_type = board_type;
178	encp->enc_clk_mult = 1; /* not used for Huntington */
179
180	/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
181	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
182		goto fail6;
183
184	/* Obtain the default PHY advertised capabilities */
185	if ((rc = ef10_phy_get_link(enp, &els)) != 0)
186		goto fail7;
187	epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
188	epp->ep_adv_cap_mask = els.els_adv_cap_mask;
189
190	/*
191	 * Enable firmware workarounds for hardware errata.
192	 * Expected responses are:
193	 *  - 0 (zero):
194	 *	Success: workaround enabled or disabled as requested.
195	 *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
196	 *	Firmware does not support the MC_CMD_WORKAROUND request.
197	 *	(assume that the workaround is not supported).
198	 *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
199	 *	Firmware does not support the requested workaround.
200	 *  - MC_CMD_ERR_EPERM  (reported as EACCES):
201	 *	Unprivileged function cannot enable/disable workarounds.
202	 *
203	 * See efx_mcdi_request_errcode() for MCDI error translations.
204	 */
205
206	/*
207	 * If the bug35388 workaround is enabled, then use an indirect access
208	 * method to avoid unsafe EVQ writes.
209	 */
210	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
211	    NULL);
212	if ((rc == 0) || (rc == EACCES))
213		encp->enc_bug35388_workaround = B_TRUE;
214	else if ((rc == ENOTSUP) || (rc == ENOENT))
215		encp->enc_bug35388_workaround = B_FALSE;
216	else
217		goto fail8;
218
219	/*
220	 * If the bug41750 workaround is enabled, then do not test interrupts,
221	 * as the test will fail (seen with Greenport controllers).
222	 */
223	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
224	    NULL);
225	if (rc == 0) {
226		encp->enc_bug41750_workaround = B_TRUE;
227	} else if (rc == EACCES) {
228		/* Assume a controller with 40G ports needs the workaround. */
229		if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
230			encp->enc_bug41750_workaround = B_TRUE;
231		else
232			encp->enc_bug41750_workaround = B_FALSE;
233	} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
234		encp->enc_bug41750_workaround = B_FALSE;
235	} else {
236		goto fail9;
237	}
238	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
239		/* Interrupt testing does not work for VFs. See bug50084. */
240		encp->enc_bug41750_workaround = B_TRUE;
241	}
242
243	/*
244	 * If the bug26807 workaround is enabled, then firmware has enabled
245	 * support for chained multicast filters. Firmware will reset (FLR)
246	 * functions which have filters in the hardware filter table when the
247	 * workaround is enabled/disabled.
248	 *
249	 * We must recheck if the workaround is enabled after inserting the
250	 * first hardware filter, in case it has been changed since this check.
251	 */
252	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
253	    B_TRUE, &flags);
254	if (rc == 0) {
255		encp->enc_bug26807_workaround = B_TRUE;
256		if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
257			/*
258			 * Other functions had installed filters before the
259			 * workaround was enabled, and they have been reset
260			 * by firmware.
261			 */
262			EFSYS_PROBE(bug26807_workaround_flr_done);
263			/* FIXME: bump MC warm boot count ? */
264		}
265	} else if (rc == EACCES) {
266		/*
267		 * Unprivileged functions cannot enable the workaround in older
268		 * firmware.
269		 */
270		encp->enc_bug26807_workaround = B_FALSE;
271	} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
272		encp->enc_bug26807_workaround = B_FALSE;
273	} else {
274		goto fail10;
275	}
276
277	/* Get clock frequencies (in MHz). */
278	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
279		goto fail11;
280
281	/*
282	 * The Huntington timer quantum is 1536 sysclk cycles, documented for
283	 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
284	 */
285	encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
286	if (encp->enc_bug35388_workaround) {
287		encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
288		ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
289	} else {
290		encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
291		FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
292	}
293
294	encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
295
296	/* Check capabilities of running datapath firmware */
297	if ((rc = ef10_get_datapath_caps(enp)) != 0)
298		goto fail12;
299
300	/* Alignment for receive packet DMA buffers */
301	encp->enc_rx_buf_align_start = 1;
302	encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
303
304	/* Alignment for WPTR updates */
305	encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
306
307	encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
308	/* No boundary crossing limits */
309	encp->enc_tx_dma_desc_boundary = 0;
310
311	/*
312	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
313	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
314	 * resources (allocated to this PCIe function), which is zero until
315	 * after we have allocated VIs.
316	 */
317	encp->enc_evq_limit = 1024;
318	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
319	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
320
321	/*
322	 * The workaround for bug35388 uses the top bit of transmit queue
323	 * descriptor writes, preventing the use of 4096 descriptor TXQs.
324	 */
325	encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
326
327	encp->enc_buftbl_limit = 0xFFFFFFFF;
328
329	encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
330	encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
331	encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
332
333	/*
334	 * Get the current privilege mask. Note that this may be modified
335	 * dynamically, so this value is informational only. DO NOT use
336	 * the privilege mask to check for sufficient privileges, as that
337	 * can result in time-of-check/time-of-use bugs.
338	 */
339	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
340		goto fail13;
341	encp->enc_privilege_mask = mask;
342
343	/* Get interrupt vector limits */
344	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
345		if (EFX_PCI_FUNCTION_IS_PF(encp))
346			goto fail14;
347
348		/* Ignore error (cannot query vector limits from a VF). */
349		base = 0;
350		nvec = 1024;
351	}
352	encp->enc_intr_vec_base = base;
353	encp->enc_intr_limit = nvec;
354
355	/*
356	 * Maximum number of bytes into the frame the TCP header can start for
357	 * firmware assisted TSO to work.
358	 */
359	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
360
361	if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
362		goto fail15;
363	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
364
365	/* All Huntington devices have a PCIe Gen3, 8 lane connector */
366	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
367
368	return (0);
369
370fail15:
371	EFSYS_PROBE(fail15);
372fail14:
373	EFSYS_PROBE(fail14);
374fail13:
375	EFSYS_PROBE(fail13);
376fail12:
377	EFSYS_PROBE(fail12);
378fail11:
379	EFSYS_PROBE(fail11);
380fail10:
381	EFSYS_PROBE(fail10);
382fail9:
383	EFSYS_PROBE(fail9);
384fail8:
385	EFSYS_PROBE(fail8);
386fail7:
387	EFSYS_PROBE(fail7);
388fail6:
389	EFSYS_PROBE(fail6);
390fail5:
391	EFSYS_PROBE(fail5);
392fail4:
393	EFSYS_PROBE(fail4);
394fail3:
395	EFSYS_PROBE(fail3);
396fail2:
397	EFSYS_PROBE(fail2);
398fail1:
399	EFSYS_PROBE1(fail1, efx_rc_t, rc);
400
401	return (rc);
402}
403
404
405#endif	/* EFSYS_OPT_HUNTINGTON */
406