1/*
2 * Copyright (c) 2013-2016 Qlogic Corporation
3 * All rights reserved.
4 *
5 *  Redistribution and use in source and binary forms, with or without
6 *  modification, are permitted provided that the following conditions
7 *  are met:
8 *
9 *  1. Redistributions of source code must retain the above copyright
10 *     notice, this list of conditions and the following disclaimer.
11 *  2. Redistributions in binary form must reproduce the above copyright
12 *     notice, this list of conditions and the following disclaimer in the
13 *     documentation and/or other materials provided with the distribution.
14 *
15 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 *  POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * File: ql_minidump.h
30 *
31 * $FreeBSD$
32 */
33#ifndef _QL_MINIDUMP_H_
34#define _QL_MINIDUMP_H_
35
36#define QL_DBG_STATE_ARRAY_LEN          16
37#define QL_DBG_CAP_SIZE_ARRAY_LEN       8
38#define QL_NO_OF_OCM_WINDOWS            16
39
40
41typedef struct ql_mdump_tmplt_hdr {
42        uint32_t  entry_type ;
43        uint32_t  first_entry_offset ;
44        uint32_t  size_of_template ;
45        uint32_t  recommended_capture_mask;
46
47        uint32_t  num_of_entries ;
48        uint32_t  version ;
49        uint32_t  driver_timestamp ;
50        uint32_t  checksum ;
51
52        uint32_t  driver_capture_mask ;
53        uint32_t  driver_info_word2 ;
54        uint32_t  driver_info_word3 ;
55        uint32_t  driver_info_word4 ;
56
57        uint32_t  saved_state_array[QL_DBG_STATE_ARRAY_LEN] ;
58        uint32_t  capture_size_array[QL_DBG_CAP_SIZE_ARRAY_LEN] ;
59
60        uint32_t ocm_window_array[QL_NO_OF_OCM_WINDOWS] ;
61} ql_minidump_template_hdr_t ;
62
63/*
64 * MIU AGENT ADDRESSES.
65 */
66
67#define MD_TA_CTL_ENABLE                0x2
68#define MD_TA_CTL_START                 0x1
69#define MD_TA_CTL_BUSY                  0x8
70#define MD_TA_CTL_CHECK                 1000
71
72#define MD_MIU_TEST_AGT_CTRL            0x41000090
73#define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
74#define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
75
76#define MD_MIU_TEST_AGT_RDDATA_0_31     0x410000A8
77#define MD_MIU_TEST_AGT_RDDATA_32_63    0x410000AC
78#define MD_MIU_TEST_AGT_RDDATA_64_95    0x410000B8
79#define MD_MIU_TEST_AGT_RDDATA_96_127   0x410000BC
80
81#define MD_MIU_TEST_AGT_WRDATA_0_31     0x410000A0
82#define MD_MIU_TEST_AGT_WRDATA_32_63    0x410000A4
83#define MD_MIU_TEST_AGT_WRDATA_64_95    0x410000B0
84#define MD_MIU_TEST_AGT_WRDATA_96_127   0x410000B4
85
86/*
87 * ROM Read Address
88 */
89
90#define MD_DIRECT_ROM_WINDOW            0x42110030
91#define MD_DIRECT_ROM_READ_BASE         0x42150000
92
93/*
94 * Entry Type Defines
95 */
96
97#define RDNOP			0
98#define RDCRB			1
99#define	RDMUX			2
100#define QUEUE			3
101#define BOARD			4
102#define RDOCM			6
103#define L1DAT			11
104#define L1INS			12
105#define L2DTG                  	21
106#define L2ITG                  	22
107#define L2DAT                  	23
108#define L2INS                  	24
109#define POLLRD                  35
110#define RDMUX2                  36
111#define POLLRDMWR               37
112#define RDROM                  	71
113#define RDMEM                  	72
114#define CNTRL                  	98
115#define TLHDR                  	99
116#define RDEND			255
117
118/*
119 * Index of State Table.  The Template header maintains
120 * an array of 8 (0..7) words that is used to store some
121 * "State Information" from the board.
122 */
123
124#define QL_PCIE_FUNC_INDX       0
125#define QL_CLK_STATE_INDX       1
126#define QL_SRE_STATE_INDX       2
127#define QL_OCM0_ADDR_INDX       3
128
129#define QL_REVID_STATE_INDX     4
130#define QL_MAJVER_STATE_INDX    5
131#define QL_MINVER_STATE_INDX    6
132#define QL_SUBVER_STATE_INDX    7
133
134/*
135 * Opcodes for Control Entries.
136 * These Flags are bit fields.
137 */
138
139#define QL_DBG_OPCODE_WR        0x01
140#define QL_DBG_OPCODE_RW        0x02
141#define QL_DBG_OPCODE_AND       0x04
142#define QL_DBG_OPCODE_OR        0x08
143#define QL_DBG_OPCODE_POLL      0x10
144#define QL_DBG_OPCODE_RDSTATE   0x20
145#define QL_DBG_OPCODE_WRSTATE   0x40
146#define QL_DBG_OPCODE_MDSTATE   0x80
147
148typedef struct ql_minidump_entry_hdr_s {
149        uint32_t      entry_type ;
150        uint32_t      entry_size ;
151        uint32_t      entry_capture_size ;
152    	union {
153        	struct {
154            		uint8_t   entry_capture_mask ;
155            		uint8_t   entry_code ;
156            		uint8_t   driver_code ;
157            		uint8_t   driver_flags ;
158        	};
159        	uint32_t entry_ctrl_word ;
160    	};
161} ql_minidump_entry_hdr_t ;
162
163/*
164 * Driver Flags
165 */
166#define QL_DBG_SKIPPED_FLAG	0x80 /*  driver skipped this entry  */
167#define QL_DBG_SIZE_ERR_FLAG    0x40 /*  entry size vs capture size mismatch*/
168
169/*
170 * Generic Entry Including Header
171 */
172
173typedef struct ql_minidump_entry_s {
174        ql_minidump_entry_hdr_t hdr ;
175
176    uint32_t entry_data00 ;
177    uint32_t entry_data01 ;
178    uint32_t entry_data02 ;
179    uint32_t entry_data03 ;
180
181    uint32_t entry_data04 ;
182    uint32_t entry_data05 ;
183    uint32_t entry_data06 ;
184    uint32_t entry_data07 ;
185} ql_minidump_entry_t;
186
187/*
188 *  Read CRB Entry Header
189 */
190
191typedef struct ql_minidump_entry_rdcrb_s {
192        ql_minidump_entry_hdr_t h;
193
194        uint32_t addr ;
195    union {
196        struct {
197            uint8_t  addr_stride ;
198            uint8_t  rsvd_0;
199            uint16_t rsvd_1 ;
200        } ;
201            uint32_t addr_cntrl  ;
202    } ;
203
204        uint32_t data_size ;
205        uint32_t op_count;
206
207    uint32_t    rsvd_2 ;
208    uint32_t    rsvd_3 ;
209    uint32_t    rsvd_4 ;
210    uint32_t    rsvd_5 ;
211
212} ql_minidump_entry_rdcrb_t ;
213
214/*
215 * Cache Entry Header
216 */
217
218typedef struct ql_minidump_entry_cache_s {
219        ql_minidump_entry_hdr_t h;
220
221        uint32_t tag_reg_addr ;
222    	union {
223        	struct {
224            		uint16_t   tag_value_stride ;
225            		uint16_t  init_tag_value ;
226        	} ;
227            	uint32_t select_addr_cntrl  ;
228    	} ;
229
230        uint32_t data_size ;
231        uint32_t op_count;
232
233    	uint32_t control_addr ;
234    	union {
235        	struct {
236            		uint16_t  write_value ;
237            		uint8_t   poll_mask ;
238            		uint8_t   poll_wait ;
239        	};
240        	uint32_t control_value ;
241    	} ;
242
243    	uint32_t read_addr ;
244    	union {
245        	struct {
246            		uint8_t   read_addr_stride ;
247            		uint8_t   read_addr_cnt ;
248            		uint16_t  rsvd_1 ;
249        	} ;
250            	uint32_t read_addr_cntrl  ;
251    	} ;
252} ql_minidump_entry_cache_t ;
253
254
255/*
256 * Read OCM Entry Header
257 */
258
259typedef struct ql_minidump_entry_rdocm_s {
260        ql_minidump_entry_hdr_t h;
261
262        uint32_t rsvd_0 ;
263        uint32_t rsvd_1 ;
264
265        uint32_t data_size ;
266        uint32_t op_count;
267
268    uint32_t rsvd_2 ;
269    uint32_t rsvd_3 ;
270
271    uint32_t read_addr ;
272    uint32_t read_addr_stride ;
273
274} ql_minidump_entry_rdocm_t ;
275
276/*
277 * Read MEM Entry Header
278 */
279
280typedef struct ql_minidump_entry_rdmem_s {
281        ql_minidump_entry_hdr_t h;
282
283    uint32_t rsvd_0[6] ;
284
285    uint32_t read_addr ;
286    uint32_t read_data_size ;
287
288} ql_minidump_entry_rdmem_t ;
289
290/*
291 * Read ROM Entry Header
292 */
293
294typedef struct ql_minidump_entry_rdrom_s {
295        ql_minidump_entry_hdr_t h;
296
297    uint32_t rsvd_0[6] ;
298
299    uint32_t read_addr ;
300    uint32_t read_data_size ;
301
302} ql_minidump_entry_rdrom_t ;
303
304/*
305 * Read MUX Entry Header
306 */
307
308typedef struct ql_minidump_entry_mux_s {
309        ql_minidump_entry_hdr_t h;
310
311        uint32_t select_addr ;
312    union {
313        struct {
314            uint32_t rsvd_0 ;
315        } ;
316            uint32_t select_addr_cntrl  ;
317    } ;
318
319        uint32_t data_size ;
320        uint32_t op_count;
321
322    uint32_t select_value ;
323    uint32_t select_value_stride ;
324
325    uint32_t read_addr ;
326    uint32_t rsvd_1 ;
327
328} ql_minidump_entry_mux_t ;
329
330/*
331 * Read MUX2 Entry Header
332 */
333
334typedef struct ql_minidump_entry_mux2_s {
335        ql_minidump_entry_hdr_t h;
336
337        uint32_t select_addr_1;
338        uint32_t select_addr_2;
339        uint32_t select_value_1;
340        uint32_t select_value_2;
341        uint32_t select_value_count;
342        uint32_t select_value_mask;
343        uint32_t read_addr;
344        union {
345                struct {
346                        uint8_t select_value_stride;
347                        uint8_t data_size;
348                        uint8_t reserved_0;
349                        uint8_t reserved_1;
350                };
351                uint32_t select_addr_value_cntrl;
352        };
353
354} ql_minidump_entry_mux2_t;
355
356/*
357 * Read QUEUE Entry Header
358 */
359
360typedef struct ql_minidump_entry_queue_s {
361        ql_minidump_entry_hdr_t h;
362
363        uint32_t select_addr ;
364    union {
365        struct {
366            uint16_t  queue_id_stride ;
367            uint16_t  rsvd_0 ;
368        } ;
369            uint32_t select_addr_cntrl  ;
370    } ;
371
372        uint32_t data_size ;
373        uint32_t op_count ;
374
375    uint32_t rsvd_1 ;
376    uint32_t rsvd_2 ;
377
378    uint32_t read_addr ;
379    union {
380        struct {
381            uint8_t   read_addr_stride ;
382            uint8_t   read_addr_cnt ;
383            uint16_t  rsvd_3 ;
384        } ;
385            uint32_t read_addr_cntrl  ;
386    } ;
387
388} ql_minidump_entry_queue_t ;
389
390/*
391 * Control Entry Header
392 */
393
394typedef struct ql_minidump_entry_cntrl_s {
395        ql_minidump_entry_hdr_t h;
396
397        uint32_t addr ;
398    union {
399        struct {
400            uint8_t  addr_stride ;
401            uint8_t  state_index_a ;
402            uint16_t poll_timeout ;
403        } ;
404            uint32_t addr_cntrl  ;
405    } ;
406
407        uint32_t data_size ;
408        uint32_t op_count;
409
410    union {
411        struct {
412            uint8_t opcode ;
413            uint8_t state_index_v ;
414            uint8_t shl ;
415            uint8_t shr ;
416        } ;
417        uint32_t control_value ;
418    } ;
419
420    uint32_t value_1 ;
421    uint32_t value_2 ;
422    uint32_t value_3 ;
423} ql_minidump_entry_cntrl_t ;
424
425/*
426 * Read with poll.
427 */
428
429typedef struct ql_minidump_entry_rdcrb_with_poll_s {
430        ql_minidump_entry_hdr_t h;
431
432        uint32_t select_addr;
433        uint32_t read_addr;
434        uint32_t select_value;
435        union {
436                struct {
437                        uint16_t select_value_stride;
438                        uint16_t op_count;
439                };
440                uint32_t select_value_cntrl;
441        };
442
443        uint32_t poll;
444        uint32_t mask;
445
446        uint32_t data_size;
447        uint32_t rsvd_0;
448
449} ql_minidump_entry_pollrd_t;
450
451/*
452 * Read_Modify_Write with poll.
453 */
454
455typedef struct ql_minidump_entry_rd_modify_wr_with_poll_s {
456        ql_minidump_entry_hdr_t h;
457
458        uint32_t addr_1;
459        uint32_t addr_2;
460        uint32_t value_1;
461        uint32_t value_2;
462        uint32_t poll;
463        uint32_t mask;
464        uint32_t modify_mask;
465        uint32_t data_size;
466
467} ql_minidump_entry_rd_modify_wr_with_poll_t;
468
469#endif /* #ifndef _QL_MINIDUMP_H_ */
470
471