1/*-
2 * Copyright (c) 1999 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
7 * NASA Ames Research Center.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 *
30 *	from: NetBSD: ofw_pci.h,v 1.5 2003/10/22 09:04:39 mjl Exp
31 *
32 * $FreeBSD$
33 */
34
35#ifndef _DEV_OFW_OFW_PCI_H_
36#define	_DEV_OFW_OFW_PCI_H_
37
38/*
39 * PCI Bus Binding to:
40 *
41 * IEEE Std 1275-1994
42 * Standard for Boot (Initialization Configuration) Firmware
43 *
44 * Revision 2.1
45 */
46
47/*
48 * Section 2.2.1. Physical Address Formats
49 *
50 * A PCI physical address is represented by 3 address cells:
51 *
52 *	phys.hi cell:	npt000ss bbbbbbbb dddddfff rrrrrrrr
53 *	phys.mid cell:	hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
54 *	phys.lo cell:	llllllll llllllll llllllll llllllll
55 *
56 *	n	nonrelocatable
57 *	p	prefetchable
58 *	t	aliased below 1MB (memory) or 64k (i/o)
59 *	ss	space code
60 *	b	bus number
61 *	d	device number
62 *	f	function number
63 *	r	register number
64 *	h	high 32-bits of PCI address
65 *	l	low 32-bits of PCI address
66 */
67
68#define	OFW_PCI_PHYS_HI_NONRELOCATABLE	0x80000000
69#define	OFW_PCI_PHYS_HI_PREFETCHABLE	0x40000000
70#define	OFW_PCI_PHYS_HI_ALIASED		0x20000000
71#define	OFW_PCI_PHYS_HI_SPACEMASK	0x03000000
72#define	OFW_PCI_PHYS_HI_BUSMASK		0x00ff0000
73#define	OFW_PCI_PHYS_HI_BUSSHIFT	16
74#define	OFW_PCI_PHYS_HI_DEVICEMASK	0x0000f800
75#define	OFW_PCI_PHYS_HI_DEVICESHIFT	11
76#define	OFW_PCI_PHYS_HI_FUNCTIONMASK	0x00000700
77#define	OFW_PCI_PHYS_HI_FUNCTIONSHIFT	8
78#define	OFW_PCI_PHYS_HI_REGISTERMASK	0x000000ff
79
80#define	OFW_PCI_PHYS_HI_SPACE_CONFIG	0x00000000
81#define	OFW_PCI_PHYS_HI_SPACE_IO	0x01000000
82#define	OFW_PCI_PHYS_HI_SPACE_MEM32	0x02000000
83#define	OFW_PCI_PHYS_HI_SPACE_MEM64	0x03000000
84
85#define OFW_PCI_PHYS_HI_BUS(hi) \
86	(((hi) & OFW_PCI_PHYS_HI_BUSMASK) >> OFW_PCI_PHYS_HI_BUSSHIFT)
87#define OFW_PCI_PHYS_HI_DEVICE(hi) \
88	(((hi) & OFW_PCI_PHYS_HI_DEVICEMASK) >> OFW_PCI_PHYS_HI_DEVICESHIFT)
89#define OFW_PCI_PHYS_HI_FUNCTION(hi) \
90	(((hi) & OFW_PCI_PHYS_HI_FUNCTIONMASK) >> OFW_PCI_PHYS_HI_FUNCTIONSHIFT)
91
92/*
93 * This has the 3 32bit cell values, plus 2 more to make up a 64-bit size.
94 */
95struct ofw_pci_register {
96	u_int32_t	phys_hi;
97	u_int32_t	phys_mid;
98	u_int32_t	phys_lo;
99	u_int32_t	size_hi;
100	u_int32_t	size_lo;
101};
102
103#endif /* _DEV_OFW_OFW_PCI_H_ */
104