1/*- 2 * Copyright (C) 2012-2014 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/bio.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/mutex.h> 39#include <sys/rman.h> 40#include <sys/systm.h> 41#include <sys/taskqueue.h> 42 43#include <vm/uma.h> 44 45#include <machine/bus.h> 46 47#include "nvme.h" 48 49#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 50 51MALLOC_DECLARE(M_NVME); 52 53#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 54#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 55 56/* 57 * For commands requiring more than 2 PRP entries, one PRP will be 58 * embedded in the command (prp1), and the rest of the PRP entries 59 * will be in a list pointed to by the command (prp2). This means 60 * that real max number of PRP entries we support is 32+1, which 61 * results in a max xfer size of 32*PAGE_SIZE. 62 */ 63#define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE) 64 65#define NVME_ADMIN_TRACKERS (16) 66#define NVME_ADMIN_ENTRIES (128) 67/* min and max are defined in admin queue attributes section of spec */ 68#define NVME_MIN_ADMIN_ENTRIES (2) 69#define NVME_MAX_ADMIN_ENTRIES (4096) 70 71/* 72 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 73 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 74 * will allow outstanding on an I/O qpair at any time. The only advantage in 75 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 76 * the contents of the submission and completion queues, it will show a longer 77 * history of data. 78 */ 79#define NVME_IO_ENTRIES (256) 80#define NVME_IO_TRACKERS (128) 81#define NVME_MIN_IO_TRACKERS (4) 82#define NVME_MAX_IO_TRACKERS (1024) 83 84/* 85 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 86 * for each controller. 87 */ 88 89#define NVME_INT_COAL_TIME (0) /* disabled */ 90#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 91 92#define NVME_MAX_NAMESPACES (16) 93#define NVME_MAX_CONSUMERS (2) 94#define NVME_MAX_ASYNC_EVENTS (8) 95 96#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 97#define NVME_MIN_TIMEOUT_PERIOD (5) 98#define NVME_MAX_TIMEOUT_PERIOD (120) 99 100#define NVME_DEFAULT_RETRY_COUNT (4) 101 102/* Maximum log page size to fetch for AERs. */ 103#define NVME_MAX_AER_LOG_SIZE (4096) 104 105/* 106 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 107 * it. 108 */ 109#ifndef CACHE_LINE_SIZE 110#define CACHE_LINE_SIZE (64) 111#endif 112 113/* 114 * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O 115 * support and the bus_dmamap_load_bio API are available on the target 116 * kernel. This will ease porting back to earlier stable branches at a 117 * later point. 118 */ 119#ifdef BIO_UNMAPPED 120#define NVME_UNMAPPED_BIO_SUPPORT 121#endif 122 123extern uma_zone_t nvme_request_zone; 124extern int32_t nvme_retry_count; 125 126struct nvme_completion_poll_status { 127 128 struct nvme_completion cpl; 129 boolean_t done; 130}; 131 132#define NVME_REQUEST_VADDR 1 133#define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 134#define NVME_REQUEST_UIO 3 135#ifdef NVME_UNMAPPED_BIO_SUPPORT 136#define NVME_REQUEST_BIO 4 137#endif 138 139struct nvme_request { 140 141 struct nvme_command cmd; 142 struct nvme_qpair *qpair; 143 union { 144 void *payload; 145 struct bio *bio; 146 } u; 147 uint32_t type; 148 uint32_t payload_size; 149 boolean_t timeout; 150 nvme_cb_fn_t cb_fn; 151 void *cb_arg; 152 int32_t retries; 153 STAILQ_ENTRY(nvme_request) stailq; 154}; 155 156struct nvme_async_event_request { 157 158 struct nvme_controller *ctrlr; 159 struct nvme_request *req; 160 struct nvme_completion cpl; 161 uint32_t log_page_id; 162 uint32_t log_page_size; 163 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 164}; 165 166struct nvme_tracker { 167 168 TAILQ_ENTRY(nvme_tracker) tailq; 169 struct nvme_request *req; 170 struct nvme_qpair *qpair; 171 struct callout timer; 172 bus_dmamap_t payload_dma_map; 173 uint16_t cid; 174 175 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 176 bus_addr_t prp_bus_addr; 177 bus_dmamap_t prp_dma_map; 178}; 179 180struct nvme_qpair { 181 182 struct nvme_controller *ctrlr; 183 uint32_t id; 184 uint32_t phase; 185 186 uint16_t vector; 187 int rid; 188 struct resource *res; 189 void *tag; 190 191 uint32_t num_entries; 192 uint32_t num_trackers; 193 uint32_t sq_tdbl_off; 194 uint32_t cq_hdbl_off; 195 196 uint32_t sq_head; 197 uint32_t sq_tail; 198 uint32_t cq_head; 199 200 int64_t num_cmds; 201 int64_t num_intr_handler_calls; 202 203 struct nvme_command *cmd; 204 struct nvme_completion *cpl; 205 206 bus_dma_tag_t dma_tag; 207 bus_dma_tag_t dma_tag_payload; 208 209 bus_dmamap_t cmd_dma_map; 210 uint64_t cmd_bus_addr; 211 212 bus_dmamap_t cpl_dma_map; 213 uint64_t cpl_bus_addr; 214 215 TAILQ_HEAD(, nvme_tracker) free_tr; 216 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 217 STAILQ_HEAD(, nvme_request) queued_req; 218 219 struct nvme_tracker **act_tr; 220 221 boolean_t is_enabled; 222 223 struct mtx lock __aligned(CACHE_LINE_SIZE); 224 225} __aligned(CACHE_LINE_SIZE); 226 227struct nvme_namespace { 228 229 struct nvme_controller *ctrlr; 230 struct nvme_namespace_data data; 231 uint16_t id; 232 uint16_t flags; 233 struct cdev *cdev; 234 void *cons_cookie[NVME_MAX_CONSUMERS]; 235 uint32_t stripesize; 236 struct mtx lock; 237}; 238 239/* 240 * One of these per allocated PCI device. 241 */ 242struct nvme_controller { 243 244 device_t dev; 245 246 struct mtx lock; 247 248 uint32_t ready_timeout_in_ms; 249 250 bus_space_tag_t bus_tag; 251 bus_space_handle_t bus_handle; 252 int resource_id; 253 struct resource *resource; 254 255 /* 256 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 257 * separate from the control registers which are in BAR 0/1. These 258 * members track the mapping of BAR 4/5 for that reason. 259 */ 260 int bar4_resource_id; 261 struct resource *bar4_resource; 262 263 uint32_t msix_enabled; 264 uint32_t force_intx; 265 uint32_t enable_aborts; 266 267 uint32_t num_io_queues; 268 uint32_t num_cpus_per_ioq; 269 270 /* Fields for tracking progress during controller initialization. */ 271 struct intr_config_hook config_hook; 272 uint32_t ns_identified; 273 uint32_t queues_created; 274 275 struct task reset_task; 276 struct task fail_req_task; 277 struct taskqueue *taskqueue; 278 279 /* For shared legacy interrupt. */ 280 int rid; 281 struct resource *res; 282 void *tag; 283 284 bus_dma_tag_t hw_desc_tag; 285 bus_dmamap_t hw_desc_map; 286 287 /** maximum i/o size in bytes */ 288 uint32_t max_xfer_size; 289 290 /** minimum page size supported by this controller in bytes */ 291 uint32_t min_page_size; 292 293 /** interrupt coalescing time period (in microseconds) */ 294 uint32_t int_coal_time; 295 296 /** interrupt coalescing threshold */ 297 uint32_t int_coal_threshold; 298 299 /** timeout period in seconds */ 300 uint32_t timeout_period; 301 302 struct nvme_qpair adminq; 303 struct nvme_qpair *ioq; 304 305 struct nvme_registers *regs; 306 307 struct nvme_controller_data cdata; 308 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 309 310 struct cdev *cdev; 311 312 /** bit mask of warning types currently enabled for async events */ 313 union nvme_critical_warning_state async_event_config; 314 315 uint32_t num_aers; 316 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 317 318 void *cons_cookie[NVME_MAX_CONSUMERS]; 319 320 uint32_t is_resetting; 321 uint32_t is_initialized; 322 uint32_t notification_sent; 323 324 boolean_t is_failed; 325 STAILQ_HEAD(, nvme_request) fail_req; 326}; 327 328#define nvme_mmio_offsetof(reg) \ 329 offsetof(struct nvme_registers, reg) 330 331#define nvme_mmio_read_4(sc, reg) \ 332 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 333 nvme_mmio_offsetof(reg)) 334 335#define nvme_mmio_write_4(sc, reg, val) \ 336 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 337 nvme_mmio_offsetof(reg), val) 338 339#define nvme_mmio_write_8(sc, reg, val) \ 340 do { \ 341 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 342 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 343 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 344 nvme_mmio_offsetof(reg)+4, \ 345 (val & 0xFFFFFFFF00000000UL) >> 32); \ 346 } while (0); 347 348#if __FreeBSD_version < 800054 349#define wmb() __asm volatile("sfence" ::: "memory") 350#define mb() __asm volatile("mfence" ::: "memory") 351#endif 352 353#define nvme_printf(ctrlr, fmt, args...) \ 354 device_printf(ctrlr->dev, fmt, ##args) 355 356void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 357 358void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 359 void *payload, 360 nvme_cb_fn_t cb_fn, void *cb_arg); 361void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 362 uint16_t nsid, void *payload, 363 nvme_cb_fn_t cb_fn, void *cb_arg); 364void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 365 uint32_t microseconds, 366 uint32_t threshold, 367 nvme_cb_fn_t cb_fn, 368 void *cb_arg); 369void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 370 struct nvme_error_information_entry *payload, 371 uint32_t num_entries, /* 0 = max */ 372 nvme_cb_fn_t cb_fn, 373 void *cb_arg); 374void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 375 uint32_t nsid, 376 struct nvme_health_information_page *payload, 377 nvme_cb_fn_t cb_fn, 378 void *cb_arg); 379void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 380 struct nvme_firmware_page *payload, 381 nvme_cb_fn_t cb_fn, 382 void *cb_arg); 383void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 384 struct nvme_qpair *io_que, uint16_t vector, 385 nvme_cb_fn_t cb_fn, void *cb_arg); 386void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 387 struct nvme_qpair *io_que, 388 nvme_cb_fn_t cb_fn, void *cb_arg); 389void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 390 struct nvme_qpair *io_que, 391 nvme_cb_fn_t cb_fn, void *cb_arg); 392void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 393 struct nvme_qpair *io_que, 394 nvme_cb_fn_t cb_fn, void *cb_arg); 395void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 396 uint32_t num_queues, nvme_cb_fn_t cb_fn, 397 void *cb_arg); 398void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 399 union nvme_critical_warning_state state, 400 nvme_cb_fn_t cb_fn, void *cb_arg); 401void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 402 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 403 404void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 405 406int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 407void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 408void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 409int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 410void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 411/* ctrlr defined as void * to allow use with config_intrhook. */ 412void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 413void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 414 struct nvme_request *req); 415void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 416 struct nvme_request *req); 417void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 418 struct nvme_request *req); 419 420void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 421 uint16_t vector, uint32_t num_entries, 422 uint32_t num_trackers, 423 struct nvme_controller *ctrlr); 424void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 425 struct nvme_tracker *tr); 426void nvme_qpair_process_completions(struct nvme_qpair *qpair); 427void nvme_qpair_submit_request(struct nvme_qpair *qpair, 428 struct nvme_request *req); 429void nvme_qpair_reset(struct nvme_qpair *qpair); 430void nvme_qpair_fail(struct nvme_qpair *qpair); 431void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 432 struct nvme_request *req, 433 uint32_t sct, uint32_t sc, 434 boolean_t print_on_error); 435 436void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 437void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 438void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 439 440void nvme_io_qpair_enable(struct nvme_qpair *qpair); 441void nvme_io_qpair_disable(struct nvme_qpair *qpair); 442void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 443 444int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 445 struct nvme_controller *ctrlr); 446void nvme_ns_destruct(struct nvme_namespace *ns); 447 448void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 449 450void nvme_dump_command(struct nvme_command *cmd); 451void nvme_dump_completion(struct nvme_completion *cpl); 452 453static __inline void 454nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 455{ 456 uint64_t *bus_addr = (uint64_t *)arg; 457 458 if (error != 0) 459 printf("nvme_single_map err %d\n", error); 460 *bus_addr = seg[0].ds_addr; 461} 462 463static __inline struct nvme_request * 464_nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 465{ 466 struct nvme_request *req; 467 468 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 469 if (req != NULL) { 470 req->cb_fn = cb_fn; 471 req->cb_arg = cb_arg; 472 req->timeout = TRUE; 473 } 474 return (req); 475} 476 477static __inline struct nvme_request * 478nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 479 nvme_cb_fn_t cb_fn, void *cb_arg) 480{ 481 struct nvme_request *req; 482 483 req = _nvme_allocate_request(cb_fn, cb_arg); 484 if (req != NULL) { 485 req->type = NVME_REQUEST_VADDR; 486 req->u.payload = payload; 487 req->payload_size = payload_size; 488 } 489 return (req); 490} 491 492static __inline struct nvme_request * 493nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 494{ 495 struct nvme_request *req; 496 497 req = _nvme_allocate_request(cb_fn, cb_arg); 498 if (req != NULL) 499 req->type = NVME_REQUEST_NULL; 500 return (req); 501} 502 503static __inline struct nvme_request * 504nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 505{ 506 struct nvme_request *req; 507 508 req = _nvme_allocate_request(cb_fn, cb_arg); 509 if (req != NULL) { 510#ifdef NVME_UNMAPPED_BIO_SUPPORT 511 req->type = NVME_REQUEST_BIO; 512 req->u.bio = bio; 513#else 514 req->type = NVME_REQUEST_VADDR; 515 req->u.payload = bio->bio_data; 516 req->payload_size = bio->bio_bcount; 517#endif 518 } 519 return (req); 520} 521 522#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 523 524void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 525 const struct nvme_completion *async_cpl, 526 uint32_t log_page_id, void *log_page_buffer, 527 uint32_t log_page_size); 528void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 529void nvme_notify_new_controller(struct nvme_controller *ctrlr); 530 531#endif /* __NVME_PRIVATE_H__ */ 532