1/* $NecBSD: nsp.c,v 1.21.12.6 2001/06/29 06:27:52 honda Exp $ */ 2/* $NetBSD$ */ 3 4#define NSP_DEBUG 5#define NSP_STATICS 6#define NSP_IO_CONTROL_FLAGS \ 7 (NSP_READ_SUSPEND_IO | NSP_WRITE_SUSPEND_IO | \ 8 NSP_READ_FIFO_INTERRUPTS | NSP_WRITE_FIFO_INTERRUPTS | \ 9 NSP_USE_MEMIO | NSP_WAIT_FOR_SELECT) 10 11/*- 12 * Copyright (c) 1998, 1999, 2000, 2001 13 * NetBSD/pc98 porting staff. All rights reserved. 14 * 15 * Copyright (c) 1998, 1999, 2000, 2001 16 * Naofumi HONDA. All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. The name of the author may not be used to endorse or promote products 27 * derived from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD$"); 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/kernel.h> 48#include <sys/bio.h> 49#include <sys/buf.h> 50#include <sys/queue.h> 51#include <sys/malloc.h> 52#include <sys/errno.h> 53 54#include <machine/cpu.h> 55#include <machine/bus.h> 56 57#include <cam/scsi/scsi_low.h> 58#include <dev/nsp/nspreg.h> 59#include <dev/nsp/nspvar.h> 60 61/*************************************************** 62 * USER SETTINGS 63 ***************************************************/ 64/* DEVICE CONFIGURATION FLAGS (MINOR) 65 * 66 * 0x01 DISCONNECT OFF 67 * 0x02 PARITY LINE OFF 68 * 0x04 IDENTIFY MSG OFF ( = single lun) 69 * 0x08 SYNC TRANSFER OFF 70 */ 71 72/*************************************************** 73 * PARAMS 74 ***************************************************/ 75#define NSP_NTARGETS 8 76#define NSP_NLUNS 8 77 78#define NSP_MAX_DATA_SIZE (64 * 1024) 79#define NSP_SELTIMEOUT (200) 80#define NSP_DELAY_MAX (2 * 1000 * 1000) 81#define NSP_DELAY_INTERVAL (1) 82#define NSP_TIMER_1MS (1000 / 51) 83 84/*************************************************** 85 * DEBUG 86 ***************************************************/ 87#ifdef NSP_DEBUG 88int nsp_debug; 89#endif /* NSP_DEBUG */ 90 91#ifdef NSP_STATICS 92struct nsp_statics { 93 int arbit_conflict_1; 94 int arbit_conflict_2; 95 int device_data_write; 96 int device_busy; 97 int disconnect; 98 int reselect; 99 int data_phase_bypass; 100} nsp_statics; 101#endif /* NSP_STATICS */ 102 103/*************************************************** 104 * IO control 105 ***************************************************/ 106#define NSP_READ_SUSPEND_IO 0x0001 107#define NSP_WRITE_SUSPEND_IO 0x0002 108#define NSP_USE_MEMIO 0x0004 109#define NSP_READ_FIFO_INTERRUPTS 0x0010 110#define NSP_WRITE_FIFO_INTERRUPTS 0x0020 111#define NSP_WAIT_FOR_SELECT 0x0100 112 113u_int nsp_io_control = NSP_IO_CONTROL_FLAGS; 114int nsp_read_suspend_bytes = DEV_BSIZE; 115int nsp_write_suspend_bytes = DEV_BSIZE; 116int nsp_read_interrupt_bytes = 4096; 117int nsp_write_interrupt_bytes = 4096; 118 119/*************************************************** 120 * DEVICE STRUCTURE 121 ***************************************************/ 122extern struct cfdriver nsp_cd; 123 124/************************************************************** 125 * DECLARE 126 **************************************************************/ 127#define NSP_FIFO_ON 1 128#define NSP_FIFO_OFF 0 129static void nsp_pio_read(struct nsp_softc *, int); 130static void nsp_pio_write(struct nsp_softc *, int); 131static int nsp_xfer(struct nsp_softc *, u_int8_t *, int, int, int); 132static int nsp_msg(struct nsp_softc *, struct targ_info *, u_int); 133static int nsp_reselected(struct nsp_softc *); 134static int nsp_disconnected(struct nsp_softc *, struct targ_info *); 135static void nsp_pdma_end(struct nsp_softc *, struct targ_info *); 136static void nsphw_init(struct nsp_softc *); 137static int nsp_target_nexus_establish(struct nsp_softc *); 138static int nsp_lun_nexus_establish(struct nsp_softc *); 139static int nsp_ccb_nexus_establish(struct nsp_softc *); 140static int nsp_world_start(struct nsp_softc *, int); 141static int nsphw_start_selection(struct nsp_softc *sc, struct slccb *); 142static void nsphw_bus_reset(struct nsp_softc *); 143static void nsphw_attention(struct nsp_softc *); 144static u_int nsp_fifo_count(struct nsp_softc *); 145static u_int nsp_request_count(struct nsp_softc *); 146static int nsp_negate_signal(struct nsp_softc *, u_int8_t, u_char *); 147static int nsp_expect_signal(struct nsp_softc *, u_int8_t, u_int8_t); 148static void nsp_start_timer(struct nsp_softc *, int); 149static void nsp_setup_fifo(struct nsp_softc *, int, int, int); 150static int nsp_targ_init(struct nsp_softc *, struct targ_info *, int); 151static void nsphw_selection_done_and_expect_msgout(struct nsp_softc *); 152static void nsp_data_padding(struct nsp_softc *, int, u_int); 153static int nsp_timeout(struct nsp_softc *); 154static int nsp_read_fifo(struct nsp_softc *, int); 155static int nsp_write_fifo(struct nsp_softc *, int); 156static int nsp_phase_match(struct nsp_softc *, u_int8_t, u_int8_t); 157static int nsp_wait_interrupt(struct nsp_softc *); 158 159struct scsi_low_funcs nspfuncs = { 160 SC_LOW_INIT_T nsp_world_start, 161 SC_LOW_BUSRST_T nsphw_bus_reset, 162 SC_LOW_TARG_INIT_T nsp_targ_init, 163 SC_LOW_LUN_INIT_T NULL, 164 165 SC_LOW_SELECT_T nsphw_start_selection, 166 SC_LOW_NEXUS_T nsp_lun_nexus_establish, 167 SC_LOW_NEXUS_T nsp_ccb_nexus_establish, 168 169 SC_LOW_ATTEN_T nsphw_attention, 170 SC_LOW_MSG_T nsp_msg, 171 172 SC_LOW_TIMEOUT_T nsp_timeout, 173 SC_LOW_POLL_T nspintr, 174 175 NULL, 176}; 177 178/**************************************************** 179 * hwfuncs 180 ****************************************************/ 181static __inline u_int8_t nsp_cr_read_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ofs); 182static __inline void nsp_cr_write_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ofs, u_int8_t va); 183 184static __inline u_int8_t 185nsp_cr_read_1(bst, bsh, ofs) 186 bus_space_tag_t bst; 187 bus_space_handle_t bsh; 188 bus_addr_t ofs; 189{ 190 191 bus_space_write_1(bst, bsh, nsp_idxr, ofs); 192 return bus_space_read_1(bst, bsh, nsp_datar); 193} 194 195static __inline void 196nsp_cr_write_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_addr_t ofs, 197 u_int8_t va) 198{ 199 200 bus_space_write_1(bst, bsh, nsp_idxr, ofs); 201 bus_space_write_1(bst, bsh, nsp_datar, va); 202} 203 204static int 205nsp_expect_signal(struct nsp_softc *sc, u_int8_t curphase, u_int8_t mask) 206{ 207 struct scsi_low_softc *slp = &sc->sc_sclow; 208 bus_space_tag_t bst = sc->sc_iot; 209 bus_space_handle_t bsh = sc->sc_ioh; 210 int wc; 211 u_int8_t ph, isrc; 212 213 for (wc = 0; wc < NSP_DELAY_MAX / NSP_DELAY_INTERVAL; wc ++) 214 { 215 ph = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON); 216 if (ph == (u_int8_t) -1) 217 return -1; 218 219 isrc = bus_space_read_1(bst, bsh, nsp_irqsr); 220 if (isrc & IRQSR_SCSI) 221 return 0; 222 223 if ((ph & mask) != 0 && (ph & SCBUSMON_PHMASK) == curphase) 224 return 1; 225 226 DELAY(NSP_DELAY_INTERVAL); 227 } 228 229 device_printf(slp->sl_dev, "nsp_expect_signal timeout\n"); 230 return -1; 231} 232 233static void 234nsphw_init(sc) 235 struct nsp_softc *sc; 236{ 237 bus_space_tag_t bst = sc->sc_iot; 238 bus_space_handle_t bsh = sc->sc_ioh; 239 240 /* block all interrupts */ 241 bus_space_write_1(bst, bsh, nsp_irqcr, IRQCR_ALLMASK); 242 243 /* setup SCSI interface */ 244 bus_space_write_1(bst, bsh, nsp_ifselr, IFSELR_IFSEL); 245 246 nsp_cr_write_1(bst, bsh, NSPR_SCIENR, 0); 247 248 nsp_cr_write_1(bst, bsh, NSPR_XFERMR, XFERMR_IO8); 249 nsp_cr_write_1(bst, bsh, NSPR_CLKDIVR, sc->sc_iclkdiv); 250 251 nsp_cr_write_1(bst, bsh, NSPR_SCIENR, sc->sc_icr); 252 nsp_cr_write_1(bst, bsh, NSPR_PARITYR, sc->sc_parr); 253 nsp_cr_write_1(bst, bsh, NSPR_PTCLRR, 254 PTCLRR_ACK | PTCLRR_REQ | PTCLRR_HOST | PTCLRR_RSS); 255 256 /* setup fifo asic */ 257 bus_space_write_1(bst, bsh, nsp_ifselr, IFSELR_REGSEL); 258 nsp_cr_write_1(bst, bsh, NSPR_TERMPWRC, 0); 259 if ((nsp_cr_read_1(bst, bsh, NSPR_OCR) & OCR_TERMPWRS) == 0) 260 nsp_cr_write_1(bst, bsh, NSPR_TERMPWRC, TERMPWRC_POWON); 261 262 nsp_cr_write_1(bst, bsh, NSPR_XFERMR, XFERMR_IO8); 263 nsp_cr_write_1(bst, bsh, NSPR_CLKDIVR, sc->sc_clkdiv); 264 nsp_cr_write_1(bst, bsh, NSPR_TIMERCNT, 0); 265 nsp_cr_write_1(bst, bsh, NSPR_TIMERCNT, 0); 266 267 nsp_cr_write_1(bst, bsh, NSPR_SYNCR, 0); 268 nsp_cr_write_1(bst, bsh, NSPR_ACKWIDTH, 0); 269 270 /* enable interrupts and ack them */ 271 nsp_cr_write_1(bst, bsh, NSPR_SCIENR, sc->sc_icr); 272 bus_space_write_1(bst, bsh, nsp_irqcr, IRQSR_MASK); 273 274 nsp_setup_fifo(sc, NSP_FIFO_OFF, SCSI_LOW_READ, 0); 275} 276 277/**************************************************** 278 * scsi low interface 279 ****************************************************/ 280static void 281nsphw_attention(sc) 282 struct nsp_softc *sc; 283{ 284 bus_space_tag_t bst = sc->sc_iot; 285 bus_space_handle_t bsh = sc->sc_ioh; 286 u_int8_t cr; 287 288 cr = nsp_cr_read_1(bst, bsh, NSPR_SCBUSCR)/* & ~SCBUSCR_ACK */; 289 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, cr | SCBUSCR_ATN); 290 DELAY(10); 291} 292 293static void 294nsphw_bus_reset(sc) 295 struct nsp_softc *sc; 296{ 297 bus_space_tag_t bst = sc->sc_iot; 298 bus_space_handle_t bsh = sc->sc_ioh; 299 int i; 300 301 bus_space_write_1(bst, bsh, nsp_irqcr, IRQCR_ALLMASK); 302 303 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, SCBUSCR_RST); 304 DELAY(100 * 1000); /* 100ms */ 305 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, 0); 306 for (i = 0; i < 5; i ++) 307 (void) nsp_cr_read_1(bst, bsh, NSPR_IRQPHS); 308 309 bus_space_write_1(bst, bsh, nsp_irqcr, IRQSR_MASK); 310} 311 312static void 313nsphw_selection_done_and_expect_msgout(sc) 314 struct nsp_softc *sc; 315{ 316 struct scsi_low_softc *slp = &sc->sc_sclow; 317 bus_space_tag_t bst = sc->sc_iot; 318 bus_space_handle_t bsh = sc->sc_ioh; 319 320 /* clear ack counter */ 321 sc->sc_cnt = 0; 322 nsp_cr_write_1(bst, bsh, NSPR_PTCLRR, PTCLRR_PT | PTCLRR_ACK | 323 PTCLRR_REQ | PTCLRR_HOST); 324 325 /* deassert sel and assert atten */ 326 sc->sc_seltout = 0; 327 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, sc->sc_busc); 328 DELAY(1); 329 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, 330 sc->sc_busc | SCBUSCR_ADIR | SCBUSCR_ACKEN); 331 SCSI_LOW_ASSERT_ATN(slp); 332} 333 334static int 335nsphw_start_selection(sc, cb) 336 struct nsp_softc *sc; 337 struct slccb *cb; 338{ 339 struct scsi_low_softc *slp = &sc->sc_sclow; 340 bus_space_tag_t bst = sc->sc_iot; 341 bus_space_handle_t bsh = sc->sc_ioh; 342 struct targ_info *ti = cb->ti; 343 register u_int8_t arbs, ph; 344 int s, wc; 345 346 wc = sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 347 sc->sc_dataout_timeout = 0; 348 349 /* check bus free */ 350 s = splhigh(); 351 ph = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON); 352 if (ph != SCBUSMON_FREE) 353 { 354 splx(s); 355#ifdef NSP_STATICS 356 nsp_statics.arbit_conflict_1 ++; 357#endif /* NSP_STATICS */ 358 return SCSI_LOW_START_FAIL; 359 } 360 361 /* start arbitration */ 362 nsp_cr_write_1(bst, bsh, NSPR_ARBITS, ARBITS_EXEC); 363 splx(s); 364 365 SCSI_LOW_SETUP_PHASE(ti, PH_ARBSTART); 366 do 367 { 368 /* XXX: what a stupid chip! */ 369 arbs = nsp_cr_read_1(bst, bsh, NSPR_ARBITS); 370 DELAY(1); 371 } 372 while ((arbs & (ARBITS_WIN | ARBITS_FAIL)) == 0 && wc -- > 0); 373 374 if ((arbs & ARBITS_WIN) == 0) 375 { 376 nsp_cr_write_1(bst, bsh, NSPR_ARBITS, ARBITS_CLR); 377#ifdef NSP_STATICS 378 nsp_statics.arbit_conflict_2 ++; 379#endif /* NSP_STATICS */ 380 return SCSI_LOW_START_FAIL; 381 } 382 383 /* assert select line */ 384 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART); 385 scsi_low_arbit_win(slp); 386 387 s = splhigh(); 388 DELAY(3); 389 nsp_cr_write_1(bst, bsh, NSPR_DATA, 390 sc->sc_idbit | (1 << ti->ti_id)); 391 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, 392 SCBUSCR_SEL | SCBUSCR_BSY | sc->sc_busc); 393 DELAY(3); 394 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, SCBUSCR_SEL | 395 SCBUSCR_BSY | SCBUSCR_DOUT | sc->sc_busc); 396 nsp_cr_write_1(bst, bsh, NSPR_ARBITS, ARBITS_CLR); 397 DELAY(3); 398 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, 399 SCBUSCR_SEL | SCBUSCR_DOUT | sc->sc_busc); 400 DELAY(1); 401 402 if ((nsp_io_control & NSP_WAIT_FOR_SELECT) != 0) 403 { 404#define NSP_FIRST_SEL_WAIT 300 405#define NSP_SEL_CHECK_INTERVAL 10 406 407 /* wait for a selection response */ 408 for (wc = 0; wc < NSP_FIRST_SEL_WAIT / NSP_SEL_CHECK_INTERVAL; 409 wc ++) 410 { 411 ph = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON); 412 if ((ph & SCBUSMON_BSY) == 0) 413 { 414 DELAY(NSP_SEL_CHECK_INTERVAL); 415 continue; 416 } 417 418 DELAY(1); 419 ph = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON); 420 if ((ph & SCBUSMON_BSY) != 0) 421 { 422 nsphw_selection_done_and_expect_msgout(sc); 423 splx(s); 424 425 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED); 426 return SCSI_LOW_START_OK; 427 } 428 } 429 } 430 splx(s); 431 432 /* check a selection timeout */ 433 nsp_start_timer(sc, NSP_TIMER_1MS); 434 sc->sc_seltout = 1; 435 return SCSI_LOW_START_OK; 436} 437 438static int 439nsp_world_start(sc, fdone) 440 struct nsp_softc *sc; 441 int fdone; 442{ 443 struct scsi_low_softc *slp = &sc->sc_sclow; 444 445 sc->sc_cnt = 0; 446 sc->sc_seltout = 0; 447 448 if ((slp->sl_cfgflags & CFG_NOATTEN) == 0) 449 sc->sc_busc = SCBUSCR_ATN; 450 else 451 sc->sc_busc = 0; 452 453 if ((slp->sl_cfgflags & CFG_NOPARITY) == 0) 454 sc->sc_parr = PARITYR_ENABLE | PARITYR_CLEAR; 455 else 456 sc->sc_parr = 0; 457 458 sc->sc_icr = (SCIENR_SCCHG | SCIENR_RESEL | SCIENR_RST); 459 460 nsphw_init(sc); 461 scsi_low_bus_reset(slp); 462 463 return 0; 464} 465 466struct ncp_synch_data { 467 u_int min_period; 468 u_int max_period; 469 u_int chip_period; 470 u_int ack_width; 471}; 472 473static struct ncp_synch_data ncp_sync_data_40M[] = { 474 {0x0c,0x0c,0x1,0}, /* 20MB 50ns*/ 475 {0x19,0x19,0x3,1}, /* 10MB 100ns*/ 476 {0x1a,0x25,0x5,2}, /* 7.5MB 150ns*/ 477 {0x26,0x32,0x7,3}, /* 5MB 200ns*/ 478 {0x0, 0, 0, 0} 479}; 480 481static struct ncp_synch_data ncp_sync_data_20M[] = { 482 {0x19,0x19,0x1,0}, /* 10MB 100ns*/ 483 {0x1a,0x25,0x2,0}, /* 7.5MB 150ns*/ 484 {0x26,0x32,0x3,1}, /* 5MB 200ns*/ 485 {0x0, 0, 0, 0} 486}; 487 488static int 489nsp_msg(sc, ti, msg) 490 struct nsp_softc *sc; 491 struct targ_info *ti; 492 u_int msg; 493{ 494 bus_space_tag_t bst = sc->sc_iot; 495 bus_space_handle_t bsh = sc->sc_ioh; 496 struct ncp_synch_data *sdp; 497 struct nsp_targ_info *nti = (void *) ti; 498 u_int period, offset; 499 int i, error; 500 501 if ((msg & SCSI_LOW_MSG_WIDE) != 0) 502 { 503 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8) 504 { 505 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 506 return EINVAL; 507 } 508 return 0; 509 } 510 511 if ((msg & SCSI_LOW_MSG_SYNCH) == 0) 512 return 0; 513 514 period = ti->ti_maxsynch.period; 515 offset = ti->ti_maxsynch.offset; 516 if (sc->sc_iclkdiv == CLKDIVR_20M) 517 sdp = &ncp_sync_data_20M[0]; 518 else 519 sdp = &ncp_sync_data_40M[0]; 520 521 for (i = 0; sdp->max_period != 0; i ++, sdp ++) 522 { 523 if (period >= sdp->min_period && period <= sdp->max_period) 524 break; 525 } 526 527 if (period != 0 && sdp->max_period == 0) 528 { 529 /* 530 * NO proper period/offset found, 531 * Retry neg with the target. 532 */ 533 ti->ti_maxsynch.period = 0; 534 ti->ti_maxsynch.offset = 0; 535 nti->nti_reg_syncr = 0; 536 nti->nti_reg_ackwidth = 0; 537 error = EINVAL; 538 } 539 else 540 { 541 nti->nti_reg_syncr = (sdp->chip_period << SYNCR_PERS) | 542 (offset & SYNCR_OFFM); 543 nti->nti_reg_ackwidth = sdp->ack_width; 544 error = 0; 545 } 546 547 nsp_cr_write_1(bst, bsh, NSPR_SYNCR, nti->nti_reg_syncr); 548 nsp_cr_write_1(bst, bsh, NSPR_ACKWIDTH, nti->nti_reg_ackwidth); 549 return error; 550} 551 552static int 553nsp_targ_init(sc, ti, action) 554 struct nsp_softc *sc; 555 struct targ_info *ti; 556 int action; 557{ 558 struct nsp_targ_info *nti = (void *) ti; 559 560 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE) 561 { 562 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 563 ti->ti_maxsynch.period = 100 / 4; 564 ti->ti_maxsynch.offset = 15; 565 nti->nti_reg_syncr = 0; 566 nti->nti_reg_ackwidth = 0; 567 } 568 return 0; 569} 570 571static void 572nsp_start_timer(sc, time) 573 struct nsp_softc *sc; 574 int time; 575{ 576 bus_space_tag_t bst = sc->sc_iot; 577 bus_space_handle_t bsh = sc->sc_ioh; 578 579 sc->sc_timer = time; 580 nsp_cr_write_1(bst, bsh, NSPR_TIMERCNT, time); 581} 582 583/************************************************************** 584 * General probe attach 585 **************************************************************/ 586int 587nspprobesubr(iot, ioh, dvcfg) 588 bus_space_tag_t iot; 589 bus_space_handle_t ioh; 590 u_int dvcfg; 591{ 592 u_int8_t regv; 593 594 regv = bus_space_read_1(iot, ioh, nsp_fifosr); 595 if (regv < 0x11 || regv >= 0x20) 596 return 0; 597 return 1; 598} 599 600void 601nspattachsubr(sc) 602 struct nsp_softc *sc; 603{ 604 struct scsi_low_softc *slp = &sc->sc_sclow; 605 606 printf("\n"); 607 608 sc->sc_idbit = (1 << slp->sl_hostid); 609 slp->sl_flags |= HW_READ_PADDING; 610 slp->sl_funcs = &nspfuncs; 611 sc->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */ 612 613 (void) scsi_low_attach(slp, 0, NSP_NTARGETS, NSP_NLUNS, 614 sizeof(struct nsp_targ_info), 0); 615} 616 617/************************************************************** 618 * PDMA functions 619 **************************************************************/ 620static u_int 621nsp_fifo_count(sc) 622 struct nsp_softc *sc; 623{ 624 bus_space_tag_t bst = sc->sc_iot; 625 bus_space_handle_t bsh = sc->sc_ioh; 626 u_int count; 627 628 nsp_cr_write_1(bst, bsh, NSPR_PTCLRR, PTCLRR_RSS_ACK | PTCLRR_PT); 629 count = bus_space_read_1(bst, bsh, nsp_datar); 630 count += (((u_int) bus_space_read_1(bst, bsh, nsp_datar)) << 8); 631 count += (((u_int) bus_space_read_1(bst, bsh, nsp_datar)) << 16); 632 return count; 633} 634 635static u_int 636nsp_request_count(sc) 637 struct nsp_softc *sc; 638{ 639 bus_space_tag_t bst = sc->sc_iot; 640 bus_space_handle_t bsh = sc->sc_ioh; 641 u_int count; 642 643 nsp_cr_write_1(bst, bsh, NSPR_PTCLRR, PTCLRR_RSS_REQ | PTCLRR_PT); 644 count = bus_space_read_1(bst, bsh, nsp_datar); 645 count += (((u_int) bus_space_read_1(bst, bsh, nsp_datar)) << 8); 646 count += (((u_int) bus_space_read_1(bst, bsh, nsp_datar)) << 16); 647 return count; 648} 649 650static void 651nsp_setup_fifo(sc, on, direction, datalen) 652 struct nsp_softc *sc; 653 int on; 654 int direction; 655 int datalen; 656{ 657 u_int8_t xfermode; 658 659 sc->sc_suspendio = 0; 660 if (on == NSP_FIFO_OFF) 661 { 662 xfermode = XFERMR_IO8; 663 goto out; 664 } 665 666 /* check if suspend io OK ? */ 667 if (datalen > 0) 668 { 669 if (direction == SCSI_LOW_READ) 670 { 671 if ((nsp_io_control & NSP_READ_SUSPEND_IO) != 0 && 672 (datalen % nsp_read_suspend_bytes) == 0) 673 sc->sc_suspendio = nsp_read_suspend_bytes; 674 } 675 else 676 { 677 if ((nsp_io_control & NSP_WRITE_SUSPEND_IO) != 0 && 678 (datalen % nsp_write_suspend_bytes) == 0) 679 sc->sc_suspendio = nsp_write_suspend_bytes; 680 } 681 } 682 683 /* determine a transfer type */ 684 if (datalen < DEV_BSIZE || (datalen & 3) != 0) 685 { 686 if (sc->sc_memh != 0 && 687 (nsp_io_control & NSP_USE_MEMIO) != 0) 688 xfermode = XFERMR_XEN | XFERMR_MEM8; 689 else 690 xfermode = XFERMR_XEN | XFERMR_IO8; 691 } 692 else 693 { 694 if (sc->sc_memh != 0 && 695 (nsp_io_control & NSP_USE_MEMIO) != 0) 696 xfermode = XFERMR_XEN | XFERMR_MEM32; 697 else 698 xfermode = XFERMR_XEN | XFERMR_IO32; 699 700 if (sc->sc_suspendio > 0) 701 xfermode |= XFERMR_FIFOEN; 702 } 703 704out: 705 sc->sc_xfermr = xfermode; 706 nsp_cr_write_1(sc->sc_iot, sc->sc_ioh, NSPR_XFERMR, sc->sc_xfermr); 707} 708 709static void 710nsp_pdma_end(sc, ti) 711 struct nsp_softc *sc; 712 struct targ_info *ti; 713{ 714 struct scsi_low_softc *slp = &sc->sc_sclow; 715 struct slccb *cb = slp->sl_Qnexus; 716 u_int len = 0, cnt; 717 718 sc->sc_dataout_timeout = 0; 719 slp->sl_flags &= ~HW_PDMASTART; 720 nsp_setup_fifo(sc, NSP_FIFO_OFF, SCSI_LOW_READ, 0); 721 if ((sc->sc_icr & SCIENR_FIFO) != 0) 722 { 723 sc->sc_icr &= ~SCIENR_FIFO; 724 nsp_cr_write_1(sc->sc_iot, sc->sc_ioh, NSPR_SCIENR, sc->sc_icr); 725 } 726 727 if (cb == NULL) 728 { 729 slp->sl_error |= PDMAERR; 730 return; 731 } 732 733 if (ti->ti_phase == PH_DATA) 734 { 735 cnt = nsp_fifo_count(sc); 736 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE) 737 { 738 len = sc->sc_cnt - cnt; 739 if (sc->sc_cnt >= cnt && 740 slp->sl_scp.scp_datalen + len <= 741 cb->ccb_scp.scp_datalen) 742 { 743 slp->sl_scp.scp_data -= len; 744 slp->sl_scp.scp_datalen += len; 745 } 746 else 747 { 748 slp->sl_error |= PDMAERR; 749 device_printf(slp->sl_dev, 750 "len %x >= datalen %x\n", 751 len, slp->sl_scp.scp_datalen); 752 } 753 } 754 else if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 755 { 756 if (sc->sc_cnt != cnt || 757 sc->sc_cnt > cb->ccb_scp.scp_datalen) 758 { 759 slp->sl_error |= PDMAERR; 760 device_printf(slp->sl_dev, 761 "data read count error %x != %x (%x)\n", 762 sc->sc_cnt, cnt, 763 cb->ccb_scp.scp_datalen); 764 } 765 } 766 sc->sc_cnt = cnt; 767 scsi_low_data_finish(slp); 768 } 769 else 770 { 771 772 device_printf(slp->sl_dev, "data phase miss\n"); 773 slp->sl_error |= PDMAERR; 774 } 775} 776 777#define RFIFO_CRIT 64 778#define WFIFO_CRIT 32 779 780static void 781nsp_data_padding(sc, direction, count) 782 struct nsp_softc *sc; 783 int direction; 784 u_int count; 785{ 786 bus_space_tag_t bst = sc->sc_iot; 787 bus_space_handle_t bsh = sc->sc_ioh; 788 789 if (count > NSP_MAX_DATA_SIZE) 790 count = NSP_MAX_DATA_SIZE; 791 792 nsp_cr_write_1(bst, bsh, NSPR_XFERMR, XFERMR_XEN | XFERMR_IO8); 793 if (direction == SCSI_LOW_READ) 794 { 795 while (count -- > 0) 796 (void) bus_space_read_1(bst, bsh, nsp_fifodr); 797 } 798 else 799 { 800 while (count -- > 0) 801 (void) bus_space_write_1(bst, bsh, nsp_fifodr, 0); 802 } 803 nsp_cr_write_1(bst, bsh, NSPR_XFERMR, sc->sc_xfermr); 804} 805 806static int 807nsp_read_fifo(sc, suspendio) 808 struct nsp_softc *sc; 809 int suspendio; 810{ 811 struct scsi_low_softc *slp = &sc->sc_sclow; 812 bus_space_tag_t bst = sc->sc_iot; 813 bus_space_handle_t bsh = sc->sc_ioh; 814 u_int res; 815 816 res = nsp_fifo_count(sc); 817 if (res == sc->sc_cnt) 818 return 0; 819 820#ifdef NSP_DEBUG 821 if (res < sc->sc_cnt || res == (u_int) -1) 822 { 823 device_printf(slp->sl_dev, 824 "strange fifo ack count 0x%x < 0x%x\n", res, sc->sc_cnt); 825 return 0; 826 } 827#endif /* NSP_DEBUG */ 828 829 res = res - sc->sc_cnt; 830 if (res > slp->sl_scp.scp_datalen) 831 { 832 if ((slp->sl_error & PDMAERR) == 0) 833 { 834 device_printf(slp->sl_dev, "data overrun 0x%x > 0x%x\n", 835 res, slp->sl_scp.scp_datalen); 836 } 837 838 slp->sl_error |= PDMAERR; 839 slp->sl_scp.scp_datalen = 0; 840 841 if ((slp->sl_flags & HW_READ_PADDING) == 0) 842 { 843 device_printf(slp->sl_dev, "read padding required\n"); 844 return 0; 845 } 846 847 nsp_data_padding(sc, SCSI_LOW_READ, res); 848 sc->sc_cnt += res; 849 return 1; /* padding start */ 850 } 851 852 if (suspendio > 0 && slp->sl_scp.scp_datalen >= suspendio) 853 res = suspendio; 854 855 if ((sc->sc_xfermr & (XFERMR_MEM32 | XFERMR_MEM8)) != 0) 856 { 857 if ((sc->sc_xfermr & XFERMR_MEM32) != 0) 858 { 859 res &= ~3; 860 bus_space_read_region_4(sc->sc_memt, sc->sc_memh, 0, 861 (u_int32_t *) slp->sl_scp.scp_data, res >> 2); 862 } 863 else 864 { 865 bus_space_read_region_1(sc->sc_memt, sc->sc_memh, 0, 866 (u_int8_t *) slp->sl_scp.scp_data, res); 867 } 868 } 869 else 870 { 871 if ((sc->sc_xfermr & XFERMR_IO32) != 0) 872 { 873 res &= ~3; 874 bus_space_read_multi_4(bst, bsh, nsp_fifodr, 875 (u_int32_t *) slp->sl_scp.scp_data, res >> 2); 876 } 877 else 878 { 879 bus_space_read_multi_1(bst, bsh, nsp_fifodr, 880 (u_int8_t *) slp->sl_scp.scp_data, res); 881 } 882 } 883 884 if (nsp_cr_read_1(bst, bsh, NSPR_PARITYR) & PARITYR_PE) 885 { 886 nsp_cr_write_1(bst, bsh, NSPR_PARITYR, 887 PARITYR_ENABLE | PARITYR_CLEAR); 888 scsi_low_assert_msg(slp, slp->sl_Tnexus, SCSI_LOW_MSG_ERROR, 1); 889 } 890 891 slp->sl_scp.scp_data += res; 892 slp->sl_scp.scp_datalen -= res; 893 sc->sc_cnt += res; 894 return 0; 895} 896 897static int 898nsp_write_fifo(sc, suspendio) 899 struct nsp_softc *sc; 900 int suspendio; 901{ 902 struct scsi_low_softc *slp = &sc->sc_sclow; 903 bus_space_tag_t bst = sc->sc_iot; 904 bus_space_handle_t bsh = sc->sc_ioh; 905 u_int res; 906 register u_int8_t stat; 907 908 if (suspendio > 0) 909 { 910#ifdef NSP_DEBUG 911 if ((slp->sl_scp.scp_datalen % WFIFO_CRIT) != 0) 912 { 913 device_printf(slp->sl_dev, 914 "strange write length 0x%x\n", 915 slp->sl_scp.scp_datalen); 916 } 917#endif /* NSP_DEBUG */ 918 res = slp->sl_scp.scp_datalen % suspendio; 919 if (res == 0) 920 { 921 res = suspendio; 922 } 923 } 924 else 925 { 926 res = WFIFO_CRIT; 927 } 928 929 if (res > slp->sl_scp.scp_datalen) 930 res = slp->sl_scp.scp_datalen; 931 932 /* XXX: reconfirm! */ 933 stat = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON) & SCBUSMON_PHMASK; 934 if (stat != PHASE_DATAOUT) 935 return 0; 936 937 if ((sc->sc_xfermr & (XFERMR_MEM32 | XFERMR_MEM8)) != 0) 938 { 939 if ((sc->sc_xfermr & XFERMR_MEM32) != 0) 940 { 941 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 0, 942 (u_int32_t *) slp->sl_scp.scp_data, res >> 2); 943 } 944 else 945 { 946 bus_space_write_region_1(sc->sc_memt, sc->sc_memh, 0, 947 (u_int8_t *) slp->sl_scp.scp_data, res); 948 } 949 } 950 else 951 { 952 if ((sc->sc_xfermr & XFERMR_IO32) != 0) 953 { 954 bus_space_write_multi_4(bst, bsh, nsp_fifodr, 955 (u_int32_t *) slp->sl_scp.scp_data, res >> 2); 956 } 957 else 958 { 959 bus_space_write_multi_1(bst, bsh, nsp_fifodr, 960 (u_int8_t *) slp->sl_scp.scp_data, res); 961 } 962 } 963 964 slp->sl_scp.scp_datalen -= res; 965 slp->sl_scp.scp_data += res; 966 sc->sc_cnt += res; 967 return 0; 968} 969 970static int 971nsp_wait_interrupt(sc) 972 struct nsp_softc *sc; 973{ 974 bus_space_tag_t bst = sc->sc_iot; 975 bus_space_handle_t bsh = sc->sc_ioh; 976 int tout; 977 register u_int8_t isrc; 978 979 for (tout = 0; tout < DEV_BSIZE / 10; tout ++) 980 { 981 isrc = bus_space_read_1(bst, bsh, nsp_irqsr); 982 if ((isrc & (IRQSR_SCSI | IRQSR_FIFO)) != 0) 983 { 984 if ((isrc & IRQSR_FIFO) != 0) 985 { 986 bus_space_write_1(bst, bsh, 987 nsp_irqcr, IRQCR_FIFOCL); 988 } 989 return 1; 990 } 991 DELAY(1); 992 } 993 return 0; 994} 995 996static void 997nsp_pio_read(sc, suspendio) 998 struct nsp_softc *sc; 999 int suspendio; 1000{ 1001 struct scsi_low_softc *slp = &sc->sc_sclow; 1002 bus_space_tag_t bst = sc->sc_iot; 1003 bus_space_handle_t bsh = sc->sc_ioh; 1004 int tout, padding, datalen; 1005 register u_int8_t stat, fstat; 1006 1007 padding = 0; 1008 tout = sc->sc_tmaxcnt; 1009 slp->sl_flags |= HW_PDMASTART; 1010 datalen = slp->sl_scp.scp_datalen; 1011 1012ReadLoop: 1013 while (1) 1014 { 1015 stat = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON); 1016 if (stat == (u_int8_t) -1) 1017 return; 1018 1019 /* out of data phase */ 1020 if ((stat & SCBUSMON_PHMASK) != PHASE_DATAIN) 1021 { 1022 nsp_read_fifo(sc, 0); 1023 return; 1024 } 1025 1026 /* data phase */ 1027 fstat = bus_space_read_1(bst, bsh, nsp_fifosr); 1028 if ((fstat & FIFOSR_FULLEMP) != 0) 1029 { 1030 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1031 { 1032 bus_space_write_1(bst, bsh, nsp_irqcr, 1033 IRQCR_FIFOCL); 1034 } 1035 1036 if (suspendio > 0) 1037 { 1038 padding |= nsp_read_fifo(sc, suspendio); 1039 } 1040 else 1041 { 1042 padding |= nsp_read_fifo(sc, 0); 1043 } 1044 1045 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1046 break; 1047 } 1048 else 1049 { 1050 if (padding == 0 && slp->sl_scp.scp_datalen <= 0) 1051 return; 1052 1053 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1054 break; 1055 1056 DELAY(1); 1057 } 1058 1059 if ((-- tout) <= 0) 1060 { 1061 device_printf(slp->sl_dev, "nsp_pio_read: timeout\n"); 1062 return; 1063 } 1064 } 1065 1066 1067 if (slp->sl_scp.scp_datalen > 0 && 1068 slp->sl_scp.scp_datalen > datalen - nsp_read_interrupt_bytes) 1069 { 1070 if (nsp_wait_interrupt(sc) != 0) 1071 goto ReadLoop; 1072 } 1073} 1074 1075static void 1076nsp_pio_write(sc, suspendio) 1077 struct nsp_softc *sc; 1078 int suspendio; 1079{ 1080 struct scsi_low_softc *slp = &sc->sc_sclow; 1081 bus_space_tag_t bst = sc->sc_iot; 1082 bus_space_handle_t bsh = sc->sc_ioh; 1083 u_int rcount, acount; 1084 int tout, datalen; 1085 register u_int8_t stat, fstat; 1086 1087 tout = sc->sc_tmaxcnt; 1088 slp->sl_flags |= HW_PDMASTART; 1089 datalen = slp->sl_scp.scp_datalen; 1090 1091WriteLoop: 1092 while (1) 1093 { 1094 stat = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON) & SCBUSMON_PHMASK; 1095 if (stat != PHASE_DATAOUT) 1096 return; 1097 1098 if (slp->sl_scp.scp_datalen <= 0) 1099 { 1100 if (sc->sc_dataout_timeout == 0) 1101 sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ; 1102 return; 1103 } 1104 1105 fstat = bus_space_read_1(bst, bsh, nsp_fifosr); 1106 if ((fstat & FIFOSR_FULLEMP) != 0) 1107 { 1108 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1109 { 1110 bus_space_write_1(bst, bsh, nsp_irqcr, 1111 IRQCR_FIFOCL); 1112 } 1113 1114 if (suspendio > 0) 1115 { 1116 /* XXX:IMPORTANT: 1117 * To avoid timeout of pcmcia bus 1118 * (not scsi bus!), we should check 1119 * the scsi device sends us request 1120 * signals, which means the scsi device 1121 * is ready to recieve data without 1122 * heavy delays. 1123 */ 1124 if ((slp->sl_scp.scp_datalen % suspendio) == 0) 1125 { 1126 /* Step I: 1127 * fill the nsp fifo, and waiting for 1128 * the fifo empty. 1129 */ 1130 nsp_write_fifo(sc, 0); 1131 } 1132 else 1133 { 1134 /* Step II: 1135 * check the request singals. 1136 */ 1137 acount = nsp_fifo_count(sc); 1138 rcount = nsp_request_count(sc); 1139 if (rcount <= acount) 1140 { 1141 nsp_write_fifo(sc, 0); 1142#ifdef NSP_STATICS 1143 nsp_statics.device_busy ++; 1144#endif /* NSP_STATICS */ 1145 } 1146 else 1147 { 1148 nsp_write_fifo(sc, suspendio); 1149#ifdef NSP_STATICS 1150 nsp_statics.device_data_write ++; 1151#endif /* NSP_STATICS */ 1152 } 1153 } 1154 } 1155 else 1156 { 1157 nsp_write_fifo(sc, 0); 1158 } 1159 1160 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1161 break; 1162 } 1163 else 1164 { 1165 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1166 break; 1167 1168 DELAY(1); 1169 } 1170 1171 if ((-- tout) <= 0) 1172 { 1173 device_printf(slp->sl_dev, "nsp_pio_write: timeout\n"); 1174 return; 1175 } 1176 } 1177 1178 if (slp->sl_scp.scp_datalen > 0 && 1179 slp->sl_scp.scp_datalen > datalen - nsp_write_interrupt_bytes) 1180 { 1181 if (nsp_wait_interrupt(sc) != 0) 1182 goto WriteLoop; 1183 } 1184} 1185 1186static int 1187nsp_negate_signal(struct nsp_softc *sc, u_int8_t mask, u_char *s) 1188{ 1189 struct scsi_low_softc *slp = &sc->sc_sclow; 1190 bus_space_tag_t bst = sc->sc_iot; 1191 bus_space_handle_t bsh = sc->sc_ioh; 1192 int wc; 1193 u_int8_t regv; 1194 1195 for (wc = 0; wc < NSP_DELAY_MAX / NSP_DELAY_INTERVAL; wc ++) 1196 { 1197 regv = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON); 1198 if (regv == (u_int8_t) -1) 1199 return -1; 1200 if ((regv & mask) == 0) 1201 return 1; 1202 DELAY(NSP_DELAY_INTERVAL); 1203 } 1204 1205 device_printf(slp->sl_dev, "%s nsp_negate_signal timeout\n", s); 1206 return -1; 1207} 1208 1209static int 1210nsp_xfer(sc, buf, len, phase, clear_atn) 1211 struct nsp_softc *sc; 1212 u_int8_t *buf; 1213 int len; 1214 int phase; 1215 int clear_atn; 1216{ 1217 bus_space_tag_t bst = sc->sc_iot; 1218 bus_space_handle_t bsh = sc->sc_ioh; 1219 int ptr, rv; 1220 1221 for (ptr = 0; len > 0; len --, ptr ++) 1222 { 1223 rv = nsp_expect_signal(sc, phase, SCBUSMON_REQ); 1224 if (rv <= 0) 1225 goto out; 1226 1227 if (len == 1 && clear_atn != 0) 1228 { 1229 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, 1230 SCBUSCR_ADIR | SCBUSCR_ACKEN); 1231 SCSI_LOW_DEASSERT_ATN(&sc->sc_sclow); 1232 } 1233 1234 if (phase & SCBUSMON_IO) 1235 { 1236 buf[ptr] = nsp_cr_read_1(bst, bsh, NSPR_DATAACK); 1237 } 1238 else 1239 { 1240 nsp_cr_write_1(bst, bsh, NSPR_DATAACK, buf[ptr]); 1241 } 1242 nsp_negate_signal(sc, SCBUSMON_ACK, "xfer<ACK>"); 1243 } 1244 1245out: 1246 return len; 1247} 1248 1249/************************************************************** 1250 * disconnect & reselect (HW low) 1251 **************************************************************/ 1252static int 1253nsp_reselected(sc) 1254 struct nsp_softc *sc; 1255{ 1256 struct scsi_low_softc *slp = &sc->sc_sclow; 1257 bus_space_tag_t bst = sc->sc_iot; 1258 bus_space_handle_t bsh = sc->sc_ioh; 1259 struct targ_info *ti; 1260 u_int sid; 1261 u_int8_t cr; 1262 1263 sid = (u_int) nsp_cr_read_1(bst, bsh, NSPR_RESELR); 1264 sid &= ~sc->sc_idbit; 1265 sid = ffs(sid) - 1; 1266 if ((ti = scsi_low_reselected(slp, sid)) == NULL) 1267 return EJUSTRETURN; 1268 1269 nsp_negate_signal(sc, SCBUSMON_SEL, "reselect<SEL>"); 1270 1271 cr = nsp_cr_read_1(bst, bsh, NSPR_SCBUSCR); 1272 cr &= ~(SCBUSCR_BSY | SCBUSCR_ATN); 1273 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, cr); 1274 cr |= SCBUSCR_ADIR | SCBUSCR_ACKEN; 1275 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, cr); 1276 1277#ifdef NSP_STATICS 1278 nsp_statics.reselect ++; 1279#endif /* NSP_STATCIS */ 1280 return EJUSTRETURN; 1281} 1282 1283static int 1284nsp_disconnected(sc, ti) 1285 struct nsp_softc *sc; 1286 struct targ_info *ti; 1287{ 1288 struct scsi_low_softc *slp = &sc->sc_sclow; 1289 bus_space_tag_t bst = sc->sc_iot; 1290 bus_space_handle_t bsh = sc->sc_ioh; 1291 1292 nsp_cr_write_1(bst, bsh, NSPR_PTCLRR, PTCLRR_PT | PTCLRR_ACK | 1293 PTCLRR_REQ | PTCLRR_HOST); 1294 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1295 { 1296 sc->sc_icr &= ~SCIENR_FIFO; 1297 nsp_cr_write_1(bst, bsh, NSPR_SCIENR, sc->sc_icr); 1298 } 1299 sc->sc_cnt = 0; 1300 sc->sc_dataout_timeout = 0; 1301#ifdef NSP_STATICS 1302 nsp_statics.disconnect ++; 1303#endif /* NSP_STATICS */ 1304 scsi_low_disconnected(slp, ti); 1305 return 1; 1306} 1307 1308/************************************************************** 1309 * SEQUENCER 1310 **************************************************************/ 1311static void nsp_error(struct nsp_softc *, u_char *, u_int8_t, u_int8_t, u_int8_t); 1312 1313static void 1314nsp_error(struct nsp_softc * sc, u_char *s, u_int8_t isrc, u_int8_t ph, 1315 u_int8_t irqphs) 1316{ 1317 struct scsi_low_softc *slp = &sc->sc_sclow; 1318 1319 device_printf(slp->sl_dev, "%s\n", s); 1320 device_printf(slp->sl_dev, "isrc 0x%x scmon 0x%x irqphs 0x%x\n", 1321 (u_int) isrc, (u_int) ph, (u_int) irqphs); 1322} 1323 1324static int 1325nsp_target_nexus_establish(sc) 1326 struct nsp_softc *sc; 1327{ 1328 struct scsi_low_softc *slp = &sc->sc_sclow; 1329 bus_space_tag_t bst = sc->sc_iot; 1330 bus_space_handle_t bsh = sc->sc_ioh; 1331 struct targ_info *ti = slp->sl_Tnexus; 1332 struct nsp_targ_info *nti = (void *) ti; 1333 1334 /* setup synch transfer registers */ 1335 nsp_cr_write_1(bst, bsh, NSPR_SYNCR, nti->nti_reg_syncr); 1336 nsp_cr_write_1(bst, bsh, NSPR_ACKWIDTH, nti->nti_reg_ackwidth); 1337 1338 /* setup pdma fifo (minimum) */ 1339 nsp_setup_fifo(sc, NSP_FIFO_ON, SCSI_LOW_READ, 0); 1340 return 0; 1341} 1342 1343static int 1344nsp_lun_nexus_establish(sc) 1345 struct nsp_softc *sc; 1346{ 1347 1348 return 0; 1349} 1350 1351static int 1352nsp_ccb_nexus_establish(sc) 1353 struct nsp_softc *sc; 1354{ 1355 struct scsi_low_softc *slp = &sc->sc_sclow; 1356 struct slccb *cb = slp->sl_Qnexus; 1357 1358 sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 1359 1360 /* setup pdma fifo */ 1361 nsp_setup_fifo(sc, NSP_FIFO_ON, 1362 slp->sl_scp.scp_direction, slp->sl_scp.scp_datalen); 1363 1364 if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 1365 { 1366 if (sc->sc_suspendio > 0 && 1367 (nsp_io_control & NSP_READ_FIFO_INTERRUPTS) != 0) 1368 { 1369 sc->sc_icr |= SCIENR_FIFO; 1370 nsp_cr_write_1(sc->sc_iot, sc->sc_ioh, 1371 NSPR_SCIENR, sc->sc_icr); 1372 } 1373 } 1374 else 1375 { 1376 if (sc->sc_suspendio > 0 && 1377 (nsp_io_control & NSP_WRITE_FIFO_INTERRUPTS) != 0) 1378 { 1379 sc->sc_icr |= SCIENR_FIFO; 1380 nsp_cr_write_1(sc->sc_iot, sc->sc_ioh, 1381 NSPR_SCIENR, sc->sc_icr); 1382 } 1383 } 1384 return 0; 1385} 1386 1387static int 1388nsp_phase_match(struct nsp_softc *sc, u_int8_t phase, u_int8_t stat) 1389{ 1390 struct scsi_low_softc *slp = &sc->sc_sclow; 1391 1392 if ((stat & SCBUSMON_PHMASK) != phase) 1393 { 1394 device_printf(slp->sl_dev, "phase mismatch 0x%x != 0x%x\n", 1395 (u_int) phase, (u_int) stat); 1396 return EINVAL; 1397 } 1398 1399 if ((stat & SCBUSMON_REQ) == 0) 1400 return EINVAL; 1401 1402 return 0; 1403} 1404 1405int 1406nspintr(arg) 1407 void *arg; 1408{ 1409 struct nsp_softc *sc = arg; 1410 struct scsi_low_softc *slp = &sc->sc_sclow; 1411 bus_space_tag_t bst = sc->sc_iot; 1412 bus_space_handle_t bsh = sc->sc_ioh; 1413 struct targ_info *ti; 1414 struct buf *bp; 1415 u_int derror, flags; 1416 int len, rv; 1417 u_int8_t isrc, ph, irqphs, cr, regv; 1418 1419 /******************************************* 1420 * interrupt check 1421 *******************************************/ 1422 if (slp->sl_flags & HW_INACTIVE) 1423 return 0; 1424 1425 bus_space_write_1(bst, bsh, nsp_irqcr, IRQCR_IRQDIS); 1426 isrc = bus_space_read_1(bst, bsh, nsp_irqsr); 1427 if (isrc == (u_int8_t) -1 || (isrc & IRQSR_MASK) == 0) 1428 { 1429 bus_space_write_1(bst, bsh, nsp_irqcr, 0); 1430 return 0; 1431 } 1432 1433 /* XXX: IMPORTANT 1434 * Do not read an irqphs register if no scsi phase interrupt. 1435 * Unless, you should lose a scsi phase interrupt. 1436 */ 1437 ph = nsp_cr_read_1(bst, bsh, NSPR_SCBUSMON); 1438 if ((isrc & IRQSR_SCSI) != 0) 1439 { 1440 irqphs = nsp_cr_read_1(bst, bsh, NSPR_IRQPHS); 1441 } 1442 else 1443 irqphs = 0; 1444 1445 /* 1446 * timer interrupt handler (scsi vs timer interrupts) 1447 */ 1448 if (sc->sc_timer != 0) 1449 { 1450 nsp_cr_write_1(bst, bsh, NSPR_TIMERCNT, 0); 1451 nsp_cr_write_1(bst, bsh, NSPR_TIMERCNT, 0); 1452 sc->sc_timer = 0; 1453 } 1454 1455 /* check a timer interrupt */ 1456 regv = 0; 1457 if ((isrc & IRQSR_TIMER) != 0) 1458 { 1459 if ((isrc & IRQSR_MASK) == IRQSR_TIMER && sc->sc_seltout == 0) 1460 { 1461 bus_space_write_1(bst, bsh, nsp_irqcr, IRQCR_TIMERCL); 1462 return 1; 1463 } 1464 regv |= IRQCR_TIMERCL; 1465 } 1466 1467 /* check a fifo interrupt */ 1468 if ((isrc & IRQSR_FIFO) != 0) 1469 { 1470 regv |= IRQCR_FIFOCL; 1471 } 1472 1473 /* OK. enable all interrupts */ 1474 bus_space_write_1(bst, bsh, nsp_irqcr, regv); 1475 1476 /******************************************* 1477 * debug section 1478 *******************************************/ 1479#ifdef NSP_DEBUG 1480 if (nsp_debug) 1481 { 1482 nsp_error(sc, "current status", isrc, ph, irqphs); 1483 scsi_low_print(slp, NULL); 1484#ifdef KDB 1485 if (nsp_debug > 1) 1486 kdb_enter(KDB_WHY_CAM, "nsp"); 1487#endif /* KDB */ 1488 } 1489#endif /* NSP_DEBUG */ 1490 1491 /******************************************* 1492 * Parse hardware SCSI irq reasons register 1493 *******************************************/ 1494 if ((isrc & IRQSR_SCSI) != 0) 1495 { 1496 if ((irqphs & IRQPHS_RST) != 0) 1497 { 1498 scsi_low_restart(slp, SCSI_LOW_RESTART_SOFT, 1499 "bus reset (power off?)"); 1500 return 1; 1501 } 1502 1503 if ((irqphs & IRQPHS_RSEL) != 0) 1504 { 1505 bus_space_write_1(bst, bsh, nsp_irqcr, IRQCR_RESCL); 1506 if (nsp_reselected(sc) == EJUSTRETURN) 1507 return 1; 1508 } 1509 1510 if ((irqphs & (IRQPHS_PCHG | IRQPHS_LBF)) == 0) 1511 return 1; 1512 } 1513 1514 /******************************************* 1515 * nexus check 1516 *******************************************/ 1517 if ((ti = slp->sl_Tnexus) == NULL) 1518 { 1519 /* unknown scsi phase changes */ 1520 nsp_error(sc, "unknown scsi phase changes", isrc, ph, irqphs); 1521 return 0; 1522 } 1523 1524 /******************************************* 1525 * aribitration & selection 1526 *******************************************/ 1527 switch (ti->ti_phase) 1528 { 1529 case PH_SELSTART: 1530 if ((ph & SCBUSMON_BSY) == 0) 1531 { 1532 if (sc->sc_seltout >= NSP_SELTIMEOUT) 1533 { 1534 sc->sc_seltout = 0; 1535 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, 0); 1536 return nsp_disconnected(sc, ti); 1537 } 1538 sc->sc_seltout ++; 1539 nsp_start_timer(sc, NSP_TIMER_1MS); 1540 return 1; 1541 } 1542 1543 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED); 1544 nsphw_selection_done_and_expect_msgout(sc); 1545 return 1; 1546 1547 case PH_SELECTED: 1548 if ((isrc & IRQSR_SCSI) == 0) 1549 return 1; 1550 1551 nsp_target_nexus_establish(sc); 1552 break; 1553 1554 case PH_RESEL: 1555 if ((isrc & IRQSR_SCSI) == 0) 1556 return 1; 1557 1558 nsp_target_nexus_establish(sc); 1559 if ((ph & SCBUSMON_PHMASK) != PHASE_MSGIN) 1560 { 1561 device_printf(slp->sl_dev, 1562 "unexpected phase after reselect\n"); 1563 slp->sl_error |= FATALIO; 1564 scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_ABORT, 1); 1565 return 1; 1566 } 1567 break; 1568 1569 case PH_DATA: 1570 if ((isrc & IRQSR_SCSI) != 0) 1571 break; 1572 if ((isrc & IRQSR_FIFO) != 0) 1573 { 1574 if (NSP_IS_PHASE_DATA(ph) == 0) 1575 return 1; 1576 irqphs = (ph & IRQPHS_PHMASK); 1577 break; 1578 } 1579 return 1; 1580 1581 default: 1582 if ((isrc & IRQSR_SCSI) == 0) 1583 return 1; 1584 break; 1585 } 1586 1587 /******************************************* 1588 * data phase control 1589 *******************************************/ 1590 if (slp->sl_flags & HW_PDMASTART) 1591 { 1592 if ((isrc & IRQSR_SCSI) != 0 && 1593 NSP_IS_IRQPHS_DATA(irqphs) == 0) 1594 { 1595 if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 1596 nsp_pio_read(sc, 0); 1597 nsp_pdma_end(sc, ti); 1598 } 1599 } 1600 1601 /******************************************* 1602 * scsi seq 1603 *******************************************/ 1604 if (slp->sl_msgphase != 0 && (irqphs & IRQPHS_LBF) != 0) 1605 return nsp_disconnected(sc, ti); 1606 1607 /* check unexpected bus free state */ 1608 if (ph == 0) 1609 { 1610 nsp_error(sc, "unexpected bus free", isrc, ph, irqphs); 1611 return nsp_disconnected(sc, ti); 1612 } 1613 1614 /* check normal scsi phase */ 1615 switch (irqphs & IRQPHS_PHMASK) 1616 { 1617 case IRQPHS_CMD: 1618 if (nsp_phase_match(sc, PHASE_CMD, ph) != 0) 1619 return 1; 1620 1621 SCSI_LOW_SETUP_PHASE(ti, PH_CMD); 1622 if (scsi_low_cmd(slp, ti) != 0) 1623 { 1624 scsi_low_attention(slp); 1625 } 1626 1627 nsp_cr_write_1(bst, bsh, NSPR_CMDCR, CMDCR_PTCLR); 1628 for (len = 0; len < slp->sl_scp.scp_cmdlen; len ++) 1629 nsp_cr_write_1(bst, bsh, NSPR_CMDDR, 1630 slp->sl_scp.scp_cmd[len]); 1631 1632 nsp_cr_write_1(bst, bsh, NSPR_CMDCR, CMDCR_PTCLR | CMDCR_EXEC); 1633 break; 1634 1635 case IRQPHS_DATAOUT: 1636 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1637 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0) 1638 { 1639 scsi_low_attention(slp); 1640 } 1641 1642 nsp_pio_write(sc, sc->sc_suspendio); 1643 break; 1644 1645 case IRQPHS_DATAIN: 1646 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1647 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0) 1648 { 1649 scsi_low_attention(slp); 1650 } 1651 1652 nsp_pio_read(sc, sc->sc_suspendio); 1653 break; 1654 1655 case IRQPHS_STATUS: 1656 if (nsp_phase_match(sc, PHASE_STATUS, ph) != 0) 1657 return 1; 1658 1659 SCSI_LOW_SETUP_PHASE(ti, PH_STAT); 1660 regv = nsp_cr_read_1(bst, bsh, NSPR_DATA); 1661 if (nsp_cr_read_1(bst, bsh, NSPR_PARITYR) & PARITYR_PE) 1662 { 1663 nsp_cr_write_1(bst, bsh, NSPR_PARITYR, 1664 PARITYR_ENABLE | PARITYR_CLEAR); 1665 derror = SCSI_LOW_DATA_PE; 1666 } 1667 else 1668 derror = 0; 1669 1670 /* assert ACK */ 1671 cr = SCBUSCR_ACK | nsp_cr_read_1(bst, bsh, NSPR_SCBUSCR); 1672 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, cr); 1673 1674 if (scsi_low_statusin(slp, ti, derror | regv) != 0) 1675 { 1676 scsi_low_attention(slp); 1677 } 1678 1679 /* check REQ nagated */ 1680 nsp_negate_signal(sc, SCBUSMON_REQ, "statin<REQ>"); 1681 1682 /* deassert ACK */ 1683 cr = nsp_cr_read_1(bst, bsh, NSPR_SCBUSCR) & (~SCBUSCR_ACK); 1684 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, cr); 1685 break; 1686 1687 case IRQPHS_MSGOUT: 1688 if (nsp_phase_match(sc, PHASE_MSGOUT, ph) != 0) 1689 return 1; 1690 1691#ifdef NSP_MSGOUT_SERIALIZE 1692 /* 1693 * XXX: NSP QUIRK 1694 * NSP invoke interrupts only in the case of scsi phase changes, 1695 * therefore we should poll the scsi phase here to catch 1696 * the next "msg out" if exists (no scsi phase changes). 1697 */ 1698 rv = len = 16; 1699 do { 1700 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); 1701 flags = (ti->ti_ophase != ti->ti_phase) ? 1702 SCSI_LOW_MSGOUT_INIT : 0; 1703 len = scsi_low_msgout(slp, ti, flags); 1704 1705 if (len > 1 && slp->sl_atten == 0) 1706 { 1707 scsi_low_attention(slp); 1708 } 1709 1710 if (nsp_xfer(sc, ti->ti_msgoutstr, len, PHASE_MSGOUT, 1711 slp->sl_clear_atten) != 0) 1712 { 1713 slp->sl_error |= FATALIO; 1714 nsp_error(sc, "MSGOUT: xfer short", 1715 isrc, ph, irqphs); 1716 } 1717 1718 /* catch a next signal */ 1719 rv = nsp_expect_signal(sc, PHASE_MSGOUT, SCBUSMON_REQ); 1720 } 1721 while (rv > 0 && len -- > 0); 1722 1723#else /* !NSP_MSGOUT_SERIALIZE */ 1724 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); 1725 flags = SCSI_LOW_MSGOUT_UNIFY; 1726 if (ti->ti_ophase != ti->ti_phase) 1727 flags |= SCSI_LOW_MSGOUT_INIT; 1728 len = scsi_low_msgout(slp, ti, flags); 1729 1730 if (len > 1 && slp->sl_atten == 0) 1731 { 1732 scsi_low_attention(slp); 1733 } 1734 1735 if (nsp_xfer(sc, ti->ti_msgoutstr, len, PHASE_MSGOUT, 1736 slp->sl_clear_atten) != 0) 1737 { 1738 nsp_error(sc, "MSGOUT: xfer short", isrc, ph, irqphs); 1739 } 1740 1741#endif /* !NSP_MSGOUT_SERIALIZE */ 1742 break; 1743 1744 case IRQPHS_MSGIN: 1745 if (nsp_phase_match(sc, PHASE_MSGIN, ph) != 0) 1746 return 1; 1747 1748 /* 1749 * XXX: NSP QUIRK 1750 * NSP invoke interrupts only in the case of scsi phase changes, 1751 * therefore we should poll the scsi phase here to catch 1752 * the next "msg in" if exists (no scsi phase changes). 1753 */ 1754 rv = len = 16; 1755 do { 1756 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1757 1758 /* read a data */ 1759 regv = nsp_cr_read_1(bst, bsh, NSPR_DATA); 1760 if (nsp_cr_read_1(bst, bsh, NSPR_PARITYR) & PARITYR_PE) 1761 { 1762 nsp_cr_write_1(bst, bsh, 1763 NSPR_PARITYR, 1764 PARITYR_ENABLE | PARITYR_CLEAR); 1765 derror = SCSI_LOW_DATA_PE; 1766 } 1767 else 1768 { 1769 derror = 0; 1770 } 1771 1772 /* assert ack */ 1773 cr = nsp_cr_read_1(bst, bsh, NSPR_SCBUSCR) | SCBUSCR_ACK; 1774 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, cr); 1775 1776 if (scsi_low_msgin(slp, ti, regv | derror) == 0) 1777 { 1778 if (scsi_low_is_msgout_continue(ti, 0) != 0) 1779 { 1780 scsi_low_attention(slp); 1781 } 1782 } 1783 1784 /* check REQ nagated */ 1785 nsp_negate_signal(sc, SCBUSMON_REQ, "msgin<REQ>"); 1786 1787 /* deassert ack */ 1788 cr = nsp_cr_read_1(bst, bsh, NSPR_SCBUSCR) & (~SCBUSCR_ACK); 1789 nsp_cr_write_1(bst, bsh, NSPR_SCBUSCR, cr); 1790 1791 /* catch a next signal */ 1792 rv = nsp_expect_signal(sc, PHASE_MSGIN, SCBUSMON_REQ); 1793 } 1794 while (rv > 0 && len -- > 0); 1795 break; 1796 1797 default: 1798 slp->sl_error |= FATALIO; 1799 nsp_error(sc, "unknown scsi phase", isrc, ph, irqphs); 1800 break; 1801 } 1802 1803 return 1; 1804 1805#if 0 1806timerout: 1807 nsp_start_timer(sc, NSP_TIMER_1MS); 1808 return 0; 1809#endif 1810} 1811 1812static int 1813nsp_timeout(sc) 1814 struct nsp_softc *sc; 1815{ 1816 struct scsi_low_softc *slp = &sc->sc_sclow; 1817 bus_space_tag_t iot = sc->sc_iot; 1818 bus_space_handle_t ioh = sc->sc_ioh; 1819 int tout; 1820 u_int8_t ph, regv; 1821 1822 if (slp->sl_Tnexus == NULL) 1823 return 0; 1824 1825 ph = nsp_cr_read_1(iot, ioh, NSPR_SCBUSMON); 1826 switch (ph & SCBUSMON_PHMASK) 1827 { 1828 case PHASE_DATAOUT: 1829 if (sc->sc_dataout_timeout == 0) 1830 break; 1831 1832 /* check a fifo empty */ 1833 regv = bus_space_read_1(iot, ioh, nsp_fifosr); 1834 if ((regv & FIFOSR_FULLEMP) == 0) 1835 break; 1836 bus_space_write_1(iot, ioh, nsp_irqcr, IRQCR_FIFOCL); 1837 1838 /* check still requested */ 1839 ph = nsp_cr_read_1(iot, ioh, NSPR_SCBUSMON); 1840 if ((ph & SCBUSMON_REQ) == 0) 1841 break; 1842 /* check timeout */ 1843 if ((-- sc->sc_dataout_timeout) > 0) 1844 break; 1845 1846 slp->sl_error |= PDMAERR; 1847 if ((slp->sl_flags & HW_WRITE_PADDING) == 0) 1848 { 1849 device_printf(slp->sl_dev, "write padding required\n"); 1850 break; 1851 } 1852 1853 tout = NSP_DELAY_MAX; 1854 while (tout -- > 0) 1855 { 1856 ph = nsp_cr_read_1(iot, ioh, NSPR_SCBUSMON); 1857 if ((ph & SCBUSMON_PHMASK) != PHASE_DATAOUT) 1858 break; 1859 regv = bus_space_read_1(iot, ioh, nsp_fifosr); 1860 if ((regv & FIFOSR_FULLEMP) == 0) 1861 { 1862 DELAY(1); 1863 continue; 1864 } 1865 1866 bus_space_write_1(iot, ioh, nsp_irqcr, IRQCR_FIFOCL); 1867 nsp_data_padding(sc, SCSI_LOW_WRITE, 32); 1868 } 1869 ph = nsp_cr_read_1(iot, ioh, NSPR_SCBUSMON); 1870 if ((ph & SCBUSMON_PHMASK) == PHASE_DATAOUT) 1871 sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ; 1872 break; 1873 1874 default: 1875 break; 1876 } 1877 return 0; 1878} 1879