mpt.c revision 275982
1/*- 2 * Generic routines for LSI Fusion adapters. 3 * FreeBSD Version. 4 * 5 * Copyright (c) 2000, 2001 by Greg Ansley 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice immediately at the beginning of the file, without modification, 12 * this list of conditions, and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28/*- 29 * Copyright (c) 2002, 2006 by Matthew Jacob 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions are 34 * met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 38 * substantially similar to the "NO WARRANTY" disclaimer below 39 * ("Disclaimer") and any redistribution must be conditioned upon including 40 * a substantially similar Disclaimer requirement for further binary 41 * redistribution. 42 * 3. Neither the names of the above listed copyright holders nor the names 43 * of any contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 47 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 50 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 51 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 52 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 53 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 54 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 55 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 56 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 * Support from Chris Ellsworth in order to make SAS adapters work 59 * is gratefully acknowledged. 60 * 61 * 62 * Support from LSI-Logic has also gone a great deal toward making this a 63 * workable subsystem and is gratefully acknowledged. 64 */ 65/*- 66 * Copyright (c) 2004, Avid Technology, Inc. and its contributors. 67 * Copyright (c) 2005, WHEEL Sp. z o.o. 68 * Copyright (c) 2004, 2005 Justin T. Gibbs 69 * All rights reserved. 70 * 71 * Redistribution and use in source and binary forms, with or without 72 * modification, are permitted provided that the following conditions are 73 * met: 74 * 1. Redistributions of source code must retain the above copyright 75 * notice, this list of conditions and the following disclaimer. 76 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 77 * substantially similar to the "NO WARRANTY" disclaimer below 78 * ("Disclaimer") and any redistribution must be conditioned upon including 79 * a substantially similar Disclaimer requirement for further binary 80 * redistribution. 81 * 3. Neither the names of the above listed copyright holders nor the names 82 * of any contributors may be used to endorse or promote products derived 83 * from this software without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 88 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 89 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 90 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 91 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 92 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 93 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 94 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 95 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 96 */ 97 98#include <sys/cdefs.h> 99__FBSDID("$FreeBSD: stable/10/sys/dev/mpt/mpt.c 275982 2014-12-21 03:06:11Z smh $"); 100 101#include <dev/mpt/mpt.h> 102#include <dev/mpt/mpt_cam.h> /* XXX For static handler registration */ 103#include <dev/mpt/mpt_raid.h> /* XXX For static handler registration */ 104 105#include <dev/mpt/mpilib/mpi.h> 106#include <dev/mpt/mpilib/mpi_ioc.h> 107#include <dev/mpt/mpilib/mpi_fc.h> 108#include <dev/mpt/mpilib/mpi_targ.h> 109 110#include <sys/sysctl.h> 111 112#define MPT_MAX_TRYS 3 113#define MPT_MAX_WAIT 300000 114 115static int maxwait_ack = 0; 116static int maxwait_int = 0; 117static int maxwait_state = 0; 118 119static TAILQ_HEAD(, mpt_softc) mpt_tailq = TAILQ_HEAD_INITIALIZER(mpt_tailq); 120mpt_reply_handler_t *mpt_reply_handlers[MPT_NUM_REPLY_HANDLERS]; 121 122static mpt_reply_handler_t mpt_default_reply_handler; 123static mpt_reply_handler_t mpt_config_reply_handler; 124static mpt_reply_handler_t mpt_handshake_reply_handler; 125static mpt_reply_handler_t mpt_event_reply_handler; 126static void mpt_send_event_ack(struct mpt_softc *mpt, request_t *ack_req, 127 MSG_EVENT_NOTIFY_REPLY *msg, uint32_t context); 128static int mpt_send_event_request(struct mpt_softc *mpt, int onoff); 129static int mpt_soft_reset(struct mpt_softc *mpt); 130static void mpt_hard_reset(struct mpt_softc *mpt); 131static int mpt_dma_buf_alloc(struct mpt_softc *mpt); 132static void mpt_dma_buf_free(struct mpt_softc *mpt); 133static int mpt_configure_ioc(struct mpt_softc *mpt, int, int); 134static int mpt_enable_ioc(struct mpt_softc *mpt, int); 135 136/************************* Personality Module Support *************************/ 137/* 138 * We include one extra entry that is guaranteed to be NULL 139 * to simplify our itterator. 140 */ 141static struct mpt_personality *mpt_personalities[MPT_MAX_PERSONALITIES + 1]; 142static __inline struct mpt_personality* 143 mpt_pers_find(struct mpt_softc *, u_int); 144static __inline struct mpt_personality* 145 mpt_pers_find_reverse(struct mpt_softc *, u_int); 146 147static __inline struct mpt_personality * 148mpt_pers_find(struct mpt_softc *mpt, u_int start_at) 149{ 150 KASSERT(start_at <= MPT_MAX_PERSONALITIES, 151 ("mpt_pers_find: starting position out of range")); 152 153 while (start_at < MPT_MAX_PERSONALITIES 154 && (mpt->mpt_pers_mask & (0x1 << start_at)) == 0) { 155 start_at++; 156 } 157 return (mpt_personalities[start_at]); 158} 159 160/* 161 * Used infrequently, so no need to optimize like a forward 162 * traversal where we use the MAX+1 is guaranteed to be NULL 163 * trick. 164 */ 165static __inline struct mpt_personality * 166mpt_pers_find_reverse(struct mpt_softc *mpt, u_int start_at) 167{ 168 while (start_at < MPT_MAX_PERSONALITIES 169 && (mpt->mpt_pers_mask & (0x1 << start_at)) == 0) { 170 start_at--; 171 } 172 if (start_at < MPT_MAX_PERSONALITIES) 173 return (mpt_personalities[start_at]); 174 return (NULL); 175} 176 177#define MPT_PERS_FOREACH(mpt, pers) \ 178 for (pers = mpt_pers_find(mpt, /*start_at*/0); \ 179 pers != NULL; \ 180 pers = mpt_pers_find(mpt, /*start_at*/pers->id+1)) 181 182#define MPT_PERS_FOREACH_REVERSE(mpt, pers) \ 183 for (pers = mpt_pers_find_reverse(mpt, MPT_MAX_PERSONALITIES-1);\ 184 pers != NULL; \ 185 pers = mpt_pers_find_reverse(mpt, /*start_at*/pers->id-1)) 186 187static mpt_load_handler_t mpt_stdload; 188static mpt_probe_handler_t mpt_stdprobe; 189static mpt_attach_handler_t mpt_stdattach; 190static mpt_enable_handler_t mpt_stdenable; 191static mpt_ready_handler_t mpt_stdready; 192static mpt_event_handler_t mpt_stdevent; 193static mpt_reset_handler_t mpt_stdreset; 194static mpt_shutdown_handler_t mpt_stdshutdown; 195static mpt_detach_handler_t mpt_stddetach; 196static mpt_unload_handler_t mpt_stdunload; 197static struct mpt_personality mpt_default_personality = 198{ 199 .load = mpt_stdload, 200 .probe = mpt_stdprobe, 201 .attach = mpt_stdattach, 202 .enable = mpt_stdenable, 203 .ready = mpt_stdready, 204 .event = mpt_stdevent, 205 .reset = mpt_stdreset, 206 .shutdown = mpt_stdshutdown, 207 .detach = mpt_stddetach, 208 .unload = mpt_stdunload 209}; 210 211static mpt_load_handler_t mpt_core_load; 212static mpt_attach_handler_t mpt_core_attach; 213static mpt_enable_handler_t mpt_core_enable; 214static mpt_reset_handler_t mpt_core_ioc_reset; 215static mpt_event_handler_t mpt_core_event; 216static mpt_shutdown_handler_t mpt_core_shutdown; 217static mpt_shutdown_handler_t mpt_core_detach; 218static mpt_unload_handler_t mpt_core_unload; 219static struct mpt_personality mpt_core_personality = 220{ 221 .name = "mpt_core", 222 .load = mpt_core_load, 223// .attach = mpt_core_attach, 224// .enable = mpt_core_enable, 225 .event = mpt_core_event, 226 .reset = mpt_core_ioc_reset, 227 .shutdown = mpt_core_shutdown, 228 .detach = mpt_core_detach, 229 .unload = mpt_core_unload, 230}; 231 232/* 233 * Manual declaration so that DECLARE_MPT_PERSONALITY doesn't need 234 * ordering information. We want the core to always register FIRST. 235 * other modules are set to SI_ORDER_SECOND. 236 */ 237static moduledata_t mpt_core_mod = { 238 "mpt_core", mpt_modevent, &mpt_core_personality 239}; 240DECLARE_MODULE(mpt_core, mpt_core_mod, SI_SUB_DRIVERS, SI_ORDER_FIRST); 241MODULE_VERSION(mpt_core, 1); 242 243#define MPT_PERS_ATTACHED(pers, mpt) ((mpt)->mpt_pers_mask & (0x1 << pers->id)) 244 245int 246mpt_modevent(module_t mod, int type, void *data) 247{ 248 struct mpt_personality *pers; 249 int error; 250 251 pers = (struct mpt_personality *)data; 252 253 error = 0; 254 switch (type) { 255 case MOD_LOAD: 256 { 257 mpt_load_handler_t **def_handler; 258 mpt_load_handler_t **pers_handler; 259 int i; 260 261 for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { 262 if (mpt_personalities[i] == NULL) 263 break; 264 } 265 if (i >= MPT_MAX_PERSONALITIES) { 266 error = ENOMEM; 267 break; 268 } 269 pers->id = i; 270 mpt_personalities[i] = pers; 271 272 /* Install standard/noop handlers for any NULL entries. */ 273 def_handler = MPT_PERS_FIRST_HANDLER(&mpt_default_personality); 274 pers_handler = MPT_PERS_FIRST_HANDLER(pers); 275 while (pers_handler <= MPT_PERS_LAST_HANDLER(pers)) { 276 if (*pers_handler == NULL) 277 *pers_handler = *def_handler; 278 pers_handler++; 279 def_handler++; 280 } 281 282 error = (pers->load(pers)); 283 if (error != 0) 284 mpt_personalities[i] = NULL; 285 break; 286 } 287 case MOD_SHUTDOWN: 288 break; 289 case MOD_QUIESCE: 290 break; 291 case MOD_UNLOAD: 292 error = pers->unload(pers); 293 mpt_personalities[pers->id] = NULL; 294 break; 295 default: 296 error = EINVAL; 297 break; 298 } 299 return (error); 300} 301 302static int 303mpt_stdload(struct mpt_personality *pers) 304{ 305 306 /* Load is always successful. */ 307 return (0); 308} 309 310static int 311mpt_stdprobe(struct mpt_softc *mpt) 312{ 313 314 /* Probe is always successful. */ 315 return (0); 316} 317 318static int 319mpt_stdattach(struct mpt_softc *mpt) 320{ 321 322 /* Attach is always successful. */ 323 return (0); 324} 325 326static int 327mpt_stdenable(struct mpt_softc *mpt) 328{ 329 330 /* Enable is always successful. */ 331 return (0); 332} 333 334static void 335mpt_stdready(struct mpt_softc *mpt) 336{ 337 338} 339 340static int 341mpt_stdevent(struct mpt_softc *mpt, request_t *req, MSG_EVENT_NOTIFY_REPLY *msg) 342{ 343 344 mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_stdevent: 0x%x\n", msg->Event & 0xFF); 345 /* Event was not for us. */ 346 return (0); 347} 348 349static void 350mpt_stdreset(struct mpt_softc *mpt, int type) 351{ 352 353} 354 355static void 356mpt_stdshutdown(struct mpt_softc *mpt) 357{ 358 359} 360 361static void 362mpt_stddetach(struct mpt_softc *mpt) 363{ 364 365} 366 367static int 368mpt_stdunload(struct mpt_personality *pers) 369{ 370 371 /* Unload is always successful. */ 372 return (0); 373} 374 375/* 376 * Post driver attachment, we may want to perform some global actions. 377 * Here is the hook to do so. 378 */ 379 380static void 381mpt_postattach(void *unused) 382{ 383 struct mpt_softc *mpt; 384 struct mpt_personality *pers; 385 386 TAILQ_FOREACH(mpt, &mpt_tailq, links) { 387 MPT_PERS_FOREACH(mpt, pers) 388 pers->ready(mpt); 389 } 390} 391SYSINIT(mptdev, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, mpt_postattach, NULL); 392 393/******************************* Bus DMA Support ******************************/ 394void 395mpt_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) 396{ 397 struct mpt_map_info *map_info; 398 399 map_info = (struct mpt_map_info *)arg; 400 map_info->error = error; 401 map_info->phys = segs->ds_addr; 402} 403 404/**************************** Reply/Event Handling ****************************/ 405int 406mpt_register_handler(struct mpt_softc *mpt, mpt_handler_type type, 407 mpt_handler_t handler, uint32_t *phandler_id) 408{ 409 410 switch (type) { 411 case MPT_HANDLER_REPLY: 412 { 413 u_int cbi; 414 u_int free_cbi; 415 416 if (phandler_id == NULL) 417 return (EINVAL); 418 419 free_cbi = MPT_HANDLER_ID_NONE; 420 for (cbi = 0; cbi < MPT_NUM_REPLY_HANDLERS; cbi++) { 421 /* 422 * If the same handler is registered multiple 423 * times, don't error out. Just return the 424 * index of the original registration. 425 */ 426 if (mpt_reply_handlers[cbi] == handler.reply_handler) { 427 *phandler_id = MPT_CBI_TO_HID(cbi); 428 return (0); 429 } 430 431 /* 432 * Fill from the front in the hope that 433 * all registered handlers consume only a 434 * single cache line. 435 * 436 * We don't break on the first empty slot so 437 * that the full table is checked to see if 438 * this handler was previously registered. 439 */ 440 if (free_cbi == MPT_HANDLER_ID_NONE && 441 (mpt_reply_handlers[cbi] 442 == mpt_default_reply_handler)) 443 free_cbi = cbi; 444 } 445 if (free_cbi == MPT_HANDLER_ID_NONE) { 446 return (ENOMEM); 447 } 448 mpt_reply_handlers[free_cbi] = handler.reply_handler; 449 *phandler_id = MPT_CBI_TO_HID(free_cbi); 450 break; 451 } 452 default: 453 mpt_prt(mpt, "mpt_register_handler unknown type %d\n", type); 454 return (EINVAL); 455 } 456 return (0); 457} 458 459int 460mpt_deregister_handler(struct mpt_softc *mpt, mpt_handler_type type, 461 mpt_handler_t handler, uint32_t handler_id) 462{ 463 464 switch (type) { 465 case MPT_HANDLER_REPLY: 466 { 467 u_int cbi; 468 469 cbi = MPT_CBI(handler_id); 470 if (cbi >= MPT_NUM_REPLY_HANDLERS 471 || mpt_reply_handlers[cbi] != handler.reply_handler) 472 return (ENOENT); 473 mpt_reply_handlers[cbi] = mpt_default_reply_handler; 474 break; 475 } 476 default: 477 mpt_prt(mpt, "mpt_deregister_handler unknown type %d\n", type); 478 return (EINVAL); 479 } 480 return (0); 481} 482 483static int 484mpt_default_reply_handler(struct mpt_softc *mpt, request_t *req, 485 uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) 486{ 487 488 mpt_prt(mpt, 489 "Default Handler Called: req=%p:%u reply_descriptor=%x frame=%p\n", 490 req, req->serno, reply_desc, reply_frame); 491 492 if (reply_frame != NULL) 493 mpt_dump_reply_frame(mpt, reply_frame); 494 495 mpt_prt(mpt, "Reply Frame Ignored\n"); 496 497 return (/*free_reply*/TRUE); 498} 499 500static int 501mpt_config_reply_handler(struct mpt_softc *mpt, request_t *req, 502 uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) 503{ 504 505 if (req != NULL) { 506 if (reply_frame != NULL) { 507 MSG_CONFIG *cfgp; 508 MSG_CONFIG_REPLY *reply; 509 510 cfgp = (MSG_CONFIG *)req->req_vbuf; 511 reply = (MSG_CONFIG_REPLY *)reply_frame; 512 req->IOCStatus = le16toh(reply_frame->IOCStatus); 513 bcopy(&reply->Header, &cfgp->Header, 514 sizeof(cfgp->Header)); 515 cfgp->ExtPageLength = reply->ExtPageLength; 516 cfgp->ExtPageType = reply->ExtPageType; 517 } 518 req->state &= ~REQ_STATE_QUEUED; 519 req->state |= REQ_STATE_DONE; 520 TAILQ_REMOVE(&mpt->request_pending_list, req, links); 521 if ((req->state & REQ_STATE_NEED_WAKEUP) != 0) { 522 wakeup(req); 523 } else if ((req->state & REQ_STATE_TIMEDOUT) != 0) { 524 /* 525 * Whew- we can free this request (late completion) 526 */ 527 mpt_free_request(mpt, req); 528 } 529 } 530 531 return (TRUE); 532} 533 534static int 535mpt_handshake_reply_handler(struct mpt_softc *mpt, request_t *req, 536 uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) 537{ 538 539 /* Nothing to be done. */ 540 return (TRUE); 541} 542 543static int 544mpt_event_reply_handler(struct mpt_softc *mpt, request_t *req, 545 uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) 546{ 547 int free_reply; 548 549 KASSERT(reply_frame != NULL, ("null reply in mpt_event_reply_handler")); 550 KASSERT(req != NULL, ("null request in mpt_event_reply_handler")); 551 552 free_reply = TRUE; 553 switch (reply_frame->Function) { 554 case MPI_FUNCTION_EVENT_NOTIFICATION: 555 { 556 MSG_EVENT_NOTIFY_REPLY *msg; 557 struct mpt_personality *pers; 558 u_int handled; 559 560 handled = 0; 561 msg = (MSG_EVENT_NOTIFY_REPLY *)reply_frame; 562 msg->EventDataLength = le16toh(msg->EventDataLength); 563 msg->IOCStatus = le16toh(msg->IOCStatus); 564 msg->IOCLogInfo = le32toh(msg->IOCLogInfo); 565 msg->Event = le32toh(msg->Event); 566 MPT_PERS_FOREACH(mpt, pers) 567 handled += pers->event(mpt, req, msg); 568 569 if (handled == 0 && mpt->mpt_pers_mask == 0) { 570 mpt_lprt(mpt, MPT_PRT_INFO, 571 "No Handlers For Any Event Notify Frames. " 572 "Event %#x (ACK %sequired).\n", 573 msg->Event, msg->AckRequired? "r" : "not r"); 574 } else if (handled == 0) { 575 mpt_lprt(mpt, 576 msg->AckRequired? MPT_PRT_WARN : MPT_PRT_INFO, 577 "Unhandled Event Notify Frame. Event %#x " 578 "(ACK %sequired).\n", 579 msg->Event, msg->AckRequired? "r" : "not r"); 580 } 581 582 if (msg->AckRequired) { 583 request_t *ack_req; 584 uint32_t context; 585 586 context = req->index | MPT_REPLY_HANDLER_EVENTS; 587 ack_req = mpt_get_request(mpt, FALSE); 588 if (ack_req == NULL) { 589 struct mpt_evtf_record *evtf; 590 591 evtf = (struct mpt_evtf_record *)reply_frame; 592 evtf->context = context; 593 LIST_INSERT_HEAD(&mpt->ack_frames, evtf, links); 594 free_reply = FALSE; 595 break; 596 } 597 mpt_send_event_ack(mpt, ack_req, msg, context); 598 /* 599 * Don't check for CONTINUATION_REPLY here 600 */ 601 return (free_reply); 602 } 603 break; 604 } 605 case MPI_FUNCTION_PORT_ENABLE: 606 mpt_lprt(mpt, MPT_PRT_DEBUG , "enable port reply\n"); 607 break; 608 case MPI_FUNCTION_EVENT_ACK: 609 break; 610 default: 611 mpt_prt(mpt, "unknown event function: %x\n", 612 reply_frame->Function); 613 break; 614 } 615 616 /* 617 * I'm not sure that this continuation stuff works as it should. 618 * 619 * I've had FC async events occur that free the frame up because 620 * the continuation bit isn't set, and then additional async events 621 * then occur using the same context. As you might imagine, this 622 * leads to Very Bad Thing. 623 * 624 * Let's just be safe for now and not free them up until we figure 625 * out what's actually happening here. 626 */ 627#if 0 628 if ((reply_frame->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY) == 0) { 629 TAILQ_REMOVE(&mpt->request_pending_list, req, links); 630 mpt_free_request(mpt, req); 631 mpt_prt(mpt, "event_reply %x for req %p:%u NOT a continuation", 632 reply_frame->Function, req, req->serno); 633 if (reply_frame->Function == MPI_FUNCTION_EVENT_NOTIFICATION) { 634 MSG_EVENT_NOTIFY_REPLY *msg = 635 (MSG_EVENT_NOTIFY_REPLY *)reply_frame; 636 mpt_prtc(mpt, " Event=0x%x AckReq=%d", 637 msg->Event, msg->AckRequired); 638 } 639 } else { 640 mpt_prt(mpt, "event_reply %x for %p:%u IS a continuation", 641 reply_frame->Function, req, req->serno); 642 if (reply_frame->Function == MPI_FUNCTION_EVENT_NOTIFICATION) { 643 MSG_EVENT_NOTIFY_REPLY *msg = 644 (MSG_EVENT_NOTIFY_REPLY *)reply_frame; 645 mpt_prtc(mpt, " Event=0x%x AckReq=%d", 646 msg->Event, msg->AckRequired); 647 } 648 mpt_prtc(mpt, "\n"); 649 } 650#endif 651 return (free_reply); 652} 653 654/* 655 * Process an asynchronous event from the IOC. 656 */ 657static int 658mpt_core_event(struct mpt_softc *mpt, request_t *req, 659 MSG_EVENT_NOTIFY_REPLY *msg) 660{ 661 662 mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_core_event: 0x%x\n", 663 msg->Event & 0xFF); 664 switch(msg->Event & 0xFF) { 665 case MPI_EVENT_NONE: 666 break; 667 case MPI_EVENT_LOG_DATA: 668 { 669 int i; 670 671 /* Some error occurred that LSI wants logged */ 672 mpt_prt(mpt, "EvtLogData: IOCLogInfo: 0x%08x\n", 673 msg->IOCLogInfo); 674 mpt_prt(mpt, "\tEvtLogData: Event Data:"); 675 for (i = 0; i < msg->EventDataLength; i++) 676 mpt_prtc(mpt, " %08x", msg->Data[i]); 677 mpt_prtc(mpt, "\n"); 678 break; 679 } 680 case MPI_EVENT_EVENT_CHANGE: 681 /* 682 * This is just an acknowledgement 683 * of our mpt_send_event_request. 684 */ 685 break; 686 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: 687 break; 688 default: 689 return (0); 690 break; 691 } 692 return (1); 693} 694 695static void 696mpt_send_event_ack(struct mpt_softc *mpt, request_t *ack_req, 697 MSG_EVENT_NOTIFY_REPLY *msg, uint32_t context) 698{ 699 MSG_EVENT_ACK *ackp; 700 701 ackp = (MSG_EVENT_ACK *)ack_req->req_vbuf; 702 memset(ackp, 0, sizeof (*ackp)); 703 ackp->Function = MPI_FUNCTION_EVENT_ACK; 704 ackp->Event = htole32(msg->Event); 705 ackp->EventContext = htole32(msg->EventContext); 706 ackp->MsgContext = htole32(context); 707 mpt_check_doorbell(mpt); 708 mpt_send_cmd(mpt, ack_req); 709} 710 711/***************************** Interrupt Handling *****************************/ 712void 713mpt_intr(void *arg) 714{ 715 struct mpt_softc *mpt; 716 uint32_t reply_desc; 717 int ntrips = 0; 718 719 mpt = (struct mpt_softc *)arg; 720 mpt_lprt(mpt, MPT_PRT_DEBUG2, "enter mpt_intr\n"); 721 MPT_LOCK_ASSERT(mpt); 722 723 while ((reply_desc = mpt_pop_reply_queue(mpt)) != MPT_REPLY_EMPTY) { 724 request_t *req; 725 MSG_DEFAULT_REPLY *reply_frame; 726 uint32_t reply_baddr; 727 uint32_t ctxt_idx; 728 u_int cb_index; 729 u_int req_index; 730 u_int offset; 731 int free_rf; 732 733 req = NULL; 734 reply_frame = NULL; 735 reply_baddr = 0; 736 offset = 0; 737 if ((reply_desc & MPI_ADDRESS_REPLY_A_BIT) != 0) { 738 /* 739 * Ensure that the reply frame is coherent. 740 */ 741 reply_baddr = MPT_REPLY_BADDR(reply_desc); 742 offset = reply_baddr - (mpt->reply_phys & 0xFFFFFFFF); 743 bus_dmamap_sync_range(mpt->reply_dmat, 744 mpt->reply_dmap, offset, MPT_REPLY_SIZE, 745 BUS_DMASYNC_POSTREAD); 746 reply_frame = MPT_REPLY_OTOV(mpt, offset); 747 ctxt_idx = le32toh(reply_frame->MsgContext); 748 } else { 749 uint32_t type; 750 751 type = MPI_GET_CONTEXT_REPLY_TYPE(reply_desc); 752 ctxt_idx = reply_desc; 753 mpt_lprt(mpt, MPT_PRT_DEBUG1, "Context Reply: 0x%08x\n", 754 reply_desc); 755 756 switch (type) { 757 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT: 758 ctxt_idx &= MPI_CONTEXT_REPLY_CONTEXT_MASK; 759 break; 760 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET: 761 ctxt_idx = GET_IO_INDEX(reply_desc); 762 if (mpt->tgt_cmd_ptrs == NULL) { 763 mpt_prt(mpt, 764 "mpt_intr: no target cmd ptrs\n"); 765 reply_desc = MPT_REPLY_EMPTY; 766 break; 767 } 768 if (ctxt_idx >= mpt->tgt_cmds_allocated) { 769 mpt_prt(mpt, 770 "mpt_intr: bad tgt cmd ctxt %u\n", 771 ctxt_idx); 772 reply_desc = MPT_REPLY_EMPTY; 773 ntrips = 1000; 774 break; 775 } 776 req = mpt->tgt_cmd_ptrs[ctxt_idx]; 777 if (req == NULL) { 778 mpt_prt(mpt, "no request backpointer " 779 "at index %u", ctxt_idx); 780 reply_desc = MPT_REPLY_EMPTY; 781 ntrips = 1000; 782 break; 783 } 784 /* 785 * Reformulate ctxt_idx to be just as if 786 * it were another type of context reply 787 * so the code below will find the request 788 * via indexing into the pool. 789 */ 790 ctxt_idx = 791 req->index | mpt->scsi_tgt_handler_id; 792 req = NULL; 793 break; 794 case MPI_CONTEXT_REPLY_TYPE_LAN: 795 mpt_prt(mpt, "LAN CONTEXT REPLY: 0x%08x\n", 796 reply_desc); 797 reply_desc = MPT_REPLY_EMPTY; 798 break; 799 default: 800 mpt_prt(mpt, "Context Reply 0x%08x?\n", type); 801 reply_desc = MPT_REPLY_EMPTY; 802 break; 803 } 804 if (reply_desc == MPT_REPLY_EMPTY) { 805 if (ntrips++ > 1000) { 806 break; 807 } 808 continue; 809 } 810 } 811 812 cb_index = MPT_CONTEXT_TO_CBI(ctxt_idx); 813 req_index = MPT_CONTEXT_TO_REQI(ctxt_idx); 814 if (req_index < MPT_MAX_REQUESTS(mpt)) { 815 req = &mpt->request_pool[req_index]; 816 } else { 817 mpt_prt(mpt, "WARN: mpt_intr index == %d (reply_desc ==" 818 " 0x%x)\n", req_index, reply_desc); 819 } 820 821 bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, 822 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 823 free_rf = mpt_reply_handlers[cb_index](mpt, req, 824 reply_desc, reply_frame); 825 826 if (reply_frame != NULL && free_rf) { 827 bus_dmamap_sync_range(mpt->reply_dmat, 828 mpt->reply_dmap, offset, MPT_REPLY_SIZE, 829 BUS_DMASYNC_PREREAD); 830 mpt_free_reply(mpt, reply_baddr); 831 } 832 833 /* 834 * If we got ourselves disabled, don't get stuck in a loop 835 */ 836 if (mpt->disabled) { 837 mpt_disable_ints(mpt); 838 break; 839 } 840 if (ntrips++ > 1000) { 841 break; 842 } 843 } 844 mpt_lprt(mpt, MPT_PRT_DEBUG2, "exit mpt_intr\n"); 845} 846 847/******************************* Error Recovery *******************************/ 848void 849mpt_complete_request_chain(struct mpt_softc *mpt, struct req_queue *chain, 850 u_int iocstatus) 851{ 852 MSG_DEFAULT_REPLY ioc_status_frame; 853 request_t *req; 854 855 memset(&ioc_status_frame, 0, sizeof(ioc_status_frame)); 856 ioc_status_frame.MsgLength = roundup2(sizeof(ioc_status_frame), 4); 857 ioc_status_frame.IOCStatus = iocstatus; 858 while((req = TAILQ_FIRST(chain)) != NULL) { 859 MSG_REQUEST_HEADER *msg_hdr; 860 u_int cb_index; 861 862 bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, 863 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 864 msg_hdr = (MSG_REQUEST_HEADER *)req->req_vbuf; 865 ioc_status_frame.Function = msg_hdr->Function; 866 ioc_status_frame.MsgContext = msg_hdr->MsgContext; 867 cb_index = MPT_CONTEXT_TO_CBI(le32toh(msg_hdr->MsgContext)); 868 mpt_reply_handlers[cb_index](mpt, req, msg_hdr->MsgContext, 869 &ioc_status_frame); 870 if (mpt_req_on_pending_list(mpt, req) != 0) 871 TAILQ_REMOVE(chain, req, links); 872 } 873} 874 875/********************************* Diagnostics ********************************/ 876/* 877 * Perform a diagnostic dump of a reply frame. 878 */ 879void 880mpt_dump_reply_frame(struct mpt_softc *mpt, MSG_DEFAULT_REPLY *reply_frame) 881{ 882 883 mpt_prt(mpt, "Address Reply:\n"); 884 mpt_print_reply(reply_frame); 885} 886 887/******************************* Doorbell Access ******************************/ 888static __inline uint32_t mpt_rd_db(struct mpt_softc *mpt); 889static __inline uint32_t mpt_rd_intr(struct mpt_softc *mpt); 890 891static __inline uint32_t 892mpt_rd_db(struct mpt_softc *mpt) 893{ 894 895 return mpt_read(mpt, MPT_OFFSET_DOORBELL); 896} 897 898static __inline uint32_t 899mpt_rd_intr(struct mpt_softc *mpt) 900{ 901 902 return mpt_read(mpt, MPT_OFFSET_INTR_STATUS); 903} 904 905/* Busy wait for a door bell to be read by IOC */ 906static int 907mpt_wait_db_ack(struct mpt_softc *mpt) 908{ 909 int i; 910 911 for (i=0; i < MPT_MAX_WAIT; i++) { 912 if (!MPT_DB_IS_BUSY(mpt_rd_intr(mpt))) { 913 maxwait_ack = i > maxwait_ack ? i : maxwait_ack; 914 return (MPT_OK); 915 } 916 DELAY(200); 917 } 918 return (MPT_FAIL); 919} 920 921/* Busy wait for a door bell interrupt */ 922static int 923mpt_wait_db_int(struct mpt_softc *mpt) 924{ 925 int i; 926 927 for (i = 0; i < MPT_MAX_WAIT; i++) { 928 if (MPT_DB_INTR(mpt_rd_intr(mpt))) { 929 maxwait_int = i > maxwait_int ? i : maxwait_int; 930 return MPT_OK; 931 } 932 DELAY(100); 933 } 934 return (MPT_FAIL); 935} 936 937/* Wait for IOC to transition to a give state */ 938void 939mpt_check_doorbell(struct mpt_softc *mpt) 940{ 941 uint32_t db = mpt_rd_db(mpt); 942 943 if (MPT_STATE(db) != MPT_DB_STATE_RUNNING) { 944 mpt_prt(mpt, "Device not running\n"); 945 mpt_print_db(db); 946 } 947} 948 949/* Wait for IOC to transition to a give state */ 950static int 951mpt_wait_state(struct mpt_softc *mpt, enum DB_STATE_BITS state) 952{ 953 int i; 954 955 for (i = 0; i < MPT_MAX_WAIT; i++) { 956 uint32_t db = mpt_rd_db(mpt); 957 if (MPT_STATE(db) == state) { 958 maxwait_state = i > maxwait_state ? i : maxwait_state; 959 return (MPT_OK); 960 } 961 DELAY(100); 962 } 963 return (MPT_FAIL); 964} 965 966 967/************************* Intialization/Configuration ************************/ 968static int mpt_download_fw(struct mpt_softc *mpt); 969 970/* Issue the reset COMMAND to the IOC */ 971static int 972mpt_soft_reset(struct mpt_softc *mpt) 973{ 974 975 mpt_lprt(mpt, MPT_PRT_DEBUG, "soft reset\n"); 976 977 /* Have to use hard reset if we are not in Running state */ 978 if (MPT_STATE(mpt_rd_db(mpt)) != MPT_DB_STATE_RUNNING) { 979 mpt_prt(mpt, "soft reset failed: device not running\n"); 980 return (MPT_FAIL); 981 } 982 983 /* If door bell is in use we don't have a chance of getting 984 * a word in since the IOC probably crashed in message 985 * processing. So don't waste our time. 986 */ 987 if (MPT_DB_IS_IN_USE(mpt_rd_db(mpt))) { 988 mpt_prt(mpt, "soft reset failed: doorbell wedged\n"); 989 return (MPT_FAIL); 990 } 991 992 /* Send the reset request to the IOC */ 993 mpt_write(mpt, MPT_OFFSET_DOORBELL, 994 MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET << MPI_DOORBELL_FUNCTION_SHIFT); 995 if (mpt_wait_db_ack(mpt) != MPT_OK) { 996 mpt_prt(mpt, "soft reset failed: ack timeout\n"); 997 return (MPT_FAIL); 998 } 999 1000 /* Wait for the IOC to reload and come out of reset state */ 1001 if (mpt_wait_state(mpt, MPT_DB_STATE_READY) != MPT_OK) { 1002 mpt_prt(mpt, "soft reset failed: device did not restart\n"); 1003 return (MPT_FAIL); 1004 } 1005 1006 return MPT_OK; 1007} 1008 1009static int 1010mpt_enable_diag_mode(struct mpt_softc *mpt) 1011{ 1012 int try; 1013 1014 try = 20; 1015 while (--try) { 1016 1017 if ((mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC) & MPI_DIAG_DRWE) != 0) 1018 break; 1019 1020 /* Enable diagnostic registers */ 1021 mpt_write(mpt, MPT_OFFSET_SEQUENCE, 0xFF); 1022 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_1ST_KEY_VALUE); 1023 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_2ND_KEY_VALUE); 1024 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_3RD_KEY_VALUE); 1025 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_4TH_KEY_VALUE); 1026 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_5TH_KEY_VALUE); 1027 1028 DELAY(100000); 1029 } 1030 if (try == 0) 1031 return (EIO); 1032 return (0); 1033} 1034 1035static void 1036mpt_disable_diag_mode(struct mpt_softc *mpt) 1037{ 1038 1039 mpt_write(mpt, MPT_OFFSET_SEQUENCE, 0xFFFFFFFF); 1040} 1041 1042/* This is a magic diagnostic reset that resets all the ARM 1043 * processors in the chip. 1044 */ 1045static void 1046mpt_hard_reset(struct mpt_softc *mpt) 1047{ 1048 int error; 1049 int wait; 1050 uint32_t diagreg; 1051 1052 mpt_lprt(mpt, MPT_PRT_DEBUG, "hard reset\n"); 1053 1054 if (mpt->is_1078) { 1055 mpt_write(mpt, MPT_OFFSET_RESET_1078, 0x07); 1056 DELAY(1000); 1057 return; 1058 } 1059 1060 error = mpt_enable_diag_mode(mpt); 1061 if (error) { 1062 mpt_prt(mpt, "WARNING - Could not enter diagnostic mode !\n"); 1063 mpt_prt(mpt, "Trying to reset anyway.\n"); 1064 } 1065 1066 diagreg = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); 1067 1068 /* 1069 * This appears to be a workaround required for some 1070 * firmware or hardware revs. 1071 */ 1072 mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, diagreg | MPI_DIAG_DISABLE_ARM); 1073 DELAY(1000); 1074 1075 /* Diag. port is now active so we can now hit the reset bit */ 1076 mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, diagreg | MPI_DIAG_RESET_ADAPTER); 1077 1078 /* 1079 * Ensure that the reset has finished. We delay 1ms 1080 * prior to reading the register to make sure the chip 1081 * has sufficiently completed its reset to handle register 1082 * accesses. 1083 */ 1084 wait = 5000; 1085 do { 1086 DELAY(1000); 1087 diagreg = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); 1088 } while (--wait && (diagreg & MPI_DIAG_RESET_ADAPTER) == 0); 1089 1090 if (wait == 0) { 1091 mpt_prt(mpt, "WARNING - Failed hard reset! " 1092 "Trying to initialize anyway.\n"); 1093 } 1094 1095 /* 1096 * If we have firmware to download, it must be loaded before 1097 * the controller will become operational. Do so now. 1098 */ 1099 if (mpt->fw_image != NULL) { 1100 1101 error = mpt_download_fw(mpt); 1102 1103 if (error) { 1104 mpt_prt(mpt, "WARNING - Firmware Download Failed!\n"); 1105 mpt_prt(mpt, "Trying to initialize anyway.\n"); 1106 } 1107 } 1108 1109 /* 1110 * Reseting the controller should have disabled write 1111 * access to the diagnostic registers, but disable 1112 * manually to be sure. 1113 */ 1114 mpt_disable_diag_mode(mpt); 1115} 1116 1117static void 1118mpt_core_ioc_reset(struct mpt_softc *mpt, int type) 1119{ 1120 1121 /* 1122 * Complete all pending requests with a status 1123 * appropriate for an IOC reset. 1124 */ 1125 mpt_complete_request_chain(mpt, &mpt->request_pending_list, 1126 MPI_IOCSTATUS_INVALID_STATE); 1127} 1128 1129/* 1130 * Reset the IOC when needed. Try software command first then if needed 1131 * poke at the magic diagnostic reset. Note that a hard reset resets 1132 * *both* IOCs on dual function chips (FC929 && LSI1030) as well as 1133 * fouls up the PCI configuration registers. 1134 */ 1135int 1136mpt_reset(struct mpt_softc *mpt, int reinit) 1137{ 1138 struct mpt_personality *pers; 1139 int ret; 1140 int retry_cnt = 0; 1141 1142 /* 1143 * Try a soft reset. If that fails, get out the big hammer. 1144 */ 1145 again: 1146 if ((ret = mpt_soft_reset(mpt)) != MPT_OK) { 1147 int cnt; 1148 for (cnt = 0; cnt < 5; cnt++) { 1149 /* Failed; do a hard reset */ 1150 mpt_hard_reset(mpt); 1151 1152 /* 1153 * Wait for the IOC to reload 1154 * and come out of reset state 1155 */ 1156 ret = mpt_wait_state(mpt, MPT_DB_STATE_READY); 1157 if (ret == MPT_OK) { 1158 break; 1159 } 1160 /* 1161 * Okay- try to check again... 1162 */ 1163 ret = mpt_wait_state(mpt, MPT_DB_STATE_READY); 1164 if (ret == MPT_OK) { 1165 break; 1166 } 1167 mpt_prt(mpt, "mpt_reset: failed hard reset (%d:%d)\n", 1168 retry_cnt, cnt); 1169 } 1170 } 1171 1172 if (retry_cnt == 0) { 1173 /* 1174 * Invoke reset handlers. We bump the reset count so 1175 * that mpt_wait_req() understands that regardless of 1176 * the specified wait condition, it should stop its wait. 1177 */ 1178 mpt->reset_cnt++; 1179 MPT_PERS_FOREACH(mpt, pers) 1180 pers->reset(mpt, ret); 1181 } 1182 1183 if (reinit) { 1184 ret = mpt_enable_ioc(mpt, 1); 1185 if (ret == MPT_OK) { 1186 mpt_enable_ints(mpt); 1187 } 1188 } 1189 if (ret != MPT_OK && retry_cnt++ < 2) { 1190 goto again; 1191 } 1192 return ret; 1193} 1194 1195/* Return a command buffer to the free queue */ 1196void 1197mpt_free_request(struct mpt_softc *mpt, request_t *req) 1198{ 1199 request_t *nxt; 1200 struct mpt_evtf_record *record; 1201 uint32_t offset, reply_baddr; 1202 1203 if (req == NULL || req != &mpt->request_pool[req->index]) { 1204 panic("mpt_free_request: bad req ptr"); 1205 } 1206 if ((nxt = req->chain) != NULL) { 1207 req->chain = NULL; 1208 mpt_free_request(mpt, nxt); /* NB: recursion */ 1209 } 1210 KASSERT(req->state != REQ_STATE_FREE, ("freeing free request")); 1211 KASSERT(!(req->state & REQ_STATE_LOCKED), ("freeing locked request")); 1212 MPT_LOCK_ASSERT(mpt); 1213 KASSERT(mpt_req_on_free_list(mpt, req) == 0, 1214 ("mpt_free_request: req %p:%u func %x already on freelist", 1215 req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1216 KASSERT(mpt_req_on_pending_list(mpt, req) == 0, 1217 ("mpt_free_request: req %p:%u func %x on pending list", 1218 req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1219#ifdef INVARIANTS 1220 mpt_req_not_spcl(mpt, req, "mpt_free_request", __LINE__); 1221#endif 1222 1223 req->ccb = NULL; 1224 if (LIST_EMPTY(&mpt->ack_frames)) { 1225 /* 1226 * Insert free ones at the tail 1227 */ 1228 req->serno = 0; 1229 req->state = REQ_STATE_FREE; 1230#ifdef INVARIANTS 1231 memset(req->req_vbuf, 0xff, sizeof (MSG_REQUEST_HEADER)); 1232#endif 1233 TAILQ_INSERT_TAIL(&mpt->request_free_list, req, links); 1234 if (mpt->getreqwaiter != 0) { 1235 mpt->getreqwaiter = 0; 1236 wakeup(&mpt->request_free_list); 1237 } 1238 return; 1239 } 1240 1241 /* 1242 * Process an ack frame deferred due to resource shortage. 1243 */ 1244 record = LIST_FIRST(&mpt->ack_frames); 1245 LIST_REMOVE(record, links); 1246 req->state = REQ_STATE_ALLOCATED; 1247 mpt_assign_serno(mpt, req); 1248 mpt_send_event_ack(mpt, req, &record->reply, record->context); 1249 offset = (uint32_t)((uint8_t *)record - mpt->reply); 1250 reply_baddr = offset + (mpt->reply_phys & 0xFFFFFFFF); 1251 bus_dmamap_sync_range(mpt->reply_dmat, mpt->reply_dmap, offset, 1252 MPT_REPLY_SIZE, BUS_DMASYNC_PREREAD); 1253 mpt_free_reply(mpt, reply_baddr); 1254} 1255 1256/* Get a command buffer from the free queue */ 1257request_t * 1258mpt_get_request(struct mpt_softc *mpt, int sleep_ok) 1259{ 1260 request_t *req; 1261 1262retry: 1263 MPT_LOCK_ASSERT(mpt); 1264 req = TAILQ_FIRST(&mpt->request_free_list); 1265 if (req != NULL) { 1266 KASSERT(req == &mpt->request_pool[req->index], 1267 ("mpt_get_request: corrupted request free list")); 1268 KASSERT(req->state == REQ_STATE_FREE, 1269 ("req %p:%u not free on free list %x index %d function %x", 1270 req, req->serno, req->state, req->index, 1271 ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1272 TAILQ_REMOVE(&mpt->request_free_list, req, links); 1273 req->state = REQ_STATE_ALLOCATED; 1274 req->chain = NULL; 1275 mpt_assign_serno(mpt, req); 1276 } else if (sleep_ok != 0) { 1277 mpt->getreqwaiter = 1; 1278 mpt_sleep(mpt, &mpt->request_free_list, PUSER, "mptgreq", 0); 1279 goto retry; 1280 } 1281 return (req); 1282} 1283 1284/* Pass the command to the IOC */ 1285void 1286mpt_send_cmd(struct mpt_softc *mpt, request_t *req) 1287{ 1288 1289 if (mpt->verbose > MPT_PRT_DEBUG2) { 1290 mpt_dump_request(mpt, req); 1291 } 1292 bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, 1293 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1294 req->state |= REQ_STATE_QUEUED; 1295 KASSERT(mpt_req_on_free_list(mpt, req) == 0, 1296 ("req %p:%u func %x on freelist list in mpt_send_cmd", 1297 req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1298 KASSERT(mpt_req_on_pending_list(mpt, req) == 0, 1299 ("req %p:%u func %x already on pending list in mpt_send_cmd", 1300 req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1301 TAILQ_INSERT_HEAD(&mpt->request_pending_list, req, links); 1302 mpt_write(mpt, MPT_OFFSET_REQUEST_Q, (uint32_t) req->req_pbuf); 1303} 1304 1305/* 1306 * Wait for a request to complete. 1307 * 1308 * Inputs: 1309 * mpt softc of controller executing request 1310 * req request to wait for 1311 * sleep_ok nonzero implies may sleep in this context 1312 * time_ms timeout in ms. 0 implies no timeout. 1313 * 1314 * Return Values: 1315 * 0 Request completed 1316 * non-0 Timeout fired before request completion. 1317 */ 1318int 1319mpt_wait_req(struct mpt_softc *mpt, request_t *req, 1320 mpt_req_state_t state, mpt_req_state_t mask, 1321 int sleep_ok, int time_ms) 1322{ 1323 int timeout; 1324 u_int saved_cnt; 1325 sbintime_t sbt; 1326 1327 /* 1328 * time_ms is in ms, 0 indicates infinite wait. 1329 * Convert to sbintime_t or 500us units depending on 1330 * our sleep mode. 1331 */ 1332 if (sleep_ok != 0) { 1333 sbt = SBT_1MS * time_ms; 1334 /* Set timeout as well so final timeout check works. */ 1335 timeout = time_ms; 1336 } else { 1337 timeout = time_ms * 2; 1338 } 1339 req->state |= REQ_STATE_NEED_WAKEUP; 1340 mask &= ~REQ_STATE_NEED_WAKEUP; 1341 saved_cnt = mpt->reset_cnt; 1342 while ((req->state & mask) != state && mpt->reset_cnt == saved_cnt) { 1343 if (sleep_ok != 0) { 1344 if (mpt_sleep(mpt, req, PUSER, "mptreq", sbt) == 1345 EWOULDBLOCK) { 1346 timeout = 0; 1347 break; 1348 } 1349 } else { 1350 if (time_ms != 0 && --timeout == 0) { 1351 break; 1352 } 1353 DELAY(500); 1354 mpt_intr(mpt); 1355 } 1356 } 1357 req->state &= ~REQ_STATE_NEED_WAKEUP; 1358 if (mpt->reset_cnt != saved_cnt) { 1359 return (EIO); 1360 } 1361 if (time_ms && timeout <= 0) { 1362 MSG_REQUEST_HEADER *msg_hdr = req->req_vbuf; 1363 req->state |= REQ_STATE_TIMEDOUT; 1364 mpt_prt(mpt, "mpt_wait_req(%x) timed out\n", msg_hdr->Function); 1365 return (ETIMEDOUT); 1366 } 1367 return (0); 1368} 1369 1370/* 1371 * Send a command to the IOC via the handshake register. 1372 * 1373 * Only done at initialization time and for certain unusual 1374 * commands such as device/bus reset as specified by LSI. 1375 */ 1376int 1377mpt_send_handshake_cmd(struct mpt_softc *mpt, size_t len, void *cmd) 1378{ 1379 int i; 1380 uint32_t data, *data32; 1381 1382 /* Check condition of the IOC */ 1383 data = mpt_rd_db(mpt); 1384 if ((MPT_STATE(data) != MPT_DB_STATE_READY 1385 && MPT_STATE(data) != MPT_DB_STATE_RUNNING 1386 && MPT_STATE(data) != MPT_DB_STATE_FAULT) 1387 || MPT_DB_IS_IN_USE(data)) { 1388 mpt_prt(mpt, "handshake aborted - invalid doorbell state\n"); 1389 mpt_print_db(data); 1390 return (EBUSY); 1391 } 1392 1393 /* We move things in 32 bit chunks */ 1394 len = (len + 3) >> 2; 1395 data32 = cmd; 1396 1397 /* Clear any left over pending doorbell interrupts */ 1398 if (MPT_DB_INTR(mpt_rd_intr(mpt))) 1399 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1400 1401 /* 1402 * Tell the handshake reg. we are going to send a command 1403 * and how long it is going to be. 1404 */ 1405 data = (MPI_FUNCTION_HANDSHAKE << MPI_DOORBELL_FUNCTION_SHIFT) | 1406 (len << MPI_DOORBELL_ADD_DWORDS_SHIFT); 1407 mpt_write(mpt, MPT_OFFSET_DOORBELL, data); 1408 1409 /* Wait for the chip to notice */ 1410 if (mpt_wait_db_int(mpt) != MPT_OK) { 1411 mpt_prt(mpt, "mpt_send_handshake_cmd: db ignored\n"); 1412 return (ETIMEDOUT); 1413 } 1414 1415 /* Clear the interrupt */ 1416 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1417 1418 if (mpt_wait_db_ack(mpt) != MPT_OK) { 1419 mpt_prt(mpt, "mpt_send_handshake_cmd: db ack timed out\n"); 1420 return (ETIMEDOUT); 1421 } 1422 1423 /* Send the command */ 1424 for (i = 0; i < len; i++) { 1425 mpt_write(mpt, MPT_OFFSET_DOORBELL, htole32(*data32++)); 1426 if (mpt_wait_db_ack(mpt) != MPT_OK) { 1427 mpt_prt(mpt, 1428 "mpt_send_handshake_cmd: timeout @ index %d\n", i); 1429 return (ETIMEDOUT); 1430 } 1431 } 1432 return MPT_OK; 1433} 1434 1435/* Get the response from the handshake register */ 1436int 1437mpt_recv_handshake_reply(struct mpt_softc *mpt, size_t reply_len, void *reply) 1438{ 1439 int left, reply_left; 1440 u_int16_t *data16; 1441 uint32_t data; 1442 MSG_DEFAULT_REPLY *hdr; 1443 1444 /* We move things out in 16 bit chunks */ 1445 reply_len >>= 1; 1446 data16 = (u_int16_t *)reply; 1447 1448 hdr = (MSG_DEFAULT_REPLY *)reply; 1449 1450 /* Get first word */ 1451 if (mpt_wait_db_int(mpt) != MPT_OK) { 1452 mpt_prt(mpt, "mpt_recv_handshake_cmd timeout1\n"); 1453 return ETIMEDOUT; 1454 } 1455 data = mpt_read(mpt, MPT_OFFSET_DOORBELL); 1456 *data16++ = le16toh(data & MPT_DB_DATA_MASK); 1457 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1458 1459 /* Get Second Word */ 1460 if (mpt_wait_db_int(mpt) != MPT_OK) { 1461 mpt_prt(mpt, "mpt_recv_handshake_cmd timeout2\n"); 1462 return ETIMEDOUT; 1463 } 1464 data = mpt_read(mpt, MPT_OFFSET_DOORBELL); 1465 *data16++ = le16toh(data & MPT_DB_DATA_MASK); 1466 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1467 1468 /* 1469 * With the second word, we can now look at the length. 1470 * Warn about a reply that's too short (except for IOC FACTS REPLY) 1471 */ 1472 if ((reply_len >> 1) != hdr->MsgLength && 1473 (hdr->Function != MPI_FUNCTION_IOC_FACTS)){ 1474 mpt_prt(mpt, "reply length does not match message length: " 1475 "got %x; expected %zx for function %x\n", 1476 hdr->MsgLength << 2, reply_len << 1, hdr->Function); 1477 } 1478 1479 /* Get rest of the reply; but don't overflow the provided buffer */ 1480 left = (hdr->MsgLength << 1) - 2; 1481 reply_left = reply_len - 2; 1482 while (left--) { 1483 u_int16_t datum; 1484 1485 if (mpt_wait_db_int(mpt) != MPT_OK) { 1486 mpt_prt(mpt, "mpt_recv_handshake_cmd timeout3\n"); 1487 return ETIMEDOUT; 1488 } 1489 data = mpt_read(mpt, MPT_OFFSET_DOORBELL); 1490 datum = le16toh(data & MPT_DB_DATA_MASK); 1491 1492 if (reply_left-- > 0) 1493 *data16++ = datum; 1494 1495 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1496 } 1497 1498 /* One more wait & clear at the end */ 1499 if (mpt_wait_db_int(mpt) != MPT_OK) { 1500 mpt_prt(mpt, "mpt_recv_handshake_cmd timeout4\n"); 1501 return ETIMEDOUT; 1502 } 1503 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1504 1505 if ((hdr->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 1506 if (mpt->verbose >= MPT_PRT_TRACE) 1507 mpt_print_reply(hdr); 1508 return (MPT_FAIL | hdr->IOCStatus); 1509 } 1510 1511 return (0); 1512} 1513 1514static int 1515mpt_get_iocfacts(struct mpt_softc *mpt, MSG_IOC_FACTS_REPLY *freplp) 1516{ 1517 MSG_IOC_FACTS f_req; 1518 int error; 1519 1520 memset(&f_req, 0, sizeof f_req); 1521 f_req.Function = MPI_FUNCTION_IOC_FACTS; 1522 f_req.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); 1523 error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); 1524 if (error) { 1525 return(error); 1526 } 1527 error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); 1528 return (error); 1529} 1530 1531static int 1532mpt_get_portfacts(struct mpt_softc *mpt, U8 port, MSG_PORT_FACTS_REPLY *freplp) 1533{ 1534 MSG_PORT_FACTS f_req; 1535 int error; 1536 1537 memset(&f_req, 0, sizeof f_req); 1538 f_req.Function = MPI_FUNCTION_PORT_FACTS; 1539 f_req.PortNumber = port; 1540 f_req.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); 1541 error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); 1542 if (error) { 1543 return(error); 1544 } 1545 error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); 1546 return (error); 1547} 1548 1549/* 1550 * Send the initialization request. This is where we specify how many 1551 * SCSI busses and how many devices per bus we wish to emulate. 1552 * This is also the command that specifies the max size of the reply 1553 * frames from the IOC that we will be allocating. 1554 */ 1555static int 1556mpt_send_ioc_init(struct mpt_softc *mpt, uint32_t who) 1557{ 1558 int error = 0; 1559 MSG_IOC_INIT init; 1560 MSG_IOC_INIT_REPLY reply; 1561 1562 memset(&init, 0, sizeof init); 1563 init.WhoInit = who; 1564 init.Function = MPI_FUNCTION_IOC_INIT; 1565 init.MaxDevices = 0; /* at least 256 devices per bus */ 1566 init.MaxBuses = 16; /* at least 16 busses */ 1567 1568 init.MsgVersion = htole16(MPI_VERSION); 1569 init.HeaderVersion = htole16(MPI_HEADER_VERSION); 1570 init.ReplyFrameSize = htole16(MPT_REPLY_SIZE); 1571 init.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); 1572 1573 if ((error = mpt_send_handshake_cmd(mpt, sizeof init, &init)) != 0) { 1574 return(error); 1575 } 1576 1577 error = mpt_recv_handshake_reply(mpt, sizeof reply, &reply); 1578 return (error); 1579} 1580 1581 1582/* 1583 * Utiltity routine to read configuration headers and pages 1584 */ 1585int 1586mpt_issue_cfg_req(struct mpt_softc *mpt, request_t *req, cfgparms_t *params, 1587 bus_addr_t addr, bus_size_t len, int sleep_ok, int timeout_ms) 1588{ 1589 MSG_CONFIG *cfgp; 1590 SGE_SIMPLE32 *se; 1591 1592 cfgp = req->req_vbuf; 1593 memset(cfgp, 0, sizeof *cfgp); 1594 cfgp->Action = params->Action; 1595 cfgp->Function = MPI_FUNCTION_CONFIG; 1596 cfgp->Header.PageVersion = params->PageVersion; 1597 cfgp->Header.PageNumber = params->PageNumber; 1598 cfgp->PageAddress = htole32(params->PageAddress); 1599 if ((params->PageType & MPI_CONFIG_PAGETYPE_MASK) == 1600 MPI_CONFIG_PAGETYPE_EXTENDED) { 1601 cfgp->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 1602 cfgp->Header.PageLength = 0; 1603 cfgp->ExtPageLength = htole16(params->ExtPageLength); 1604 cfgp->ExtPageType = params->ExtPageType; 1605 } else { 1606 cfgp->Header.PageType = params->PageType; 1607 cfgp->Header.PageLength = params->PageLength; 1608 } 1609 se = (SGE_SIMPLE32 *)&cfgp->PageBufferSGE; 1610 se->Address = htole32(addr); 1611 MPI_pSGE_SET_LENGTH(se, len); 1612 MPI_pSGE_SET_FLAGS(se, (MPI_SGE_FLAGS_SIMPLE_ELEMENT | 1613 MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | 1614 MPI_SGE_FLAGS_END_OF_LIST | 1615 ((params->Action == MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT 1616 || params->Action == MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM) 1617 ? MPI_SGE_FLAGS_HOST_TO_IOC : MPI_SGE_FLAGS_IOC_TO_HOST))); 1618 se->FlagsLength = htole32(se->FlagsLength); 1619 cfgp->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_CONFIG); 1620 1621 mpt_check_doorbell(mpt); 1622 mpt_send_cmd(mpt, req); 1623 return (mpt_wait_req(mpt, req, REQ_STATE_DONE, REQ_STATE_DONE, 1624 sleep_ok, timeout_ms)); 1625} 1626 1627int 1628mpt_read_extcfg_header(struct mpt_softc *mpt, int PageVersion, int PageNumber, 1629 uint32_t PageAddress, int ExtPageType, 1630 CONFIG_EXTENDED_PAGE_HEADER *rslt, 1631 int sleep_ok, int timeout_ms) 1632{ 1633 request_t *req; 1634 cfgparms_t params; 1635 MSG_CONFIG_REPLY *cfgp; 1636 int error; 1637 1638 req = mpt_get_request(mpt, sleep_ok); 1639 if (req == NULL) { 1640 mpt_prt(mpt, "mpt_extread_cfg_header: Get request failed!\n"); 1641 return (ENOMEM); 1642 } 1643 1644 params.Action = MPI_CONFIG_ACTION_PAGE_HEADER; 1645 params.PageVersion = PageVersion; 1646 params.PageLength = 0; 1647 params.PageNumber = PageNumber; 1648 params.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 1649 params.PageAddress = PageAddress; 1650 params.ExtPageType = ExtPageType; 1651 params.ExtPageLength = 0; 1652 error = mpt_issue_cfg_req(mpt, req, ¶ms, /*addr*/0, /*len*/0, 1653 sleep_ok, timeout_ms); 1654 if (error != 0) { 1655 /* 1656 * Leave the request. Without resetting the chip, it's 1657 * still owned by it and we'll just get into trouble 1658 * freeing it now. Mark it as abandoned so that if it 1659 * shows up later it can be freed. 1660 */ 1661 mpt_prt(mpt, "read_extcfg_header timed out\n"); 1662 return (ETIMEDOUT); 1663 } 1664 1665 switch (req->IOCStatus & MPI_IOCSTATUS_MASK) { 1666 case MPI_IOCSTATUS_SUCCESS: 1667 cfgp = req->req_vbuf; 1668 rslt->PageVersion = cfgp->Header.PageVersion; 1669 rslt->PageNumber = cfgp->Header.PageNumber; 1670 rslt->PageType = cfgp->Header.PageType; 1671 rslt->ExtPageLength = le16toh(cfgp->ExtPageLength); 1672 rslt->ExtPageType = cfgp->ExtPageType; 1673 error = 0; 1674 break; 1675 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: 1676 mpt_lprt(mpt, MPT_PRT_DEBUG, 1677 "Invalid Page Type %d Number %d Addr 0x%0x\n", 1678 MPI_CONFIG_PAGETYPE_EXTENDED, PageNumber, PageAddress); 1679 error = EINVAL; 1680 break; 1681 default: 1682 mpt_prt(mpt, "mpt_read_extcfg_header: Config Info Status %x\n", 1683 req->IOCStatus); 1684 error = EIO; 1685 break; 1686 } 1687 mpt_free_request(mpt, req); 1688 return (error); 1689} 1690 1691int 1692mpt_read_extcfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, 1693 CONFIG_EXTENDED_PAGE_HEADER *hdr, void *buf, size_t len, 1694 int sleep_ok, int timeout_ms) 1695{ 1696 request_t *req; 1697 cfgparms_t params; 1698 int error; 1699 1700 req = mpt_get_request(mpt, sleep_ok); 1701 if (req == NULL) { 1702 mpt_prt(mpt, "mpt_read_extcfg_page: Get request failed!\n"); 1703 return (-1); 1704 } 1705 1706 params.Action = Action; 1707 params.PageVersion = hdr->PageVersion; 1708 params.PageLength = 0; 1709 params.PageNumber = hdr->PageNumber; 1710 params.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 1711 params.PageAddress = PageAddress; 1712 params.ExtPageType = hdr->ExtPageType; 1713 params.ExtPageLength = hdr->ExtPageLength; 1714 error = mpt_issue_cfg_req(mpt, req, ¶ms, 1715 req->req_pbuf + MPT_RQSL(mpt), 1716 len, sleep_ok, timeout_ms); 1717 if (error != 0) { 1718 mpt_prt(mpt, "read_extcfg_page(%d) timed out\n", Action); 1719 return (-1); 1720 } 1721 1722 if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 1723 mpt_prt(mpt, "mpt_read_extcfg_page: Config Info Status %x\n", 1724 req->IOCStatus); 1725 mpt_free_request(mpt, req); 1726 return (-1); 1727 } 1728 memcpy(buf, ((uint8_t *)req->req_vbuf)+MPT_RQSL(mpt), len); 1729 mpt_free_request(mpt, req); 1730 return (0); 1731} 1732 1733int 1734mpt_read_cfg_header(struct mpt_softc *mpt, int PageType, int PageNumber, 1735 uint32_t PageAddress, CONFIG_PAGE_HEADER *rslt, 1736 int sleep_ok, int timeout_ms) 1737{ 1738 request_t *req; 1739 cfgparms_t params; 1740 MSG_CONFIG *cfgp; 1741 int error; 1742 1743 req = mpt_get_request(mpt, sleep_ok); 1744 if (req == NULL) { 1745 mpt_prt(mpt, "mpt_read_cfg_header: Get request failed!\n"); 1746 return (ENOMEM); 1747 } 1748 1749 params.Action = MPI_CONFIG_ACTION_PAGE_HEADER; 1750 params.PageVersion = 0; 1751 params.PageLength = 0; 1752 params.PageNumber = PageNumber; 1753 params.PageType = PageType; 1754 params.PageAddress = PageAddress; 1755 error = mpt_issue_cfg_req(mpt, req, ¶ms, /*addr*/0, /*len*/0, 1756 sleep_ok, timeout_ms); 1757 if (error != 0) { 1758 /* 1759 * Leave the request. Without resetting the chip, it's 1760 * still owned by it and we'll just get into trouble 1761 * freeing it now. Mark it as abandoned so that if it 1762 * shows up later it can be freed. 1763 */ 1764 mpt_prt(mpt, "read_cfg_header timed out\n"); 1765 return (ETIMEDOUT); 1766 } 1767 1768 switch (req->IOCStatus & MPI_IOCSTATUS_MASK) { 1769 case MPI_IOCSTATUS_SUCCESS: 1770 cfgp = req->req_vbuf; 1771 bcopy(&cfgp->Header, rslt, sizeof(*rslt)); 1772 error = 0; 1773 break; 1774 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: 1775 mpt_lprt(mpt, MPT_PRT_DEBUG, 1776 "Invalid Page Type %d Number %d Addr 0x%0x\n", 1777 PageType, PageNumber, PageAddress); 1778 error = EINVAL; 1779 break; 1780 default: 1781 mpt_prt(mpt, "mpt_read_cfg_header: Config Info Status %x\n", 1782 req->IOCStatus); 1783 error = EIO; 1784 break; 1785 } 1786 mpt_free_request(mpt, req); 1787 return (error); 1788} 1789 1790int 1791mpt_read_cfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, 1792 CONFIG_PAGE_HEADER *hdr, size_t len, int sleep_ok, 1793 int timeout_ms) 1794{ 1795 request_t *req; 1796 cfgparms_t params; 1797 int error; 1798 1799 req = mpt_get_request(mpt, sleep_ok); 1800 if (req == NULL) { 1801 mpt_prt(mpt, "mpt_read_cfg_page: Get request failed!\n"); 1802 return (-1); 1803 } 1804 1805 params.Action = Action; 1806 params.PageVersion = hdr->PageVersion; 1807 params.PageLength = hdr->PageLength; 1808 params.PageNumber = hdr->PageNumber; 1809 params.PageType = hdr->PageType & MPI_CONFIG_PAGETYPE_MASK; 1810 params.PageAddress = PageAddress; 1811 error = mpt_issue_cfg_req(mpt, req, ¶ms, 1812 req->req_pbuf + MPT_RQSL(mpt), 1813 len, sleep_ok, timeout_ms); 1814 if (error != 0) { 1815 mpt_prt(mpt, "read_cfg_page(%d) timed out\n", Action); 1816 return (-1); 1817 } 1818 1819 if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 1820 mpt_prt(mpt, "mpt_read_cfg_page: Config Info Status %x\n", 1821 req->IOCStatus); 1822 mpt_free_request(mpt, req); 1823 return (-1); 1824 } 1825 memcpy(hdr, ((uint8_t *)req->req_vbuf)+MPT_RQSL(mpt), len); 1826 mpt_free_request(mpt, req); 1827 return (0); 1828} 1829 1830int 1831mpt_write_cfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, 1832 CONFIG_PAGE_HEADER *hdr, size_t len, int sleep_ok, 1833 int timeout_ms) 1834{ 1835 request_t *req; 1836 cfgparms_t params; 1837 u_int hdr_attr; 1838 int error; 1839 1840 hdr_attr = hdr->PageType & MPI_CONFIG_PAGEATTR_MASK; 1841 if (hdr_attr != MPI_CONFIG_PAGEATTR_CHANGEABLE && 1842 hdr_attr != MPI_CONFIG_PAGEATTR_PERSISTENT) { 1843 mpt_prt(mpt, "page type 0x%x not changeable\n", 1844 hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); 1845 return (-1); 1846 } 1847 1848#if 0 1849 /* 1850 * We shouldn't mask off other bits here. 1851 */ 1852 hdr->PageType &= MPI_CONFIG_PAGETYPE_MASK; 1853#endif 1854 1855 req = mpt_get_request(mpt, sleep_ok); 1856 if (req == NULL) 1857 return (-1); 1858 1859 memcpy(((caddr_t)req->req_vbuf) + MPT_RQSL(mpt), hdr, len); 1860 1861 /* 1862 * There isn't any point in restoring stripped out attributes 1863 * if you then mask them going down to issue the request. 1864 */ 1865 1866 params.Action = Action; 1867 params.PageVersion = hdr->PageVersion; 1868 params.PageLength = hdr->PageLength; 1869 params.PageNumber = hdr->PageNumber; 1870 params.PageAddress = PageAddress; 1871#if 0 1872 /* Restore stripped out attributes */ 1873 hdr->PageType |= hdr_attr; 1874 params.PageType = hdr->PageType & MPI_CONFIG_PAGETYPE_MASK; 1875#else 1876 params.PageType = hdr->PageType; 1877#endif 1878 error = mpt_issue_cfg_req(mpt, req, ¶ms, 1879 req->req_pbuf + MPT_RQSL(mpt), 1880 len, sleep_ok, timeout_ms); 1881 if (error != 0) { 1882 mpt_prt(mpt, "mpt_write_cfg_page timed out\n"); 1883 return (-1); 1884 } 1885 1886 if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 1887 mpt_prt(mpt, "mpt_write_cfg_page: Config Info Status %x\n", 1888 req->IOCStatus); 1889 mpt_free_request(mpt, req); 1890 return (-1); 1891 } 1892 mpt_free_request(mpt, req); 1893 return (0); 1894} 1895 1896/* 1897 * Read IOC configuration information 1898 */ 1899static int 1900mpt_read_config_info_ioc(struct mpt_softc *mpt) 1901{ 1902 CONFIG_PAGE_HEADER hdr; 1903 struct mpt_raid_volume *mpt_raid; 1904 int rv; 1905 int i; 1906 size_t len; 1907 1908 rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_IOC, 1909 2, 0, &hdr, FALSE, 5000); 1910 /* 1911 * If it's an invalid page, so what? Not a supported function.... 1912 */ 1913 if (rv == EINVAL) { 1914 return (0); 1915 } 1916 if (rv) { 1917 return (rv); 1918 } 1919 1920 mpt_lprt(mpt, MPT_PRT_DEBUG, 1921 "IOC Page 2 Header: Version %x len %x PageNumber %x PageType %x\n", 1922 hdr.PageVersion, hdr.PageLength << 2, 1923 hdr.PageNumber, hdr.PageType); 1924 1925 len = hdr.PageLength * sizeof(uint32_t); 1926 mpt->ioc_page2 = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 1927 if (mpt->ioc_page2 == NULL) { 1928 mpt_prt(mpt, "unable to allocate memory for IOC page 2\n"); 1929 mpt_raid_free_mem(mpt); 1930 return (ENOMEM); 1931 } 1932 memcpy(&mpt->ioc_page2->Header, &hdr, sizeof(hdr)); 1933 rv = mpt_read_cur_cfg_page(mpt, 0, 1934 &mpt->ioc_page2->Header, len, FALSE, 5000); 1935 if (rv) { 1936 mpt_prt(mpt, "failed to read IOC Page 2\n"); 1937 mpt_raid_free_mem(mpt); 1938 return (EIO); 1939 } 1940 mpt2host_config_page_ioc2(mpt->ioc_page2); 1941 1942 if (mpt->ioc_page2->CapabilitiesFlags != 0) { 1943 uint32_t mask; 1944 1945 mpt_prt(mpt, "Capabilities: ("); 1946 for (mask = 1; mask != 0; mask <<= 1) { 1947 if ((mpt->ioc_page2->CapabilitiesFlags & mask) == 0) { 1948 continue; 1949 } 1950 switch (mask) { 1951 case MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT: 1952 mpt_prtc(mpt, " RAID-0"); 1953 break; 1954 case MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT: 1955 mpt_prtc(mpt, " RAID-1E"); 1956 break; 1957 case MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT: 1958 mpt_prtc(mpt, " RAID-1"); 1959 break; 1960 case MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT: 1961 mpt_prtc(mpt, " SES"); 1962 break; 1963 case MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT: 1964 mpt_prtc(mpt, " SAFTE"); 1965 break; 1966 case MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT: 1967 mpt_prtc(mpt, " Multi-Channel-Arrays"); 1968 default: 1969 break; 1970 } 1971 } 1972 mpt_prtc(mpt, " )\n"); 1973 if ((mpt->ioc_page2->CapabilitiesFlags 1974 & (MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT 1975 | MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT 1976 | MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT)) != 0) { 1977 mpt_prt(mpt, "%d Active Volume%s(%d Max)\n", 1978 mpt->ioc_page2->NumActiveVolumes, 1979 mpt->ioc_page2->NumActiveVolumes != 1 1980 ? "s " : " ", 1981 mpt->ioc_page2->MaxVolumes); 1982 mpt_prt(mpt, "%d Hidden Drive Member%s(%d Max)\n", 1983 mpt->ioc_page2->NumActivePhysDisks, 1984 mpt->ioc_page2->NumActivePhysDisks != 1 1985 ? "s " : " ", 1986 mpt->ioc_page2->MaxPhysDisks); 1987 } 1988 } 1989 1990 len = mpt->ioc_page2->MaxVolumes * sizeof(struct mpt_raid_volume); 1991 mpt->raid_volumes = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 1992 if (mpt->raid_volumes == NULL) { 1993 mpt_prt(mpt, "Could not allocate RAID volume data\n"); 1994 mpt_raid_free_mem(mpt); 1995 return (ENOMEM); 1996 } 1997 1998 /* 1999 * Copy critical data out of ioc_page2 so that we can 2000 * safely refresh the page without windows of unreliable 2001 * data. 2002 */ 2003 mpt->raid_max_volumes = mpt->ioc_page2->MaxVolumes; 2004 2005 len = sizeof(*mpt->raid_volumes->config_page) + 2006 (sizeof (RAID_VOL0_PHYS_DISK) * (mpt->ioc_page2->MaxPhysDisks - 1)); 2007 for (i = 0; i < mpt->ioc_page2->MaxVolumes; i++) { 2008 mpt_raid = &mpt->raid_volumes[i]; 2009 mpt_raid->config_page = 2010 malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 2011 if (mpt_raid->config_page == NULL) { 2012 mpt_prt(mpt, "Could not allocate RAID page data\n"); 2013 mpt_raid_free_mem(mpt); 2014 return (ENOMEM); 2015 } 2016 } 2017 mpt->raid_page0_len = len; 2018 2019 len = mpt->ioc_page2->MaxPhysDisks * sizeof(struct mpt_raid_disk); 2020 mpt->raid_disks = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 2021 if (mpt->raid_disks == NULL) { 2022 mpt_prt(mpt, "Could not allocate RAID disk data\n"); 2023 mpt_raid_free_mem(mpt); 2024 return (ENOMEM); 2025 } 2026 mpt->raid_max_disks = mpt->ioc_page2->MaxPhysDisks; 2027 2028 /* 2029 * Load page 3. 2030 */ 2031 rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_IOC, 2032 3, 0, &hdr, FALSE, 5000); 2033 if (rv) { 2034 mpt_raid_free_mem(mpt); 2035 return (EIO); 2036 } 2037 2038 mpt_lprt(mpt, MPT_PRT_DEBUG, "IOC Page 3 Header: %x %x %x %x\n", 2039 hdr.PageVersion, hdr.PageLength, hdr.PageNumber, hdr.PageType); 2040 2041 len = hdr.PageLength * sizeof(uint32_t); 2042 mpt->ioc_page3 = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 2043 if (mpt->ioc_page3 == NULL) { 2044 mpt_prt(mpt, "unable to allocate memory for IOC page 3\n"); 2045 mpt_raid_free_mem(mpt); 2046 return (ENOMEM); 2047 } 2048 memcpy(&mpt->ioc_page3->Header, &hdr, sizeof(hdr)); 2049 rv = mpt_read_cur_cfg_page(mpt, 0, 2050 &mpt->ioc_page3->Header, len, FALSE, 5000); 2051 if (rv) { 2052 mpt_raid_free_mem(mpt); 2053 return (EIO); 2054 } 2055 mpt2host_config_page_ioc3(mpt->ioc_page3); 2056 mpt_raid_wakeup(mpt); 2057 return (0); 2058} 2059 2060/* 2061 * Enable IOC port 2062 */ 2063static int 2064mpt_send_port_enable(struct mpt_softc *mpt, int port) 2065{ 2066 request_t *req; 2067 MSG_PORT_ENABLE *enable_req; 2068 int error; 2069 2070 req = mpt_get_request(mpt, /*sleep_ok*/FALSE); 2071 if (req == NULL) 2072 return (-1); 2073 2074 enable_req = req->req_vbuf; 2075 memset(enable_req, 0, MPT_RQSL(mpt)); 2076 2077 enable_req->Function = MPI_FUNCTION_PORT_ENABLE; 2078 enable_req->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_CONFIG); 2079 enable_req->PortNumber = port; 2080 2081 mpt_check_doorbell(mpt); 2082 mpt_lprt(mpt, MPT_PRT_DEBUG, "enabling port %d\n", port); 2083 2084 mpt_send_cmd(mpt, req); 2085 error = mpt_wait_req(mpt, req, REQ_STATE_DONE, REQ_STATE_DONE, 2086 FALSE, (mpt->is_sas || mpt->is_fc)? 300000 : 30000); 2087 if (error != 0) { 2088 mpt_prt(mpt, "port %d enable timed out\n", port); 2089 return (-1); 2090 } 2091 mpt_free_request(mpt, req); 2092 mpt_lprt(mpt, MPT_PRT_DEBUG, "enabled port %d\n", port); 2093 return (0); 2094} 2095 2096/* 2097 * Enable/Disable asynchronous event reporting. 2098 */ 2099static int 2100mpt_send_event_request(struct mpt_softc *mpt, int onoff) 2101{ 2102 request_t *req; 2103 MSG_EVENT_NOTIFY *enable_req; 2104 2105 req = mpt_get_request(mpt, FALSE); 2106 if (req == NULL) { 2107 return (ENOMEM); 2108 } 2109 enable_req = req->req_vbuf; 2110 memset(enable_req, 0, sizeof *enable_req); 2111 2112 enable_req->Function = MPI_FUNCTION_EVENT_NOTIFICATION; 2113 enable_req->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_EVENTS); 2114 enable_req->Switch = onoff; 2115 2116 mpt_check_doorbell(mpt); 2117 mpt_lprt(mpt, MPT_PRT_DEBUG, "%sabling async events\n", 2118 onoff ? "en" : "dis"); 2119 /* 2120 * Send the command off, but don't wait for it. 2121 */ 2122 mpt_send_cmd(mpt, req); 2123 return (0); 2124} 2125 2126/* 2127 * Un-mask the interrupts on the chip. 2128 */ 2129void 2130mpt_enable_ints(struct mpt_softc *mpt) 2131{ 2132 2133 /* Unmask every thing except door bell int */ 2134 mpt_write(mpt, MPT_OFFSET_INTR_MASK, MPT_INTR_DB_MASK); 2135} 2136 2137/* 2138 * Mask the interrupts on the chip. 2139 */ 2140void 2141mpt_disable_ints(struct mpt_softc *mpt) 2142{ 2143 2144 /* Mask all interrupts */ 2145 mpt_write(mpt, MPT_OFFSET_INTR_MASK, 2146 MPT_INTR_REPLY_MASK | MPT_INTR_DB_MASK); 2147} 2148 2149static void 2150mpt_sysctl_attach(struct mpt_softc *mpt) 2151{ 2152 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(mpt->dev); 2153 struct sysctl_oid *tree = device_get_sysctl_tree(mpt->dev); 2154 2155 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2156 "debug", CTLFLAG_RW, &mpt->verbose, 0, 2157 "Debugging/Verbose level"); 2158 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2159 "role", CTLFLAG_RD, &mpt->role, 0, 2160 "HBA role"); 2161#ifdef MPT_TEST_MULTIPATH 2162 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2163 "failure_id", CTLFLAG_RW, &mpt->failure_id, -1, 2164 "Next Target to Fail"); 2165#endif 2166} 2167 2168int 2169mpt_attach(struct mpt_softc *mpt) 2170{ 2171 struct mpt_personality *pers; 2172 int i; 2173 int error; 2174 2175 mpt_core_attach(mpt); 2176 mpt_core_enable(mpt); 2177 2178 TAILQ_INSERT_TAIL(&mpt_tailq, mpt, links); 2179 for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { 2180 pers = mpt_personalities[i]; 2181 if (pers == NULL) { 2182 continue; 2183 } 2184 if (pers->probe(mpt) == 0) { 2185 error = pers->attach(mpt); 2186 if (error != 0) { 2187 mpt_detach(mpt); 2188 return (error); 2189 } 2190 mpt->mpt_pers_mask |= (0x1 << pers->id); 2191 pers->use_count++; 2192 } 2193 } 2194 2195 /* 2196 * Now that we've attached everything, do the enable function 2197 * for all of the personalities. This allows the personalities 2198 * to do setups that are appropriate for them prior to enabling 2199 * any ports. 2200 */ 2201 for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { 2202 pers = mpt_personalities[i]; 2203 if (pers != NULL && MPT_PERS_ATTACHED(pers, mpt) != 0) { 2204 error = pers->enable(mpt); 2205 if (error != 0) { 2206 mpt_prt(mpt, "personality %s attached but would" 2207 " not enable (%d)\n", pers->name, error); 2208 mpt_detach(mpt); 2209 return (error); 2210 } 2211 } 2212 } 2213 return (0); 2214} 2215 2216int 2217mpt_shutdown(struct mpt_softc *mpt) 2218{ 2219 struct mpt_personality *pers; 2220 2221 MPT_PERS_FOREACH_REVERSE(mpt, pers) { 2222 pers->shutdown(mpt); 2223 } 2224 return (0); 2225} 2226 2227int 2228mpt_detach(struct mpt_softc *mpt) 2229{ 2230 struct mpt_personality *pers; 2231 2232 MPT_PERS_FOREACH_REVERSE(mpt, pers) { 2233 pers->detach(mpt); 2234 mpt->mpt_pers_mask &= ~(0x1 << pers->id); 2235 pers->use_count--; 2236 } 2237 TAILQ_REMOVE(&mpt_tailq, mpt, links); 2238 return (0); 2239} 2240 2241static int 2242mpt_core_load(struct mpt_personality *pers) 2243{ 2244 int i; 2245 2246 /* 2247 * Setup core handlers and insert the default handler 2248 * into all "empty slots". 2249 */ 2250 for (i = 0; i < MPT_NUM_REPLY_HANDLERS; i++) { 2251 mpt_reply_handlers[i] = mpt_default_reply_handler; 2252 } 2253 2254 mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_EVENTS)] = 2255 mpt_event_reply_handler; 2256 mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_CONFIG)] = 2257 mpt_config_reply_handler; 2258 mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_HANDSHAKE)] = 2259 mpt_handshake_reply_handler; 2260 return (0); 2261} 2262 2263/* 2264 * Initialize per-instance driver data and perform 2265 * initial controller configuration. 2266 */ 2267static int 2268mpt_core_attach(struct mpt_softc *mpt) 2269{ 2270 int val, error; 2271 2272 LIST_INIT(&mpt->ack_frames); 2273 /* Put all request buffers on the free list */ 2274 TAILQ_INIT(&mpt->request_pending_list); 2275 TAILQ_INIT(&mpt->request_free_list); 2276 TAILQ_INIT(&mpt->request_timeout_list); 2277 for (val = 0; val < MPT_MAX_LUNS; val++) { 2278 STAILQ_INIT(&mpt->trt[val].atios); 2279 STAILQ_INIT(&mpt->trt[val].inots); 2280 } 2281 STAILQ_INIT(&mpt->trt_wildcard.atios); 2282 STAILQ_INIT(&mpt->trt_wildcard.inots); 2283#ifdef MPT_TEST_MULTIPATH 2284 mpt->failure_id = -1; 2285#endif 2286 mpt->scsi_tgt_handler_id = MPT_HANDLER_ID_NONE; 2287 mpt_sysctl_attach(mpt); 2288 mpt_lprt(mpt, MPT_PRT_DEBUG, "doorbell req = %s\n", 2289 mpt_ioc_diag(mpt_read(mpt, MPT_OFFSET_DOORBELL))); 2290 2291 MPT_LOCK(mpt); 2292 error = mpt_configure_ioc(mpt, 0, 0); 2293 MPT_UNLOCK(mpt); 2294 2295 return (error); 2296} 2297 2298static int 2299mpt_core_enable(struct mpt_softc *mpt) 2300{ 2301 2302 /* 2303 * We enter with the IOC enabled, but async events 2304 * not enabled, ports not enabled and interrupts 2305 * not enabled. 2306 */ 2307 MPT_LOCK(mpt); 2308 2309 /* 2310 * Enable asynchronous event reporting- all personalities 2311 * have attached so that they should be able to now field 2312 * async events. 2313 */ 2314 mpt_send_event_request(mpt, 1); 2315 2316 /* 2317 * Catch any pending interrupts 2318 * 2319 * This seems to be crucial- otherwise 2320 * the portenable below times out. 2321 */ 2322 mpt_intr(mpt); 2323 2324 /* 2325 * Enable Interrupts 2326 */ 2327 mpt_enable_ints(mpt); 2328 2329 /* 2330 * Catch any pending interrupts 2331 * 2332 * This seems to be crucial- otherwise 2333 * the portenable below times out. 2334 */ 2335 mpt_intr(mpt); 2336 2337 /* 2338 * Enable the port. 2339 */ 2340 if (mpt_send_port_enable(mpt, 0) != MPT_OK) { 2341 mpt_prt(mpt, "failed to enable port 0\n"); 2342 MPT_UNLOCK(mpt); 2343 return (ENXIO); 2344 } 2345 MPT_UNLOCK(mpt); 2346 return (0); 2347} 2348 2349static void 2350mpt_core_shutdown(struct mpt_softc *mpt) 2351{ 2352 2353 mpt_disable_ints(mpt); 2354} 2355 2356static void 2357mpt_core_detach(struct mpt_softc *mpt) 2358{ 2359 int val; 2360 2361 /* 2362 * XXX: FREE MEMORY 2363 */ 2364 mpt_disable_ints(mpt); 2365 2366 /* Make sure no request has pending timeouts. */ 2367 for (val = 0; val < MPT_MAX_REQUESTS(mpt); val++) { 2368 request_t *req = &mpt->request_pool[val]; 2369 mpt_callout_drain(mpt, &req->callout); 2370 } 2371 2372 mpt_dma_buf_free(mpt); 2373} 2374 2375static int 2376mpt_core_unload(struct mpt_personality *pers) 2377{ 2378 2379 /* Unload is always successful. */ 2380 return (0); 2381} 2382 2383#define FW_UPLOAD_REQ_SIZE \ 2384 (sizeof(MSG_FW_UPLOAD) - sizeof(SGE_MPI_UNION) \ 2385 + sizeof(FW_UPLOAD_TCSGE) + sizeof(SGE_SIMPLE32)) 2386 2387static int 2388mpt_upload_fw(struct mpt_softc *mpt) 2389{ 2390 uint8_t fw_req_buf[FW_UPLOAD_REQ_SIZE]; 2391 MSG_FW_UPLOAD_REPLY fw_reply; 2392 MSG_FW_UPLOAD *fw_req; 2393 FW_UPLOAD_TCSGE *tsge; 2394 SGE_SIMPLE32 *sge; 2395 uint32_t flags; 2396 int error; 2397 2398 memset(&fw_req_buf, 0, sizeof(fw_req_buf)); 2399 fw_req = (MSG_FW_UPLOAD *)fw_req_buf; 2400 fw_req->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM; 2401 fw_req->Function = MPI_FUNCTION_FW_UPLOAD; 2402 fw_req->MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); 2403 tsge = (FW_UPLOAD_TCSGE *)&fw_req->SGL; 2404 tsge->DetailsLength = 12; 2405 tsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT; 2406 tsge->ImageSize = htole32(mpt->fw_image_size); 2407 sge = (SGE_SIMPLE32 *)(tsge + 1); 2408 flags = (MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER 2409 | MPI_SGE_FLAGS_END_OF_LIST | MPI_SGE_FLAGS_SIMPLE_ELEMENT 2410 | MPI_SGE_FLAGS_32_BIT_ADDRESSING | MPI_SGE_FLAGS_IOC_TO_HOST); 2411 flags <<= MPI_SGE_FLAGS_SHIFT; 2412 sge->FlagsLength = htole32(flags | mpt->fw_image_size); 2413 sge->Address = htole32(mpt->fw_phys); 2414 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_PREREAD); 2415 error = mpt_send_handshake_cmd(mpt, sizeof(fw_req_buf), &fw_req_buf); 2416 if (error) 2417 return(error); 2418 error = mpt_recv_handshake_reply(mpt, sizeof(fw_reply), &fw_reply); 2419 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_POSTREAD); 2420 return (error); 2421} 2422 2423static void 2424mpt_diag_outsl(struct mpt_softc *mpt, uint32_t addr, 2425 uint32_t *data, bus_size_t len) 2426{ 2427 uint32_t *data_end; 2428 2429 data_end = data + (roundup2(len, sizeof(uint32_t)) / 4); 2430 if (mpt->is_sas) { 2431 pci_enable_io(mpt->dev, SYS_RES_IOPORT); 2432 } 2433 mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, addr); 2434 while (data != data_end) { 2435 mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, *data); 2436 data++; 2437 } 2438 if (mpt->is_sas) { 2439 pci_disable_io(mpt->dev, SYS_RES_IOPORT); 2440 } 2441} 2442 2443static int 2444mpt_download_fw(struct mpt_softc *mpt) 2445{ 2446 MpiFwHeader_t *fw_hdr; 2447 int error; 2448 uint32_t ext_offset; 2449 uint32_t data; 2450 2451 if (mpt->pci_pio_reg == NULL) { 2452 mpt_prt(mpt, "No PIO resource!\n"); 2453 return (ENXIO); 2454 } 2455 2456 mpt_prt(mpt, "Downloading Firmware - Image Size %d\n", 2457 mpt->fw_image_size); 2458 2459 error = mpt_enable_diag_mode(mpt); 2460 if (error != 0) { 2461 mpt_prt(mpt, "Could not enter diagnostic mode!\n"); 2462 return (EIO); 2463 } 2464 2465 mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, 2466 MPI_DIAG_RW_ENABLE|MPI_DIAG_DISABLE_ARM); 2467 2468 fw_hdr = (MpiFwHeader_t *)mpt->fw_image; 2469 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_PREWRITE); 2470 mpt_diag_outsl(mpt, fw_hdr->LoadStartAddress, (uint32_t*)fw_hdr, 2471 fw_hdr->ImageSize); 2472 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_POSTWRITE); 2473 2474 ext_offset = fw_hdr->NextImageHeaderOffset; 2475 while (ext_offset != 0) { 2476 MpiExtImageHeader_t *ext; 2477 2478 ext = (MpiExtImageHeader_t *)((uintptr_t)fw_hdr + ext_offset); 2479 ext_offset = ext->NextImageHeaderOffset; 2480 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, 2481 BUS_DMASYNC_PREWRITE); 2482 mpt_diag_outsl(mpt, ext->LoadStartAddress, (uint32_t*)ext, 2483 ext->ImageSize); 2484 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, 2485 BUS_DMASYNC_POSTWRITE); 2486 } 2487 2488 if (mpt->is_sas) { 2489 pci_enable_io(mpt->dev, SYS_RES_IOPORT); 2490 } 2491 /* Setup the address to jump to on reset. */ 2492 mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, fw_hdr->IopResetRegAddr); 2493 mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, fw_hdr->IopResetVectorValue); 2494 2495 /* 2496 * The controller sets the "flash bad" status after attempting 2497 * to auto-boot from flash. Clear the status so that the controller 2498 * will continue the boot process with our newly installed firmware. 2499 */ 2500 mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, MPT_DIAG_MEM_CFG_BASE); 2501 data = mpt_pio_read(mpt, MPT_OFFSET_DIAG_DATA) | MPT_DIAG_MEM_CFG_BADFL; 2502 mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, MPT_DIAG_MEM_CFG_BASE); 2503 mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, data); 2504 2505 if (mpt->is_sas) { 2506 pci_disable_io(mpt->dev, SYS_RES_IOPORT); 2507 } 2508 2509 /* 2510 * Re-enable the processor and clear the boot halt flag. 2511 */ 2512 data = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); 2513 data &= ~(MPI_DIAG_PREVENT_IOC_BOOT|MPI_DIAG_DISABLE_ARM); 2514 mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, data); 2515 2516 mpt_disable_diag_mode(mpt); 2517 return (0); 2518} 2519 2520static int 2521mpt_dma_buf_alloc(struct mpt_softc *mpt) 2522{ 2523 struct mpt_map_info mi; 2524 uint8_t *vptr; 2525 uint32_t pptr, end; 2526 int i, error; 2527 2528 /* Create a child tag for data buffers */ 2529 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, 1, 2530 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 2531 NULL, NULL, (mpt->max_cam_seg_cnt - 1) * PAGE_SIZE, 2532 mpt->max_cam_seg_cnt, BUS_SPACE_MAXSIZE_32BIT, 0, 2533 &mpt->buffer_dmat) != 0) { 2534 mpt_prt(mpt, "cannot create a dma tag for data buffers\n"); 2535 return (1); 2536 } 2537 2538 /* Create a child tag for request buffers */ 2539 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0, 2540 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 2541 NULL, NULL, MPT_REQ_MEM_SIZE(mpt), 1, BUS_SPACE_MAXSIZE_32BIT, 0, 2542 &mpt->request_dmat) != 0) { 2543 mpt_prt(mpt, "cannot create a dma tag for requests\n"); 2544 return (1); 2545 } 2546 2547 /* Allocate some DMA accessible memory for requests */ 2548 if (bus_dmamem_alloc(mpt->request_dmat, (void **)&mpt->request, 2549 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &mpt->request_dmap) != 0) { 2550 mpt_prt(mpt, "cannot allocate %d bytes of request memory\n", 2551 MPT_REQ_MEM_SIZE(mpt)); 2552 return (1); 2553 } 2554 2555 mi.mpt = mpt; 2556 mi.error = 0; 2557 2558 /* Load and lock it into "bus space" */ 2559 bus_dmamap_load(mpt->request_dmat, mpt->request_dmap, mpt->request, 2560 MPT_REQ_MEM_SIZE(mpt), mpt_map_rquest, &mi, 0); 2561 2562 if (mi.error) { 2563 mpt_prt(mpt, "error %d loading dma map for DMA request queue\n", 2564 mi.error); 2565 return (1); 2566 } 2567 mpt->request_phys = mi.phys; 2568 2569 /* 2570 * Now create per-request dma maps 2571 */ 2572 i = 0; 2573 pptr = mpt->request_phys; 2574 vptr = mpt->request; 2575 end = pptr + MPT_REQ_MEM_SIZE(mpt); 2576 while(pptr < end) { 2577 request_t *req = &mpt->request_pool[i]; 2578 req->index = i++; 2579 2580 /* Store location of Request Data */ 2581 req->req_pbuf = pptr; 2582 req->req_vbuf = vptr; 2583 2584 pptr += MPT_REQUEST_AREA; 2585 vptr += MPT_REQUEST_AREA; 2586 2587 req->sense_pbuf = (pptr - MPT_SENSE_SIZE); 2588 req->sense_vbuf = (vptr - MPT_SENSE_SIZE); 2589 2590 error = bus_dmamap_create(mpt->buffer_dmat, 0, &req->dmap); 2591 if (error) { 2592 mpt_prt(mpt, "error %d creating per-cmd DMA maps\n", 2593 error); 2594 return (1); 2595 } 2596 } 2597 2598 return (0); 2599} 2600 2601static void 2602mpt_dma_buf_free(struct mpt_softc *mpt) 2603{ 2604 int i; 2605 2606 if (mpt->request_dmat == 0) { 2607 mpt_lprt(mpt, MPT_PRT_DEBUG, "already released dma memory\n"); 2608 return; 2609 } 2610 for (i = 0; i < MPT_MAX_REQUESTS(mpt); i++) { 2611 bus_dmamap_destroy(mpt->buffer_dmat, mpt->request_pool[i].dmap); 2612 } 2613 bus_dmamap_unload(mpt->request_dmat, mpt->request_dmap); 2614 bus_dmamem_free(mpt->request_dmat, mpt->request, mpt->request_dmap); 2615 bus_dma_tag_destroy(mpt->request_dmat); 2616 mpt->request_dmat = 0; 2617 bus_dma_tag_destroy(mpt->buffer_dmat); 2618} 2619 2620/* 2621 * Allocate/Initialize data structures for the controller. Called 2622 * once at instance startup. 2623 */ 2624static int 2625mpt_configure_ioc(struct mpt_softc *mpt, int tn, int needreset) 2626{ 2627 PTR_MSG_PORT_FACTS_REPLY pfp; 2628 int error, port, val; 2629 size_t len; 2630 2631 if (tn == MPT_MAX_TRYS) { 2632 return (-1); 2633 } 2634 2635 /* 2636 * No need to reset if the IOC is already in the READY state. 2637 * 2638 * Force reset if initialization failed previously. 2639 * Note that a hard_reset of the second channel of a '929 2640 * will stop operation of the first channel. Hopefully, if the 2641 * first channel is ok, the second will not require a hard 2642 * reset. 2643 */ 2644 if (needreset || MPT_STATE(mpt_rd_db(mpt)) != MPT_DB_STATE_READY) { 2645 if (mpt_reset(mpt, FALSE) != MPT_OK) { 2646 return (mpt_configure_ioc(mpt, tn++, 1)); 2647 } 2648 needreset = 0; 2649 } 2650 2651 if (mpt_get_iocfacts(mpt, &mpt->ioc_facts) != MPT_OK) { 2652 mpt_prt(mpt, "mpt_get_iocfacts failed\n"); 2653 return (mpt_configure_ioc(mpt, tn++, 1)); 2654 } 2655 mpt2host_iocfacts_reply(&mpt->ioc_facts); 2656 2657 mpt_prt(mpt, "MPI Version=%d.%d.%d.%d\n", 2658 mpt->ioc_facts.MsgVersion >> 8, 2659 mpt->ioc_facts.MsgVersion & 0xFF, 2660 mpt->ioc_facts.HeaderVersion >> 8, 2661 mpt->ioc_facts.HeaderVersion & 0xFF); 2662 2663 /* 2664 * Now that we know request frame size, we can calculate 2665 * the actual (reasonable) segment limit for read/write I/O. 2666 * 2667 * This limit is constrained by: 2668 * 2669 * + The size of each area we allocate per command (and how 2670 * many chain segments we can fit into it). 2671 * + The total number of areas we've set up. 2672 * + The actual chain depth the card will allow. 2673 * 2674 * The first area's segment count is limited by the I/O request 2675 * at the head of it. We cannot allocate realistically more 2676 * than MPT_MAX_REQUESTS areas. Therefore, to account for both 2677 * conditions, we'll just start out with MPT_MAX_REQUESTS-2. 2678 * 2679 */ 2680 /* total number of request areas we (can) allocate */ 2681 mpt->max_seg_cnt = MPT_MAX_REQUESTS(mpt) - 2; 2682 2683 /* converted to the number of chain areas possible */ 2684 mpt->max_seg_cnt *= MPT_NRFM(mpt); 2685 2686 /* limited by the number of chain areas the card will support */ 2687 if (mpt->max_seg_cnt > mpt->ioc_facts.MaxChainDepth) { 2688 mpt_lprt(mpt, MPT_PRT_INFO, 2689 "chain depth limited to %u (from %u)\n", 2690 mpt->ioc_facts.MaxChainDepth, mpt->max_seg_cnt); 2691 mpt->max_seg_cnt = mpt->ioc_facts.MaxChainDepth; 2692 } 2693 2694 /* converted to the number of simple sges in chain segments. */ 2695 mpt->max_seg_cnt *= (MPT_NSGL(mpt) - 1); 2696 2697 /* 2698 * Use this as the basis for reporting the maximum I/O size to CAM. 2699 */ 2700 mpt->max_cam_seg_cnt = min(mpt->max_seg_cnt, (MAXPHYS / PAGE_SIZE) + 1); 2701 2702 error = mpt_dma_buf_alloc(mpt); 2703 if (error != 0) { 2704 mpt_prt(mpt, "mpt_dma_buf_alloc() failed!\n"); 2705 return (EIO); 2706 } 2707 2708 for (val = 0; val < MPT_MAX_REQUESTS(mpt); val++) { 2709 request_t *req = &mpt->request_pool[val]; 2710 req->state = REQ_STATE_ALLOCATED; 2711 mpt_callout_init(mpt, &req->callout); 2712 mpt_free_request(mpt, req); 2713 } 2714 2715 mpt_lprt(mpt, MPT_PRT_INFO, "Maximum Segment Count: %u, Maximum " 2716 "CAM Segment Count: %u\n", mpt->max_seg_cnt, 2717 mpt->max_cam_seg_cnt); 2718 2719 mpt_lprt(mpt, MPT_PRT_INFO, "MsgLength=%u IOCNumber = %d\n", 2720 mpt->ioc_facts.MsgLength, mpt->ioc_facts.IOCNumber); 2721 mpt_lprt(mpt, MPT_PRT_INFO, 2722 "IOCFACTS: GlobalCredits=%d BlockSize=%u bytes " 2723 "Request Frame Size %u bytes Max Chain Depth %u\n", 2724 mpt->ioc_facts.GlobalCredits, mpt->ioc_facts.BlockSize, 2725 mpt->ioc_facts.RequestFrameSize << 2, 2726 mpt->ioc_facts.MaxChainDepth); 2727 mpt_lprt(mpt, MPT_PRT_INFO, "IOCFACTS: Num Ports %d, FWImageSize %d, " 2728 "Flags=%#x\n", mpt->ioc_facts.NumberOfPorts, 2729 mpt->ioc_facts.FWImageSize, mpt->ioc_facts.Flags); 2730 2731 len = mpt->ioc_facts.NumberOfPorts * sizeof (MSG_PORT_FACTS_REPLY); 2732 mpt->port_facts = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 2733 if (mpt->port_facts == NULL) { 2734 mpt_prt(mpt, "unable to allocate memory for port facts\n"); 2735 return (ENOMEM); 2736 } 2737 2738 2739 if ((mpt->ioc_facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) && 2740 (mpt->fw_uploaded == 0)) { 2741 struct mpt_map_info mi; 2742 2743 /* 2744 * In some configurations, the IOC's firmware is 2745 * stored in a shared piece of system NVRAM that 2746 * is only accessible via the BIOS. In this 2747 * case, the firmware keeps a copy of firmware in 2748 * RAM until the OS driver retrieves it. Once 2749 * retrieved, we are responsible for re-downloading 2750 * the firmware after any hard-reset. 2751 */ 2752 mpt->fw_image_size = mpt->ioc_facts.FWImageSize; 2753 error = mpt_dma_tag_create(mpt, mpt->parent_dmat, 1, 0, 2754 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2755 mpt->fw_image_size, 1, mpt->fw_image_size, 0, 2756 &mpt->fw_dmat); 2757 if (error != 0) { 2758 mpt_prt(mpt, "cannot create firmware dma tag\n"); 2759 return (ENOMEM); 2760 } 2761 error = bus_dmamem_alloc(mpt->fw_dmat, 2762 (void **)&mpt->fw_image, BUS_DMA_NOWAIT | 2763 BUS_DMA_COHERENT, &mpt->fw_dmap); 2764 if (error != 0) { 2765 mpt_prt(mpt, "cannot allocate firmware memory\n"); 2766 bus_dma_tag_destroy(mpt->fw_dmat); 2767 return (ENOMEM); 2768 } 2769 mi.mpt = mpt; 2770 mi.error = 0; 2771 bus_dmamap_load(mpt->fw_dmat, mpt->fw_dmap, 2772 mpt->fw_image, mpt->fw_image_size, mpt_map_rquest, &mi, 0); 2773 mpt->fw_phys = mi.phys; 2774 2775 error = mpt_upload_fw(mpt); 2776 if (error != 0) { 2777 mpt_prt(mpt, "firmware upload failed.\n"); 2778 bus_dmamap_unload(mpt->fw_dmat, mpt->fw_dmap); 2779 bus_dmamem_free(mpt->fw_dmat, mpt->fw_image, 2780 mpt->fw_dmap); 2781 bus_dma_tag_destroy(mpt->fw_dmat); 2782 mpt->fw_image = NULL; 2783 return (EIO); 2784 } 2785 mpt->fw_uploaded = 1; 2786 } 2787 2788 for (port = 0; port < mpt->ioc_facts.NumberOfPorts; port++) { 2789 pfp = &mpt->port_facts[port]; 2790 error = mpt_get_portfacts(mpt, 0, pfp); 2791 if (error != MPT_OK) { 2792 mpt_prt(mpt, 2793 "mpt_get_portfacts on port %d failed\n", port); 2794 free(mpt->port_facts, M_DEVBUF); 2795 mpt->port_facts = NULL; 2796 return (mpt_configure_ioc(mpt, tn++, 1)); 2797 } 2798 mpt2host_portfacts_reply(pfp); 2799 2800 if (port > 0) { 2801 error = MPT_PRT_INFO; 2802 } else { 2803 error = MPT_PRT_DEBUG; 2804 } 2805 mpt_lprt(mpt, error, 2806 "PORTFACTS[%d]: Type %x PFlags %x IID %d MaxDev %d\n", 2807 port, pfp->PortType, pfp->ProtocolFlags, pfp->PortSCSIID, 2808 pfp->MaxDevices); 2809 2810 } 2811 2812 /* 2813 * XXX: Not yet supporting more than port 0 2814 */ 2815 pfp = &mpt->port_facts[0]; 2816 if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_FC) { 2817 mpt->is_fc = 1; 2818 mpt->is_sas = 0; 2819 mpt->is_spi = 0; 2820 } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_SAS) { 2821 mpt->is_fc = 0; 2822 mpt->is_sas = 1; 2823 mpt->is_spi = 0; 2824 } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_SCSI) { 2825 mpt->is_fc = 0; 2826 mpt->is_sas = 0; 2827 mpt->is_spi = 1; 2828 if (mpt->mpt_ini_id == MPT_INI_ID_NONE) 2829 mpt->mpt_ini_id = pfp->PortSCSIID; 2830 } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_ISCSI) { 2831 mpt_prt(mpt, "iSCSI not supported yet\n"); 2832 return (ENXIO); 2833 } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_INACTIVE) { 2834 mpt_prt(mpt, "Inactive Port\n"); 2835 return (ENXIO); 2836 } else { 2837 mpt_prt(mpt, "unknown Port Type %#x\n", pfp->PortType); 2838 return (ENXIO); 2839 } 2840 2841 /* 2842 * Set our role with what this port supports. 2843 * 2844 * Note this might be changed later in different modules 2845 * if this is different from what is wanted. 2846 */ 2847 mpt->role = MPT_ROLE_NONE; 2848 if (pfp->ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) { 2849 mpt->role |= MPT_ROLE_INITIATOR; 2850 } 2851 if (pfp->ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2852 mpt->role |= MPT_ROLE_TARGET; 2853 } 2854 2855 /* 2856 * Enable the IOC 2857 */ 2858 if (mpt_enable_ioc(mpt, 1) != MPT_OK) { 2859 mpt_prt(mpt, "unable to initialize IOC\n"); 2860 return (ENXIO); 2861 } 2862 2863 /* 2864 * Read IOC configuration information. 2865 * 2866 * We need this to determine whether or not we have certain 2867 * settings for Integrated Mirroring (e.g.). 2868 */ 2869 mpt_read_config_info_ioc(mpt); 2870 2871 return (0); 2872} 2873 2874static int 2875mpt_enable_ioc(struct mpt_softc *mpt, int portenable) 2876{ 2877 uint32_t pptr; 2878 int val; 2879 2880 if (mpt_send_ioc_init(mpt, MPI_WHOINIT_HOST_DRIVER) != MPT_OK) { 2881 mpt_prt(mpt, "mpt_send_ioc_init failed\n"); 2882 return (EIO); 2883 } 2884 2885 mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_send_ioc_init ok\n"); 2886 2887 if (mpt_wait_state(mpt, MPT_DB_STATE_RUNNING) != MPT_OK) { 2888 mpt_prt(mpt, "IOC failed to go to run state\n"); 2889 return (ENXIO); 2890 } 2891 mpt_lprt(mpt, MPT_PRT_DEBUG, "IOC now at RUNSTATE\n"); 2892 2893 /* 2894 * Give it reply buffers 2895 * 2896 * Do *not* exceed global credits. 2897 */ 2898 for (val = 0, pptr = mpt->reply_phys; 2899 (pptr + MPT_REPLY_SIZE) < (mpt->reply_phys + PAGE_SIZE); 2900 pptr += MPT_REPLY_SIZE) { 2901 mpt_free_reply(mpt, pptr); 2902 if (++val == mpt->ioc_facts.GlobalCredits - 1) 2903 break; 2904 } 2905 2906 2907 /* 2908 * Enable the port if asked. This is only done if we're resetting 2909 * the IOC after initial startup. 2910 */ 2911 if (portenable) { 2912 /* 2913 * Enable asynchronous event reporting 2914 */ 2915 mpt_send_event_request(mpt, 1); 2916 2917 if (mpt_send_port_enable(mpt, 0) != MPT_OK) { 2918 mpt_prt(mpt, "%s: failed to enable port 0\n", __func__); 2919 return (ENXIO); 2920 } 2921 } 2922 return (MPT_OK); 2923} 2924 2925/* 2926 * Endian Conversion Functions- only used on Big Endian machines 2927 */ 2928#if _BYTE_ORDER == _BIG_ENDIAN 2929void 2930mpt2host_sge_simple_union(SGE_SIMPLE_UNION *sge) 2931{ 2932 2933 MPT_2_HOST32(sge, FlagsLength); 2934 MPT_2_HOST32(sge, u.Address64.Low); 2935 MPT_2_HOST32(sge, u.Address64.High); 2936} 2937 2938void 2939mpt2host_iocfacts_reply(MSG_IOC_FACTS_REPLY *rp) 2940{ 2941 2942 MPT_2_HOST16(rp, MsgVersion); 2943 MPT_2_HOST16(rp, HeaderVersion); 2944 MPT_2_HOST32(rp, MsgContext); 2945 MPT_2_HOST16(rp, IOCExceptions); 2946 MPT_2_HOST16(rp, IOCStatus); 2947 MPT_2_HOST32(rp, IOCLogInfo); 2948 MPT_2_HOST16(rp, ReplyQueueDepth); 2949 MPT_2_HOST16(rp, RequestFrameSize); 2950 MPT_2_HOST16(rp, Reserved_0101_FWVersion); 2951 MPT_2_HOST16(rp, ProductID); 2952 MPT_2_HOST32(rp, CurrentHostMfaHighAddr); 2953 MPT_2_HOST16(rp, GlobalCredits); 2954 MPT_2_HOST32(rp, CurrentSenseBufferHighAddr); 2955 MPT_2_HOST16(rp, CurReplyFrameSize); 2956 MPT_2_HOST32(rp, FWImageSize); 2957 MPT_2_HOST32(rp, IOCCapabilities); 2958 MPT_2_HOST32(rp, FWVersion.Word); 2959 MPT_2_HOST16(rp, HighPriorityQueueDepth); 2960 MPT_2_HOST16(rp, Reserved2); 2961 mpt2host_sge_simple_union(&rp->HostPageBufferSGE); 2962 MPT_2_HOST32(rp, ReplyFifoHostSignalingAddr); 2963} 2964 2965void 2966mpt2host_portfacts_reply(MSG_PORT_FACTS_REPLY *pfp) 2967{ 2968 2969 MPT_2_HOST16(pfp, Reserved); 2970 MPT_2_HOST16(pfp, Reserved1); 2971 MPT_2_HOST32(pfp, MsgContext); 2972 MPT_2_HOST16(pfp, Reserved2); 2973 MPT_2_HOST16(pfp, IOCStatus); 2974 MPT_2_HOST32(pfp, IOCLogInfo); 2975 MPT_2_HOST16(pfp, MaxDevices); 2976 MPT_2_HOST16(pfp, PortSCSIID); 2977 MPT_2_HOST16(pfp, ProtocolFlags); 2978 MPT_2_HOST16(pfp, MaxPostedCmdBuffers); 2979 MPT_2_HOST16(pfp, MaxPersistentIDs); 2980 MPT_2_HOST16(pfp, MaxLanBuckets); 2981 MPT_2_HOST16(pfp, Reserved4); 2982 MPT_2_HOST32(pfp, Reserved5); 2983} 2984 2985void 2986mpt2host_config_page_ioc2(CONFIG_PAGE_IOC_2 *ioc2) 2987{ 2988 int i; 2989 2990 MPT_2_HOST32(ioc2, CapabilitiesFlags); 2991 for (i = 0; i < MPI_IOC_PAGE_2_RAID_VOLUME_MAX; i++) { 2992 MPT_2_HOST16(ioc2, RaidVolume[i].Reserved3); 2993 } 2994} 2995 2996void 2997mpt2host_config_page_ioc3(CONFIG_PAGE_IOC_3 *ioc3) 2998{ 2999 3000 MPT_2_HOST16(ioc3, Reserved2); 3001} 3002 3003void 3004mpt2host_config_page_scsi_port_0(CONFIG_PAGE_SCSI_PORT_0 *sp0) 3005{ 3006 3007 MPT_2_HOST32(sp0, Capabilities); 3008 MPT_2_HOST32(sp0, PhysicalInterface); 3009} 3010 3011void 3012mpt2host_config_page_scsi_port_1(CONFIG_PAGE_SCSI_PORT_1 *sp1) 3013{ 3014 3015 MPT_2_HOST32(sp1, Configuration); 3016 MPT_2_HOST32(sp1, OnBusTimerValue); 3017 MPT_2_HOST16(sp1, IDConfig); 3018} 3019 3020void 3021host2mpt_config_page_scsi_port_1(CONFIG_PAGE_SCSI_PORT_1 *sp1) 3022{ 3023 3024 HOST_2_MPT32(sp1, Configuration); 3025 HOST_2_MPT32(sp1, OnBusTimerValue); 3026 HOST_2_MPT16(sp1, IDConfig); 3027} 3028 3029void 3030mpt2host_config_page_scsi_port_2(CONFIG_PAGE_SCSI_PORT_2 *sp2) 3031{ 3032 int i; 3033 3034 MPT_2_HOST32(sp2, PortFlags); 3035 MPT_2_HOST32(sp2, PortSettings); 3036 for (i = 0; i < sizeof(sp2->DeviceSettings) / 3037 sizeof(*sp2->DeviceSettings); i++) { 3038 MPT_2_HOST16(sp2, DeviceSettings[i].DeviceFlags); 3039 } 3040} 3041 3042void 3043mpt2host_config_page_scsi_device_0(CONFIG_PAGE_SCSI_DEVICE_0 *sd0) 3044{ 3045 3046 MPT_2_HOST32(sd0, NegotiatedParameters); 3047 MPT_2_HOST32(sd0, Information); 3048} 3049 3050void 3051mpt2host_config_page_scsi_device_1(CONFIG_PAGE_SCSI_DEVICE_1 *sd1) 3052{ 3053 3054 MPT_2_HOST32(sd1, RequestedParameters); 3055 MPT_2_HOST32(sd1, Reserved); 3056 MPT_2_HOST32(sd1, Configuration); 3057} 3058 3059void 3060host2mpt_config_page_scsi_device_1(CONFIG_PAGE_SCSI_DEVICE_1 *sd1) 3061{ 3062 3063 HOST_2_MPT32(sd1, RequestedParameters); 3064 HOST_2_MPT32(sd1, Reserved); 3065 HOST_2_MPT32(sd1, Configuration); 3066} 3067 3068void 3069mpt2host_config_page_fc_port_0(CONFIG_PAGE_FC_PORT_0 *fp0) 3070{ 3071 3072 MPT_2_HOST32(fp0, Flags); 3073 MPT_2_HOST32(fp0, PortIdentifier); 3074 MPT_2_HOST32(fp0, WWNN.Low); 3075 MPT_2_HOST32(fp0, WWNN.High); 3076 MPT_2_HOST32(fp0, WWPN.Low); 3077 MPT_2_HOST32(fp0, WWPN.High); 3078 MPT_2_HOST32(fp0, SupportedServiceClass); 3079 MPT_2_HOST32(fp0, SupportedSpeeds); 3080 MPT_2_HOST32(fp0, CurrentSpeed); 3081 MPT_2_HOST32(fp0, MaxFrameSize); 3082 MPT_2_HOST32(fp0, FabricWWNN.Low); 3083 MPT_2_HOST32(fp0, FabricWWNN.High); 3084 MPT_2_HOST32(fp0, FabricWWPN.Low); 3085 MPT_2_HOST32(fp0, FabricWWPN.High); 3086 MPT_2_HOST32(fp0, DiscoveredPortsCount); 3087 MPT_2_HOST32(fp0, MaxInitiators); 3088} 3089 3090void 3091mpt2host_config_page_fc_port_1(CONFIG_PAGE_FC_PORT_1 *fp1) 3092{ 3093 3094 MPT_2_HOST32(fp1, Flags); 3095 MPT_2_HOST32(fp1, NoSEEPROMWWNN.Low); 3096 MPT_2_HOST32(fp1, NoSEEPROMWWNN.High); 3097 MPT_2_HOST32(fp1, NoSEEPROMWWPN.Low); 3098 MPT_2_HOST32(fp1, NoSEEPROMWWPN.High); 3099} 3100 3101void 3102host2mpt_config_page_fc_port_1(CONFIG_PAGE_FC_PORT_1 *fp1) 3103{ 3104 3105 HOST_2_MPT32(fp1, Flags); 3106 HOST_2_MPT32(fp1, NoSEEPROMWWNN.Low); 3107 HOST_2_MPT32(fp1, NoSEEPROMWWNN.High); 3108 HOST_2_MPT32(fp1, NoSEEPROMWWPN.Low); 3109 HOST_2_MPT32(fp1, NoSEEPROMWWPN.High); 3110} 3111 3112void 3113mpt2host_config_page_raid_vol_0(CONFIG_PAGE_RAID_VOL_0 *volp) 3114{ 3115 int i; 3116 3117 MPT_2_HOST16(volp, VolumeStatus.Reserved); 3118 MPT_2_HOST16(volp, VolumeSettings.Settings); 3119 MPT_2_HOST32(volp, MaxLBA); 3120 MPT_2_HOST32(volp, MaxLBAHigh); 3121 MPT_2_HOST32(volp, StripeSize); 3122 MPT_2_HOST32(volp, Reserved2); 3123 MPT_2_HOST32(volp, Reserved3); 3124 for (i = 0; i < MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX; i++) { 3125 MPT_2_HOST16(volp, PhysDisk[i].Reserved); 3126 } 3127} 3128 3129void 3130mpt2host_config_page_raid_phys_disk_0(CONFIG_PAGE_RAID_PHYS_DISK_0 *rpd0) 3131{ 3132 3133 MPT_2_HOST32(rpd0, Reserved1); 3134 MPT_2_HOST16(rpd0, PhysDiskStatus.Reserved); 3135 MPT_2_HOST32(rpd0, MaxLBA); 3136 MPT_2_HOST16(rpd0, ErrorData.Reserved); 3137 MPT_2_HOST16(rpd0, ErrorData.ErrorCount); 3138 MPT_2_HOST16(rpd0, ErrorData.SmartCount); 3139} 3140 3141void 3142mpt2host_mpi_raid_vol_indicator(MPI_RAID_VOL_INDICATOR *vi) 3143{ 3144 3145 MPT_2_HOST16(vi, TotalBlocks.High); 3146 MPT_2_HOST16(vi, TotalBlocks.Low); 3147 MPT_2_HOST16(vi, BlocksRemaining.High); 3148 MPT_2_HOST16(vi, BlocksRemaining.Low); 3149} 3150#endif 3151