1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#ifndef IXL_STANDALONE_BUILD 36#include "opt_inet.h" 37#include "opt_inet6.h" 38#endif 39 40#include "ixl.h" 41#include "ixl_pf.h" 42 43#ifdef RSS 44#include <net/rss_config.h> 45#endif 46 47/********************************************************************* 48 * Driver version 49 *********************************************************************/ 50char ixl_driver_version[] = "1.4.3"; 51 52/********************************************************************* 53 * PCI Device ID Table 54 * 55 * Used by probe to select devices to load on 56 * Last field stores an index into ixl_strings 57 * Last entry must be all 0s 58 * 59 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 60 *********************************************************************/ 61 62static ixl_vendor_info_t ixl_vendor_info_array[] = 63{ 64 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710, 0, 0, 0}, 65 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_A, 0, 0, 0}, 66 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B, 0, 0, 0}, 67 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C, 0, 0, 0}, 68 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A, 0, 0, 0}, 69 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B, 0, 0, 0}, 70 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C, 0, 0, 0}, 71 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T, 0, 0, 0}, 72 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4, 0, 0, 0}, 73 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2, 0, 0, 0}, 74 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A, 0, 0, 0}, 75#ifdef X722_SUPPORT 76 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722, 0, 0, 0}, 77 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722, 0, 0, 0}, 78 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722, 0, 0, 0}, 79#endif 80 /* required last entry */ 81 {0, 0, 0, 0, 0} 82}; 83 84/********************************************************************* 85 * Table of branding strings 86 *********************************************************************/ 87 88static char *ixl_strings[] = { 89 "Intel(R) Ethernet Connection XL710 Driver" 90}; 91 92 93/********************************************************************* 94 * Function prototypes 95 *********************************************************************/ 96static int ixl_probe(device_t); 97static int ixl_attach(device_t); 98static int ixl_detach(device_t); 99static int ixl_shutdown(device_t); 100static int ixl_get_hw_capabilities(struct ixl_pf *); 101static void ixl_cap_txcsum_tso(struct ixl_vsi *, struct ifnet *, int); 102static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 103static void ixl_init(void *); 104static void ixl_init_locked(struct ixl_pf *); 105static void ixl_stop(struct ixl_pf *); 106static void ixl_media_status(struct ifnet *, struct ifmediareq *); 107static int ixl_media_change(struct ifnet *); 108static void ixl_update_link_status(struct ixl_pf *); 109static int ixl_allocate_pci_resources(struct ixl_pf *); 110static u16 ixl_get_bus_info(struct i40e_hw *, device_t); 111static int ixl_setup_stations(struct ixl_pf *); 112static int ixl_switch_config(struct ixl_pf *); 113static int ixl_initialize_vsi(struct ixl_vsi *); 114static int ixl_assign_vsi_msix(struct ixl_pf *); 115static int ixl_assign_vsi_legacy(struct ixl_pf *); 116static int ixl_init_msix(struct ixl_pf *); 117static void ixl_configure_msix(struct ixl_pf *); 118static void ixl_configure_itr(struct ixl_pf *); 119static void ixl_configure_legacy(struct ixl_pf *); 120static void ixl_free_pci_resources(struct ixl_pf *); 121static void ixl_local_timer(void *); 122static int ixl_setup_interface(device_t, struct ixl_vsi *); 123static void ixl_link_event(struct ixl_pf *, struct i40e_arq_event_info *); 124static void ixl_config_rss(struct ixl_vsi *); 125static void ixl_set_queue_rx_itr(struct ixl_queue *); 126static void ixl_set_queue_tx_itr(struct ixl_queue *); 127static int ixl_set_advertised_speeds(struct ixl_pf *, int); 128 129static int ixl_enable_rings(struct ixl_vsi *); 130static int ixl_disable_rings(struct ixl_vsi *); 131static void ixl_enable_intr(struct ixl_vsi *); 132static void ixl_disable_intr(struct ixl_vsi *); 133static void ixl_disable_rings_intr(struct ixl_vsi *); 134 135static void ixl_enable_adminq(struct i40e_hw *); 136static void ixl_disable_adminq(struct i40e_hw *); 137static void ixl_enable_queue(struct i40e_hw *, int); 138static void ixl_disable_queue(struct i40e_hw *, int); 139static void ixl_enable_legacy(struct i40e_hw *); 140static void ixl_disable_legacy(struct i40e_hw *); 141 142static void ixl_set_promisc(struct ixl_vsi *); 143static void ixl_add_multi(struct ixl_vsi *); 144static void ixl_del_multi(struct ixl_vsi *); 145static void ixl_register_vlan(void *, struct ifnet *, u16); 146static void ixl_unregister_vlan(void *, struct ifnet *, u16); 147static void ixl_setup_vlan_filters(struct ixl_vsi *); 148 149static void ixl_init_filters(struct ixl_vsi *); 150static void ixl_reconfigure_filters(struct ixl_vsi *vsi); 151static void ixl_add_filter(struct ixl_vsi *, u8 *, s16 vlan); 152static void ixl_del_filter(struct ixl_vsi *, u8 *, s16 vlan); 153static void ixl_add_hw_filters(struct ixl_vsi *, int, int); 154static void ixl_del_hw_filters(struct ixl_vsi *, int); 155static struct ixl_mac_filter * 156 ixl_find_filter(struct ixl_vsi *, u8 *, s16); 157static void ixl_add_mc_filter(struct ixl_vsi *, u8 *); 158static void ixl_free_mac_filters(struct ixl_vsi *vsi); 159 160 161/* Sysctl debug interface */ 162#ifdef IXL_DEBUG_SYSCTL 163static int ixl_debug_info(SYSCTL_HANDLER_ARGS); 164static void ixl_print_debug_info(struct ixl_pf *); 165#endif 166 167/* The MSI/X Interrupt handlers */ 168static void ixl_intr(void *); 169static void ixl_msix_que(void *); 170static void ixl_msix_adminq(void *); 171static void ixl_handle_mdd_event(struct ixl_pf *); 172 173/* Deferred interrupt tasklets */ 174static void ixl_do_adminq(void *, int); 175 176/* Sysctl handlers */ 177static int ixl_set_flowcntl(SYSCTL_HANDLER_ARGS); 178static int ixl_set_advertise(SYSCTL_HANDLER_ARGS); 179static int ixl_current_speed(SYSCTL_HANDLER_ARGS); 180static int ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS); 181 182/* Statistics */ 183static void ixl_add_hw_stats(struct ixl_pf *); 184static void ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *, 185 struct sysctl_oid_list *, struct i40e_hw_port_stats *); 186static void ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *, 187 struct sysctl_oid_list *, 188 struct i40e_eth_stats *); 189static void ixl_update_stats_counters(struct ixl_pf *); 190static void ixl_update_eth_stats(struct ixl_vsi *); 191static void ixl_update_vsi_stats(struct ixl_vsi *); 192static void ixl_pf_reset_stats(struct ixl_pf *); 193static void ixl_vsi_reset_stats(struct ixl_vsi *); 194static void ixl_stat_update48(struct i40e_hw *, u32, u32, bool, 195 u64 *, u64 *); 196static void ixl_stat_update32(struct i40e_hw *, u32, bool, 197 u64 *, u64 *); 198 199#ifdef IXL_DEBUG_SYSCTL 200static int ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS); 201static int ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS); 202static int ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS); 203static int ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS); 204static int ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS); 205#endif 206 207#ifdef PCI_IOV 208static int ixl_adminq_err_to_errno(enum i40e_admin_queue_err err); 209 210static int ixl_init_iov(device_t dev, uint16_t num_vfs, const nvlist_t*); 211static void ixl_uninit_iov(device_t dev); 212static int ixl_add_vf(device_t dev, uint16_t vfnum, const nvlist_t*); 213 214static void ixl_handle_vf_msg(struct ixl_pf *, 215 struct i40e_arq_event_info *); 216static void ixl_handle_vflr(void *arg, int pending); 217 218static void ixl_reset_vf(struct ixl_pf *pf, struct ixl_vf *vf); 219static void ixl_reinit_vf(struct ixl_pf *pf, struct ixl_vf *vf); 220#endif 221 222/********************************************************************* 223 * FreeBSD Device Interface Entry Points 224 *********************************************************************/ 225 226static device_method_t ixl_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, ixl_probe), 229 DEVMETHOD(device_attach, ixl_attach), 230 DEVMETHOD(device_detach, ixl_detach), 231 DEVMETHOD(device_shutdown, ixl_shutdown), 232#ifdef PCI_IOV 233 DEVMETHOD(pci_init_iov, ixl_init_iov), 234 DEVMETHOD(pci_uninit_iov, ixl_uninit_iov), 235 DEVMETHOD(pci_add_vf, ixl_add_vf), 236#endif 237 {0, 0} 238}; 239 240static driver_t ixl_driver = { 241 "ixl", ixl_methods, sizeof(struct ixl_pf), 242}; 243 244devclass_t ixl_devclass; 245DRIVER_MODULE(ixl, pci, ixl_driver, ixl_devclass, 0, 0); 246 247MODULE_DEPEND(ixl, pci, 1, 1, 1); 248MODULE_DEPEND(ixl, ether, 1, 1, 1); 249#ifdef DEV_NETMAP 250MODULE_DEPEND(ixl, netmap, 1, 1, 1); 251#endif /* DEV_NETMAP */ 252 253/* 254** Global reset mutex 255*/ 256static struct mtx ixl_reset_mtx; 257 258/* 259** TUNEABLE PARAMETERS: 260*/ 261 262static SYSCTL_NODE(_hw, OID_AUTO, ixl, CTLFLAG_RD, 0, 263 "IXL driver parameters"); 264 265/* 266 * MSIX should be the default for best performance, 267 * but this allows it to be forced off for testing. 268 */ 269static int ixl_enable_msix = 1; 270TUNABLE_INT("hw.ixl.enable_msix", &ixl_enable_msix); 271SYSCTL_INT(_hw_ixl, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixl_enable_msix, 0, 272 "Enable MSI-X interrupts"); 273 274/* 275** Number of descriptors per ring: 276** - TX and RX are the same size 277*/ 278static int ixl_ringsz = DEFAULT_RING; 279TUNABLE_INT("hw.ixl.ringsz", &ixl_ringsz); 280SYSCTL_INT(_hw_ixl, OID_AUTO, ring_size, CTLFLAG_RDTUN, 281 &ixl_ringsz, 0, "Descriptor Ring Size"); 282 283/* 284** This can be set manually, if left as 0 the 285** number of queues will be calculated based 286** on cpus and msix vectors available. 287*/ 288int ixl_max_queues = 0; 289TUNABLE_INT("hw.ixl.max_queues", &ixl_max_queues); 290SYSCTL_INT(_hw_ixl, OID_AUTO, max_queues, CTLFLAG_RDTUN, 291 &ixl_max_queues, 0, "Number of Queues"); 292 293/* 294** Controls for Interrupt Throttling 295** - true/false for dynamic adjustment 296** - default values for static ITR 297*/ 298int ixl_dynamic_rx_itr = 0; 299TUNABLE_INT("hw.ixl.dynamic_rx_itr", &ixl_dynamic_rx_itr); 300SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_rx_itr, CTLFLAG_RDTUN, 301 &ixl_dynamic_rx_itr, 0, "Dynamic RX Interrupt Rate"); 302 303int ixl_dynamic_tx_itr = 0; 304TUNABLE_INT("hw.ixl.dynamic_tx_itr", &ixl_dynamic_tx_itr); 305SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_tx_itr, CTLFLAG_RDTUN, 306 &ixl_dynamic_tx_itr, 0, "Dynamic TX Interrupt Rate"); 307 308int ixl_rx_itr = IXL_ITR_8K; 309TUNABLE_INT("hw.ixl.rx_itr", &ixl_rx_itr); 310SYSCTL_INT(_hw_ixl, OID_AUTO, rx_itr, CTLFLAG_RDTUN, 311 &ixl_rx_itr, 0, "RX Interrupt Rate"); 312 313int ixl_tx_itr = IXL_ITR_4K; 314TUNABLE_INT("hw.ixl.tx_itr", &ixl_tx_itr); 315SYSCTL_INT(_hw_ixl, OID_AUTO, tx_itr, CTLFLAG_RDTUN, 316 &ixl_tx_itr, 0, "TX Interrupt Rate"); 317 318#ifdef IXL_FDIR 319static int ixl_enable_fdir = 1; 320TUNABLE_INT("hw.ixl.enable_fdir", &ixl_enable_fdir); 321/* Rate at which we sample */ 322int ixl_atr_rate = 20; 323TUNABLE_INT("hw.ixl.atr_rate", &ixl_atr_rate); 324#endif 325 326#ifdef DEV_NETMAP 327#define NETMAP_IXL_MAIN /* only bring in one part of the netmap code */ 328#include <dev/netmap/if_ixl_netmap.h> 329#endif /* DEV_NETMAP */ 330 331static char *ixl_fc_string[6] = { 332 "None", 333 "Rx", 334 "Tx", 335 "Full", 336 "Priority", 337 "Default" 338}; 339 340static MALLOC_DEFINE(M_IXL, "ixl", "ixl driver allocations"); 341 342static uint8_t ixl_bcast_addr[ETHER_ADDR_LEN] = 343 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 344 345/********************************************************************* 346 * Device identification routine 347 * 348 * ixl_probe determines if the driver should be loaded on 349 * the hardware based on PCI vendor/device id of the device. 350 * 351 * return BUS_PROBE_DEFAULT on success, positive on failure 352 *********************************************************************/ 353 354static int 355ixl_probe(device_t dev) 356{ 357 ixl_vendor_info_t *ent; 358 359 u16 pci_vendor_id, pci_device_id; 360 u16 pci_subvendor_id, pci_subdevice_id; 361 char device_name[256]; 362 static bool lock_init = FALSE; 363 364 INIT_DEBUGOUT("ixl_probe: begin"); 365 366 pci_vendor_id = pci_get_vendor(dev); 367 if (pci_vendor_id != I40E_INTEL_VENDOR_ID) 368 return (ENXIO); 369 370 pci_device_id = pci_get_device(dev); 371 pci_subvendor_id = pci_get_subvendor(dev); 372 pci_subdevice_id = pci_get_subdevice(dev); 373 374 ent = ixl_vendor_info_array; 375 while (ent->vendor_id != 0) { 376 if ((pci_vendor_id == ent->vendor_id) && 377 (pci_device_id == ent->device_id) && 378 379 ((pci_subvendor_id == ent->subvendor_id) || 380 (ent->subvendor_id == 0)) && 381 382 ((pci_subdevice_id == ent->subdevice_id) || 383 (ent->subdevice_id == 0))) { 384 sprintf(device_name, "%s, Version - %s", 385 ixl_strings[ent->index], 386 ixl_driver_version); 387 device_set_desc_copy(dev, device_name); 388 /* One shot mutex init */ 389 if (lock_init == FALSE) { 390 lock_init = TRUE; 391 mtx_init(&ixl_reset_mtx, 392 "ixl_reset", 393 "IXL RESET Lock", MTX_DEF); 394 } 395 return (BUS_PROBE_DEFAULT); 396 } 397 ent++; 398 } 399 return (ENXIO); 400} 401 402/********************************************************************* 403 * Device initialization routine 404 * 405 * The attach entry point is called when the driver is being loaded. 406 * This routine identifies the type of hardware, allocates all resources 407 * and initializes the hardware. 408 * 409 * return 0 on success, positive on failure 410 *********************************************************************/ 411 412static int 413ixl_attach(device_t dev) 414{ 415 struct ixl_pf *pf; 416 struct i40e_hw *hw; 417 struct ixl_vsi *vsi; 418 u16 bus; 419 int error = 0; 420#ifdef PCI_IOV 421 nvlist_t *pf_schema, *vf_schema; 422 int iov_error; 423#endif 424 425 INIT_DEBUGOUT("ixl_attach: begin"); 426 427 /* Allocate, clear, and link in our primary soft structure */ 428 pf = device_get_softc(dev); 429 pf->dev = pf->osdep.dev = dev; 430 hw = &pf->hw; 431 432 /* 433 ** Note this assumes we have a single embedded VSI, 434 ** this could be enhanced later to allocate multiple 435 */ 436 vsi = &pf->vsi; 437 vsi->dev = pf->dev; 438 439 /* Core Lock Init*/ 440 IXL_PF_LOCK_INIT(pf, device_get_nameunit(dev)); 441 442 /* Set up the timer callout */ 443 callout_init_mtx(&pf->timer, &pf->pf_mtx, 0); 444 445 /* Set up sysctls */ 446 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 447 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 448 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW, 449 pf, 0, ixl_set_flowcntl, "I", "Flow Control"); 450 451 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 452 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 453 OID_AUTO, "advertise_speed", CTLTYPE_INT | CTLFLAG_RW, 454 pf, 0, ixl_set_advertise, "I", "Advertised Speed"); 455 456 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 457 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 458 OID_AUTO, "current_speed", CTLTYPE_STRING | CTLFLAG_RD, 459 pf, 0, ixl_current_speed, "A", "Current Port Speed"); 460 461 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 462 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 463 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, 464 pf, 0, ixl_sysctl_show_fw, "A", "Firmware version"); 465 466 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 467 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 468 OID_AUTO, "rx_itr", CTLFLAG_RW, 469 &ixl_rx_itr, IXL_ITR_8K, "RX ITR"); 470 471 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 472 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 473 OID_AUTO, "dynamic_rx_itr", CTLFLAG_RW, 474 &ixl_dynamic_rx_itr, 0, "Dynamic RX ITR"); 475 476 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 477 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 478 OID_AUTO, "tx_itr", CTLFLAG_RW, 479 &ixl_tx_itr, IXL_ITR_4K, "TX ITR"); 480 481 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 482 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 483 OID_AUTO, "dynamic_tx_itr", CTLFLAG_RW, 484 &ixl_dynamic_tx_itr, 0, "Dynamic TX ITR"); 485 486#ifdef IXL_DEBUG_SYSCTL 487 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 489 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, pf, 0, 490 ixl_debug_info, "I", "Debug Information"); 491 492 /* Debug shared-code message level */ 493 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 494 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 495 OID_AUTO, "debug_mask", CTLFLAG_RW, 496 &pf->hw.debug_mask, 0, "Debug Message Level"); 497 498 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 499 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 500 OID_AUTO, "vc_debug_level", CTLFLAG_RW, &pf->vc_debug_lvl, 501 0, "PF/VF Virtual Channel debug level"); 502 503 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 504 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 505 OID_AUTO, "link_status", CTLTYPE_STRING | CTLFLAG_RD, 506 pf, 0, ixl_sysctl_link_status, "A", "Current Link Status"); 507 508 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 509 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 510 OID_AUTO, "phy_abilities", CTLTYPE_STRING | CTLFLAG_RD, 511 pf, 0, ixl_sysctl_phy_abilities, "A", "PHY Abilities"); 512 513 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 514 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 515 OID_AUTO, "filter_list", CTLTYPE_STRING | CTLFLAG_RD, 516 pf, 0, ixl_sysctl_sw_filter_list, "A", "SW Filter List"); 517 518 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 519 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 520 OID_AUTO, "hw_res_alloc", CTLTYPE_STRING | CTLFLAG_RD, 521 pf, 0, ixl_sysctl_hw_res_alloc, "A", "HW Resource Allocation"); 522 523 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 524 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 525 OID_AUTO, "switch_config", CTLTYPE_STRING | CTLFLAG_RD, 526 pf, 0, ixl_sysctl_switch_config, "A", "HW Switch Configuration"); 527#endif 528 529 /* Save off the PCI information */ 530 hw->vendor_id = pci_get_vendor(dev); 531 hw->device_id = pci_get_device(dev); 532 hw->revision_id = pci_read_config(dev, PCIR_REVID, 1); 533 hw->subsystem_vendor_id = 534 pci_read_config(dev, PCIR_SUBVEND_0, 2); 535 hw->subsystem_device_id = 536 pci_read_config(dev, PCIR_SUBDEV_0, 2); 537 538 hw->bus.device = pci_get_slot(dev); 539 hw->bus.func = pci_get_function(dev); 540 541 pf->vc_debug_lvl = 1; 542 543 /* Do PCI setup - map BAR0, etc */ 544 if (ixl_allocate_pci_resources(pf)) { 545 device_printf(dev, "Allocation of PCI resources failed\n"); 546 error = ENXIO; 547 goto err_out; 548 } 549 550 /* Establish a clean starting point */ 551 i40e_clear_hw(hw); 552 error = i40e_pf_reset(hw); 553 if (error) { 554 device_printf(dev,"PF reset failure %x\n", error); 555 error = EIO; 556 goto err_out; 557 } 558 559 /* Set admin queue parameters */ 560 hw->aq.num_arq_entries = IXL_AQ_LEN; 561 hw->aq.num_asq_entries = IXL_AQ_LEN; 562 hw->aq.arq_buf_size = IXL_AQ_BUFSZ; 563 hw->aq.asq_buf_size = IXL_AQ_BUFSZ; 564 565 /* Initialize the shared code */ 566 error = i40e_init_shared_code(hw); 567 if (error) { 568 device_printf(dev,"Unable to initialize the shared code\n"); 569 error = EIO; 570 goto err_out; 571 } 572 573 /* Set up the admin queue */ 574 error = i40e_init_adminq(hw); 575 if (error) { 576 device_printf(dev, "The driver for the device stopped " 577 "because the NVM image is newer than expected.\n" 578 "You must install the most recent version of " 579 " the network driver.\n"); 580 goto err_out; 581 } 582 device_printf(dev, "%s\n", ixl_fw_version_str(hw)); 583 584 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 585 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) 586 device_printf(dev, "The driver for the device detected " 587 "a newer version of the NVM image than expected.\n" 588 "Please install the most recent version of the network driver.\n"); 589 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR || 590 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1)) 591 device_printf(dev, "The driver for the device detected " 592 "an older version of the NVM image than expected.\n" 593 "Please update the NVM image.\n"); 594 595 /* Clear PXE mode */ 596 i40e_clear_pxe_mode(hw); 597 598 /* Get capabilities from the device */ 599 error = ixl_get_hw_capabilities(pf); 600 if (error) { 601 device_printf(dev, "HW capabilities failure!\n"); 602 goto err_get_cap; 603 } 604 605 /* Set up host memory cache */ 606 error = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 607 hw->func_caps.num_rx_qp, 0, 0); 608 if (error) { 609 device_printf(dev, "init_lan_hmc failed: %d\n", error); 610 goto err_get_cap; 611 } 612 613 error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 614 if (error) { 615 device_printf(dev, "configure_lan_hmc failed: %d\n", error); 616 goto err_mac_hmc; 617 } 618 619 /* Disable LLDP from the firmware */ 620 i40e_aq_stop_lldp(hw, TRUE, NULL); 621 622 i40e_get_mac_addr(hw, hw->mac.addr); 623 error = i40e_validate_mac_addr(hw->mac.addr); 624 if (error) { 625 device_printf(dev, "validate_mac_addr failed: %d\n", error); 626 goto err_mac_hmc; 627 } 628 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN); 629 i40e_get_port_mac_addr(hw, hw->mac.port_addr); 630 631 /* Set up VSI and queues */ 632 if (ixl_setup_stations(pf) != 0) { 633 device_printf(dev, "setup stations failed!\n"); 634 error = ENOMEM; 635 goto err_mac_hmc; 636 } 637 638 /* Initialize mac filter list for VSI */ 639 SLIST_INIT(&vsi->ftl); 640 641 /* Set up interrupt routing here */ 642 if (pf->msix > 1) 643 error = ixl_assign_vsi_msix(pf); 644 else 645 error = ixl_assign_vsi_legacy(pf); 646 if (error) 647 goto err_late; 648 649 if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) || 650 (hw->aq.fw_maj_ver < 4)) { 651 i40e_msec_delay(75); 652 error = i40e_aq_set_link_restart_an(hw, TRUE, NULL); 653 if (error) 654 device_printf(dev, "link restart failed, aq_err=%d\n", 655 pf->hw.aq.asq_last_status); 656 } 657 658 /* Determine link state */ 659 i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 660 i40e_get_link_status(hw, &pf->link_up); 661 662 /* Setup OS specific network interface */ 663 if (ixl_setup_interface(dev, vsi) != 0) { 664 device_printf(dev, "interface setup failed!\n"); 665 error = EIO; 666 goto err_late; 667 } 668 669 error = ixl_switch_config(pf); 670 if (error) { 671 device_printf(dev, "Initial switch config failed: %d\n", error); 672 goto err_mac_hmc; 673 } 674 675 /* Limit phy interrupts to link and modules failure */ 676 error = i40e_aq_set_phy_int_mask(hw, ~(I40E_AQ_EVENT_LINK_UPDOWN | 677 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); 678 if (error) 679 device_printf(dev, "set phy mask failed: %d\n", error); 680 681 /* Get the bus configuration and set the shared code */ 682 bus = ixl_get_bus_info(hw, dev); 683 i40e_set_pci_config_data(hw, bus); 684 685 /* Initialize statistics */ 686 ixl_pf_reset_stats(pf); 687 ixl_update_stats_counters(pf); 688 ixl_add_hw_stats(pf); 689 690 /* Register for VLAN events */ 691 vsi->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 692 ixl_register_vlan, vsi, EVENTHANDLER_PRI_FIRST); 693 vsi->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 694 ixl_unregister_vlan, vsi, EVENTHANDLER_PRI_FIRST); 695 696#ifdef PCI_IOV 697 /* SR-IOV is only supported when MSI-X is in use. */ 698 if (pf->msix > 1) { 699 pf_schema = pci_iov_schema_alloc_node(); 700 vf_schema = pci_iov_schema_alloc_node(); 701 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 702 pci_iov_schema_add_bool(vf_schema, "mac-anti-spoof", 703 IOV_SCHEMA_HASDEFAULT, TRUE); 704 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", 705 IOV_SCHEMA_HASDEFAULT, FALSE); 706 pci_iov_schema_add_bool(vf_schema, "allow-promisc", 707 IOV_SCHEMA_HASDEFAULT, FALSE); 708 709 iov_error = pci_iov_attach(dev, pf_schema, vf_schema); 710 if (iov_error != 0) 711 device_printf(dev, 712 "Failed to initialize SR-IOV (error=%d)\n", 713 iov_error); 714 } 715#endif 716 717#ifdef DEV_NETMAP 718 ixl_netmap_attach(vsi); 719#endif /* DEV_NETMAP */ 720 INIT_DEBUGOUT("ixl_attach: end"); 721 return (0); 722 723err_late: 724 if (vsi->ifp != NULL) 725 if_free(vsi->ifp); 726err_mac_hmc: 727 i40e_shutdown_lan_hmc(hw); 728err_get_cap: 729 i40e_shutdown_adminq(hw); 730err_out: 731 ixl_free_pci_resources(pf); 732 ixl_free_vsi(vsi); 733 IXL_PF_LOCK_DESTROY(pf); 734 return (error); 735} 736 737/********************************************************************* 738 * Device removal routine 739 * 740 * The detach entry point is called when the driver is being removed. 741 * This routine stops the adapter and deallocates all the resources 742 * that were allocated for driver operation. 743 * 744 * return 0 on success, positive on failure 745 *********************************************************************/ 746 747static int 748ixl_detach(device_t dev) 749{ 750 struct ixl_pf *pf = device_get_softc(dev); 751 struct i40e_hw *hw = &pf->hw; 752 struct ixl_vsi *vsi = &pf->vsi; 753 struct ixl_queue *que = vsi->queues; 754 i40e_status status; 755#ifdef PCI_IOV 756 int error; 757#endif 758 759 INIT_DEBUGOUT("ixl_detach: begin"); 760 761 /* Make sure VLANS are not using driver */ 762 if (vsi->ifp->if_vlantrunk != NULL) { 763 device_printf(dev,"Vlan in use, detach first\n"); 764 return (EBUSY); 765 } 766 767#ifdef PCI_IOV 768 error = pci_iov_detach(dev); 769 if (error != 0) { 770 device_printf(dev, "SR-IOV in use; detach first.\n"); 771 return (error); 772 } 773#endif 774 775 ether_ifdetach(vsi->ifp); 776 if (vsi->ifp->if_drv_flags & IFF_DRV_RUNNING) { 777 IXL_PF_LOCK(pf); 778 ixl_stop(pf); 779 IXL_PF_UNLOCK(pf); 780 } 781 782 for (int i = 0; i < vsi->num_queues; i++, que++) { 783 if (que->tq) { 784 taskqueue_drain(que->tq, &que->task); 785 taskqueue_drain(que->tq, &que->tx_task); 786 taskqueue_free(que->tq); 787 } 788 } 789 790 /* Shutdown LAN HMC */ 791 status = i40e_shutdown_lan_hmc(hw); 792 if (status) 793 device_printf(dev, 794 "Shutdown LAN HMC failed with code %d\n", status); 795 796 /* Shutdown admin queue */ 797 status = i40e_shutdown_adminq(hw); 798 if (status) 799 device_printf(dev, 800 "Shutdown Admin queue failed with code %d\n", status); 801 802 /* Unregister VLAN events */ 803 if (vsi->vlan_attach != NULL) 804 EVENTHANDLER_DEREGISTER(vlan_config, vsi->vlan_attach); 805 if (vsi->vlan_detach != NULL) 806 EVENTHANDLER_DEREGISTER(vlan_unconfig, vsi->vlan_detach); 807 808 callout_drain(&pf->timer); 809#ifdef DEV_NETMAP 810 netmap_detach(vsi->ifp); 811#endif /* DEV_NETMAP */ 812 ixl_free_pci_resources(pf); 813 bus_generic_detach(dev); 814 if_free(vsi->ifp); 815 ixl_free_vsi(vsi); 816 IXL_PF_LOCK_DESTROY(pf); 817 return (0); 818} 819 820/********************************************************************* 821 * 822 * Shutdown entry point 823 * 824 **********************************************************************/ 825 826static int 827ixl_shutdown(device_t dev) 828{ 829 struct ixl_pf *pf = device_get_softc(dev); 830 IXL_PF_LOCK(pf); 831 ixl_stop(pf); 832 IXL_PF_UNLOCK(pf); 833 return (0); 834} 835 836 837/********************************************************************* 838 * 839 * Get the hardware capabilities 840 * 841 **********************************************************************/ 842 843static int 844ixl_get_hw_capabilities(struct ixl_pf *pf) 845{ 846 struct i40e_aqc_list_capabilities_element_resp *buf; 847 struct i40e_hw *hw = &pf->hw; 848 device_t dev = pf->dev; 849 int error, len; 850 u16 needed; 851 bool again = TRUE; 852 853 len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); 854retry: 855 if (!(buf = (struct i40e_aqc_list_capabilities_element_resp *) 856 malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO))) { 857 device_printf(dev, "Unable to allocate cap memory\n"); 858 return (ENOMEM); 859 } 860 861 /* This populates the hw struct */ 862 error = i40e_aq_discover_capabilities(hw, buf, len, 863 &needed, i40e_aqc_opc_list_func_capabilities, NULL); 864 free(buf, M_DEVBUF); 865 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) && 866 (again == TRUE)) { 867 /* retry once with a larger buffer */ 868 again = FALSE; 869 len = needed; 870 goto retry; 871 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { 872 device_printf(dev, "capability discovery failed: %d\n", 873 pf->hw.aq.asq_last_status); 874 return (ENODEV); 875 } 876 877 /* Capture this PF's starting queue pair */ 878 pf->qbase = hw->func_caps.base_queue; 879 880#ifdef IXL_DEBUG 881 device_printf(dev,"pf_id=%d, num_vfs=%d, msix_pf=%d, " 882 "msix_vf=%d, fd_g=%d, fd_b=%d, tx_qp=%d rx_qp=%d qbase=%d\n", 883 hw->pf_id, hw->func_caps.num_vfs, 884 hw->func_caps.num_msix_vectors, 885 hw->func_caps.num_msix_vectors_vf, 886 hw->func_caps.fd_filters_guaranteed, 887 hw->func_caps.fd_filters_best_effort, 888 hw->func_caps.num_tx_qp, 889 hw->func_caps.num_rx_qp, 890 hw->func_caps.base_queue); 891#endif 892 return (error); 893} 894 895static void 896ixl_cap_txcsum_tso(struct ixl_vsi *vsi, struct ifnet *ifp, int mask) 897{ 898 device_t dev = vsi->dev; 899 900 /* Enable/disable TXCSUM/TSO4 */ 901 if (!(ifp->if_capenable & IFCAP_TXCSUM) 902 && !(ifp->if_capenable & IFCAP_TSO4)) { 903 if (mask & IFCAP_TXCSUM) { 904 ifp->if_capenable |= IFCAP_TXCSUM; 905 /* enable TXCSUM, restore TSO if previously enabled */ 906 if (vsi->flags & IXL_FLAGS_KEEP_TSO4) { 907 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 908 ifp->if_capenable |= IFCAP_TSO4; 909 } 910 } 911 else if (mask & IFCAP_TSO4) { 912 ifp->if_capenable |= (IFCAP_TXCSUM | IFCAP_TSO4); 913 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 914 device_printf(dev, 915 "TSO4 requires txcsum, enabling both...\n"); 916 } 917 } else if((ifp->if_capenable & IFCAP_TXCSUM) 918 && !(ifp->if_capenable & IFCAP_TSO4)) { 919 if (mask & IFCAP_TXCSUM) 920 ifp->if_capenable &= ~IFCAP_TXCSUM; 921 else if (mask & IFCAP_TSO4) 922 ifp->if_capenable |= IFCAP_TSO4; 923 } else if((ifp->if_capenable & IFCAP_TXCSUM) 924 && (ifp->if_capenable & IFCAP_TSO4)) { 925 if (mask & IFCAP_TXCSUM) { 926 vsi->flags |= IXL_FLAGS_KEEP_TSO4; 927 ifp->if_capenable &= ~(IFCAP_TXCSUM | IFCAP_TSO4); 928 device_printf(dev, 929 "TSO4 requires txcsum, disabling both...\n"); 930 } else if (mask & IFCAP_TSO4) 931 ifp->if_capenable &= ~IFCAP_TSO4; 932 } 933 934 /* Enable/disable TXCSUM_IPV6/TSO6 */ 935 if (!(ifp->if_capenable & IFCAP_TXCSUM_IPV6) 936 && !(ifp->if_capenable & IFCAP_TSO6)) { 937 if (mask & IFCAP_TXCSUM_IPV6) { 938 ifp->if_capenable |= IFCAP_TXCSUM_IPV6; 939 if (vsi->flags & IXL_FLAGS_KEEP_TSO6) { 940 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 941 ifp->if_capenable |= IFCAP_TSO6; 942 } 943 } else if (mask & IFCAP_TSO6) { 944 ifp->if_capenable |= (IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 945 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 946 device_printf(dev, 947 "TSO6 requires txcsum6, enabling both...\n"); 948 } 949 } else if((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 950 && !(ifp->if_capenable & IFCAP_TSO6)) { 951 if (mask & IFCAP_TXCSUM_IPV6) 952 ifp->if_capenable &= ~IFCAP_TXCSUM_IPV6; 953 else if (mask & IFCAP_TSO6) 954 ifp->if_capenable |= IFCAP_TSO6; 955 } else if ((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 956 && (ifp->if_capenable & IFCAP_TSO6)) { 957 if (mask & IFCAP_TXCSUM_IPV6) { 958 vsi->flags |= IXL_FLAGS_KEEP_TSO6; 959 ifp->if_capenable &= ~(IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 960 device_printf(dev, 961 "TSO6 requires txcsum6, disabling both...\n"); 962 } else if (mask & IFCAP_TSO6) 963 ifp->if_capenable &= ~IFCAP_TSO6; 964 } 965} 966 967/********************************************************************* 968 * Ioctl entry point 969 * 970 * ixl_ioctl is called when the user wants to configure the 971 * interface. 972 * 973 * return 0 on success, positive on failure 974 **********************************************************************/ 975 976static int 977ixl_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 978{ 979 struct ixl_vsi *vsi = ifp->if_softc; 980 struct ixl_pf *pf = vsi->back; 981 struct ifreq *ifr = (struct ifreq *) data; 982#if defined(INET) || defined(INET6) 983 struct ifaddr *ifa = (struct ifaddr *)data; 984 bool avoid_reset = FALSE; 985#endif 986 int error = 0; 987 988 switch (command) { 989 990 case SIOCSIFADDR: 991#ifdef INET 992 if (ifa->ifa_addr->sa_family == AF_INET) 993 avoid_reset = TRUE; 994#endif 995#ifdef INET6 996 if (ifa->ifa_addr->sa_family == AF_INET6) 997 avoid_reset = TRUE; 998#endif 999#if defined(INET) || defined(INET6) 1000 /* 1001 ** Calling init results in link renegotiation, 1002 ** so we avoid doing it when possible. 1003 */ 1004 if (avoid_reset) { 1005 ifp->if_flags |= IFF_UP; 1006 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1007 ixl_init(pf); 1008#ifdef INET 1009 if (!(ifp->if_flags & IFF_NOARP)) 1010 arp_ifinit(ifp, ifa); 1011#endif 1012 } else 1013 error = ether_ioctl(ifp, command, data); 1014 break; 1015#endif 1016 case SIOCSIFMTU: 1017 IOCTL_DEBUGOUT("ioctl: SIOCSIFMTU (Set Interface MTU)"); 1018 if (ifr->ifr_mtu > IXL_MAX_FRAME - 1019 ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) { 1020 error = EINVAL; 1021 } else { 1022 IXL_PF_LOCK(pf); 1023 ifp->if_mtu = ifr->ifr_mtu; 1024 vsi->max_frame_size = 1025 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 1026 + ETHER_VLAN_ENCAP_LEN; 1027 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1028 ixl_init_locked(pf); 1029 IXL_PF_UNLOCK(pf); 1030 } 1031 break; 1032 case SIOCSIFFLAGS: 1033 IOCTL_DEBUGOUT("ioctl: SIOCSIFFLAGS (Set Interface Flags)"); 1034 IXL_PF_LOCK(pf); 1035 if (ifp->if_flags & IFF_UP) { 1036 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1037 if ((ifp->if_flags ^ pf->if_flags) & 1038 (IFF_PROMISC | IFF_ALLMULTI)) { 1039 ixl_set_promisc(vsi); 1040 } 1041 } else 1042 ixl_init_locked(pf); 1043 } else 1044 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1045 ixl_stop(pf); 1046 pf->if_flags = ifp->if_flags; 1047 IXL_PF_UNLOCK(pf); 1048 break; 1049 case SIOCADDMULTI: 1050 IOCTL_DEBUGOUT("ioctl: SIOCADDMULTI"); 1051 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1052 IXL_PF_LOCK(pf); 1053 ixl_disable_intr(vsi); 1054 ixl_add_multi(vsi); 1055 ixl_enable_intr(vsi); 1056 IXL_PF_UNLOCK(pf); 1057 } 1058 break; 1059 case SIOCDELMULTI: 1060 IOCTL_DEBUGOUT("ioctl: SIOCDELMULTI"); 1061 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1062 IXL_PF_LOCK(pf); 1063 ixl_disable_intr(vsi); 1064 ixl_del_multi(vsi); 1065 ixl_enable_intr(vsi); 1066 IXL_PF_UNLOCK(pf); 1067 } 1068 break; 1069 case SIOCSIFMEDIA: 1070 case SIOCGIFMEDIA: 1071#ifdef IFM_ETH_XTYPE 1072 case SIOCGIFXMEDIA: 1073#endif 1074 IOCTL_DEBUGOUT("ioctl: SIOCxIFMEDIA (Get/Set Interface Media)"); 1075 error = ifmedia_ioctl(ifp, ifr, &vsi->media, command); 1076 break; 1077 case SIOCSIFCAP: 1078 { 1079 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1080 IOCTL_DEBUGOUT("ioctl: SIOCSIFCAP (Set Capabilities)"); 1081 1082 ixl_cap_txcsum_tso(vsi, ifp, mask); 1083 1084 if (mask & IFCAP_RXCSUM) 1085 ifp->if_capenable ^= IFCAP_RXCSUM; 1086 if (mask & IFCAP_RXCSUM_IPV6) 1087 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1088 if (mask & IFCAP_LRO) 1089 ifp->if_capenable ^= IFCAP_LRO; 1090 if (mask & IFCAP_VLAN_HWTAGGING) 1091 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1092 if (mask & IFCAP_VLAN_HWFILTER) 1093 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 1094 if (mask & IFCAP_VLAN_HWTSO) 1095 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1096 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1097 IXL_PF_LOCK(pf); 1098 ixl_init_locked(pf); 1099 IXL_PF_UNLOCK(pf); 1100 } 1101 VLAN_CAPABILITIES(ifp); 1102 1103 break; 1104 } 1105 1106 default: 1107 IOCTL_DEBUGOUT("ioctl: UNKNOWN (0x%X)\n", (int)command); 1108 error = ether_ioctl(ifp, command, data); 1109 break; 1110 } 1111 1112 return (error); 1113} 1114 1115 1116/********************************************************************* 1117 * Init entry point 1118 * 1119 * This routine is used in two ways. It is used by the stack as 1120 * init entry point in network interface structure. It is also used 1121 * by the driver as a hw/sw initialization routine to get to a 1122 * consistent state. 1123 * 1124 * return 0 on success, positive on failure 1125 **********************************************************************/ 1126 1127static void 1128ixl_init_locked(struct ixl_pf *pf) 1129{ 1130 struct i40e_hw *hw = &pf->hw; 1131 struct ixl_vsi *vsi = &pf->vsi; 1132 struct ifnet *ifp = vsi->ifp; 1133 device_t dev = pf->dev; 1134 struct i40e_filter_control_settings filter; 1135 u8 tmpaddr[ETHER_ADDR_LEN]; 1136 int ret; 1137 1138 mtx_assert(&pf->pf_mtx, MA_OWNED); 1139 INIT_DEBUGOUT("ixl_init: begin"); 1140 ixl_stop(pf); 1141 1142 /* Get the latest mac address... User might use a LAA */ 1143 bcopy(IF_LLADDR(vsi->ifp), tmpaddr, 1144 I40E_ETH_LENGTH_OF_ADDRESS); 1145 if (!cmp_etheraddr(hw->mac.addr, tmpaddr) && 1146 (i40e_validate_mac_addr(tmpaddr) == I40E_SUCCESS)) { 1147 ixl_del_filter(vsi, hw->mac.addr, IXL_VLAN_ANY); 1148 bcopy(tmpaddr, hw->mac.addr, 1149 I40E_ETH_LENGTH_OF_ADDRESS); 1150 ret = i40e_aq_mac_address_write(hw, 1151 I40E_AQC_WRITE_TYPE_LAA_ONLY, 1152 hw->mac.addr, NULL); 1153 if (ret) { 1154 device_printf(dev, "LLA address" 1155 "change failed!!\n"); 1156 return; 1157 } else { 1158 ixl_add_filter(vsi, hw->mac.addr, IXL_VLAN_ANY); 1159 } 1160 } 1161 1162 /* Set the various hardware offload abilities */ 1163 ifp->if_hwassist = 0; 1164 if (ifp->if_capenable & IFCAP_TSO) 1165 ifp->if_hwassist |= CSUM_TSO; 1166 if (ifp->if_capenable & IFCAP_TXCSUM) 1167 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1168 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 1169 ifp->if_hwassist |= (CSUM_TCP_IPV6 | CSUM_UDP_IPV6); 1170 1171 /* Set up the device filtering */ 1172 bzero(&filter, sizeof(filter)); 1173 filter.enable_ethtype = TRUE; 1174 filter.enable_macvlan = TRUE; 1175#ifdef IXL_FDIR 1176 filter.enable_fdir = TRUE; 1177#endif 1178 if (i40e_set_filter_control(hw, &filter)) 1179 device_printf(dev, "set_filter_control() failed\n"); 1180 1181 /* Set up RSS */ 1182 ixl_config_rss(vsi); 1183 1184 /* 1185 ** Prepare the VSI: rings, hmc contexts, etc... 1186 */ 1187 if (ixl_initialize_vsi(vsi)) { 1188 device_printf(dev, "initialize vsi failed!!\n"); 1189 return; 1190 } 1191 1192 /* Add protocol filters to list */ 1193 ixl_init_filters(vsi); 1194 1195 /* Setup vlan's if needed */ 1196 ixl_setup_vlan_filters(vsi); 1197 1198 /* Start the local timer */ 1199 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1200 1201 /* Set up MSI/X routing and the ITR settings */ 1202 if (ixl_enable_msix) { 1203 ixl_configure_msix(pf); 1204 ixl_configure_itr(pf); 1205 } else 1206 ixl_configure_legacy(pf); 1207 1208 ixl_enable_rings(vsi); 1209 1210 i40e_aq_set_default_vsi(hw, vsi->seid, NULL); 1211 1212 ixl_reconfigure_filters(vsi); 1213 1214 /* Set MTU in hardware*/ 1215 int aq_error = i40e_aq_set_mac_config(hw, vsi->max_frame_size, 1216 TRUE, 0, NULL); 1217 if (aq_error) 1218 device_printf(vsi->dev, 1219 "aq_set_mac_config in init error, code %d\n", 1220 aq_error); 1221 1222 /* And now turn on interrupts */ 1223 ixl_enable_intr(vsi); 1224 1225 /* Now inform the stack we're ready */ 1226 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1227 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1228 1229 return; 1230} 1231 1232static void 1233ixl_init(void *arg) 1234{ 1235 struct ixl_pf *pf = arg; 1236 1237 IXL_PF_LOCK(pf); 1238 ixl_init_locked(pf); 1239 IXL_PF_UNLOCK(pf); 1240 return; 1241} 1242 1243/* 1244** 1245** MSIX Interrupt Handlers and Tasklets 1246** 1247*/ 1248static void 1249ixl_handle_que(void *context, int pending) 1250{ 1251 struct ixl_queue *que = context; 1252 struct ixl_vsi *vsi = que->vsi; 1253 struct i40e_hw *hw = vsi->hw; 1254 struct tx_ring *txr = &que->txr; 1255 struct ifnet *ifp = vsi->ifp; 1256 bool more; 1257 1258 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1259 more = ixl_rxeof(que, IXL_RX_LIMIT); 1260 IXL_TX_LOCK(txr); 1261 ixl_txeof(que); 1262 if (!drbr_empty(ifp, txr->br)) 1263 ixl_mq_start_locked(ifp, txr); 1264 IXL_TX_UNLOCK(txr); 1265 if (more) { 1266 taskqueue_enqueue(que->tq, &que->task); 1267 return; 1268 } 1269 } 1270 1271 /* Reenable this interrupt - hmmm */ 1272 ixl_enable_queue(hw, que->me); 1273 return; 1274} 1275 1276 1277/********************************************************************* 1278 * 1279 * Legacy Interrupt Service routine 1280 * 1281 **********************************************************************/ 1282void 1283ixl_intr(void *arg) 1284{ 1285 struct ixl_pf *pf = arg; 1286 struct i40e_hw *hw = &pf->hw; 1287 struct ixl_vsi *vsi = &pf->vsi; 1288 struct ixl_queue *que = vsi->queues; 1289 struct ifnet *ifp = vsi->ifp; 1290 struct tx_ring *txr = &que->txr; 1291 u32 reg, icr0, mask; 1292 bool more_tx, more_rx; 1293 1294 ++que->irqs; 1295 1296 /* Protect against spurious interrupts */ 1297 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1298 return; 1299 1300 icr0 = rd32(hw, I40E_PFINT_ICR0); 1301 1302 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1303 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1304 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1305 1306 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1307 1308#ifdef PCI_IOV 1309 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) 1310 taskqueue_enqueue(pf->tq, &pf->vflr_task); 1311#endif 1312 1313 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 1314 taskqueue_enqueue(pf->tq, &pf->adminq); 1315 return; 1316 } 1317 1318 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1319 1320 IXL_TX_LOCK(txr); 1321 more_tx = ixl_txeof(que); 1322 if (!drbr_empty(vsi->ifp, txr->br)) 1323 more_tx = 1; 1324 IXL_TX_UNLOCK(txr); 1325 1326 /* re-enable other interrupt causes */ 1327 wr32(hw, I40E_PFINT_ICR0_ENA, mask); 1328 1329 /* And now the queues */ 1330 reg = rd32(hw, I40E_QINT_RQCTL(0)); 1331 reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1332 wr32(hw, I40E_QINT_RQCTL(0), reg); 1333 1334 reg = rd32(hw, I40E_QINT_TQCTL(0)); 1335 reg |= I40E_QINT_TQCTL_CAUSE_ENA_MASK; 1336 reg &= ~I40E_PFINT_ICR0_INTEVENT_MASK; 1337 wr32(hw, I40E_QINT_TQCTL(0), reg); 1338 1339 ixl_enable_legacy(hw); 1340 1341 return; 1342} 1343 1344 1345/********************************************************************* 1346 * 1347 * MSIX VSI Interrupt Service routine 1348 * 1349 **********************************************************************/ 1350void 1351ixl_msix_que(void *arg) 1352{ 1353 struct ixl_queue *que = arg; 1354 struct ixl_vsi *vsi = que->vsi; 1355 struct i40e_hw *hw = vsi->hw; 1356 struct tx_ring *txr = &que->txr; 1357 bool more_tx, more_rx; 1358 1359 /* Protect against spurious interrupts */ 1360 if (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING)) 1361 return; 1362 1363 ++que->irqs; 1364 1365 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1366 1367 IXL_TX_LOCK(txr); 1368 more_tx = ixl_txeof(que); 1369 /* 1370 ** Make certain that if the stack 1371 ** has anything queued the task gets 1372 ** scheduled to handle it. 1373 */ 1374 if (!drbr_empty(vsi->ifp, txr->br)) 1375 more_tx = 1; 1376 IXL_TX_UNLOCK(txr); 1377 1378 ixl_set_queue_rx_itr(que); 1379 ixl_set_queue_tx_itr(que); 1380 1381 if (more_tx || more_rx) 1382 taskqueue_enqueue(que->tq, &que->task); 1383 else 1384 ixl_enable_queue(hw, que->me); 1385 1386 return; 1387} 1388 1389 1390/********************************************************************* 1391 * 1392 * MSIX Admin Queue Interrupt Service routine 1393 * 1394 **********************************************************************/ 1395static void 1396ixl_msix_adminq(void *arg) 1397{ 1398 struct ixl_pf *pf = arg; 1399 struct i40e_hw *hw = &pf->hw; 1400 u32 reg, mask; 1401 1402 ++pf->admin_irq; 1403 1404 reg = rd32(hw, I40E_PFINT_ICR0); 1405 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1406 1407 /* Check on the cause */ 1408 if (reg & I40E_PFINT_ICR0_ADMINQ_MASK) 1409 mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 1410 1411 if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) { 1412 ixl_handle_mdd_event(pf); 1413 mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 1414 } 1415 1416#ifdef PCI_IOV 1417 if (reg & I40E_PFINT_ICR0_VFLR_MASK) { 1418 mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; 1419 taskqueue_enqueue(pf->tq, &pf->vflr_task); 1420 } 1421#endif 1422 1423 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1424 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1425 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1426 1427 taskqueue_enqueue(pf->tq, &pf->adminq); 1428 return; 1429} 1430 1431/********************************************************************* 1432 * 1433 * Media Ioctl callback 1434 * 1435 * This routine is called whenever the user queries the status of 1436 * the interface using ifconfig. 1437 * 1438 **********************************************************************/ 1439static void 1440ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr) 1441{ 1442 struct ixl_vsi *vsi = ifp->if_softc; 1443 struct ixl_pf *pf = vsi->back; 1444 struct i40e_hw *hw = &pf->hw; 1445 1446 INIT_DEBUGOUT("ixl_media_status: begin"); 1447 IXL_PF_LOCK(pf); 1448 1449 hw->phy.get_link_info = TRUE; 1450 i40e_get_link_status(hw, &pf->link_up); 1451 ixl_update_link_status(pf); 1452 1453 ifmr->ifm_status = IFM_AVALID; 1454 ifmr->ifm_active = IFM_ETHER; 1455 1456 if (!pf->link_up) { 1457 IXL_PF_UNLOCK(pf); 1458 return; 1459 } 1460 1461 ifmr->ifm_status |= IFM_ACTIVE; 1462 /* Hardware is always full-duplex */ 1463 ifmr->ifm_active |= IFM_FDX; 1464 1465 switch (hw->phy.link_info.phy_type) { 1466 /* 100 M */ 1467 case I40E_PHY_TYPE_100BASE_TX: 1468 ifmr->ifm_active |= IFM_100_TX; 1469 break; 1470 /* 1 G */ 1471 case I40E_PHY_TYPE_1000BASE_T: 1472 ifmr->ifm_active |= IFM_1000_T; 1473 break; 1474 case I40E_PHY_TYPE_1000BASE_SX: 1475 ifmr->ifm_active |= IFM_1000_SX; 1476 break; 1477 case I40E_PHY_TYPE_1000BASE_LX: 1478 ifmr->ifm_active |= IFM_1000_LX; 1479 break; 1480 /* 10 G */ 1481 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1482 ifmr->ifm_active |= IFM_10G_TWINAX; 1483 break; 1484 case I40E_PHY_TYPE_10GBASE_SR: 1485 ifmr->ifm_active |= IFM_10G_SR; 1486 break; 1487 case I40E_PHY_TYPE_10GBASE_LR: 1488 ifmr->ifm_active |= IFM_10G_LR; 1489 break; 1490 case I40E_PHY_TYPE_10GBASE_T: 1491 ifmr->ifm_active |= IFM_10G_T; 1492 break; 1493 /* 40 G */ 1494 case I40E_PHY_TYPE_40GBASE_CR4: 1495 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1496 ifmr->ifm_active |= IFM_40G_CR4; 1497 break; 1498 case I40E_PHY_TYPE_40GBASE_SR4: 1499 ifmr->ifm_active |= IFM_40G_SR4; 1500 break; 1501 case I40E_PHY_TYPE_40GBASE_LR4: 1502 ifmr->ifm_active |= IFM_40G_LR4; 1503 break; 1504#ifndef IFM_ETH_XTYPE 1505 case I40E_PHY_TYPE_1000BASE_KX: 1506 ifmr->ifm_active |= IFM_1000_CX; 1507 break; 1508 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1509 case I40E_PHY_TYPE_10GBASE_CR1: 1510 ifmr->ifm_active |= IFM_10G_TWINAX; 1511 break; 1512 case I40E_PHY_TYPE_10GBASE_KX4: 1513 ifmr->ifm_active |= IFM_10G_CX4; 1514 break; 1515 case I40E_PHY_TYPE_10GBASE_KR: 1516 ifmr->ifm_active |= IFM_10G_SR; 1517 break; 1518 case I40E_PHY_TYPE_40GBASE_KR4: 1519 case I40E_PHY_TYPE_XLPPI: 1520 ifmr->ifm_active |= IFM_40G_SR4; 1521 break; 1522#else 1523 case I40E_PHY_TYPE_1000BASE_KX: 1524 ifmr->ifm_active |= IFM_1000_KX; 1525 break; 1526 /* ERJ: What's the difference between these? */ 1527 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1528 case I40E_PHY_TYPE_10GBASE_CR1: 1529 ifmr->ifm_active |= IFM_10G_CR1; 1530 break; 1531 case I40E_PHY_TYPE_10GBASE_KX4: 1532 ifmr->ifm_active |= IFM_10G_KX4; 1533 break; 1534 case I40E_PHY_TYPE_10GBASE_KR: 1535 ifmr->ifm_active |= IFM_10G_KR; 1536 break; 1537 case I40E_PHY_TYPE_20GBASE_KR2: 1538 ifmr->ifm_active |= IFM_20G_KR2; 1539 break; 1540 case I40E_PHY_TYPE_40GBASE_KR4: 1541 ifmr->ifm_active |= IFM_40G_KR4; 1542 break; 1543 case I40E_PHY_TYPE_XLPPI: 1544 ifmr->ifm_active |= IFM_40G_XLPPI; 1545 break; 1546#endif 1547 default: 1548 ifmr->ifm_active |= IFM_UNKNOWN; 1549 break; 1550 } 1551 /* Report flow control status as well */ 1552 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) 1553 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 1554 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) 1555 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 1556 1557 IXL_PF_UNLOCK(pf); 1558 1559 return; 1560} 1561 1562/********************************************************************* 1563 * 1564 * Media Ioctl callback 1565 * 1566 * This routine is called when the user changes speed/duplex using 1567 * media/mediopt option with ifconfig. 1568 * 1569 **********************************************************************/ 1570static int 1571ixl_media_change(struct ifnet * ifp) 1572{ 1573 struct ixl_vsi *vsi = ifp->if_softc; 1574 struct ifmedia *ifm = &vsi->media; 1575 1576 INIT_DEBUGOUT("ixl_media_change: begin"); 1577 1578 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1579 return (EINVAL); 1580 1581 if_printf(ifp, "Media change is currently not supported.\n"); 1582 1583 return (ENODEV); 1584} 1585 1586 1587#ifdef IXL_FDIR 1588/* 1589** ATR: Application Targetted Receive - creates a filter 1590** based on TX flow info that will keep the receive 1591** portion of the flow on the same queue. Based on the 1592** implementation this is only available for TCP connections 1593*/ 1594void 1595ixl_atr(struct ixl_queue *que, struct tcphdr *th, int etype) 1596{ 1597 struct ixl_vsi *vsi = que->vsi; 1598 struct tx_ring *txr = &que->txr; 1599 struct i40e_filter_program_desc *FDIR; 1600 u32 ptype, dtype; 1601 int idx; 1602 1603 /* check if ATR is enabled and sample rate */ 1604 if ((!ixl_enable_fdir) || (!txr->atr_rate)) 1605 return; 1606 /* 1607 ** We sample all TCP SYN/FIN packets, 1608 ** or at the selected sample rate 1609 */ 1610 txr->atr_count++; 1611 if (((th->th_flags & (TH_FIN | TH_SYN)) == 0) && 1612 (txr->atr_count < txr->atr_rate)) 1613 return; 1614 txr->atr_count = 0; 1615 1616 /* Get a descriptor to use */ 1617 idx = txr->next_avail; 1618 FDIR = (struct i40e_filter_program_desc *) &txr->base[idx]; 1619 if (++idx == que->num_desc) 1620 idx = 0; 1621 txr->avail--; 1622 txr->next_avail = idx; 1623 1624 ptype = (que->me << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 1625 I40E_TXD_FLTR_QW0_QINDEX_MASK; 1626 1627 ptype |= (etype == ETHERTYPE_IP) ? 1628 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 1629 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 1630 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 1631 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 1632 1633 ptype |= vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 1634 1635 dtype = I40E_TX_DESC_DTYPE_FILTER_PROG; 1636 1637 /* 1638 ** We use the TCP TH_FIN as a trigger to remove 1639 ** the filter, otherwise its an update. 1640 */ 1641 dtype |= (th->th_flags & TH_FIN) ? 1642 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 1643 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 1644 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 1645 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 1646 1647 dtype |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 1648 I40E_TXD_FLTR_QW1_DEST_SHIFT; 1649 1650 dtype |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 1651 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 1652 1653 FDIR->qindex_flex_ptype_vsi = htole32(ptype); 1654 FDIR->dtype_cmd_cntindex = htole32(dtype); 1655 return; 1656} 1657#endif 1658 1659 1660static void 1661ixl_set_promisc(struct ixl_vsi *vsi) 1662{ 1663 struct ifnet *ifp = vsi->ifp; 1664 struct i40e_hw *hw = vsi->hw; 1665 int err, mcnt = 0; 1666 bool uni = FALSE, multi = FALSE; 1667 1668 if (ifp->if_flags & IFF_ALLMULTI) 1669 multi = TRUE; 1670 else { /* Need to count the multicast addresses */ 1671 struct ifmultiaddr *ifma; 1672 if_maddr_rlock(ifp); 1673 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1674 if (ifma->ifma_addr->sa_family != AF_LINK) 1675 continue; 1676 if (mcnt == MAX_MULTICAST_ADDR) 1677 break; 1678 mcnt++; 1679 } 1680 if_maddr_runlock(ifp); 1681 } 1682 1683 if (mcnt >= MAX_MULTICAST_ADDR) 1684 multi = TRUE; 1685 if (ifp->if_flags & IFF_PROMISC) 1686 uni = TRUE; 1687 1688 err = i40e_aq_set_vsi_unicast_promiscuous(hw, 1689 vsi->seid, uni, NULL); 1690 err = i40e_aq_set_vsi_multicast_promiscuous(hw, 1691 vsi->seid, multi, NULL); 1692 return; 1693} 1694 1695/********************************************************************* 1696 * Filter Routines 1697 * 1698 * Routines for multicast and vlan filter management. 1699 * 1700 *********************************************************************/ 1701static void 1702ixl_add_multi(struct ixl_vsi *vsi) 1703{ 1704 struct ifmultiaddr *ifma; 1705 struct ifnet *ifp = vsi->ifp; 1706 struct i40e_hw *hw = vsi->hw; 1707 int mcnt = 0, flags; 1708 1709 IOCTL_DEBUGOUT("ixl_add_multi: begin"); 1710 1711 if_maddr_rlock(ifp); 1712 /* 1713 ** First just get a count, to decide if we 1714 ** we simply use multicast promiscuous. 1715 */ 1716 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1717 if (ifma->ifma_addr->sa_family != AF_LINK) 1718 continue; 1719 mcnt++; 1720 } 1721 if_maddr_runlock(ifp); 1722 1723 if (__predict_false(mcnt >= MAX_MULTICAST_ADDR)) { 1724 /* delete existing MC filters */ 1725 ixl_del_hw_filters(vsi, mcnt); 1726 i40e_aq_set_vsi_multicast_promiscuous(hw, 1727 vsi->seid, TRUE, NULL); 1728 return; 1729 } 1730 1731 mcnt = 0; 1732 if_maddr_rlock(ifp); 1733 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1734 if (ifma->ifma_addr->sa_family != AF_LINK) 1735 continue; 1736 ixl_add_mc_filter(vsi, 1737 (u8*)LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 1738 mcnt++; 1739 } 1740 if_maddr_runlock(ifp); 1741 if (mcnt > 0) { 1742 flags = (IXL_FILTER_ADD | IXL_FILTER_USED | IXL_FILTER_MC); 1743 ixl_add_hw_filters(vsi, flags, mcnt); 1744 } 1745 1746 IOCTL_DEBUGOUT("ixl_add_multi: end"); 1747 return; 1748} 1749 1750static void 1751ixl_del_multi(struct ixl_vsi *vsi) 1752{ 1753 struct ifnet *ifp = vsi->ifp; 1754 struct ifmultiaddr *ifma; 1755 struct ixl_mac_filter *f; 1756 int mcnt = 0; 1757 bool match = FALSE; 1758 1759 IOCTL_DEBUGOUT("ixl_del_multi: begin"); 1760 1761 /* Search for removed multicast addresses */ 1762 if_maddr_rlock(ifp); 1763 SLIST_FOREACH(f, &vsi->ftl, next) { 1764 if ((f->flags & IXL_FILTER_USED) && (f->flags & IXL_FILTER_MC)) { 1765 match = FALSE; 1766 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1767 if (ifma->ifma_addr->sa_family != AF_LINK) 1768 continue; 1769 u8 *mc_addr = (u8 *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1770 if (cmp_etheraddr(f->macaddr, mc_addr)) { 1771 match = TRUE; 1772 break; 1773 } 1774 } 1775 if (match == FALSE) { 1776 f->flags |= IXL_FILTER_DEL; 1777 mcnt++; 1778 } 1779 } 1780 } 1781 if_maddr_runlock(ifp); 1782 1783 if (mcnt > 0) 1784 ixl_del_hw_filters(vsi, mcnt); 1785} 1786 1787 1788/********************************************************************* 1789 * Timer routine 1790 * 1791 * This routine checks for link status,updates statistics, 1792 * and runs the watchdog check. 1793 * 1794 **********************************************************************/ 1795 1796static void 1797ixl_local_timer(void *arg) 1798{ 1799 struct ixl_pf *pf = arg; 1800 struct i40e_hw *hw = &pf->hw; 1801 struct ixl_vsi *vsi = &pf->vsi; 1802 struct ixl_queue *que = vsi->queues; 1803 device_t dev = pf->dev; 1804 int hung = 0; 1805 u32 mask; 1806 1807 mtx_assert(&pf->pf_mtx, MA_OWNED); 1808 1809 /* Fire off the adminq task */ 1810 taskqueue_enqueue(pf->tq, &pf->adminq); 1811 1812 /* Update stats */ 1813 ixl_update_stats_counters(pf); 1814 1815 /* 1816 ** Check status of the queues 1817 */ 1818 mask = (I40E_PFINT_DYN_CTLN_INTENA_MASK | 1819 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK); 1820 1821 for (int i = 0; i < vsi->num_queues; i++,que++) { 1822 /* Any queues with outstanding work get a sw irq */ 1823 if (que->busy) 1824 wr32(hw, I40E_PFINT_DYN_CTLN(que->me), mask); 1825 /* 1826 ** Each time txeof runs without cleaning, but there 1827 ** are uncleaned descriptors it increments busy. If 1828 ** we get to 5 we declare it hung. 1829 */ 1830 if (que->busy == IXL_QUEUE_HUNG) { 1831 ++hung; 1832 /* Mark the queue as inactive */ 1833 vsi->active_queues &= ~((u64)1 << que->me); 1834 continue; 1835 } else { 1836 /* Check if we've come back from hung */ 1837 if ((vsi->active_queues & ((u64)1 << que->me)) == 0) 1838 vsi->active_queues |= ((u64)1 << que->me); 1839 } 1840 if (que->busy >= IXL_MAX_TX_BUSY) { 1841#ifdef IXL_DEBUG 1842 device_printf(dev,"Warning queue %d " 1843 "appears to be hung!\n", i); 1844#endif 1845 que->busy = IXL_QUEUE_HUNG; 1846 ++hung; 1847 } 1848 } 1849 /* Only reinit if all queues show hung */ 1850 if (hung == vsi->num_queues) 1851 goto hung; 1852 1853 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1854 return; 1855 1856hung: 1857 device_printf(dev, "Local Timer: HANG DETECT - Resetting!!\n"); 1858 ixl_init_locked(pf); 1859} 1860 1861/* 1862** Note: this routine updates the OS on the link state 1863** the real check of the hardware only happens with 1864** a link interrupt. 1865*/ 1866static void 1867ixl_update_link_status(struct ixl_pf *pf) 1868{ 1869 struct ixl_vsi *vsi = &pf->vsi; 1870 struct i40e_hw *hw = &pf->hw; 1871 struct ifnet *ifp = vsi->ifp; 1872 device_t dev = pf->dev; 1873 1874 if (pf->link_up){ 1875 if (vsi->link_active == FALSE) { 1876 pf->fc = hw->fc.current_mode; 1877 if (bootverbose) { 1878 device_printf(dev,"Link is up %d Gbps %s," 1879 " Flow Control: %s\n", 1880 ((pf->link_speed == 1881 I40E_LINK_SPEED_40GB)? 40:10), 1882 "Full Duplex", ixl_fc_string[pf->fc]); 1883 } 1884 vsi->link_active = TRUE; 1885 /* 1886 ** Warn user if link speed on NPAR enabled 1887 ** partition is not at least 10GB 1888 */ 1889 if (hw->func_caps.npar_enable && 1890 (hw->phy.link_info.link_speed == 1891 I40E_LINK_SPEED_1GB || 1892 hw->phy.link_info.link_speed == 1893 I40E_LINK_SPEED_100MB)) 1894 device_printf(dev, "The partition detected" 1895 "link speed that is less than 10Gbps\n"); 1896 if_link_state_change(ifp, LINK_STATE_UP); 1897 } 1898 } else { /* Link down */ 1899 if (vsi->link_active == TRUE) { 1900 if (bootverbose) 1901 device_printf(dev,"Link is Down\n"); 1902 if_link_state_change(ifp, LINK_STATE_DOWN); 1903 vsi->link_active = FALSE; 1904 } 1905 } 1906 1907 return; 1908} 1909 1910/********************************************************************* 1911 * 1912 * This routine disables all traffic on the adapter by issuing a 1913 * global reset on the MAC and deallocates TX/RX buffers. 1914 * 1915 **********************************************************************/ 1916 1917static void 1918ixl_stop(struct ixl_pf *pf) 1919{ 1920 struct ixl_vsi *vsi = &pf->vsi; 1921 struct ifnet *ifp = vsi->ifp; 1922 1923 mtx_assert(&pf->pf_mtx, MA_OWNED); 1924 1925 INIT_DEBUGOUT("ixl_stop: begin\n"); 1926 if (pf->num_vfs == 0) 1927 ixl_disable_intr(vsi); 1928 else 1929 ixl_disable_rings_intr(vsi); 1930 ixl_disable_rings(vsi); 1931 1932 /* Tell the stack that the interface is no longer active */ 1933 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1934 1935 /* Stop the local timer */ 1936 callout_stop(&pf->timer); 1937 1938 return; 1939} 1940 1941 1942/********************************************************************* 1943 * 1944 * Setup MSIX Interrupt resources and handlers for the VSI 1945 * 1946 **********************************************************************/ 1947static int 1948ixl_assign_vsi_legacy(struct ixl_pf *pf) 1949{ 1950 device_t dev = pf->dev; 1951 struct ixl_vsi *vsi = &pf->vsi; 1952 struct ixl_queue *que = vsi->queues; 1953 int error, rid = 0; 1954 1955 if (pf->msix == 1) 1956 rid = 1; 1957 pf->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1958 &rid, RF_SHAREABLE | RF_ACTIVE); 1959 if (pf->res == NULL) { 1960 device_printf(dev,"Unable to allocate" 1961 " bus resource: vsi legacy/msi interrupt\n"); 1962 return (ENXIO); 1963 } 1964 1965 /* Set the handler function */ 1966 error = bus_setup_intr(dev, pf->res, 1967 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1968 ixl_intr, pf, &pf->tag); 1969 if (error) { 1970 pf->res = NULL; 1971 device_printf(dev, "Failed to register legacy/msi handler"); 1972 return (error); 1973 } 1974 bus_describe_intr(dev, pf->res, pf->tag, "irq0"); 1975 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 1976 TASK_INIT(&que->task, 0, ixl_handle_que, que); 1977 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 1978 taskqueue_thread_enqueue, &que->tq); 1979 taskqueue_start_threads(&que->tq, 1, PI_NET, "%s que", 1980 device_get_nameunit(dev)); 1981 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 1982 1983#ifdef PCI_IOV 1984 TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf); 1985#endif 1986 1987 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 1988 taskqueue_thread_enqueue, &pf->tq); 1989 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 1990 device_get_nameunit(dev)); 1991 1992 return (0); 1993} 1994 1995 1996/********************************************************************* 1997 * 1998 * Setup MSIX Interrupt resources and handlers for the VSI 1999 * 2000 **********************************************************************/ 2001static int 2002ixl_assign_vsi_msix(struct ixl_pf *pf) 2003{ 2004 device_t dev = pf->dev; 2005 struct ixl_vsi *vsi = &pf->vsi; 2006 struct ixl_queue *que = vsi->queues; 2007 struct tx_ring *txr; 2008 int error, rid, vector = 0; 2009 2010 /* Admin Que is vector 0*/ 2011 rid = vector + 1; 2012 pf->res = bus_alloc_resource_any(dev, 2013 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 2014 if (!pf->res) { 2015 device_printf(dev,"Unable to allocate" 2016 " bus resource: Adminq interrupt [%d]\n", rid); 2017 return (ENXIO); 2018 } 2019 /* Set the adminq vector and handler */ 2020 error = bus_setup_intr(dev, pf->res, 2021 INTR_TYPE_NET | INTR_MPSAFE, NULL, 2022 ixl_msix_adminq, pf, &pf->tag); 2023 if (error) { 2024 pf->res = NULL; 2025 device_printf(dev, "Failed to register Admin que handler"); 2026 return (error); 2027 } 2028 bus_describe_intr(dev, pf->res, pf->tag, "aq"); 2029 pf->admvec = vector; 2030 /* Tasklet for Admin Queue */ 2031 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 2032 2033#ifdef PCI_IOV 2034 TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf); 2035#endif 2036 2037 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 2038 taskqueue_thread_enqueue, &pf->tq); 2039 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 2040 device_get_nameunit(pf->dev)); 2041 ++vector; 2042 2043 /* Now set up the stations */ 2044 for (int i = 0; i < vsi->num_queues; i++, vector++, que++) { 2045 int cpu_id = i; 2046 rid = vector + 1; 2047 txr = &que->txr; 2048 que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2049 RF_SHAREABLE | RF_ACTIVE); 2050 if (que->res == NULL) { 2051 device_printf(dev,"Unable to allocate" 2052 " bus resource: que interrupt [%d]\n", vector); 2053 return (ENXIO); 2054 } 2055 /* Set the handler function */ 2056 error = bus_setup_intr(dev, que->res, 2057 INTR_TYPE_NET | INTR_MPSAFE, NULL, 2058 ixl_msix_que, que, &que->tag); 2059 if (error) { 2060 que->res = NULL; 2061 device_printf(dev, "Failed to register que handler"); 2062 return (error); 2063 } 2064 bus_describe_intr(dev, que->res, que->tag, "q%d", i); 2065 /* Bind the vector to a CPU */ 2066#ifdef RSS 2067 cpu_id = rss_getcpu(i % rss_getnumbuckets()); 2068#endif 2069 bus_bind_intr(dev, que->res, cpu_id); 2070 que->msix = vector; 2071 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 2072 TASK_INIT(&que->task, 0, ixl_handle_que, que); 2073 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 2074 taskqueue_thread_enqueue, &que->tq); 2075#ifdef RSS 2076 taskqueue_start_threads_pinned(&que->tq, 1, PI_NET, 2077 cpu_id, "%s (bucket %d)", 2078 device_get_nameunit(dev), cpu_id); 2079#else 2080 taskqueue_start_threads(&que->tq, 1, PI_NET, 2081 "%s que", device_get_nameunit(dev)); 2082#endif 2083 } 2084 2085 return (0); 2086} 2087 2088 2089/* 2090 * Allocate MSI/X vectors 2091 */ 2092static int 2093ixl_init_msix(struct ixl_pf *pf) 2094{ 2095 device_t dev = pf->dev; 2096 int rid, want, vectors, queues, available; 2097 2098 /* Override by tuneable */ 2099 if (ixl_enable_msix == 0) 2100 goto msi; 2101 2102 /* 2103 ** When used in a virtualized environment 2104 ** PCI BUSMASTER capability may not be set 2105 ** so explicity set it here and rewrite 2106 ** the ENABLE in the MSIX control register 2107 ** at this point to cause the host to 2108 ** successfully initialize us. 2109 */ 2110 { 2111 u16 pci_cmd_word; 2112 int msix_ctrl; 2113 pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2114 pci_cmd_word |= PCIM_CMD_BUSMASTEREN; 2115 pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2); 2116 pci_find_cap(dev, PCIY_MSIX, &rid); 2117 rid += PCIR_MSIX_CTRL; 2118 msix_ctrl = pci_read_config(dev, rid, 2); 2119 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 2120 pci_write_config(dev, rid, msix_ctrl, 2); 2121 } 2122 2123 /* First try MSI/X */ 2124 rid = PCIR_BAR(IXL_BAR); 2125 pf->msix_mem = bus_alloc_resource_any(dev, 2126 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2127 if (!pf->msix_mem) { 2128 /* May not be enabled */ 2129 device_printf(pf->dev, 2130 "Unable to map MSIX table \n"); 2131 goto msi; 2132 } 2133 2134 available = pci_msix_count(dev); 2135 if (available == 0) { /* system has msix disabled */ 2136 bus_release_resource(dev, SYS_RES_MEMORY, 2137 rid, pf->msix_mem); 2138 pf->msix_mem = NULL; 2139 goto msi; 2140 } 2141 2142 /* Figure out a reasonable auto config value */ 2143 queues = (mp_ncpus > (available - 1)) ? (available - 1) : mp_ncpus; 2144 2145 /* Override with hardcoded value if sane */ 2146 if ((ixl_max_queues != 0) && (ixl_max_queues <= queues)) 2147 queues = ixl_max_queues; 2148 2149#ifdef RSS 2150 /* If we're doing RSS, clamp at the number of RSS buckets */ 2151 if (queues > rss_getnumbuckets()) 2152 queues = rss_getnumbuckets(); 2153#endif 2154 2155 /* 2156 ** Want one vector (RX/TX pair) per queue 2157 ** plus an additional for the admin queue. 2158 */ 2159 want = queues + 1; 2160 if (want <= available) /* Have enough */ 2161 vectors = want; 2162 else { 2163 device_printf(pf->dev, 2164 "MSIX Configuration Problem, " 2165 "%d vectors available but %d wanted!\n", 2166 available, want); 2167 return (0); /* Will go to Legacy setup */ 2168 } 2169 2170 if (pci_alloc_msix(dev, &vectors) == 0) { 2171 device_printf(pf->dev, 2172 "Using MSIX interrupts with %d vectors\n", vectors); 2173 pf->msix = vectors; 2174 pf->vsi.num_queues = queues; 2175#ifdef RSS 2176 /* 2177 * If we're doing RSS, the number of queues needs to 2178 * match the number of RSS buckets that are configured. 2179 * 2180 * + If there's more queues than RSS buckets, we'll end 2181 * up with queues that get no traffic. 2182 * 2183 * + If there's more RSS buckets than queues, we'll end 2184 * up having multiple RSS buckets map to the same queue, 2185 * so there'll be some contention. 2186 */ 2187 if (queues != rss_getnumbuckets()) { 2188 device_printf(dev, 2189 "%s: queues (%d) != RSS buckets (%d)" 2190 "; performance will be impacted.\n", 2191 __func__, queues, rss_getnumbuckets()); 2192 } 2193#endif 2194 return (vectors); 2195 } 2196msi: 2197 vectors = pci_msi_count(dev); 2198 pf->vsi.num_queues = 1; 2199 pf->msix = 1; 2200 ixl_max_queues = 1; 2201 ixl_enable_msix = 0; 2202 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) 2203 device_printf(pf->dev,"Using an MSI interrupt\n"); 2204 else { 2205 pf->msix = 0; 2206 device_printf(pf->dev,"Using a Legacy interrupt\n"); 2207 } 2208 return (vectors); 2209} 2210 2211 2212/* 2213 * Plumb MSI/X vectors 2214 */ 2215static void 2216ixl_configure_msix(struct ixl_pf *pf) 2217{ 2218 struct i40e_hw *hw = &pf->hw; 2219 struct ixl_vsi *vsi = &pf->vsi; 2220 u32 reg; 2221 u16 vector = 1; 2222 2223 /* First set up the adminq - vector 0 */ 2224 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ 2225 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ 2226 2227 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 2228 I40E_PFINT_ICR0_ENA_GRST_MASK | 2229 I40E_PFINT_ICR0_HMC_ERR_MASK | 2230 I40E_PFINT_ICR0_ENA_ADMINQ_MASK | 2231 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 2232 I40E_PFINT_ICR0_ENA_VFLR_MASK | 2233 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK; 2234 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2235 2236 wr32(hw, I40E_PFINT_LNKLST0, 0x7FF); 2237 wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR), 0x003E); 2238 2239 wr32(hw, I40E_PFINT_DYN_CTL0, 2240 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | 2241 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); 2242 2243 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2244 2245 /* Next configure the queues */ 2246 for (int i = 0; i < vsi->num_queues; i++, vector++) { 2247 wr32(hw, I40E_PFINT_DYN_CTLN(i), i); 2248 wr32(hw, I40E_PFINT_LNKLSTN(i), i); 2249 2250 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK | 2251 (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2252 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2253 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2254 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); 2255 wr32(hw, I40E_QINT_RQCTL(i), reg); 2256 2257 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK | 2258 (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2259 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2260 ((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2261 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2262 if (i == (vsi->num_queues - 1)) 2263 reg |= (IXL_QUEUE_EOL 2264 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2265 wr32(hw, I40E_QINT_TQCTL(i), reg); 2266 } 2267} 2268 2269/* 2270 * Configure for MSI single vector operation 2271 */ 2272static void 2273ixl_configure_legacy(struct ixl_pf *pf) 2274{ 2275 struct i40e_hw *hw = &pf->hw; 2276 u32 reg; 2277 2278 2279 wr32(hw, I40E_PFINT_ITR0(0), 0); 2280 wr32(hw, I40E_PFINT_ITR0(1), 0); 2281 2282 2283 /* Setup "other" causes */ 2284 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK 2285 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK 2286 | I40E_PFINT_ICR0_ENA_GRST_MASK 2287 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK 2288 | I40E_PFINT_ICR0_ENA_GPIO_MASK 2289 | I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK 2290 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK 2291 | I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK 2292 | I40E_PFINT_ICR0_ENA_VFLR_MASK 2293 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK 2294 ; 2295 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2296 2297 /* SW_ITR_IDX = 0, but don't change INTENA */ 2298 wr32(hw, I40E_PFINT_DYN_CTL0, 2299 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK | 2300 I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK); 2301 /* SW_ITR_IDX = 0, OTHER_ITR_IDX = 0 */ 2302 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2303 2304 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ 2305 wr32(hw, I40E_PFINT_LNKLST0, 0); 2306 2307 /* Associate the queue pair to the vector and enable the q int */ 2308 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK 2309 | (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) 2310 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2311 wr32(hw, I40E_QINT_RQCTL(0), reg); 2312 2313 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK 2314 | (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) 2315 | (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2316 wr32(hw, I40E_QINT_TQCTL(0), reg); 2317 2318 /* Next enable the queue pair */ 2319 reg = rd32(hw, I40E_QTX_ENA(0)); 2320 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 2321 wr32(hw, I40E_QTX_ENA(0), reg); 2322 2323 reg = rd32(hw, I40E_QRX_ENA(0)); 2324 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 2325 wr32(hw, I40E_QRX_ENA(0), reg); 2326} 2327 2328 2329/* 2330 * Set the Initial ITR state 2331 */ 2332static void 2333ixl_configure_itr(struct ixl_pf *pf) 2334{ 2335 struct i40e_hw *hw = &pf->hw; 2336 struct ixl_vsi *vsi = &pf->vsi; 2337 struct ixl_queue *que = vsi->queues; 2338 2339 vsi->rx_itr_setting = ixl_rx_itr; 2340 if (ixl_dynamic_rx_itr) 2341 vsi->rx_itr_setting |= IXL_ITR_DYNAMIC; 2342 vsi->tx_itr_setting = ixl_tx_itr; 2343 if (ixl_dynamic_tx_itr) 2344 vsi->tx_itr_setting |= IXL_ITR_DYNAMIC; 2345 2346 for (int i = 0; i < vsi->num_queues; i++, que++) { 2347 struct tx_ring *txr = &que->txr; 2348 struct rx_ring *rxr = &que->rxr; 2349 2350 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i), 2351 vsi->rx_itr_setting); 2352 rxr->itr = vsi->rx_itr_setting; 2353 rxr->latency = IXL_AVE_LATENCY; 2354 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i), 2355 vsi->tx_itr_setting); 2356 txr->itr = vsi->tx_itr_setting; 2357 txr->latency = IXL_AVE_LATENCY; 2358 } 2359} 2360 2361 2362static int 2363ixl_allocate_pci_resources(struct ixl_pf *pf) 2364{ 2365 int rid; 2366 device_t dev = pf->dev; 2367 2368 rid = PCIR_BAR(0); 2369 pf->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2370 &rid, RF_ACTIVE); 2371 2372 if (!(pf->pci_mem)) { 2373 device_printf(dev,"Unable to allocate bus resource: memory\n"); 2374 return (ENXIO); 2375 } 2376 2377 pf->osdep.mem_bus_space_tag = 2378 rman_get_bustag(pf->pci_mem); 2379 pf->osdep.mem_bus_space_handle = 2380 rman_get_bushandle(pf->pci_mem); 2381 pf->osdep.mem_bus_space_size = rman_get_size(pf->pci_mem); 2382 pf->osdep.flush_reg = I40E_GLGEN_STAT; 2383 pf->hw.hw_addr = (u8 *) &pf->osdep.mem_bus_space_handle; 2384 2385 pf->hw.back = &pf->osdep; 2386 2387 /* 2388 ** Now setup MSI or MSI/X, should 2389 ** return us the number of supported 2390 ** vectors. (Will be 1 for MSI) 2391 */ 2392 pf->msix = ixl_init_msix(pf); 2393 return (0); 2394} 2395 2396static void 2397ixl_free_pci_resources(struct ixl_pf * pf) 2398{ 2399 struct ixl_vsi *vsi = &pf->vsi; 2400 struct ixl_queue *que = vsi->queues; 2401 device_t dev = pf->dev; 2402 int rid, memrid; 2403 2404 memrid = PCIR_BAR(IXL_BAR); 2405 2406 /* We may get here before stations are setup */ 2407 if ((!ixl_enable_msix) || (que == NULL)) 2408 goto early; 2409 2410 /* 2411 ** Release all msix VSI resources: 2412 */ 2413 for (int i = 0; i < vsi->num_queues; i++, que++) { 2414 rid = que->msix + 1; 2415 if (que->tag != NULL) { 2416 bus_teardown_intr(dev, que->res, que->tag); 2417 que->tag = NULL; 2418 } 2419 if (que->res != NULL) 2420 bus_release_resource(dev, SYS_RES_IRQ, rid, que->res); 2421 } 2422 2423early: 2424 /* Clean the AdminQ interrupt last */ 2425 if (pf->admvec) /* we are doing MSIX */ 2426 rid = pf->admvec + 1; 2427 else 2428 (pf->msix != 0) ? (rid = 1):(rid = 0); 2429 2430 if (pf->tag != NULL) { 2431 bus_teardown_intr(dev, pf->res, pf->tag); 2432 pf->tag = NULL; 2433 } 2434 if (pf->res != NULL) 2435 bus_release_resource(dev, SYS_RES_IRQ, rid, pf->res); 2436 2437 if (pf->msix) 2438 pci_release_msi(dev); 2439 2440 if (pf->msix_mem != NULL) 2441 bus_release_resource(dev, SYS_RES_MEMORY, 2442 memrid, pf->msix_mem); 2443 2444 if (pf->pci_mem != NULL) 2445 bus_release_resource(dev, SYS_RES_MEMORY, 2446 PCIR_BAR(0), pf->pci_mem); 2447 2448 return; 2449} 2450 2451static void 2452ixl_add_ifmedia(struct ixl_vsi *vsi, u32 phy_type) 2453{ 2454 /* Display supported media types */ 2455 if (phy_type & (1 << I40E_PHY_TYPE_100BASE_TX)) 2456 ifmedia_add(&vsi->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2457 2458 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_T)) 2459 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2460 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_SX)) 2461 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 2462 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_LX)) 2463 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_LX, 0, NULL); 2464 2465 if (phy_type & (1 << I40E_PHY_TYPE_XAUI) || 2466 phy_type & (1 << I40E_PHY_TYPE_XFI) || 2467 phy_type & (1 << I40E_PHY_TYPE_10GBASE_SFPP_CU)) 2468 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL); 2469 2470 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_SR)) 2471 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 2472 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_LR)) 2473 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 2474 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_T)) 2475 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_T, 0, NULL); 2476 2477 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4) || 2478 phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4_CU) || 2479 phy_type & (1 << I40E_PHY_TYPE_40GBASE_AOC) || 2480 phy_type & (1 << I40E_PHY_TYPE_XLAUI) || 2481 phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2482 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL); 2483 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_SR4)) 2484 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL); 2485 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_LR4)) 2486 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_LR4, 0, NULL); 2487 2488#ifndef IFM_ETH_XTYPE 2489 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_KX)) 2490 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 2491 2492 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) || 2493 phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1) || 2494 phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC) || 2495 phy_type & (1 << I40E_PHY_TYPE_SFI)) 2496 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL); 2497 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4)) 2498 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 2499 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR)) 2500 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 2501 2502 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2503 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL); 2504 if (phy_type & (1 << I40E_PHY_TYPE_XLPPI)) 2505 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL); 2506#else 2507 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_KX)) 2508 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 2509 2510 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) 2511 || phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1)) 2512 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CR1, 0, NULL); 2513 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC)) 2514 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX_LONG, 0, NULL); 2515 if (phy_type & (1 << I40E_PHY_TYPE_SFI)) 2516 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SFI, 0, NULL); 2517 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4)) 2518 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KX4, 0, NULL); 2519 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR)) 2520 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 2521 2522 if (phy_type & (1 << I40E_PHY_TYPE_20GBASE_KR2)) 2523 ifmedia_add(&vsi->media, IFM_ETHER | IFM_20G_KR2, 0, NULL); 2524 2525 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2526 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_KR4, 0, NULL); 2527 if (phy_type & (1 << I40E_PHY_TYPE_XLPPI)) 2528 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_XLPPI, 0, NULL); 2529#endif 2530} 2531 2532/********************************************************************* 2533 * 2534 * Setup networking device structure and register an interface. 2535 * 2536 **********************************************************************/ 2537static int 2538ixl_setup_interface(device_t dev, struct ixl_vsi *vsi) 2539{ 2540 struct ifnet *ifp; 2541 struct i40e_hw *hw = vsi->hw; 2542 struct ixl_queue *que = vsi->queues; 2543 struct i40e_aq_get_phy_abilities_resp abilities; 2544 enum i40e_status_code aq_error = 0; 2545 2546 INIT_DEBUGOUT("ixl_setup_interface: begin"); 2547 2548 ifp = vsi->ifp = if_alloc(IFT_ETHER); 2549 if (ifp == NULL) { 2550 device_printf(dev, "can not allocate ifnet structure\n"); 2551 return (-1); 2552 } 2553 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2554 ifp->if_mtu = ETHERMTU; 2555 if_initbaudrate(ifp, IF_Gbps(40)); 2556 ifp->if_init = ixl_init; 2557 ifp->if_softc = vsi; 2558 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2559 ifp->if_ioctl = ixl_ioctl; 2560 2561#if __FreeBSD_version >= 1100036 2562 if_setgetcounterfn(ifp, ixl_get_counter); 2563#endif 2564 2565 ifp->if_transmit = ixl_mq_start; 2566 2567 ifp->if_qflush = ixl_qflush; 2568 2569 ifp->if_snd.ifq_maxlen = que->num_desc - 2; 2570 2571 vsi->max_frame_size = 2572 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 2573 + ETHER_VLAN_ENCAP_LEN; 2574 2575 /* 2576 * Tell the upper layer(s) we support long frames. 2577 */ 2578 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2579 2580 ifp->if_capabilities |= IFCAP_HWCSUM; 2581 ifp->if_capabilities |= IFCAP_HWCSUM_IPV6; 2582 ifp->if_capabilities |= IFCAP_TSO; 2583 ifp->if_capabilities |= IFCAP_JUMBO_MTU; 2584 ifp->if_capabilities |= IFCAP_LRO; 2585 2586 /* VLAN capabilties */ 2587 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING 2588 | IFCAP_VLAN_HWTSO 2589 | IFCAP_VLAN_MTU 2590 | IFCAP_VLAN_HWCSUM; 2591 ifp->if_capenable = ifp->if_capabilities; 2592 2593 /* 2594 ** Don't turn this on by default, if vlans are 2595 ** created on another pseudo device (eg. lagg) 2596 ** then vlan events are not passed thru, breaking 2597 ** operation, but with HW FILTER off it works. If 2598 ** using vlans directly on the ixl driver you can 2599 ** enable this and get full hardware tag filtering. 2600 */ 2601 ifp->if_capabilities |= IFCAP_VLAN_HWFILTER; 2602 2603 /* 2604 * Specify the media types supported by this adapter and register 2605 * callbacks to update media and link information 2606 */ 2607 ifmedia_init(&vsi->media, IFM_IMASK, ixl_media_change, 2608 ixl_media_status); 2609 2610 aq_error = i40e_aq_get_phy_capabilities(hw, 2611 FALSE, TRUE, &abilities, NULL); 2612 /* May need delay to detect fiber correctly */ 2613 if (aq_error == I40E_ERR_UNKNOWN_PHY) { 2614 i40e_msec_delay(200); 2615 aq_error = i40e_aq_get_phy_capabilities(hw, FALSE, 2616 TRUE, &abilities, NULL); 2617 } 2618 if (aq_error) { 2619 if (aq_error == I40E_ERR_UNKNOWN_PHY) 2620 device_printf(dev, "Unknown PHY type detected!\n"); 2621 else 2622 device_printf(dev, 2623 "Error getting supported media types, err %d," 2624 " AQ error %d\n", aq_error, hw->aq.asq_last_status); 2625 return (0); 2626 } 2627 2628 ixl_add_ifmedia(vsi, abilities.phy_type); 2629 2630 /* Use autoselect media by default */ 2631 ifmedia_add(&vsi->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2632 ifmedia_set(&vsi->media, IFM_ETHER | IFM_AUTO); 2633 2634 ether_ifattach(ifp, hw->mac.addr); 2635 2636 return (0); 2637} 2638 2639/* 2640** Run when the Admin Queue gets a 2641** link transition interrupt. 2642*/ 2643static void 2644ixl_link_event(struct ixl_pf *pf, struct i40e_arq_event_info *e) 2645{ 2646 struct i40e_hw *hw = &pf->hw; 2647 struct i40e_aqc_get_link_status *status = 2648 (struct i40e_aqc_get_link_status *)&e->desc.params.raw; 2649 bool check; 2650 2651 hw->phy.get_link_info = TRUE; 2652 i40e_get_link_status(hw, &check); 2653 pf->link_up = check; 2654#ifdef IXL_DEBUG 2655 printf("Link is %s\n", check ? "up":"down"); 2656#endif 2657 /* Report if Unqualified modules are found */ 2658 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && 2659 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && 2660 (!(status->link_info & I40E_AQ_LINK_UP))) 2661 device_printf(pf->dev, "Link failed because " 2662 "an unqualified module was detected\n"); 2663 2664 return; 2665} 2666 2667/********************************************************************* 2668 * 2669 * Get Firmware Switch configuration 2670 * - this will need to be more robust when more complex 2671 * switch configurations are enabled. 2672 * 2673 **********************************************************************/ 2674static int 2675ixl_switch_config(struct ixl_pf *pf) 2676{ 2677 struct i40e_hw *hw = &pf->hw; 2678 struct ixl_vsi *vsi = &pf->vsi; 2679 device_t dev = vsi->dev; 2680 struct i40e_aqc_get_switch_config_resp *sw_config; 2681 u8 aq_buf[I40E_AQ_LARGE_BUF]; 2682 int ret; 2683 u16 next = 0; 2684 2685 memset(&aq_buf, 0, sizeof(aq_buf)); 2686 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 2687 ret = i40e_aq_get_switch_config(hw, sw_config, 2688 sizeof(aq_buf), &next, NULL); 2689 if (ret) { 2690 device_printf(dev,"aq_get_switch_config failed (ret=%d)!!\n", 2691 ret); 2692 return (ret); 2693 } 2694#ifdef IXL_DEBUG 2695 device_printf(dev, 2696 "Switch config: header reported: %d in structure, %d total\n", 2697 sw_config->header.num_reported, sw_config->header.num_total); 2698 for (int i = 0; i < sw_config->header.num_reported; i++) { 2699 device_printf(dev, 2700 "%d: type=%d seid=%d uplink=%d downlink=%d\n", i, 2701 sw_config->element[i].element_type, 2702 sw_config->element[i].seid, 2703 sw_config->element[i].uplink_seid, 2704 sw_config->element[i].downlink_seid); 2705 } 2706#endif 2707 /* Simplified due to a single VSI at the moment */ 2708 vsi->uplink_seid = sw_config->element[0].uplink_seid; 2709 vsi->downlink_seid = sw_config->element[0].downlink_seid; 2710 vsi->seid = sw_config->element[0].seid; 2711 return (ret); 2712} 2713 2714/********************************************************************* 2715 * 2716 * Initialize the VSI: this handles contexts, which means things 2717 * like the number of descriptors, buffer size, 2718 * plus we init the rings thru this function. 2719 * 2720 **********************************************************************/ 2721static int 2722ixl_initialize_vsi(struct ixl_vsi *vsi) 2723{ 2724 struct ixl_pf *pf = vsi->back; 2725 struct ixl_queue *que = vsi->queues; 2726 device_t dev = vsi->dev; 2727 struct i40e_hw *hw = vsi->hw; 2728 struct i40e_vsi_context ctxt; 2729 int err = 0; 2730 2731 memset(&ctxt, 0, sizeof(ctxt)); 2732 ctxt.seid = vsi->seid; 2733 if (pf->veb_seid != 0) 2734 ctxt.uplink_seid = pf->veb_seid; 2735 ctxt.pf_num = hw->pf_id; 2736 err = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 2737 if (err) { 2738 device_printf(dev,"get vsi params failed %x!!\n", err); 2739 return (err); 2740 } 2741#ifdef IXL_DEBUG 2742 printf("get_vsi_params: seid: %d, uplinkseid: %d, vsi_number: %d, " 2743 "vsis_allocated: %d, vsis_unallocated: %d, flags: 0x%x, " 2744 "pfnum: %d, vfnum: %d, stat idx: %d, enabled: %d\n", ctxt.seid, 2745 ctxt.uplink_seid, ctxt.vsi_number, 2746 ctxt.vsis_allocated, ctxt.vsis_unallocated, 2747 ctxt.flags, ctxt.pf_num, ctxt.vf_num, 2748 ctxt.info.stat_counter_idx, ctxt.info.up_enable_bits); 2749#endif 2750 /* 2751 ** Set the queue and traffic class bits 2752 ** - when multiple traffic classes are supported 2753 ** this will need to be more robust. 2754 */ 2755 ctxt.info.valid_sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; 2756 ctxt.info.mapping_flags |= I40E_AQ_VSI_QUE_MAP_CONTIG; 2757 ctxt.info.queue_mapping[0] = 0; 2758 ctxt.info.tc_mapping[0] = 0x0800; 2759 2760 /* Set VLAN receive stripping mode */ 2761 ctxt.info.valid_sections |= I40E_AQ_VSI_PROP_VLAN_VALID; 2762 ctxt.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL; 2763 if (vsi->ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2764 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 2765 else 2766 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 2767 2768 /* Keep copy of VSI info in VSI for statistic counters */ 2769 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 2770 2771 /* Reset VSI statistics */ 2772 ixl_vsi_reset_stats(vsi); 2773 vsi->hw_filters_add = 0; 2774 vsi->hw_filters_del = 0; 2775 2776 ctxt.flags = htole16(I40E_AQ_VSI_TYPE_PF); 2777 2778 err = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 2779 if (err) { 2780 device_printf(dev,"update vsi params failed %x!!\n", 2781 hw->aq.asq_last_status); 2782 return (err); 2783 } 2784 2785 for (int i = 0; i < vsi->num_queues; i++, que++) { 2786 struct tx_ring *txr = &que->txr; 2787 struct rx_ring *rxr = &que->rxr; 2788 struct i40e_hmc_obj_txq tctx; 2789 struct i40e_hmc_obj_rxq rctx; 2790 u32 txctl; 2791 u16 size; 2792 2793 2794 /* Setup the HMC TX Context */ 2795 size = que->num_desc * sizeof(struct i40e_tx_desc); 2796 memset(&tctx, 0, sizeof(struct i40e_hmc_obj_txq)); 2797 tctx.new_context = 1; 2798 tctx.base = (txr->dma.pa/IXL_TX_CTX_BASE_UNITS); 2799 tctx.qlen = que->num_desc; 2800 tctx.fc_ena = 0; 2801 tctx.rdylist = vsi->info.qs_handle[0]; /* index is TC */ 2802 /* Enable HEAD writeback */ 2803 tctx.head_wb_ena = 1; 2804 tctx.head_wb_addr = txr->dma.pa + 2805 (que->num_desc * sizeof(struct i40e_tx_desc)); 2806 tctx.rdylist_act = 0; 2807 err = i40e_clear_lan_tx_queue_context(hw, i); 2808 if (err) { 2809 device_printf(dev, "Unable to clear TX context\n"); 2810 break; 2811 } 2812 err = i40e_set_lan_tx_queue_context(hw, i, &tctx); 2813 if (err) { 2814 device_printf(dev, "Unable to set TX context\n"); 2815 break; 2816 } 2817 /* Associate the ring with this PF */ 2818 txctl = I40E_QTX_CTL_PF_QUEUE; 2819 txctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & 2820 I40E_QTX_CTL_PF_INDX_MASK); 2821 wr32(hw, I40E_QTX_CTL(i), txctl); 2822 ixl_flush(hw); 2823 2824 /* Do ring (re)init */ 2825 ixl_init_tx_ring(que); 2826 2827 /* Next setup the HMC RX Context */ 2828 if (vsi->max_frame_size <= MCLBYTES) 2829 rxr->mbuf_sz = MCLBYTES; 2830 else 2831 rxr->mbuf_sz = MJUMPAGESIZE; 2832 2833 u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len; 2834 2835 /* Set up an RX context for the HMC */ 2836 memset(&rctx, 0, sizeof(struct i40e_hmc_obj_rxq)); 2837 rctx.dbuff = rxr->mbuf_sz >> I40E_RXQ_CTX_DBUFF_SHIFT; 2838 /* ignore header split for now */ 2839 rctx.hbuff = 0 >> I40E_RXQ_CTX_HBUFF_SHIFT; 2840 rctx.rxmax = (vsi->max_frame_size < max_rxmax) ? 2841 vsi->max_frame_size : max_rxmax; 2842 rctx.dtype = 0; 2843 rctx.dsize = 1; /* do 32byte descriptors */ 2844 rctx.hsplit_0 = 0; /* no HDR split initially */ 2845 rctx.base = (rxr->dma.pa/IXL_RX_CTX_BASE_UNITS); 2846 rctx.qlen = que->num_desc; 2847 rctx.tphrdesc_ena = 1; 2848 rctx.tphwdesc_ena = 1; 2849 rctx.tphdata_ena = 0; 2850 rctx.tphhead_ena = 0; 2851 rctx.lrxqthresh = 2; 2852 rctx.crcstrip = 1; 2853 rctx.l2tsel = 1; 2854 rctx.showiv = 1; 2855 rctx.fc_ena = 0; 2856 rctx.prefena = 1; 2857 2858 err = i40e_clear_lan_rx_queue_context(hw, i); 2859 if (err) { 2860 device_printf(dev, 2861 "Unable to clear RX context %d\n", i); 2862 break; 2863 } 2864 err = i40e_set_lan_rx_queue_context(hw, i, &rctx); 2865 if (err) { 2866 device_printf(dev, "Unable to set RX context %d\n", i); 2867 break; 2868 } 2869 err = ixl_init_rx_ring(que); 2870 if (err) { 2871 device_printf(dev, "Fail in init_rx_ring %d\n", i); 2872 break; 2873 } 2874 wr32(vsi->hw, I40E_QRX_TAIL(que->me), 0); 2875#ifdef DEV_NETMAP 2876 /* preserve queue */ 2877 if (vsi->ifp->if_capenable & IFCAP_NETMAP) { 2878 struct netmap_adapter *na = NA(vsi->ifp); 2879 struct netmap_kring *kring = &na->rx_rings[i]; 2880 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 2881 wr32(vsi->hw, I40E_QRX_TAIL(que->me), t); 2882 } else 2883#endif /* DEV_NETMAP */ 2884 wr32(vsi->hw, I40E_QRX_TAIL(que->me), que->num_desc - 1); 2885 } 2886 return (err); 2887} 2888 2889 2890/********************************************************************* 2891 * 2892 * Free all VSI structs. 2893 * 2894 **********************************************************************/ 2895void 2896ixl_free_vsi(struct ixl_vsi *vsi) 2897{ 2898 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 2899 struct ixl_queue *que = vsi->queues; 2900 2901 /* Free station queues */ 2902 for (int i = 0; i < vsi->num_queues; i++, que++) { 2903 struct tx_ring *txr = &que->txr; 2904 struct rx_ring *rxr = &que->rxr; 2905 2906 if (!mtx_initialized(&txr->mtx)) /* uninitialized */ 2907 continue; 2908 IXL_TX_LOCK(txr); 2909 ixl_free_que_tx(que); 2910 if (txr->base) 2911 i40e_free_dma_mem(&pf->hw, &txr->dma); 2912 IXL_TX_UNLOCK(txr); 2913 IXL_TX_LOCK_DESTROY(txr); 2914 2915 if (!mtx_initialized(&rxr->mtx)) /* uninitialized */ 2916 continue; 2917 IXL_RX_LOCK(rxr); 2918 ixl_free_que_rx(que); 2919 if (rxr->base) 2920 i40e_free_dma_mem(&pf->hw, &rxr->dma); 2921 IXL_RX_UNLOCK(rxr); 2922 IXL_RX_LOCK_DESTROY(rxr); 2923 2924 } 2925 free(vsi->queues, M_DEVBUF); 2926 2927 /* Free VSI filter list */ 2928 ixl_free_mac_filters(vsi); 2929} 2930 2931static void 2932ixl_free_mac_filters(struct ixl_vsi *vsi) 2933{ 2934 struct ixl_mac_filter *f; 2935 2936 while (!SLIST_EMPTY(&vsi->ftl)) { 2937 f = SLIST_FIRST(&vsi->ftl); 2938 SLIST_REMOVE_HEAD(&vsi->ftl, next); 2939 free(f, M_DEVBUF); 2940 } 2941} 2942 2943 2944/********************************************************************* 2945 * 2946 * Allocate memory for the VSI (virtual station interface) and their 2947 * associated queues, rings and the descriptors associated with each, 2948 * called only once at attach. 2949 * 2950 **********************************************************************/ 2951static int 2952ixl_setup_stations(struct ixl_pf *pf) 2953{ 2954 device_t dev = pf->dev; 2955 struct ixl_vsi *vsi; 2956 struct ixl_queue *que; 2957 struct tx_ring *txr; 2958 struct rx_ring *rxr; 2959 int rsize, tsize; 2960 int error = I40E_SUCCESS; 2961 2962 vsi = &pf->vsi; 2963 vsi->back = (void *)pf; 2964 vsi->hw = &pf->hw; 2965 vsi->id = 0; 2966 vsi->num_vlans = 0; 2967 vsi->back = pf; 2968 2969 /* Get memory for the station queues */ 2970 if (!(vsi->queues = 2971 (struct ixl_queue *) malloc(sizeof(struct ixl_queue) * 2972 vsi->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2973 device_printf(dev, "Unable to allocate queue memory\n"); 2974 error = ENOMEM; 2975 goto early; 2976 } 2977 2978 for (int i = 0; i < vsi->num_queues; i++) { 2979 que = &vsi->queues[i]; 2980 que->num_desc = ixl_ringsz; 2981 que->me = i; 2982 que->vsi = vsi; 2983 /* mark the queue as active */ 2984 vsi->active_queues |= (u64)1 << que->me; 2985 txr = &que->txr; 2986 txr->que = que; 2987 txr->tail = I40E_QTX_TAIL(que->me); 2988 2989 /* Initialize the TX lock */ 2990 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 2991 device_get_nameunit(dev), que->me); 2992 mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF); 2993 /* Create the TX descriptor ring */ 2994 tsize = roundup2((que->num_desc * 2995 sizeof(struct i40e_tx_desc)) + 2996 sizeof(u32), DBA_ALIGN); 2997 if (i40e_allocate_dma_mem(&pf->hw, 2998 &txr->dma, i40e_mem_reserved, tsize, DBA_ALIGN)) { 2999 device_printf(dev, 3000 "Unable to allocate TX Descriptor memory\n"); 3001 error = ENOMEM; 3002 goto fail; 3003 } 3004 txr->base = (struct i40e_tx_desc *)txr->dma.va; 3005 bzero((void *)txr->base, tsize); 3006 /* Now allocate transmit soft structs for the ring */ 3007 if (ixl_allocate_tx_data(que)) { 3008 device_printf(dev, 3009 "Critical Failure setting up TX structures\n"); 3010 error = ENOMEM; 3011 goto fail; 3012 } 3013 /* Allocate a buf ring */ 3014 txr->br = buf_ring_alloc(4096, M_DEVBUF, 3015 M_WAITOK, &txr->mtx); 3016 if (txr->br == NULL) { 3017 device_printf(dev, 3018 "Critical Failure setting up TX buf ring\n"); 3019 error = ENOMEM; 3020 goto fail; 3021 } 3022 3023 /* 3024 * Next the RX queues... 3025 */ 3026 rsize = roundup2(que->num_desc * 3027 sizeof(union i40e_rx_desc), DBA_ALIGN); 3028 rxr = &que->rxr; 3029 rxr->que = que; 3030 rxr->tail = I40E_QRX_TAIL(que->me); 3031 3032 /* Initialize the RX side lock */ 3033 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 3034 device_get_nameunit(dev), que->me); 3035 mtx_init(&rxr->mtx, rxr->mtx_name, NULL, MTX_DEF); 3036 3037 if (i40e_allocate_dma_mem(&pf->hw, 3038 &rxr->dma, i40e_mem_reserved, rsize, 4096)) { 3039 device_printf(dev, 3040 "Unable to allocate RX Descriptor memory\n"); 3041 error = ENOMEM; 3042 goto fail; 3043 } 3044 rxr->base = (union i40e_rx_desc *)rxr->dma.va; 3045 bzero((void *)rxr->base, rsize); 3046 3047 /* Allocate receive soft structs for the ring*/ 3048 if (ixl_allocate_rx_data(que)) { 3049 device_printf(dev, 3050 "Critical Failure setting up receive structs\n"); 3051 error = ENOMEM; 3052 goto fail; 3053 } 3054 } 3055 3056 return (0); 3057 3058fail: 3059 for (int i = 0; i < vsi->num_queues; i++) { 3060 que = &vsi->queues[i]; 3061 rxr = &que->rxr; 3062 txr = &que->txr; 3063 if (rxr->base) 3064 i40e_free_dma_mem(&pf->hw, &rxr->dma); 3065 if (txr->base) 3066 i40e_free_dma_mem(&pf->hw, &txr->dma); 3067 } 3068 3069early: 3070 return (error); 3071} 3072 3073/* 3074** Provide a update to the queue RX 3075** interrupt moderation value. 3076*/ 3077static void 3078ixl_set_queue_rx_itr(struct ixl_queue *que) 3079{ 3080 struct ixl_vsi *vsi = que->vsi; 3081 struct i40e_hw *hw = vsi->hw; 3082 struct rx_ring *rxr = &que->rxr; 3083 u16 rx_itr; 3084 u16 rx_latency = 0; 3085 int rx_bytes; 3086 3087 3088 /* Idle, do nothing */ 3089 if (rxr->bytes == 0) 3090 return; 3091 3092 if (ixl_dynamic_rx_itr) { 3093 rx_bytes = rxr->bytes/rxr->itr; 3094 rx_itr = rxr->itr; 3095 3096 /* Adjust latency range */ 3097 switch (rxr->latency) { 3098 case IXL_LOW_LATENCY: 3099 if (rx_bytes > 10) { 3100 rx_latency = IXL_AVE_LATENCY; 3101 rx_itr = IXL_ITR_20K; 3102 } 3103 break; 3104 case IXL_AVE_LATENCY: 3105 if (rx_bytes > 20) { 3106 rx_latency = IXL_BULK_LATENCY; 3107 rx_itr = IXL_ITR_8K; 3108 } else if (rx_bytes <= 10) { 3109 rx_latency = IXL_LOW_LATENCY; 3110 rx_itr = IXL_ITR_100K; 3111 } 3112 break; 3113 case IXL_BULK_LATENCY: 3114 if (rx_bytes <= 20) { 3115 rx_latency = IXL_AVE_LATENCY; 3116 rx_itr = IXL_ITR_20K; 3117 } 3118 break; 3119 } 3120 3121 rxr->latency = rx_latency; 3122 3123 if (rx_itr != rxr->itr) { 3124 /* do an exponential smoothing */ 3125 rx_itr = (10 * rx_itr * rxr->itr) / 3126 ((9 * rx_itr) + rxr->itr); 3127 rxr->itr = rx_itr & IXL_MAX_ITR; 3128 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 3129 que->me), rxr->itr); 3130 } 3131 } else { /* We may have have toggled to non-dynamic */ 3132 if (vsi->rx_itr_setting & IXL_ITR_DYNAMIC) 3133 vsi->rx_itr_setting = ixl_rx_itr; 3134 /* Update the hardware if needed */ 3135 if (rxr->itr != vsi->rx_itr_setting) { 3136 rxr->itr = vsi->rx_itr_setting; 3137 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 3138 que->me), rxr->itr); 3139 } 3140 } 3141 rxr->bytes = 0; 3142 rxr->packets = 0; 3143 return; 3144} 3145 3146 3147/* 3148** Provide a update to the queue TX 3149** interrupt moderation value. 3150*/ 3151static void 3152ixl_set_queue_tx_itr(struct ixl_queue *que) 3153{ 3154 struct ixl_vsi *vsi = que->vsi; 3155 struct i40e_hw *hw = vsi->hw; 3156 struct tx_ring *txr = &que->txr; 3157 u16 tx_itr; 3158 u16 tx_latency = 0; 3159 int tx_bytes; 3160 3161 3162 /* Idle, do nothing */ 3163 if (txr->bytes == 0) 3164 return; 3165 3166 if (ixl_dynamic_tx_itr) { 3167 tx_bytes = txr->bytes/txr->itr; 3168 tx_itr = txr->itr; 3169 3170 switch (txr->latency) { 3171 case IXL_LOW_LATENCY: 3172 if (tx_bytes > 10) { 3173 tx_latency = IXL_AVE_LATENCY; 3174 tx_itr = IXL_ITR_20K; 3175 } 3176 break; 3177 case IXL_AVE_LATENCY: 3178 if (tx_bytes > 20) { 3179 tx_latency = IXL_BULK_LATENCY; 3180 tx_itr = IXL_ITR_8K; 3181 } else if (tx_bytes <= 10) { 3182 tx_latency = IXL_LOW_LATENCY; 3183 tx_itr = IXL_ITR_100K; 3184 } 3185 break; 3186 case IXL_BULK_LATENCY: 3187 if (tx_bytes <= 20) { 3188 tx_latency = IXL_AVE_LATENCY; 3189 tx_itr = IXL_ITR_20K; 3190 } 3191 break; 3192 } 3193 3194 txr->latency = tx_latency; 3195 3196 if (tx_itr != txr->itr) { 3197 /* do an exponential smoothing */ 3198 tx_itr = (10 * tx_itr * txr->itr) / 3199 ((9 * tx_itr) + txr->itr); 3200 txr->itr = tx_itr & IXL_MAX_ITR; 3201 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3202 que->me), txr->itr); 3203 } 3204 3205 } else { /* We may have have toggled to non-dynamic */ 3206 if (vsi->tx_itr_setting & IXL_ITR_DYNAMIC) 3207 vsi->tx_itr_setting = ixl_tx_itr; 3208 /* Update the hardware if needed */ 3209 if (txr->itr != vsi->tx_itr_setting) { 3210 txr->itr = vsi->tx_itr_setting; 3211 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3212 que->me), txr->itr); 3213 } 3214 } 3215 txr->bytes = 0; 3216 txr->packets = 0; 3217 return; 3218} 3219 3220#define QUEUE_NAME_LEN 32 3221 3222static void 3223ixl_add_vsi_sysctls(struct ixl_pf *pf, struct ixl_vsi *vsi, 3224 struct sysctl_ctx_list *ctx, const char *sysctl_name) 3225{ 3226 struct sysctl_oid *tree; 3227 struct sysctl_oid_list *child; 3228 struct sysctl_oid_list *vsi_list; 3229 3230 tree = device_get_sysctl_tree(pf->dev); 3231 child = SYSCTL_CHILDREN(tree); 3232 vsi->vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, sysctl_name, 3233 CTLFLAG_RD, NULL, "VSI Number"); 3234 vsi_list = SYSCTL_CHILDREN(vsi->vsi_node); 3235 3236 ixl_add_sysctls_eth_stats(ctx, vsi_list, &vsi->eth_stats); 3237} 3238 3239static void 3240ixl_add_hw_stats(struct ixl_pf *pf) 3241{ 3242 device_t dev = pf->dev; 3243 struct ixl_vsi *vsi = &pf->vsi; 3244 struct ixl_queue *queues = vsi->queues; 3245 struct i40e_hw_port_stats *pf_stats = &pf->stats; 3246 3247 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3248 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3249 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3250 struct sysctl_oid_list *vsi_list; 3251 3252 struct sysctl_oid *queue_node; 3253 struct sysctl_oid_list *queue_list; 3254 3255 struct tx_ring *txr; 3256 struct rx_ring *rxr; 3257 char queue_namebuf[QUEUE_NAME_LEN]; 3258 3259 /* Driver statistics */ 3260 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events", 3261 CTLFLAG_RD, &pf->watchdog_events, 3262 "Watchdog timeouts"); 3263 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "admin_irq", 3264 CTLFLAG_RD, &pf->admin_irq, 3265 "Admin Queue IRQ Handled"); 3266 3267 ixl_add_vsi_sysctls(pf, &pf->vsi, ctx, "pf"); 3268 vsi_list = SYSCTL_CHILDREN(pf->vsi.vsi_node); 3269 3270 /* Queue statistics */ 3271 for (int q = 0; q < vsi->num_queues; q++) { 3272 snprintf(queue_namebuf, QUEUE_NAME_LEN, "que%d", q); 3273 queue_node = SYSCTL_ADD_NODE(ctx, vsi_list, 3274 OID_AUTO, queue_namebuf, CTLFLAG_RD, NULL, "Queue #"); 3275 queue_list = SYSCTL_CHILDREN(queue_node); 3276 3277 txr = &(queues[q].txr); 3278 rxr = &(queues[q].rxr); 3279 3280 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed", 3281 CTLFLAG_RD, &(queues[q].mbuf_defrag_failed), 3282 "m_defrag() failed"); 3283 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "dropped", 3284 CTLFLAG_RD, &(queues[q].dropped_pkts), 3285 "Driver dropped packets"); 3286 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 3287 CTLFLAG_RD, &(queues[q].irqs), 3288 "irqs on this queue"); 3289 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 3290 CTLFLAG_RD, &(queues[q].tso), 3291 "TSO"); 3292 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_dma_setup", 3293 CTLFLAG_RD, &(queues[q].tx_dma_setup), 3294 "Driver tx dma failure in xmit"); 3295 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "no_desc_avail", 3296 CTLFLAG_RD, &(txr->no_desc), 3297 "Queue No Descriptor Available"); 3298 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 3299 CTLFLAG_RD, &(txr->total_packets), 3300 "Queue Packets Transmitted"); 3301 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_bytes", 3302 CTLFLAG_RD, &(txr->tx_bytes), 3303 "Queue Bytes Transmitted"); 3304 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 3305 CTLFLAG_RD, &(rxr->rx_packets), 3306 "Queue Packets Received"); 3307 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 3308 CTLFLAG_RD, &(rxr->rx_bytes), 3309 "Queue Bytes Received"); 3310 } 3311 3312 /* MAC stats */ 3313 ixl_add_sysctls_mac_stats(ctx, child, pf_stats); 3314} 3315 3316static void 3317ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx, 3318 struct sysctl_oid_list *child, 3319 struct i40e_eth_stats *eth_stats) 3320{ 3321 struct ixl_sysctl_info ctls[] = 3322 { 3323 {ð_stats->rx_bytes, "good_octets_rcvd", "Good Octets Received"}, 3324 {ð_stats->rx_unicast, "ucast_pkts_rcvd", 3325 "Unicast Packets Received"}, 3326 {ð_stats->rx_multicast, "mcast_pkts_rcvd", 3327 "Multicast Packets Received"}, 3328 {ð_stats->rx_broadcast, "bcast_pkts_rcvd", 3329 "Broadcast Packets Received"}, 3330 {ð_stats->rx_discards, "rx_discards", "Discarded RX packets"}, 3331 {ð_stats->tx_bytes, "good_octets_txd", "Good Octets Transmitted"}, 3332 {ð_stats->tx_unicast, "ucast_pkts_txd", "Unicast Packets Transmitted"}, 3333 {ð_stats->tx_multicast, "mcast_pkts_txd", 3334 "Multicast Packets Transmitted"}, 3335 {ð_stats->tx_broadcast, "bcast_pkts_txd", 3336 "Broadcast Packets Transmitted"}, 3337 // end 3338 {0,0,0} 3339 }; 3340 3341 struct ixl_sysctl_info *entry = ctls; 3342 while (entry->stat != 0) 3343 { 3344 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, entry->name, 3345 CTLFLAG_RD, entry->stat, 3346 entry->description); 3347 entry++; 3348 } 3349} 3350 3351static void 3352ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx, 3353 struct sysctl_oid_list *child, 3354 struct i40e_hw_port_stats *stats) 3355{ 3356 struct sysctl_oid *stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac", 3357 CTLFLAG_RD, NULL, "Mac Statistics"); 3358 struct sysctl_oid_list *stat_list = SYSCTL_CHILDREN(stat_node); 3359 3360 struct i40e_eth_stats *eth_stats = &stats->eth; 3361 ixl_add_sysctls_eth_stats(ctx, stat_list, eth_stats); 3362 3363 struct ixl_sysctl_info ctls[] = 3364 { 3365 {&stats->crc_errors, "crc_errors", "CRC Errors"}, 3366 {&stats->illegal_bytes, "illegal_bytes", "Illegal Byte Errors"}, 3367 {&stats->mac_local_faults, "local_faults", "MAC Local Faults"}, 3368 {&stats->mac_remote_faults, "remote_faults", "MAC Remote Faults"}, 3369 {&stats->rx_length_errors, "rx_length_errors", "Receive Length Errors"}, 3370 /* Packet Reception Stats */ 3371 {&stats->rx_size_64, "rx_frames_64", "64 byte frames received"}, 3372 {&stats->rx_size_127, "rx_frames_65_127", "65-127 byte frames received"}, 3373 {&stats->rx_size_255, "rx_frames_128_255", "128-255 byte frames received"}, 3374 {&stats->rx_size_511, "rx_frames_256_511", "256-511 byte frames received"}, 3375 {&stats->rx_size_1023, "rx_frames_512_1023", "512-1023 byte frames received"}, 3376 {&stats->rx_size_1522, "rx_frames_1024_1522", "1024-1522 byte frames received"}, 3377 {&stats->rx_size_big, "rx_frames_big", "1523-9522 byte frames received"}, 3378 {&stats->rx_undersize, "rx_undersize", "Undersized packets received"}, 3379 {&stats->rx_fragments, "rx_fragmented", "Fragmented packets received"}, 3380 {&stats->rx_oversize, "rx_oversized", "Oversized packets received"}, 3381 {&stats->rx_jabber, "rx_jabber", "Received Jabber"}, 3382 {&stats->checksum_error, "checksum_errors", "Checksum Errors"}, 3383 /* Packet Transmission Stats */ 3384 {&stats->tx_size_64, "tx_frames_64", "64 byte frames transmitted"}, 3385 {&stats->tx_size_127, "tx_frames_65_127", "65-127 byte frames transmitted"}, 3386 {&stats->tx_size_255, "tx_frames_128_255", "128-255 byte frames transmitted"}, 3387 {&stats->tx_size_511, "tx_frames_256_511", "256-511 byte frames transmitted"}, 3388 {&stats->tx_size_1023, "tx_frames_512_1023", "512-1023 byte frames transmitted"}, 3389 {&stats->tx_size_1522, "tx_frames_1024_1522", "1024-1522 byte frames transmitted"}, 3390 {&stats->tx_size_big, "tx_frames_big", "1523-9522 byte frames transmitted"}, 3391 /* Flow control */ 3392 {&stats->link_xon_tx, "xon_txd", "Link XON transmitted"}, 3393 {&stats->link_xon_rx, "xon_recvd", "Link XON received"}, 3394 {&stats->link_xoff_tx, "xoff_txd", "Link XOFF transmitted"}, 3395 {&stats->link_xoff_rx, "xoff_recvd", "Link XOFF received"}, 3396 /* End */ 3397 {0,0,0} 3398 }; 3399 3400 struct ixl_sysctl_info *entry = ctls; 3401 while (entry->stat != 0) 3402 { 3403 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, entry->name, 3404 CTLFLAG_RD, entry->stat, 3405 entry->description); 3406 entry++; 3407 } 3408} 3409 3410 3411/* 3412** ixl_config_rss - setup RSS 3413** - note this is done for the single vsi 3414*/ 3415static void ixl_config_rss(struct ixl_vsi *vsi) 3416{ 3417 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3418 struct i40e_hw *hw = vsi->hw; 3419 u32 lut = 0; 3420 u64 set_hena = 0, hena; 3421 int i, j, que_id; 3422#ifdef RSS 3423 u32 rss_hash_config; 3424 u32 rss_seed[IXL_KEYSZ]; 3425#else 3426 u32 rss_seed[IXL_KEYSZ] = {0x41b01687, 3427 0x183cfd8c, 0xce880440, 0x580cbc3c, 3428 0x35897377, 0x328b25e1, 0x4fa98922, 3429 0xb7d90c14, 0xd5bad70d, 0xcd15a2c1}; 3430#endif 3431 3432#ifdef RSS 3433 /* Fetch the configured RSS key */ 3434 rss_getkey((uint8_t *) &rss_seed); 3435#endif 3436 3437 /* Fill out hash function seed */ 3438 for (i = 0; i < IXL_KEYSZ; i++) 3439 wr32(hw, I40E_PFQF_HKEY(i), rss_seed[i]); 3440 3441 /* Enable PCTYPES for RSS: */ 3442#ifdef RSS 3443 rss_hash_config = rss_gethashconfig(); 3444 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 3445 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER); 3446 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 3447 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP); 3448 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 3449 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP); 3450 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 3451 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER); 3452 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 3453 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6); 3454 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 3455 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP); 3456 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 3457 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP); 3458#else 3459 set_hena = 3460 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | 3461 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | 3462 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | 3463 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | 3464 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | 3465 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | 3466 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | 3467 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | 3468 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | 3469 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | 3470 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD); 3471#endif 3472 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) | 3473 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32); 3474 hena |= set_hena; 3475 wr32(hw, I40E_PFQF_HENA(0), (u32)hena); 3476 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); 3477 3478 /* Populate the LUT with max no. of queues in round robin fashion */ 3479 for (i = j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) { 3480 if (j == vsi->num_queues) 3481 j = 0; 3482#ifdef RSS 3483 /* 3484 * Fetch the RSS bucket id for the given indirection entry. 3485 * Cap it at the number of configured buckets (which is 3486 * num_queues.) 3487 */ 3488 que_id = rss_get_indirection_to_bucket(i); 3489 que_id = que_id % vsi->num_queues; 3490#else 3491 que_id = j; 3492#endif 3493 /* lut = 4-byte sliding window of 4 lut entries */ 3494 lut = (lut << 8) | (que_id & 3495 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1)); 3496 /* On i = 3, we have 4 entries in lut; write to the register */ 3497 if ((i & 3) == 3) 3498 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut); 3499 } 3500 ixl_flush(hw); 3501} 3502 3503 3504/* 3505** This routine is run via an vlan config EVENT, 3506** it enables us to use the HW Filter table since 3507** we can get the vlan id. This just creates the 3508** entry in the soft version of the VFTA, init will 3509** repopulate the real table. 3510*/ 3511static void 3512ixl_register_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3513{ 3514 struct ixl_vsi *vsi = ifp->if_softc; 3515 struct i40e_hw *hw = vsi->hw; 3516 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3517 3518 if (ifp->if_softc != arg) /* Not our event */ 3519 return; 3520 3521 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3522 return; 3523 3524 IXL_PF_LOCK(pf); 3525 ++vsi->num_vlans; 3526 ixl_add_filter(vsi, hw->mac.addr, vtag); 3527 IXL_PF_UNLOCK(pf); 3528} 3529 3530/* 3531** This routine is run via an vlan 3532** unconfig EVENT, remove our entry 3533** in the soft vfta. 3534*/ 3535static void 3536ixl_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3537{ 3538 struct ixl_vsi *vsi = ifp->if_softc; 3539 struct i40e_hw *hw = vsi->hw; 3540 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3541 3542 if (ifp->if_softc != arg) 3543 return; 3544 3545 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3546 return; 3547 3548 IXL_PF_LOCK(pf); 3549 --vsi->num_vlans; 3550 ixl_del_filter(vsi, hw->mac.addr, vtag); 3551 IXL_PF_UNLOCK(pf); 3552} 3553 3554/* 3555** This routine updates vlan filters, called by init 3556** it scans the filter table and then updates the hw 3557** after a soft reset. 3558*/ 3559static void 3560ixl_setup_vlan_filters(struct ixl_vsi *vsi) 3561{ 3562 struct ixl_mac_filter *f; 3563 int cnt = 0, flags; 3564 3565 if (vsi->num_vlans == 0) 3566 return; 3567 /* 3568 ** Scan the filter list for vlan entries, 3569 ** mark them for addition and then call 3570 ** for the AQ update. 3571 */ 3572 SLIST_FOREACH(f, &vsi->ftl, next) { 3573 if (f->flags & IXL_FILTER_VLAN) { 3574 f->flags |= 3575 (IXL_FILTER_ADD | 3576 IXL_FILTER_USED); 3577 cnt++; 3578 } 3579 } 3580 if (cnt == 0) { 3581 printf("setup vlan: no filters found!\n"); 3582 return; 3583 } 3584 flags = IXL_FILTER_VLAN; 3585 flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3586 ixl_add_hw_filters(vsi, flags, cnt); 3587 return; 3588} 3589 3590/* 3591** Initialize filter list and add filters that the hardware 3592** needs to know about. 3593*/ 3594static void 3595ixl_init_filters(struct ixl_vsi *vsi) 3596{ 3597 /* Add broadcast address */ 3598 ixl_add_filter(vsi, ixl_bcast_addr, IXL_VLAN_ANY); 3599} 3600 3601/* 3602** This routine adds mulicast filters 3603*/ 3604static void 3605ixl_add_mc_filter(struct ixl_vsi *vsi, u8 *macaddr) 3606{ 3607 struct ixl_mac_filter *f; 3608 3609 /* Does one already exist */ 3610 f = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3611 if (f != NULL) 3612 return; 3613 3614 f = ixl_get_filter(vsi); 3615 if (f == NULL) { 3616 printf("WARNING: no filter available!!\n"); 3617 return; 3618 } 3619 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3620 f->vlan = IXL_VLAN_ANY; 3621 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED 3622 | IXL_FILTER_MC); 3623 3624 return; 3625} 3626 3627static void 3628ixl_reconfigure_filters(struct ixl_vsi *vsi) 3629{ 3630 3631 ixl_add_hw_filters(vsi, IXL_FILTER_USED, vsi->num_macs); 3632} 3633 3634/* 3635** This routine adds macvlan filters 3636*/ 3637static void 3638ixl_add_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3639{ 3640 struct ixl_mac_filter *f, *tmp; 3641 struct ixl_pf *pf; 3642 device_t dev; 3643 3644 DEBUGOUT("ixl_add_filter: begin"); 3645 3646 pf = vsi->back; 3647 dev = pf->dev; 3648 3649 /* Does one already exist */ 3650 f = ixl_find_filter(vsi, macaddr, vlan); 3651 if (f != NULL) 3652 return; 3653 /* 3654 ** Is this the first vlan being registered, if so we 3655 ** need to remove the ANY filter that indicates we are 3656 ** not in a vlan, and replace that with a 0 filter. 3657 */ 3658 if ((vlan != IXL_VLAN_ANY) && (vsi->num_vlans == 1)) { 3659 tmp = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3660 if (tmp != NULL) { 3661 ixl_del_filter(vsi, macaddr, IXL_VLAN_ANY); 3662 ixl_add_filter(vsi, macaddr, 0); 3663 } 3664 } 3665 3666 f = ixl_get_filter(vsi); 3667 if (f == NULL) { 3668 device_printf(dev, "WARNING: no filter available!!\n"); 3669 return; 3670 } 3671 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3672 f->vlan = vlan; 3673 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3674 if (f->vlan != IXL_VLAN_ANY) 3675 f->flags |= IXL_FILTER_VLAN; 3676 else 3677 vsi->num_macs++; 3678 3679 ixl_add_hw_filters(vsi, f->flags, 1); 3680 return; 3681} 3682 3683static void 3684ixl_del_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3685{ 3686 struct ixl_mac_filter *f; 3687 3688 f = ixl_find_filter(vsi, macaddr, vlan); 3689 if (f == NULL) 3690 return; 3691 3692 f->flags |= IXL_FILTER_DEL; 3693 ixl_del_hw_filters(vsi, 1); 3694 vsi->num_macs--; 3695 3696 /* Check if this is the last vlan removal */ 3697 if (vlan != IXL_VLAN_ANY && vsi->num_vlans == 0) { 3698 /* Switch back to a non-vlan filter */ 3699 ixl_del_filter(vsi, macaddr, 0); 3700 ixl_add_filter(vsi, macaddr, IXL_VLAN_ANY); 3701 } 3702 return; 3703} 3704 3705/* 3706** Find the filter with both matching mac addr and vlan id 3707*/ 3708static struct ixl_mac_filter * 3709ixl_find_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3710{ 3711 struct ixl_mac_filter *f; 3712 bool match = FALSE; 3713 3714 SLIST_FOREACH(f, &vsi->ftl, next) { 3715 if (!cmp_etheraddr(f->macaddr, macaddr)) 3716 continue; 3717 if (f->vlan == vlan) { 3718 match = TRUE; 3719 break; 3720 } 3721 } 3722 3723 if (!match) 3724 f = NULL; 3725 return (f); 3726} 3727 3728/* 3729** This routine takes additions to the vsi filter 3730** table and creates an Admin Queue call to create 3731** the filters in the hardware. 3732*/ 3733static void 3734ixl_add_hw_filters(struct ixl_vsi *vsi, int flags, int cnt) 3735{ 3736 struct i40e_aqc_add_macvlan_element_data *a, *b; 3737 struct ixl_mac_filter *f; 3738 struct ixl_pf *pf; 3739 struct i40e_hw *hw; 3740 device_t dev; 3741 int err, j = 0; 3742 3743 pf = vsi->back; 3744 dev = pf->dev; 3745 hw = &pf->hw; 3746 IXL_PF_LOCK_ASSERT(pf); 3747 3748 a = malloc(sizeof(struct i40e_aqc_add_macvlan_element_data) * cnt, 3749 M_DEVBUF, M_NOWAIT | M_ZERO); 3750 if (a == NULL) { 3751 device_printf(dev, "add_hw_filters failed to get memory\n"); 3752 return; 3753 } 3754 3755 /* 3756 ** Scan the filter list, each time we find one 3757 ** we add it to the admin queue array and turn off 3758 ** the add bit. 3759 */ 3760 SLIST_FOREACH(f, &vsi->ftl, next) { 3761 if (f->flags == flags) { 3762 b = &a[j]; // a pox on fvl long names :) 3763 bcopy(f->macaddr, b->mac_addr, ETHER_ADDR_LEN); 3764 if (f->vlan == IXL_VLAN_ANY) { 3765 b->vlan_tag = 0; 3766 b->flags = I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 3767 } else { 3768 b->vlan_tag = f->vlan; 3769 b->flags = 0; 3770 } 3771 b->flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 3772 f->flags &= ~IXL_FILTER_ADD; 3773 j++; 3774 } 3775 if (j == cnt) 3776 break; 3777 } 3778 if (j > 0) { 3779 err = i40e_aq_add_macvlan(hw, vsi->seid, a, j, NULL); 3780 if (err) 3781 device_printf(dev, "aq_add_macvlan err %d, " 3782 "aq_error %d\n", err, hw->aq.asq_last_status); 3783 else 3784 vsi->hw_filters_add += j; 3785 } 3786 free(a, M_DEVBUF); 3787 return; 3788} 3789 3790/* 3791** This routine takes removals in the vsi filter 3792** table and creates an Admin Queue call to delete 3793** the filters in the hardware. 3794*/ 3795static void 3796ixl_del_hw_filters(struct ixl_vsi *vsi, int cnt) 3797{ 3798 struct i40e_aqc_remove_macvlan_element_data *d, *e; 3799 struct ixl_pf *pf; 3800 struct i40e_hw *hw; 3801 device_t dev; 3802 struct ixl_mac_filter *f, *f_temp; 3803 int err, j = 0; 3804 3805 DEBUGOUT("ixl_del_hw_filters: begin\n"); 3806 3807 pf = vsi->back; 3808 hw = &pf->hw; 3809 dev = pf->dev; 3810 3811 d = malloc(sizeof(struct i40e_aqc_remove_macvlan_element_data) * cnt, 3812 M_DEVBUF, M_NOWAIT | M_ZERO); 3813 if (d == NULL) { 3814 printf("del hw filter failed to get memory\n"); 3815 return; 3816 } 3817 3818 SLIST_FOREACH_SAFE(f, &vsi->ftl, next, f_temp) { 3819 if (f->flags & IXL_FILTER_DEL) { 3820 e = &d[j]; // a pox on fvl long names :) 3821 bcopy(f->macaddr, e->mac_addr, ETHER_ADDR_LEN); 3822 e->vlan_tag = (f->vlan == IXL_VLAN_ANY ? 0 : f->vlan); 3823 e->flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 3824 /* delete entry from vsi list */ 3825 SLIST_REMOVE(&vsi->ftl, f, ixl_mac_filter, next); 3826 free(f, M_DEVBUF); 3827 j++; 3828 } 3829 if (j == cnt) 3830 break; 3831 } 3832 if (j > 0) { 3833 err = i40e_aq_remove_macvlan(hw, vsi->seid, d, j, NULL); 3834 /* NOTE: returns ENOENT every time but seems to work fine, 3835 so we'll ignore that specific error. */ 3836 // TODO: Does this still occur on current firmwares? 3837 if (err && hw->aq.asq_last_status != I40E_AQ_RC_ENOENT) { 3838 int sc = 0; 3839 for (int i = 0; i < j; i++) 3840 sc += (!d[i].error_code); 3841 vsi->hw_filters_del += sc; 3842 device_printf(dev, 3843 "Failed to remove %d/%d filters, aq error %d\n", 3844 j - sc, j, hw->aq.asq_last_status); 3845 } else 3846 vsi->hw_filters_del += j; 3847 } 3848 free(d, M_DEVBUF); 3849 3850 DEBUGOUT("ixl_del_hw_filters: end\n"); 3851 return; 3852} 3853 3854static int 3855ixl_enable_rings(struct ixl_vsi *vsi) 3856{ 3857 struct ixl_pf *pf = vsi->back; 3858 struct i40e_hw *hw = &pf->hw; 3859 int index, error; 3860 u32 reg; 3861 3862 error = 0; 3863 for (int i = 0; i < vsi->num_queues; i++) { 3864 index = vsi->first_queue + i; 3865 i40e_pre_tx_queue_cfg(hw, index, TRUE); 3866 3867 reg = rd32(hw, I40E_QTX_ENA(index)); 3868 reg |= I40E_QTX_ENA_QENA_REQ_MASK | 3869 I40E_QTX_ENA_QENA_STAT_MASK; 3870 wr32(hw, I40E_QTX_ENA(index), reg); 3871 /* Verify the enable took */ 3872 for (int j = 0; j < 10; j++) { 3873 reg = rd32(hw, I40E_QTX_ENA(index)); 3874 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 3875 break; 3876 i40e_msec_delay(10); 3877 } 3878 if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) { 3879 device_printf(pf->dev, "TX queue %d disabled!\n", 3880 index); 3881 error = ETIMEDOUT; 3882 } 3883 3884 reg = rd32(hw, I40E_QRX_ENA(index)); 3885 reg |= I40E_QRX_ENA_QENA_REQ_MASK | 3886 I40E_QRX_ENA_QENA_STAT_MASK; 3887 wr32(hw, I40E_QRX_ENA(index), reg); 3888 /* Verify the enable took */ 3889 for (int j = 0; j < 10; j++) { 3890 reg = rd32(hw, I40E_QRX_ENA(index)); 3891 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 3892 break; 3893 i40e_msec_delay(10); 3894 } 3895 if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) { 3896 device_printf(pf->dev, "RX queue %d disabled!\n", 3897 index); 3898 error = ETIMEDOUT; 3899 } 3900 } 3901 3902 return (error); 3903} 3904 3905static int 3906ixl_disable_rings(struct ixl_vsi *vsi) 3907{ 3908 struct ixl_pf *pf = vsi->back; 3909 struct i40e_hw *hw = &pf->hw; 3910 int index, error; 3911 u32 reg; 3912 3913 error = 0; 3914 for (int i = 0; i < vsi->num_queues; i++) { 3915 index = vsi->first_queue + i; 3916 3917 i40e_pre_tx_queue_cfg(hw, index, FALSE); 3918 i40e_usec_delay(500); 3919 3920 reg = rd32(hw, I40E_QTX_ENA(index)); 3921 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 3922 wr32(hw, I40E_QTX_ENA(index), reg); 3923 /* Verify the disable took */ 3924 for (int j = 0; j < 10; j++) { 3925 reg = rd32(hw, I40E_QTX_ENA(index)); 3926 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 3927 break; 3928 i40e_msec_delay(10); 3929 } 3930 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) { 3931 device_printf(pf->dev, "TX queue %d still enabled!\n", 3932 index); 3933 error = ETIMEDOUT; 3934 } 3935 3936 reg = rd32(hw, I40E_QRX_ENA(index)); 3937 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 3938 wr32(hw, I40E_QRX_ENA(index), reg); 3939 /* Verify the disable took */ 3940 for (int j = 0; j < 10; j++) { 3941 reg = rd32(hw, I40E_QRX_ENA(index)); 3942 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 3943 break; 3944 i40e_msec_delay(10); 3945 } 3946 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) { 3947 device_printf(pf->dev, "RX queue %d still enabled!\n", 3948 index); 3949 error = ETIMEDOUT; 3950 } 3951 } 3952 3953 return (error); 3954} 3955 3956/** 3957 * ixl_handle_mdd_event 3958 * 3959 * Called from interrupt handler to identify possibly malicious vfs 3960 * (But also detects events from the PF, as well) 3961 **/ 3962static void ixl_handle_mdd_event(struct ixl_pf *pf) 3963{ 3964 struct i40e_hw *hw = &pf->hw; 3965 device_t dev = pf->dev; 3966 bool mdd_detected = false; 3967 bool pf_mdd_detected = false; 3968 u32 reg; 3969 3970 /* find what triggered the MDD event */ 3971 reg = rd32(hw, I40E_GL_MDET_TX); 3972 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 3973 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> 3974 I40E_GL_MDET_TX_PF_NUM_SHIFT; 3975 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> 3976 I40E_GL_MDET_TX_EVENT_SHIFT; 3977 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >> 3978 I40E_GL_MDET_TX_QUEUE_SHIFT; 3979 device_printf(dev, 3980 "Malicious Driver Detection event 0x%02x" 3981 " on TX queue %d pf number 0x%02x\n", 3982 event, queue, pf_num); 3983 wr32(hw, I40E_GL_MDET_TX, 0xffffffff); 3984 mdd_detected = true; 3985 } 3986 reg = rd32(hw, I40E_GL_MDET_RX); 3987 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 3988 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> 3989 I40E_GL_MDET_RX_FUNCTION_SHIFT; 3990 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> 3991 I40E_GL_MDET_RX_EVENT_SHIFT; 3992 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >> 3993 I40E_GL_MDET_RX_QUEUE_SHIFT; 3994 device_printf(dev, 3995 "Malicious Driver Detection event 0x%02x" 3996 " on RX queue %d of function 0x%02x\n", 3997 event, queue, func); 3998 wr32(hw, I40E_GL_MDET_RX, 0xffffffff); 3999 mdd_detected = true; 4000 } 4001 4002 if (mdd_detected) { 4003 reg = rd32(hw, I40E_PF_MDET_TX); 4004 if (reg & I40E_PF_MDET_TX_VALID_MASK) { 4005 wr32(hw, I40E_PF_MDET_TX, 0xFFFF); 4006 device_printf(dev, 4007 "MDD TX event is for this function 0x%08x", 4008 reg); 4009 pf_mdd_detected = true; 4010 } 4011 reg = rd32(hw, I40E_PF_MDET_RX); 4012 if (reg & I40E_PF_MDET_RX_VALID_MASK) { 4013 wr32(hw, I40E_PF_MDET_RX, 0xFFFF); 4014 device_printf(dev, 4015 "MDD RX event is for this function 0x%08x", 4016 reg); 4017 pf_mdd_detected = true; 4018 } 4019 } 4020 4021 /* re-enable mdd interrupt cause */ 4022 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 4023 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 4024 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 4025 ixl_flush(hw); 4026} 4027 4028static void 4029ixl_enable_intr(struct ixl_vsi *vsi) 4030{ 4031 struct i40e_hw *hw = vsi->hw; 4032 struct ixl_queue *que = vsi->queues; 4033 4034 if (ixl_enable_msix) { 4035 ixl_enable_adminq(hw); 4036 for (int i = 0; i < vsi->num_queues; i++, que++) 4037 ixl_enable_queue(hw, que->me); 4038 } else 4039 ixl_enable_legacy(hw); 4040} 4041 4042static void 4043ixl_disable_rings_intr(struct ixl_vsi *vsi) 4044{ 4045 struct i40e_hw *hw = vsi->hw; 4046 struct ixl_queue *que = vsi->queues; 4047 4048 for (int i = 0; i < vsi->num_queues; i++, que++) 4049 ixl_disable_queue(hw, que->me); 4050} 4051 4052static void 4053ixl_disable_intr(struct ixl_vsi *vsi) 4054{ 4055 struct i40e_hw *hw = vsi->hw; 4056 4057 if (ixl_enable_msix) 4058 ixl_disable_adminq(hw); 4059 else 4060 ixl_disable_legacy(hw); 4061} 4062 4063static void 4064ixl_enable_adminq(struct i40e_hw *hw) 4065{ 4066 u32 reg; 4067 4068 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 4069 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 4070 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 4071 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4072 ixl_flush(hw); 4073 return; 4074} 4075 4076static void 4077ixl_disable_adminq(struct i40e_hw *hw) 4078{ 4079 u32 reg; 4080 4081 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 4082 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4083 4084 return; 4085} 4086 4087static void 4088ixl_enable_queue(struct i40e_hw *hw, int id) 4089{ 4090 u32 reg; 4091 4092 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK | 4093 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 4094 (IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 4095 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 4096} 4097 4098static void 4099ixl_disable_queue(struct i40e_hw *hw, int id) 4100{ 4101 u32 reg; 4102 4103 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 4104 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 4105 4106 return; 4107} 4108 4109static void 4110ixl_enable_legacy(struct i40e_hw *hw) 4111{ 4112 u32 reg; 4113 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 4114 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 4115 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 4116 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4117} 4118 4119static void 4120ixl_disable_legacy(struct i40e_hw *hw) 4121{ 4122 u32 reg; 4123 4124 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 4125 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4126 4127 return; 4128} 4129 4130static void 4131ixl_update_stats_counters(struct ixl_pf *pf) 4132{ 4133 struct i40e_hw *hw = &pf->hw; 4134 struct ixl_vsi *vsi = &pf->vsi; 4135 struct ixl_vf *vf; 4136 4137 struct i40e_hw_port_stats *nsd = &pf->stats; 4138 struct i40e_hw_port_stats *osd = &pf->stats_offsets; 4139 4140 /* Update hw stats */ 4141 ixl_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), 4142 pf->stat_offsets_loaded, 4143 &osd->crc_errors, &nsd->crc_errors); 4144 ixl_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), 4145 pf->stat_offsets_loaded, 4146 &osd->illegal_bytes, &nsd->illegal_bytes); 4147 ixl_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), 4148 I40E_GLPRT_GORCL(hw->port), 4149 pf->stat_offsets_loaded, 4150 &osd->eth.rx_bytes, &nsd->eth.rx_bytes); 4151 ixl_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), 4152 I40E_GLPRT_GOTCL(hw->port), 4153 pf->stat_offsets_loaded, 4154 &osd->eth.tx_bytes, &nsd->eth.tx_bytes); 4155 ixl_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), 4156 pf->stat_offsets_loaded, 4157 &osd->eth.rx_discards, 4158 &nsd->eth.rx_discards); 4159 ixl_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), 4160 I40E_GLPRT_UPRCL(hw->port), 4161 pf->stat_offsets_loaded, 4162 &osd->eth.rx_unicast, 4163 &nsd->eth.rx_unicast); 4164 ixl_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), 4165 I40E_GLPRT_UPTCL(hw->port), 4166 pf->stat_offsets_loaded, 4167 &osd->eth.tx_unicast, 4168 &nsd->eth.tx_unicast); 4169 ixl_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), 4170 I40E_GLPRT_MPRCL(hw->port), 4171 pf->stat_offsets_loaded, 4172 &osd->eth.rx_multicast, 4173 &nsd->eth.rx_multicast); 4174 ixl_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), 4175 I40E_GLPRT_MPTCL(hw->port), 4176 pf->stat_offsets_loaded, 4177 &osd->eth.tx_multicast, 4178 &nsd->eth.tx_multicast); 4179 ixl_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), 4180 I40E_GLPRT_BPRCL(hw->port), 4181 pf->stat_offsets_loaded, 4182 &osd->eth.rx_broadcast, 4183 &nsd->eth.rx_broadcast); 4184 ixl_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), 4185 I40E_GLPRT_BPTCL(hw->port), 4186 pf->stat_offsets_loaded, 4187 &osd->eth.tx_broadcast, 4188 &nsd->eth.tx_broadcast); 4189 4190 ixl_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), 4191 pf->stat_offsets_loaded, 4192 &osd->tx_dropped_link_down, 4193 &nsd->tx_dropped_link_down); 4194 ixl_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), 4195 pf->stat_offsets_loaded, 4196 &osd->mac_local_faults, 4197 &nsd->mac_local_faults); 4198 ixl_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), 4199 pf->stat_offsets_loaded, 4200 &osd->mac_remote_faults, 4201 &nsd->mac_remote_faults); 4202 ixl_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), 4203 pf->stat_offsets_loaded, 4204 &osd->rx_length_errors, 4205 &nsd->rx_length_errors); 4206 4207 /* Flow control (LFC) stats */ 4208 ixl_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), 4209 pf->stat_offsets_loaded, 4210 &osd->link_xon_rx, &nsd->link_xon_rx); 4211 ixl_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), 4212 pf->stat_offsets_loaded, 4213 &osd->link_xon_tx, &nsd->link_xon_tx); 4214 ixl_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 4215 pf->stat_offsets_loaded, 4216 &osd->link_xoff_rx, &nsd->link_xoff_rx); 4217 ixl_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 4218 pf->stat_offsets_loaded, 4219 &osd->link_xoff_tx, &nsd->link_xoff_tx); 4220 4221 /* Packet size stats rx */ 4222 ixl_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), 4223 I40E_GLPRT_PRC64L(hw->port), 4224 pf->stat_offsets_loaded, 4225 &osd->rx_size_64, &nsd->rx_size_64); 4226 ixl_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), 4227 I40E_GLPRT_PRC127L(hw->port), 4228 pf->stat_offsets_loaded, 4229 &osd->rx_size_127, &nsd->rx_size_127); 4230 ixl_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), 4231 I40E_GLPRT_PRC255L(hw->port), 4232 pf->stat_offsets_loaded, 4233 &osd->rx_size_255, &nsd->rx_size_255); 4234 ixl_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), 4235 I40E_GLPRT_PRC511L(hw->port), 4236 pf->stat_offsets_loaded, 4237 &osd->rx_size_511, &nsd->rx_size_511); 4238 ixl_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), 4239 I40E_GLPRT_PRC1023L(hw->port), 4240 pf->stat_offsets_loaded, 4241 &osd->rx_size_1023, &nsd->rx_size_1023); 4242 ixl_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), 4243 I40E_GLPRT_PRC1522L(hw->port), 4244 pf->stat_offsets_loaded, 4245 &osd->rx_size_1522, &nsd->rx_size_1522); 4246 ixl_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), 4247 I40E_GLPRT_PRC9522L(hw->port), 4248 pf->stat_offsets_loaded, 4249 &osd->rx_size_big, &nsd->rx_size_big); 4250 4251 /* Packet size stats tx */ 4252 ixl_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), 4253 I40E_GLPRT_PTC64L(hw->port), 4254 pf->stat_offsets_loaded, 4255 &osd->tx_size_64, &nsd->tx_size_64); 4256 ixl_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), 4257 I40E_GLPRT_PTC127L(hw->port), 4258 pf->stat_offsets_loaded, 4259 &osd->tx_size_127, &nsd->tx_size_127); 4260 ixl_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), 4261 I40E_GLPRT_PTC255L(hw->port), 4262 pf->stat_offsets_loaded, 4263 &osd->tx_size_255, &nsd->tx_size_255); 4264 ixl_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), 4265 I40E_GLPRT_PTC511L(hw->port), 4266 pf->stat_offsets_loaded, 4267 &osd->tx_size_511, &nsd->tx_size_511); 4268 ixl_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), 4269 I40E_GLPRT_PTC1023L(hw->port), 4270 pf->stat_offsets_loaded, 4271 &osd->tx_size_1023, &nsd->tx_size_1023); 4272 ixl_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), 4273 I40E_GLPRT_PTC1522L(hw->port), 4274 pf->stat_offsets_loaded, 4275 &osd->tx_size_1522, &nsd->tx_size_1522); 4276 ixl_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), 4277 I40E_GLPRT_PTC9522L(hw->port), 4278 pf->stat_offsets_loaded, 4279 &osd->tx_size_big, &nsd->tx_size_big); 4280 4281 ixl_stat_update32(hw, I40E_GLPRT_RUC(hw->port), 4282 pf->stat_offsets_loaded, 4283 &osd->rx_undersize, &nsd->rx_undersize); 4284 ixl_stat_update32(hw, I40E_GLPRT_RFC(hw->port), 4285 pf->stat_offsets_loaded, 4286 &osd->rx_fragments, &nsd->rx_fragments); 4287 ixl_stat_update32(hw, I40E_GLPRT_ROC(hw->port), 4288 pf->stat_offsets_loaded, 4289 &osd->rx_oversize, &nsd->rx_oversize); 4290 ixl_stat_update32(hw, I40E_GLPRT_RJC(hw->port), 4291 pf->stat_offsets_loaded, 4292 &osd->rx_jabber, &nsd->rx_jabber); 4293 pf->stat_offsets_loaded = true; 4294 /* End hw stats */ 4295 4296 /* Update vsi stats */ 4297 ixl_update_vsi_stats(vsi); 4298 4299 for (int i = 0; i < pf->num_vfs; i++) { 4300 vf = &pf->vfs[i]; 4301 if (vf->vf_flags & VF_FLAG_ENABLED) 4302 ixl_update_eth_stats(&pf->vfs[i].vsi); 4303 } 4304} 4305 4306/* 4307** Tasklet handler for MSIX Adminq interrupts 4308** - do outside interrupt since it might sleep 4309*/ 4310static void 4311ixl_do_adminq(void *context, int pending) 4312{ 4313 struct ixl_pf *pf = context; 4314 struct i40e_hw *hw = &pf->hw; 4315 struct ixl_vsi *vsi = &pf->vsi; 4316 struct i40e_arq_event_info event; 4317 i40e_status ret; 4318 u32 reg, loop = 0; 4319 u16 opcode, result; 4320 4321 event.buf_len = IXL_AQ_BUF_SZ; 4322 event.msg_buf = malloc(event.buf_len, 4323 M_DEVBUF, M_NOWAIT | M_ZERO); 4324 if (!event.msg_buf) { 4325 printf("Unable to allocate adminq memory\n"); 4326 return; 4327 } 4328 4329 IXL_PF_LOCK(pf); 4330 /* clean and process any events */ 4331 do { 4332 ret = i40e_clean_arq_element(hw, &event, &result); 4333 if (ret) 4334 break; 4335 opcode = LE16_TO_CPU(event.desc.opcode); 4336 switch (opcode) { 4337 case i40e_aqc_opc_get_link_status: 4338 ixl_link_event(pf, &event); 4339 ixl_update_link_status(pf); 4340 break; 4341 case i40e_aqc_opc_send_msg_to_pf: 4342#ifdef PCI_IOV 4343 ixl_handle_vf_msg(pf, &event); 4344#endif 4345 break; 4346 case i40e_aqc_opc_event_lan_overflow: 4347 break; 4348 default: 4349#ifdef IXL_DEBUG 4350 printf("AdminQ unknown event %x\n", opcode); 4351#endif 4352 break; 4353 } 4354 4355 } while (result && (loop++ < IXL_ADM_LIMIT)); 4356 4357 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 4358 reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 4359 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 4360 free(event.msg_buf, M_DEVBUF); 4361 4362 /* 4363 * If there are still messages to process, reschedule ourselves. 4364 * Otherwise, re-enable our interrupt and go to sleep. 4365 */ 4366 if (result > 0) 4367 taskqueue_enqueue(pf->tq, &pf->adminq); 4368 else 4369 ixl_enable_intr(vsi); 4370 4371 IXL_PF_UNLOCK(pf); 4372} 4373 4374#ifdef IXL_DEBUG_SYSCTL 4375static int 4376ixl_debug_info(SYSCTL_HANDLER_ARGS) 4377{ 4378 struct ixl_pf *pf; 4379 int error, input = 0; 4380 4381 error = sysctl_handle_int(oidp, &input, 0, req); 4382 4383 if (error || !req->newptr) 4384 return (error); 4385 4386 if (input == 1) { 4387 pf = (struct ixl_pf *)arg1; 4388 ixl_print_debug_info(pf); 4389 } 4390 4391 return (error); 4392} 4393 4394static void 4395ixl_print_debug_info(struct ixl_pf *pf) 4396{ 4397 struct i40e_hw *hw = &pf->hw; 4398 struct ixl_vsi *vsi = &pf->vsi; 4399 struct ixl_queue *que = vsi->queues; 4400 struct rx_ring *rxr = &que->rxr; 4401 struct tx_ring *txr = &que->txr; 4402 u32 reg; 4403 4404 4405 printf("Queue irqs = %jx\n", (uintmax_t)que->irqs); 4406 printf("AdminQ irqs = %jx\n", (uintmax_t)pf->admin_irq); 4407 printf("RX next check = %x\n", rxr->next_check); 4408 printf("RX not ready = %jx\n", (uintmax_t)rxr->not_done); 4409 printf("RX packets = %jx\n", (uintmax_t)rxr->rx_packets); 4410 printf("TX desc avail = %x\n", txr->avail); 4411 4412 reg = rd32(hw, I40E_GLV_GORCL(0xc)); 4413 printf("RX Bytes = %x\n", reg); 4414 reg = rd32(hw, I40E_GLPRT_GORCL(hw->port)); 4415 printf("Port RX Bytes = %x\n", reg); 4416 reg = rd32(hw, I40E_GLV_RDPC(0xc)); 4417 printf("RX discard = %x\n", reg); 4418 reg = rd32(hw, I40E_GLPRT_RDPC(hw->port)); 4419 printf("Port RX discard = %x\n", reg); 4420 4421 reg = rd32(hw, I40E_GLV_TEPC(0xc)); 4422 printf("TX errors = %x\n", reg); 4423 reg = rd32(hw, I40E_GLV_GOTCL(0xc)); 4424 printf("TX Bytes = %x\n", reg); 4425 4426 reg = rd32(hw, I40E_GLPRT_RUC(hw->port)); 4427 printf("RX undersize = %x\n", reg); 4428 reg = rd32(hw, I40E_GLPRT_RFC(hw->port)); 4429 printf("RX fragments = %x\n", reg); 4430 reg = rd32(hw, I40E_GLPRT_ROC(hw->port)); 4431 printf("RX oversize = %x\n", reg); 4432 reg = rd32(hw, I40E_GLPRT_RLEC(hw->port)); 4433 printf("RX length error = %x\n", reg); 4434 reg = rd32(hw, I40E_GLPRT_MRFC(hw->port)); 4435 printf("mac remote fault = %x\n", reg); 4436 reg = rd32(hw, I40E_GLPRT_MLFC(hw->port)); 4437 printf("mac local fault = %x\n", reg); 4438} 4439#endif 4440 4441/** 4442 * Update VSI-specific ethernet statistics counters. 4443 **/ 4444void ixl_update_eth_stats(struct ixl_vsi *vsi) 4445{ 4446 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 4447 struct i40e_hw *hw = &pf->hw; 4448 struct i40e_eth_stats *es; 4449 struct i40e_eth_stats *oes; 4450 struct i40e_hw_port_stats *nsd; 4451 u16 stat_idx = vsi->info.stat_counter_idx; 4452 4453 es = &vsi->eth_stats; 4454 oes = &vsi->eth_stats_offsets; 4455 nsd = &pf->stats; 4456 4457 /* Gather up the stats that the hw collects */ 4458 ixl_stat_update32(hw, I40E_GLV_TEPC(stat_idx), 4459 vsi->stat_offsets_loaded, 4460 &oes->tx_errors, &es->tx_errors); 4461 ixl_stat_update32(hw, I40E_GLV_RDPC(stat_idx), 4462 vsi->stat_offsets_loaded, 4463 &oes->rx_discards, &es->rx_discards); 4464 4465 ixl_stat_update48(hw, I40E_GLV_GORCH(stat_idx), 4466 I40E_GLV_GORCL(stat_idx), 4467 vsi->stat_offsets_loaded, 4468 &oes->rx_bytes, &es->rx_bytes); 4469 ixl_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), 4470 I40E_GLV_UPRCL(stat_idx), 4471 vsi->stat_offsets_loaded, 4472 &oes->rx_unicast, &es->rx_unicast); 4473 ixl_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), 4474 I40E_GLV_MPRCL(stat_idx), 4475 vsi->stat_offsets_loaded, 4476 &oes->rx_multicast, &es->rx_multicast); 4477 ixl_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), 4478 I40E_GLV_BPRCL(stat_idx), 4479 vsi->stat_offsets_loaded, 4480 &oes->rx_broadcast, &es->rx_broadcast); 4481 4482 ixl_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), 4483 I40E_GLV_GOTCL(stat_idx), 4484 vsi->stat_offsets_loaded, 4485 &oes->tx_bytes, &es->tx_bytes); 4486 ixl_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), 4487 I40E_GLV_UPTCL(stat_idx), 4488 vsi->stat_offsets_loaded, 4489 &oes->tx_unicast, &es->tx_unicast); 4490 ixl_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), 4491 I40E_GLV_MPTCL(stat_idx), 4492 vsi->stat_offsets_loaded, 4493 &oes->tx_multicast, &es->tx_multicast); 4494 ixl_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), 4495 I40E_GLV_BPTCL(stat_idx), 4496 vsi->stat_offsets_loaded, 4497 &oes->tx_broadcast, &es->tx_broadcast); 4498 vsi->stat_offsets_loaded = true; 4499} 4500 4501static void 4502ixl_update_vsi_stats(struct ixl_vsi *vsi) 4503{ 4504 struct ixl_pf *pf; 4505 struct ifnet *ifp; 4506 struct i40e_eth_stats *es; 4507 u64 tx_discards; 4508 4509 struct i40e_hw_port_stats *nsd; 4510 4511 pf = vsi->back; 4512 ifp = vsi->ifp; 4513 es = &vsi->eth_stats; 4514 nsd = &pf->stats; 4515 4516 ixl_update_eth_stats(vsi); 4517 4518 tx_discards = es->tx_discards + nsd->tx_dropped_link_down; 4519 for (int i = 0; i < vsi->num_queues; i++) 4520 tx_discards += vsi->queues[i].txr.br->br_drops; 4521 4522 /* Update ifnet stats */ 4523 IXL_SET_IPACKETS(vsi, es->rx_unicast + 4524 es->rx_multicast + 4525 es->rx_broadcast); 4526 IXL_SET_OPACKETS(vsi, es->tx_unicast + 4527 es->tx_multicast + 4528 es->tx_broadcast); 4529 IXL_SET_IBYTES(vsi, es->rx_bytes); 4530 IXL_SET_OBYTES(vsi, es->tx_bytes); 4531 IXL_SET_IMCASTS(vsi, es->rx_multicast); 4532 IXL_SET_OMCASTS(vsi, es->tx_multicast); 4533 4534 IXL_SET_IERRORS(vsi, nsd->crc_errors + nsd->illegal_bytes + 4535 nsd->rx_undersize + nsd->rx_oversize + nsd->rx_fragments + 4536 nsd->rx_jabber); 4537 IXL_SET_OERRORS(vsi, es->tx_errors); 4538 IXL_SET_IQDROPS(vsi, es->rx_discards + nsd->eth.rx_discards); 4539 IXL_SET_OQDROPS(vsi, tx_discards); 4540 IXL_SET_NOPROTO(vsi, es->rx_unknown_protocol); 4541 IXL_SET_COLLISIONS(vsi, 0); 4542} 4543 4544/** 4545 * Reset all of the stats for the given pf 4546 **/ 4547void ixl_pf_reset_stats(struct ixl_pf *pf) 4548{ 4549 bzero(&pf->stats, sizeof(struct i40e_hw_port_stats)); 4550 bzero(&pf->stats_offsets, sizeof(struct i40e_hw_port_stats)); 4551 pf->stat_offsets_loaded = false; 4552} 4553 4554/** 4555 * Resets all stats of the given vsi 4556 **/ 4557void ixl_vsi_reset_stats(struct ixl_vsi *vsi) 4558{ 4559 bzero(&vsi->eth_stats, sizeof(struct i40e_eth_stats)); 4560 bzero(&vsi->eth_stats_offsets, sizeof(struct i40e_eth_stats)); 4561 vsi->stat_offsets_loaded = false; 4562} 4563 4564/** 4565 * Read and update a 48 bit stat from the hw 4566 * 4567 * Since the device stats are not reset at PFReset, they likely will not 4568 * be zeroed when the driver starts. We'll save the first values read 4569 * and use them as offsets to be subtracted from the raw values in order 4570 * to report stats that count from zero. 4571 **/ 4572static void 4573ixl_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, 4574 bool offset_loaded, u64 *offset, u64 *stat) 4575{ 4576 u64 new_data; 4577 4578#if defined(__FreeBSD__) && (__FreeBSD_version >= 1000000) && defined(__amd64__) 4579 new_data = rd64(hw, loreg); 4580#else 4581 /* 4582 * Use two rd32's instead of one rd64; FreeBSD versions before 4583 * 10 don't support 8 byte bus reads/writes. 4584 */ 4585 new_data = rd32(hw, loreg); 4586 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; 4587#endif 4588 4589 if (!offset_loaded) 4590 *offset = new_data; 4591 if (new_data >= *offset) 4592 *stat = new_data - *offset; 4593 else 4594 *stat = (new_data + ((u64)1 << 48)) - *offset; 4595 *stat &= 0xFFFFFFFFFFFFULL; 4596} 4597 4598/** 4599 * Read and update a 32 bit stat from the hw 4600 **/ 4601static void 4602ixl_stat_update32(struct i40e_hw *hw, u32 reg, 4603 bool offset_loaded, u64 *offset, u64 *stat) 4604{ 4605 u32 new_data; 4606 4607 new_data = rd32(hw, reg); 4608 if (!offset_loaded) 4609 *offset = new_data; 4610 if (new_data >= *offset) 4611 *stat = (u32)(new_data - *offset); 4612 else 4613 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset); 4614} 4615 4616/* 4617** Set flow control using sysctl: 4618** 0 - off 4619** 1 - rx pause 4620** 2 - tx pause 4621** 3 - full 4622*/ 4623static int 4624ixl_set_flowcntl(SYSCTL_HANDLER_ARGS) 4625{ 4626 /* 4627 * TODO: ensure flow control is disabled if 4628 * priority flow control is enabled 4629 * 4630 * TODO: ensure tx CRC by hardware should be enabled 4631 * if tx flow control is enabled. 4632 */ 4633 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4634 struct i40e_hw *hw = &pf->hw; 4635 device_t dev = pf->dev; 4636 int error = 0; 4637 enum i40e_status_code aq_error = 0; 4638 u8 fc_aq_err = 0; 4639 4640 /* Get request */ 4641 error = sysctl_handle_int(oidp, &pf->fc, 0, req); 4642 if ((error) || (req->newptr == NULL)) 4643 return (error); 4644 if (pf->fc < 0 || pf->fc > 3) { 4645 device_printf(dev, 4646 "Invalid fc mode; valid modes are 0 through 3\n"); 4647 return (EINVAL); 4648 } 4649 4650 /* 4651 ** Changing flow control mode currently does not work on 4652 ** 40GBASE-CR4 PHYs 4653 */ 4654 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4 4655 || hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4_CU) { 4656 device_printf(dev, "Changing flow control mode unsupported" 4657 " on 40GBase-CR4 media.\n"); 4658 return (ENODEV); 4659 } 4660 4661 /* Set fc ability for port */ 4662 hw->fc.requested_mode = pf->fc; 4663 aq_error = i40e_set_fc(hw, &fc_aq_err, TRUE); 4664 if (aq_error) { 4665 device_printf(dev, 4666 "%s: Error setting new fc mode %d; fc_err %#x\n", 4667 __func__, aq_error, fc_aq_err); 4668 return (EAGAIN); 4669 } 4670 4671 return (0); 4672} 4673 4674static int 4675ixl_current_speed(SYSCTL_HANDLER_ARGS) 4676{ 4677 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4678 struct i40e_hw *hw = &pf->hw; 4679 int error = 0, index = 0; 4680 4681 char *speeds[] = { 4682 "Unknown", 4683 "100M", 4684 "1G", 4685 "10G", 4686 "40G", 4687 "20G" 4688 }; 4689 4690 ixl_update_link_status(pf); 4691 4692 switch (hw->phy.link_info.link_speed) { 4693 case I40E_LINK_SPEED_100MB: 4694 index = 1; 4695 break; 4696 case I40E_LINK_SPEED_1GB: 4697 index = 2; 4698 break; 4699 case I40E_LINK_SPEED_10GB: 4700 index = 3; 4701 break; 4702 case I40E_LINK_SPEED_40GB: 4703 index = 4; 4704 break; 4705 case I40E_LINK_SPEED_20GB: 4706 index = 5; 4707 break; 4708 case I40E_LINK_SPEED_UNKNOWN: 4709 default: 4710 index = 0; 4711 break; 4712 } 4713 4714 error = sysctl_handle_string(oidp, speeds[index], 4715 strlen(speeds[index]), req); 4716 return (error); 4717} 4718 4719static int 4720ixl_set_advertised_speeds(struct ixl_pf *pf, int speeds) 4721{ 4722 struct i40e_hw *hw = &pf->hw; 4723 device_t dev = pf->dev; 4724 struct i40e_aq_get_phy_abilities_resp abilities; 4725 struct i40e_aq_set_phy_config config; 4726 enum i40e_status_code aq_error = 0; 4727 4728 /* Get current capability information */ 4729 aq_error = i40e_aq_get_phy_capabilities(hw, 4730 FALSE, FALSE, &abilities, NULL); 4731 if (aq_error) { 4732 device_printf(dev, 4733 "%s: Error getting phy capabilities %d," 4734 " aq error: %d\n", __func__, aq_error, 4735 hw->aq.asq_last_status); 4736 return (EAGAIN); 4737 } 4738 4739 /* Prepare new config */ 4740 bzero(&config, sizeof(config)); 4741 config.phy_type = abilities.phy_type; 4742 config.abilities = abilities.abilities 4743 | I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 4744 config.eee_capability = abilities.eee_capability; 4745 config.eeer = abilities.eeer_val; 4746 config.low_power_ctrl = abilities.d3_lpan; 4747 /* Translate into aq cmd link_speed */ 4748 if (speeds & 0x8) 4749 config.link_speed |= I40E_LINK_SPEED_20GB; 4750 if (speeds & 0x4) 4751 config.link_speed |= I40E_LINK_SPEED_10GB; 4752 if (speeds & 0x2) 4753 config.link_speed |= I40E_LINK_SPEED_1GB; 4754 if (speeds & 0x1) 4755 config.link_speed |= I40E_LINK_SPEED_100MB; 4756 4757 /* Do aq command & restart link */ 4758 aq_error = i40e_aq_set_phy_config(hw, &config, NULL); 4759 if (aq_error) { 4760 device_printf(dev, 4761 "%s: Error setting new phy config %d," 4762 " aq error: %d\n", __func__, aq_error, 4763 hw->aq.asq_last_status); 4764 return (EAGAIN); 4765 } 4766 4767 /* 4768 ** This seems a bit heavy handed, but we 4769 ** need to get a reinit on some devices 4770 */ 4771 IXL_PF_LOCK(pf); 4772 ixl_stop(pf); 4773 ixl_init_locked(pf); 4774 IXL_PF_UNLOCK(pf); 4775 4776 return (0); 4777} 4778 4779/* 4780** Control link advertise speed: 4781** Flags: 4782** 0x1 - advertise 100 Mb 4783** 0x2 - advertise 1G 4784** 0x4 - advertise 10G 4785** 0x8 - advertise 20G 4786** 4787** Does not work on 40G devices. 4788*/ 4789static int 4790ixl_set_advertise(SYSCTL_HANDLER_ARGS) 4791{ 4792 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4793 struct i40e_hw *hw = &pf->hw; 4794 device_t dev = pf->dev; 4795 int requested_ls = 0; 4796 int error = 0; 4797 4798 /* 4799 ** FW doesn't support changing advertised speed 4800 ** for 40G devices; speed is always 40G. 4801 */ 4802 if (i40e_is_40G_device(hw->device_id)) 4803 return (ENODEV); 4804 4805 /* Read in new mode */ 4806 requested_ls = pf->advertised_speed; 4807 error = sysctl_handle_int(oidp, &requested_ls, 0, req); 4808 if ((error) || (req->newptr == NULL)) 4809 return (error); 4810 /* Check for sane value */ 4811 if (requested_ls < 0x1 || requested_ls > 0xE) { 4812 device_printf(dev, "Invalid advertised speed; " 4813 "valid modes are 0x1 through 0xE\n"); 4814 return (EINVAL); 4815 } 4816 /* Then check for validity based on adapter type */ 4817 switch (hw->device_id) { 4818 case I40E_DEV_ID_10G_BASE_T: 4819 if (requested_ls & 0x8) { 4820 device_printf(dev, 4821 "20Gbs speed not supported on this device.\n"); 4822 return (EINVAL); 4823 } 4824 break; 4825 case I40E_DEV_ID_20G_KR2: 4826 if (requested_ls & 0x1) { 4827 device_printf(dev, 4828 "100Mbs speed not supported on this device.\n"); 4829 return (EINVAL); 4830 } 4831 break; 4832 default: 4833 if (requested_ls & ~0x6) { 4834 device_printf(dev, 4835 "Only 1/10Gbs speeds are supported on this device.\n"); 4836 return (EINVAL); 4837 } 4838 break; 4839 } 4840 4841 /* Exit if no change */ 4842 if (pf->advertised_speed == requested_ls) 4843 return (0); 4844 4845 error = ixl_set_advertised_speeds(pf, requested_ls); 4846 if (error) 4847 return (error); 4848 4849 pf->advertised_speed = requested_ls; 4850 ixl_update_link_status(pf); 4851 return (0); 4852} 4853 4854/* 4855** Get the width and transaction speed of 4856** the bus this adapter is plugged into. 4857*/ 4858static u16 4859ixl_get_bus_info(struct i40e_hw *hw, device_t dev) 4860{ 4861 u16 link; 4862 u32 offset; 4863 4864 4865 /* Get the PCI Express Capabilities offset */ 4866 pci_find_cap(dev, PCIY_EXPRESS, &offset); 4867 4868 /* ...and read the Link Status Register */ 4869 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 4870 4871 switch (link & I40E_PCI_LINK_WIDTH) { 4872 case I40E_PCI_LINK_WIDTH_1: 4873 hw->bus.width = i40e_bus_width_pcie_x1; 4874 break; 4875 case I40E_PCI_LINK_WIDTH_2: 4876 hw->bus.width = i40e_bus_width_pcie_x2; 4877 break; 4878 case I40E_PCI_LINK_WIDTH_4: 4879 hw->bus.width = i40e_bus_width_pcie_x4; 4880 break; 4881 case I40E_PCI_LINK_WIDTH_8: 4882 hw->bus.width = i40e_bus_width_pcie_x8; 4883 break; 4884 default: 4885 hw->bus.width = i40e_bus_width_unknown; 4886 break; 4887 } 4888 4889 switch (link & I40E_PCI_LINK_SPEED) { 4890 case I40E_PCI_LINK_SPEED_2500: 4891 hw->bus.speed = i40e_bus_speed_2500; 4892 break; 4893 case I40E_PCI_LINK_SPEED_5000: 4894 hw->bus.speed = i40e_bus_speed_5000; 4895 break; 4896 case I40E_PCI_LINK_SPEED_8000: 4897 hw->bus.speed = i40e_bus_speed_8000; 4898 break; 4899 default: 4900 hw->bus.speed = i40e_bus_speed_unknown; 4901 break; 4902 } 4903 4904 4905 device_printf(dev,"PCI Express Bus: Speed %s %s\n", 4906 ((hw->bus.speed == i40e_bus_speed_8000) ? "8.0GT/s": 4907 (hw->bus.speed == i40e_bus_speed_5000) ? "5.0GT/s": 4908 (hw->bus.speed == i40e_bus_speed_2500) ? "2.5GT/s":"Unknown"), 4909 (hw->bus.width == i40e_bus_width_pcie_x8) ? "Width x8" : 4910 (hw->bus.width == i40e_bus_width_pcie_x4) ? "Width x4" : 4911 (hw->bus.width == i40e_bus_width_pcie_x1) ? "Width x1" : 4912 ("Unknown")); 4913 4914 if ((hw->bus.width <= i40e_bus_width_pcie_x8) && 4915 (hw->bus.speed < i40e_bus_speed_8000)) { 4916 device_printf(dev, "PCI-Express bandwidth available" 4917 " for this device\n may be insufficient for" 4918 " optimal performance.\n"); 4919 device_printf(dev, "For expected performance a x8 " 4920 "PCIE Gen3 slot is required.\n"); 4921 } 4922 4923 return (link); 4924} 4925 4926static int 4927ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS) 4928{ 4929 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4930 struct i40e_hw *hw = &pf->hw; 4931 char buf[32]; 4932 4933 snprintf(buf, sizeof(buf), 4934 "f%d.%d a%d.%d n%02x.%02x e%08x", 4935 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 4936 hw->aq.api_maj_ver, hw->aq.api_min_ver, 4937 (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >> 4938 IXL_NVM_VERSION_HI_SHIFT, 4939 (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >> 4940 IXL_NVM_VERSION_LO_SHIFT, 4941 hw->nvm.eetrack); 4942 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4943} 4944 4945 4946#ifdef IXL_DEBUG_SYSCTL 4947static int 4948ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS) 4949{ 4950 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4951 struct i40e_hw *hw = &pf->hw; 4952 struct i40e_link_status link_status; 4953 char buf[512]; 4954 4955 enum i40e_status_code aq_error = 0; 4956 4957 aq_error = i40e_aq_get_link_info(hw, TRUE, &link_status, NULL); 4958 if (aq_error) { 4959 printf("i40e_aq_get_link_info() error %d\n", aq_error); 4960 return (EPERM); 4961 } 4962 4963 sprintf(buf, "\n" 4964 "PHY Type : %#04x\n" 4965 "Speed : %#04x\n" 4966 "Link info: %#04x\n" 4967 "AN info : %#04x\n" 4968 "Ext info : %#04x", 4969 link_status.phy_type, link_status.link_speed, 4970 link_status.link_info, link_status.an_info, 4971 link_status.ext_info); 4972 4973 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4974} 4975 4976static int 4977ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS) 4978{ 4979 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4980 struct i40e_hw *hw = &pf->hw; 4981 char buf[512]; 4982 enum i40e_status_code aq_error = 0; 4983 4984 struct i40e_aq_get_phy_abilities_resp abilities; 4985 4986 aq_error = i40e_aq_get_phy_capabilities(hw, 4987 TRUE, FALSE, &abilities, NULL); 4988 if (aq_error) { 4989 printf("i40e_aq_get_phy_capabilities() error %d\n", aq_error); 4990 return (EPERM); 4991 } 4992 4993 sprintf(buf, "\n" 4994 "PHY Type : %#010x\n" 4995 "Speed : %#04x\n" 4996 "Abilities: %#04x\n" 4997 "EEE cap : %#06x\n" 4998 "EEER reg : %#010x\n" 4999 "D3 Lpan : %#04x", 5000 abilities.phy_type, abilities.link_speed, 5001 abilities.abilities, abilities.eee_capability, 5002 abilities.eeer_val, abilities.d3_lpan); 5003 5004 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 5005} 5006 5007static int 5008ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS) 5009{ 5010 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5011 struct ixl_vsi *vsi = &pf->vsi; 5012 struct ixl_mac_filter *f; 5013 char *buf, *buf_i; 5014 5015 int error = 0; 5016 int ftl_len = 0; 5017 int ftl_counter = 0; 5018 int buf_len = 0; 5019 int entry_len = 42; 5020 5021 SLIST_FOREACH(f, &vsi->ftl, next) { 5022 ftl_len++; 5023 } 5024 5025 if (ftl_len < 1) { 5026 sysctl_handle_string(oidp, "(none)", 6, req); 5027 return (0); 5028 } 5029 5030 buf_len = sizeof(char) * (entry_len + 1) * ftl_len + 2; 5031 buf = buf_i = malloc(buf_len, M_DEVBUF, M_NOWAIT); 5032 5033 sprintf(buf_i++, "\n"); 5034 SLIST_FOREACH(f, &vsi->ftl, next) { 5035 sprintf(buf_i, 5036 MAC_FORMAT ", vlan %4d, flags %#06x", 5037 MAC_FORMAT_ARGS(f->macaddr), f->vlan, f->flags); 5038 buf_i += entry_len; 5039 /* don't print '\n' for last entry */ 5040 if (++ftl_counter != ftl_len) { 5041 sprintf(buf_i, "\n"); 5042 buf_i++; 5043 } 5044 } 5045 5046 error = sysctl_handle_string(oidp, buf, strlen(buf), req); 5047 if (error) 5048 printf("sysctl error: %d\n", error); 5049 free(buf, M_DEVBUF); 5050 return error; 5051} 5052 5053#define IXL_SW_RES_SIZE 0x14 5054static int 5055ixl_res_alloc_cmp(const void *a, const void *b) 5056{ 5057 const struct i40e_aqc_switch_resource_alloc_element_resp *one, *two; 5058 one = (const struct i40e_aqc_switch_resource_alloc_element_resp *)a; 5059 two = (const struct i40e_aqc_switch_resource_alloc_element_resp *)b; 5060 5061 return ((int)one->resource_type - (int)two->resource_type); 5062} 5063 5064static int 5065ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS) 5066{ 5067 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5068 struct i40e_hw *hw = &pf->hw; 5069 device_t dev = pf->dev; 5070 struct sbuf *buf; 5071 int error = 0; 5072 5073 u8 num_entries; 5074 struct i40e_aqc_switch_resource_alloc_element_resp resp[IXL_SW_RES_SIZE]; 5075 5076 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 5077 if (!buf) { 5078 device_printf(dev, "Could not allocate sbuf for output.\n"); 5079 return (ENOMEM); 5080 } 5081 5082 bzero(resp, sizeof(resp)); 5083 error = i40e_aq_get_switch_resource_alloc(hw, &num_entries, 5084 resp, 5085 IXL_SW_RES_SIZE, 5086 NULL); 5087 if (error) { 5088 device_printf(dev, 5089 "%s: get_switch_resource_alloc() error %d, aq error %d\n", 5090 __func__, error, hw->aq.asq_last_status); 5091 sbuf_delete(buf); 5092 return error; 5093 } 5094 5095 /* Sort entries by type for display */ 5096 qsort(resp, num_entries, 5097 sizeof(struct i40e_aqc_switch_resource_alloc_element_resp), 5098 &ixl_res_alloc_cmp); 5099 5100 sbuf_cat(buf, "\n"); 5101 sbuf_printf(buf, "# of entries: %d\n", num_entries); 5102 sbuf_printf(buf, 5103 "Type | Guaranteed | Total | Used | Un-allocated\n" 5104 " | (this) | (all) | (this) | (all) \n"); 5105 for (int i = 0; i < num_entries; i++) { 5106 sbuf_printf(buf, 5107 "%#4x | %10d %5d %6d %12d", 5108 resp[i].resource_type, 5109 resp[i].guaranteed, 5110 resp[i].total, 5111 resp[i].used, 5112 resp[i].total_unalloced); 5113 if (i < num_entries - 1) 5114 sbuf_cat(buf, "\n"); 5115 } 5116 5117 error = sbuf_finish(buf); 5118 if (error) { 5119 device_printf(dev, "Error finishing sbuf: %d\n", error); 5120 sbuf_delete(buf); 5121 return error; 5122 } 5123 5124 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 5125 if (error) 5126 device_printf(dev, "sysctl error: %d\n", error); 5127 sbuf_delete(buf); 5128 5129 return (error); 5130} 5131 5132/* 5133** Caller must init and delete sbuf; this function will clear and 5134** finish it for caller. 5135*/ 5136static char * 5137ixl_switch_element_string(struct sbuf *s, u16 seid, bool uplink) 5138{ 5139 sbuf_clear(s); 5140 5141 if (seid == 0 && uplink) 5142 sbuf_cat(s, "Network"); 5143 else if (seid == 0) 5144 sbuf_cat(s, "Host"); 5145 else if (seid == 1) 5146 sbuf_cat(s, "EMP"); 5147 else if (seid <= 5) 5148 sbuf_printf(s, "MAC %d", seid - 2); 5149 else if (seid <= 15) 5150 sbuf_cat(s, "Reserved"); 5151 else if (seid <= 31) 5152 sbuf_printf(s, "PF %d", seid - 16); 5153 else if (seid <= 159) 5154 sbuf_printf(s, "VF %d", seid - 32); 5155 else if (seid <= 287) 5156 sbuf_cat(s, "Reserved"); 5157 else if (seid <= 511) 5158 sbuf_cat(s, "Other"); // for other structures 5159 else if (seid <= 895) 5160 sbuf_printf(s, "VSI %d", seid - 512); 5161 else if (seid <= 1023) 5162 sbuf_printf(s, "Reserved"); 5163 else 5164 sbuf_cat(s, "Invalid"); 5165 5166 sbuf_finish(s); 5167 return sbuf_data(s); 5168} 5169 5170static int 5171ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS) 5172{ 5173 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5174 struct i40e_hw *hw = &pf->hw; 5175 device_t dev = pf->dev; 5176 struct sbuf *buf; 5177 struct sbuf *nmbuf; 5178 int error = 0; 5179 u8 aq_buf[I40E_AQ_LARGE_BUF]; 5180 5181 u16 next = 0; 5182 struct i40e_aqc_get_switch_config_resp *sw_config; 5183 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 5184 5185 buf = sbuf_new_for_sysctl(NULL, NULL, 0, req); 5186 if (!buf) { 5187 device_printf(dev, "Could not allocate sbuf for sysctl output.\n"); 5188 return (ENOMEM); 5189 } 5190 5191 error = i40e_aq_get_switch_config(hw, sw_config, 5192 sizeof(aq_buf), &next, NULL); 5193 if (error) { 5194 device_printf(dev, 5195 "%s: aq_get_switch_config() error %d, aq error %d\n", 5196 __func__, error, hw->aq.asq_last_status); 5197 sbuf_delete(buf); 5198 return error; 5199 } 5200 5201 nmbuf = sbuf_new_auto(); 5202 if (!nmbuf) { 5203 device_printf(dev, "Could not allocate sbuf for name output.\n"); 5204 return (ENOMEM); 5205 } 5206 5207 sbuf_cat(buf, "\n"); 5208 // Assuming <= 255 elements in switch 5209 sbuf_printf(buf, "# of elements: %d\n", sw_config->header.num_reported); 5210 /* Exclude: 5211 ** Revision -- all elements are revision 1 for now 5212 */ 5213 sbuf_printf(buf, 5214 "SEID ( Name ) | Uplink | Downlink | Conn Type\n" 5215 " | | | (uplink)\n"); 5216 for (int i = 0; i < sw_config->header.num_reported; i++) { 5217 // "%4d (%8s) | %8s %8s %#8x", 5218 sbuf_printf(buf, "%4d", sw_config->element[i].seid); 5219 sbuf_cat(buf, " "); 5220 sbuf_printf(buf, "(%8s)", ixl_switch_element_string(nmbuf, 5221 sw_config->element[i].seid, false)); 5222 sbuf_cat(buf, " | "); 5223 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, 5224 sw_config->element[i].uplink_seid, true)); 5225 sbuf_cat(buf, " "); 5226 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, 5227 sw_config->element[i].downlink_seid, false)); 5228 sbuf_cat(buf, " "); 5229 sbuf_printf(buf, "%#8x", sw_config->element[i].connection_type); 5230 if (i < sw_config->header.num_reported - 1) 5231 sbuf_cat(buf, "\n"); 5232 } 5233 sbuf_delete(nmbuf); 5234 5235 error = sbuf_finish(buf); 5236 if (error) { 5237 device_printf(dev, "Error finishing sbuf: %d\n", error); 5238 sbuf_delete(buf); 5239 return error; 5240 } 5241 5242 error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req); 5243 if (error) 5244 device_printf(dev, "sysctl error: %d\n", error); 5245 sbuf_delete(buf); 5246 5247 return (error); 5248} 5249#endif /* IXL_DEBUG_SYSCTL */ 5250 5251 5252#ifdef PCI_IOV 5253static int 5254ixl_vf_alloc_vsi(struct ixl_pf *pf, struct ixl_vf *vf) 5255{ 5256 struct i40e_hw *hw; 5257 struct ixl_vsi *vsi; 5258 struct i40e_vsi_context vsi_ctx; 5259 int i; 5260 uint16_t first_queue; 5261 enum i40e_status_code code; 5262 5263 hw = &pf->hw; 5264 vsi = &pf->vsi; 5265 5266 vsi_ctx.pf_num = hw->pf_id; 5267 vsi_ctx.uplink_seid = pf->veb_seid; 5268 vsi_ctx.connection_type = IXL_VSI_DATA_PORT; 5269 vsi_ctx.vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5270 vsi_ctx.flags = I40E_AQ_VSI_TYPE_VF; 5271 5272 bzero(&vsi_ctx.info, sizeof(vsi_ctx.info)); 5273 5274 vsi_ctx.info.valid_sections = htole16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5275 vsi_ctx.info.switch_id = htole16(0); 5276 5277 vsi_ctx.info.valid_sections |= htole16(I40E_AQ_VSI_PROP_SECURITY_VALID); 5278 vsi_ctx.info.sec_flags = 0; 5279 if (vf->vf_flags & VF_FLAG_MAC_ANTI_SPOOF) 5280 vsi_ctx.info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK; 5281 5282 vsi_ctx.info.valid_sections |= htole16(I40E_AQ_VSI_PROP_VLAN_VALID); 5283 vsi_ctx.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 5284 I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 5285 5286 vsi_ctx.info.valid_sections |= 5287 htole16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 5288 vsi_ctx.info.mapping_flags = htole16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 5289 first_queue = vsi->num_queues + vf->vf_num * IXLV_MAX_QUEUES; 5290 for (i = 0; i < IXLV_MAX_QUEUES; i++) 5291 vsi_ctx.info.queue_mapping[i] = htole16(first_queue + i); 5292 for (; i < nitems(vsi_ctx.info.queue_mapping); i++) 5293 vsi_ctx.info.queue_mapping[i] = htole16(I40E_AQ_VSI_QUEUE_MASK); 5294 5295 vsi_ctx.info.tc_mapping[0] = htole16( 5296 (0 << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 5297 (1 << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 5298 5299 code = i40e_aq_add_vsi(hw, &vsi_ctx, NULL); 5300 if (code != I40E_SUCCESS) 5301 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5302 vf->vsi.seid = vsi_ctx.seid; 5303 vf->vsi.vsi_num = vsi_ctx.vsi_number; 5304 vf->vsi.first_queue = first_queue; 5305 vf->vsi.num_queues = IXLV_MAX_QUEUES; 5306 5307 code = i40e_aq_get_vsi_params(hw, &vsi_ctx, NULL); 5308 if (code != I40E_SUCCESS) 5309 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5310 5311 code = i40e_aq_config_vsi_bw_limit(hw, vf->vsi.seid, 0, 0, NULL); 5312 if (code != I40E_SUCCESS) { 5313 device_printf(pf->dev, "Failed to disable BW limit: %d\n", 5314 ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5315 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5316 } 5317 5318 memcpy(&vf->vsi.info, &vsi_ctx.info, sizeof(vf->vsi.info)); 5319 return (0); 5320} 5321 5322static int 5323ixl_vf_setup_vsi(struct ixl_pf *pf, struct ixl_vf *vf) 5324{ 5325 struct i40e_hw *hw; 5326 int error; 5327 5328 hw = &pf->hw; 5329 5330 error = ixl_vf_alloc_vsi(pf, vf); 5331 if (error != 0) 5332 return (error); 5333 5334 vf->vsi.hw_filters_add = 0; 5335 vf->vsi.hw_filters_del = 0; 5336 ixl_add_filter(&vf->vsi, ixl_bcast_addr, IXL_VLAN_ANY); 5337 ixl_reconfigure_filters(&vf->vsi); 5338 5339 return (0); 5340} 5341 5342static void 5343ixl_vf_map_vsi_queue(struct i40e_hw *hw, struct ixl_vf *vf, int qnum, 5344 uint32_t val) 5345{ 5346 uint32_t qtable; 5347 int index, shift; 5348 5349 /* 5350 * Two queues are mapped in a single register, so we have to do some 5351 * gymnastics to convert the queue number into a register index and 5352 * shift. 5353 */ 5354 index = qnum / 2; 5355 shift = (qnum % 2) * I40E_VSILAN_QTABLE_QINDEX_1_SHIFT; 5356 5357 qtable = rd32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num)); 5358 qtable &= ~(I40E_VSILAN_QTABLE_QINDEX_0_MASK << shift); 5359 qtable |= val << shift; 5360 wr32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num), qtable); 5361} 5362 5363static void 5364ixl_vf_map_queues(struct ixl_pf *pf, struct ixl_vf *vf) 5365{ 5366 struct i40e_hw *hw; 5367 uint32_t qtable; 5368 int i; 5369 5370 hw = &pf->hw; 5371 5372 /* 5373 * Contiguous mappings aren't actually supported by the hardware, 5374 * so we have to use non-contiguous mappings. 5375 */ 5376 wr32(hw, I40E_VSILAN_QBASE(vf->vsi.vsi_num), 5377 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK); 5378 5379 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_num), 5380 I40E_VPLAN_MAPENA_TXRX_ENA_MASK); 5381 5382 for (i = 0; i < vf->vsi.num_queues; i++) { 5383 qtable = (vf->vsi.first_queue + i) << 5384 I40E_VPLAN_QTABLE_QINDEX_SHIFT; 5385 5386 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_num), qtable); 5387 } 5388 5389 /* Map queues allocated to VF to its VSI. */ 5390 for (i = 0; i < vf->vsi.num_queues; i++) 5391 ixl_vf_map_vsi_queue(hw, vf, i, vf->vsi.first_queue + i); 5392 5393 /* Set rest of VSI queues as unused. */ 5394 for (; i < IXL_MAX_VSI_QUEUES; i++) 5395 ixl_vf_map_vsi_queue(hw, vf, i, 5396 I40E_VSILAN_QTABLE_QINDEX_0_MASK); 5397 5398 ixl_flush(hw); 5399} 5400 5401static void 5402ixl_vf_vsi_release(struct ixl_pf *pf, struct ixl_vsi *vsi) 5403{ 5404 struct i40e_hw *hw; 5405 5406 hw = &pf->hw; 5407 5408 if (vsi->seid == 0) 5409 return; 5410 5411 i40e_aq_delete_element(hw, vsi->seid, NULL); 5412} 5413 5414static void 5415ixl_vf_disable_queue_intr(struct i40e_hw *hw, uint32_t vfint_reg) 5416{ 5417 5418 wr32(hw, vfint_reg, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK); 5419 ixl_flush(hw); 5420} 5421 5422static void 5423ixl_vf_unregister_intr(struct i40e_hw *hw, uint32_t vpint_reg) 5424{ 5425 5426 wr32(hw, vpint_reg, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK | 5427 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK); 5428 ixl_flush(hw); 5429} 5430 5431static void 5432ixl_vf_release_resources(struct ixl_pf *pf, struct ixl_vf *vf) 5433{ 5434 struct i40e_hw *hw; 5435 uint32_t vfint_reg, vpint_reg; 5436 int i; 5437 5438 hw = &pf->hw; 5439 5440 ixl_vf_vsi_release(pf, &vf->vsi); 5441 5442 /* Index 0 has a special register. */ 5443 ixl_vf_disable_queue_intr(hw, I40E_VFINT_DYN_CTL0(vf->vf_num)); 5444 5445 for (i = 1; i < hw->func_caps.num_msix_vectors_vf; i++) { 5446 vfint_reg = IXL_VFINT_DYN_CTLN_REG(hw, i , vf->vf_num); 5447 ixl_vf_disable_queue_intr(hw, vfint_reg); 5448 } 5449 5450 /* Index 0 has a special register. */ 5451 ixl_vf_unregister_intr(hw, I40E_VPINT_LNKLST0(vf->vf_num)); 5452 5453 for (i = 1; i < hw->func_caps.num_msix_vectors_vf; i++) { 5454 vpint_reg = IXL_VPINT_LNKLSTN_REG(hw, i, vf->vf_num); 5455 ixl_vf_unregister_intr(hw, vpint_reg); 5456 } 5457 5458 vf->vsi.num_queues = 0; 5459} 5460 5461static int 5462ixl_flush_pcie(struct ixl_pf *pf, struct ixl_vf *vf) 5463{ 5464 struct i40e_hw *hw; 5465 int i; 5466 uint16_t global_vf_num; 5467 uint32_t ciad; 5468 5469 hw = &pf->hw; 5470 global_vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5471 5472 wr32(hw, I40E_PF_PCI_CIAA, IXL_PF_PCI_CIAA_VF_DEVICE_STATUS | 5473 (global_vf_num << I40E_PF_PCI_CIAA_VF_NUM_SHIFT)); 5474 for (i = 0; i < IXL_VF_RESET_TIMEOUT; i++) { 5475 ciad = rd32(hw, I40E_PF_PCI_CIAD); 5476 if ((ciad & IXL_PF_PCI_CIAD_VF_TRANS_PENDING_MASK) == 0) 5477 return (0); 5478 DELAY(1); 5479 } 5480 5481 return (ETIMEDOUT); 5482} 5483 5484static void 5485ixl_reset_vf(struct ixl_pf *pf, struct ixl_vf *vf) 5486{ 5487 struct i40e_hw *hw; 5488 uint32_t vfrtrig; 5489 5490 hw = &pf->hw; 5491 5492 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num)); 5493 vfrtrig |= I40E_VPGEN_VFRTRIG_VFSWR_MASK; 5494 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); 5495 ixl_flush(hw); 5496 5497 ixl_reinit_vf(pf, vf); 5498} 5499 5500static void 5501ixl_reinit_vf(struct ixl_pf *pf, struct ixl_vf *vf) 5502{ 5503 struct i40e_hw *hw; 5504 uint32_t vfrstat, vfrtrig; 5505 int i, error; 5506 5507 hw = &pf->hw; 5508 5509 error = ixl_flush_pcie(pf, vf); 5510 if (error != 0) 5511 device_printf(pf->dev, 5512 "Timed out waiting for PCIe activity to stop on VF-%d\n", 5513 vf->vf_num); 5514 5515 for (i = 0; i < IXL_VF_RESET_TIMEOUT; i++) { 5516 DELAY(10); 5517 5518 vfrstat = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_num)); 5519 if (vfrstat & I40E_VPGEN_VFRSTAT_VFRD_MASK) 5520 break; 5521 } 5522 5523 if (i == IXL_VF_RESET_TIMEOUT) 5524 device_printf(pf->dev, "VF %d failed to reset\n", vf->vf_num); 5525 5526 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), I40E_VFR_COMPLETED); 5527 5528 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num)); 5529 vfrtrig &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK; 5530 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); 5531 5532 if (vf->vsi.seid != 0) 5533 ixl_disable_rings(&vf->vsi); 5534 5535 ixl_vf_release_resources(pf, vf); 5536 ixl_vf_setup_vsi(pf, vf); 5537 ixl_vf_map_queues(pf, vf); 5538 5539 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), I40E_VFR_VFACTIVE); 5540 ixl_flush(hw); 5541} 5542 5543static const char * 5544ixl_vc_opcode_str(uint16_t op) 5545{ 5546 5547 switch (op) { 5548 case I40E_VIRTCHNL_OP_VERSION: 5549 return ("VERSION"); 5550 case I40E_VIRTCHNL_OP_RESET_VF: 5551 return ("RESET_VF"); 5552 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES: 5553 return ("GET_VF_RESOURCES"); 5554 case I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE: 5555 return ("CONFIG_TX_QUEUE"); 5556 case I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE: 5557 return ("CONFIG_RX_QUEUE"); 5558 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES: 5559 return ("CONFIG_VSI_QUEUES"); 5560 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP: 5561 return ("CONFIG_IRQ_MAP"); 5562 case I40E_VIRTCHNL_OP_ENABLE_QUEUES: 5563 return ("ENABLE_QUEUES"); 5564 case I40E_VIRTCHNL_OP_DISABLE_QUEUES: 5565 return ("DISABLE_QUEUES"); 5566 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS: 5567 return ("ADD_ETHER_ADDRESS"); 5568 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS: 5569 return ("DEL_ETHER_ADDRESS"); 5570 case I40E_VIRTCHNL_OP_ADD_VLAN: 5571 return ("ADD_VLAN"); 5572 case I40E_VIRTCHNL_OP_DEL_VLAN: 5573 return ("DEL_VLAN"); 5574 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: 5575 return ("CONFIG_PROMISCUOUS_MODE"); 5576 case I40E_VIRTCHNL_OP_GET_STATS: 5577 return ("GET_STATS"); 5578 case I40E_VIRTCHNL_OP_FCOE: 5579 return ("FCOE"); 5580 case I40E_VIRTCHNL_OP_EVENT: 5581 return ("EVENT"); 5582 default: 5583 return ("UNKNOWN"); 5584 } 5585} 5586 5587static int 5588ixl_vc_opcode_level(uint16_t opcode) 5589{ 5590 5591 switch (opcode) { 5592 case I40E_VIRTCHNL_OP_GET_STATS: 5593 return (10); 5594 default: 5595 return (5); 5596 } 5597} 5598 5599static void 5600ixl_send_vf_msg(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op, 5601 enum i40e_status_code status, void *msg, uint16_t len) 5602{ 5603 struct i40e_hw *hw; 5604 int global_vf_id; 5605 5606 hw = &pf->hw; 5607 global_vf_id = hw->func_caps.vf_base_id + vf->vf_num; 5608 5609 I40E_VC_DEBUG(pf, ixl_vc_opcode_level(op), 5610 "Sending msg (op=%s[%d], status=%d) to VF-%d\n", 5611 ixl_vc_opcode_str(op), op, status, vf->vf_num); 5612 5613 i40e_aq_send_msg_to_vf(hw, global_vf_id, op, status, msg, len, NULL); 5614} 5615 5616static void 5617ixl_send_vf_ack(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op) 5618{ 5619 5620 ixl_send_vf_msg(pf, vf, op, I40E_SUCCESS, NULL, 0); 5621} 5622 5623static void 5624ixl_send_vf_nack_msg(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op, 5625 enum i40e_status_code status, const char *file, int line) 5626{ 5627 5628 I40E_VC_DEBUG(pf, 1, 5629 "Sending NACK (op=%s[%d], err=%d) to VF-%d from %s:%d\n", 5630 ixl_vc_opcode_str(op), op, status, vf->vf_num, file, line); 5631 ixl_send_vf_msg(pf, vf, op, status, NULL, 0); 5632} 5633 5634static void 5635ixl_vf_version_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5636 uint16_t msg_size) 5637{ 5638 struct i40e_virtchnl_version_info reply; 5639 5640 if (msg_size != sizeof(struct i40e_virtchnl_version_info)) { 5641 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_VERSION, 5642 I40E_ERR_PARAM); 5643 return; 5644 } 5645 5646 reply.major = I40E_VIRTCHNL_VERSION_MAJOR; 5647 reply.minor = I40E_VIRTCHNL_VERSION_MINOR; 5648 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_VERSION, I40E_SUCCESS, &reply, 5649 sizeof(reply)); 5650} 5651 5652static void 5653ixl_vf_reset_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5654 uint16_t msg_size) 5655{ 5656 5657 if (msg_size != 0) { 5658 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_RESET_VF, 5659 I40E_ERR_PARAM); 5660 return; 5661 } 5662 5663 ixl_reset_vf(pf, vf); 5664 5665 /* No response to a reset message. */ 5666} 5667 5668static void 5669ixl_vf_get_resources_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5670 uint16_t msg_size) 5671{ 5672 struct i40e_virtchnl_vf_resource reply; 5673 5674 if (msg_size != 0) { 5675 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES, 5676 I40E_ERR_PARAM); 5677 return; 5678 } 5679 5680 bzero(&reply, sizeof(reply)); 5681 5682 reply.vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2; 5683 5684 reply.num_vsis = 1; 5685 reply.num_queue_pairs = vf->vsi.num_queues; 5686 reply.max_vectors = pf->hw.func_caps.num_msix_vectors_vf; 5687 reply.vsi_res[0].vsi_id = vf->vsi.vsi_num; 5688 reply.vsi_res[0].vsi_type = I40E_VSI_SRIOV; 5689 reply.vsi_res[0].num_queue_pairs = vf->vsi.num_queues; 5690 memcpy(reply.vsi_res[0].default_mac_addr, vf->mac, ETHER_ADDR_LEN); 5691 5692 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES, 5693 I40E_SUCCESS, &reply, sizeof(reply)); 5694} 5695 5696static int 5697ixl_vf_config_tx_queue(struct ixl_pf *pf, struct ixl_vf *vf, 5698 struct i40e_virtchnl_txq_info *info) 5699{ 5700 struct i40e_hw *hw; 5701 struct i40e_hmc_obj_txq txq; 5702 uint16_t global_queue_num, global_vf_num; 5703 enum i40e_status_code status; 5704 uint32_t qtx_ctl; 5705 5706 hw = &pf->hw; 5707 global_queue_num = vf->vsi.first_queue + info->queue_id; 5708 global_vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5709 bzero(&txq, sizeof(txq)); 5710 5711 status = i40e_clear_lan_tx_queue_context(hw, global_queue_num); 5712 if (status != I40E_SUCCESS) 5713 return (EINVAL); 5714 5715 txq.base = info->dma_ring_addr / IXL_TX_CTX_BASE_UNITS; 5716 5717 txq.head_wb_ena = info->headwb_enabled; 5718 txq.head_wb_addr = info->dma_headwb_addr; 5719 txq.qlen = info->ring_len; 5720 txq.rdylist = le16_to_cpu(vf->vsi.info.qs_handle[0]); 5721 txq.rdylist_act = 0; 5722 5723 status = i40e_set_lan_tx_queue_context(hw, global_queue_num, &txq); 5724 if (status != I40E_SUCCESS) 5725 return (EINVAL); 5726 5727 qtx_ctl = I40E_QTX_CTL_VF_QUEUE | 5728 (hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) | 5729 (global_vf_num << I40E_QTX_CTL_VFVM_INDX_SHIFT); 5730 wr32(hw, I40E_QTX_CTL(global_queue_num), qtx_ctl); 5731 ixl_flush(hw); 5732 5733 return (0); 5734} 5735 5736static int 5737ixl_vf_config_rx_queue(struct ixl_pf *pf, struct ixl_vf *vf, 5738 struct i40e_virtchnl_rxq_info *info) 5739{ 5740 struct i40e_hw *hw; 5741 struct i40e_hmc_obj_rxq rxq; 5742 uint16_t global_queue_num; 5743 enum i40e_status_code status; 5744 5745 hw = &pf->hw; 5746 global_queue_num = vf->vsi.first_queue + info->queue_id; 5747 bzero(&rxq, sizeof(rxq)); 5748 5749 if (info->databuffer_size > IXL_VF_MAX_BUFFER) 5750 return (EINVAL); 5751 5752 if (info->max_pkt_size > IXL_VF_MAX_FRAME || 5753 info->max_pkt_size < ETHER_MIN_LEN) 5754 return (EINVAL); 5755 5756 if (info->splithdr_enabled) { 5757 if (info->hdr_size > IXL_VF_MAX_HDR_BUFFER) 5758 return (EINVAL); 5759 5760 rxq.hsplit_0 = info->rx_split_pos & 5761 (I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 | 5762 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP | 5763 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP | 5764 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP); 5765 rxq.hbuff = info->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT; 5766 5767 rxq.dtype = 2; 5768 } 5769 5770 status = i40e_clear_lan_rx_queue_context(hw, global_queue_num); 5771 if (status != I40E_SUCCESS) 5772 return (EINVAL); 5773 5774 rxq.base = info->dma_ring_addr / IXL_RX_CTX_BASE_UNITS; 5775 rxq.qlen = info->ring_len; 5776 5777 rxq.dbuff = info->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT; 5778 5779 rxq.dsize = 1; 5780 rxq.crcstrip = 1; 5781 rxq.l2tsel = 1; 5782 5783 rxq.rxmax = info->max_pkt_size; 5784 rxq.tphrdesc_ena = 1; 5785 rxq.tphwdesc_ena = 1; 5786 rxq.tphdata_ena = 1; 5787 rxq.tphhead_ena = 1; 5788 rxq.lrxqthresh = 2; 5789 rxq.prefena = 1; 5790 5791 status = i40e_set_lan_rx_queue_context(hw, global_queue_num, &rxq); 5792 if (status != I40E_SUCCESS) 5793 return (EINVAL); 5794 5795 return (0); 5796} 5797 5798static void 5799ixl_vf_config_vsi_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5800 uint16_t msg_size) 5801{ 5802 struct i40e_virtchnl_vsi_queue_config_info *info; 5803 struct i40e_virtchnl_queue_pair_info *pair; 5804 int i; 5805 5806 if (msg_size < sizeof(*info)) { 5807 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5808 I40E_ERR_PARAM); 5809 return; 5810 } 5811 5812 info = msg; 5813 if (info->num_queue_pairs == 0) { 5814 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5815 I40E_ERR_PARAM); 5816 return; 5817 } 5818 5819 if (msg_size != sizeof(*info) + info->num_queue_pairs * sizeof(*pair)) { 5820 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5821 I40E_ERR_PARAM); 5822 return; 5823 } 5824 5825 if (info->vsi_id != vf->vsi.vsi_num) { 5826 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5827 I40E_ERR_PARAM); 5828 return; 5829 } 5830 5831 for (i = 0; i < info->num_queue_pairs; i++) { 5832 pair = &info->qpair[i]; 5833 5834 if (pair->txq.vsi_id != vf->vsi.vsi_num || 5835 pair->rxq.vsi_id != vf->vsi.vsi_num || 5836 pair->txq.queue_id != pair->rxq.queue_id || 5837 pair->txq.queue_id >= vf->vsi.num_queues) { 5838 5839 i40e_send_vf_nack(pf, vf, 5840 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5841 return; 5842 } 5843 5844 if (ixl_vf_config_tx_queue(pf, vf, &pair->txq) != 0) { 5845 i40e_send_vf_nack(pf, vf, 5846 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5847 return; 5848 } 5849 5850 if (ixl_vf_config_rx_queue(pf, vf, &pair->rxq) != 0) { 5851 i40e_send_vf_nack(pf, vf, 5852 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5853 return; 5854 } 5855 } 5856 5857 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES); 5858} 5859 5860static void 5861ixl_vf_set_qctl(struct ixl_pf *pf, 5862 const struct i40e_virtchnl_vector_map *vector, 5863 enum i40e_queue_type cur_type, uint16_t cur_queue, 5864 enum i40e_queue_type *last_type, uint16_t *last_queue) 5865{ 5866 uint32_t offset, qctl; 5867 uint16_t itr_indx; 5868 5869 if (cur_type == I40E_QUEUE_TYPE_RX) { 5870 offset = I40E_QINT_RQCTL(cur_queue); 5871 itr_indx = vector->rxitr_idx; 5872 } else { 5873 offset = I40E_QINT_TQCTL(cur_queue); 5874 itr_indx = vector->txitr_idx; 5875 } 5876 5877 qctl = htole32((vector->vector_id << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 5878 (*last_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 5879 (*last_queue << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 5880 I40E_QINT_RQCTL_CAUSE_ENA_MASK | 5881 (itr_indx << I40E_QINT_RQCTL_ITR_INDX_SHIFT)); 5882 5883 wr32(&pf->hw, offset, qctl); 5884 5885 *last_type = cur_type; 5886 *last_queue = cur_queue; 5887} 5888 5889static void 5890ixl_vf_config_vector(struct ixl_pf *pf, struct ixl_vf *vf, 5891 const struct i40e_virtchnl_vector_map *vector) 5892{ 5893 struct i40e_hw *hw; 5894 u_int qindex; 5895 enum i40e_queue_type type, last_type; 5896 uint32_t lnklst_reg; 5897 uint16_t rxq_map, txq_map, cur_queue, last_queue; 5898 5899 hw = &pf->hw; 5900 5901 rxq_map = vector->rxq_map; 5902 txq_map = vector->txq_map; 5903 5904 last_queue = IXL_END_OF_INTR_LNKLST; 5905 last_type = I40E_QUEUE_TYPE_RX; 5906 5907 /* 5908 * The datasheet says to optimize performance, RX queues and TX queues 5909 * should be interleaved in the interrupt linked list, so we process 5910 * both at once here. 5911 */ 5912 while ((rxq_map != 0) || (txq_map != 0)) { 5913 if (txq_map != 0) { 5914 qindex = ffs(txq_map) - 1; 5915 type = I40E_QUEUE_TYPE_TX; 5916 cur_queue = vf->vsi.first_queue + qindex; 5917 ixl_vf_set_qctl(pf, vector, type, cur_queue, 5918 &last_type, &last_queue); 5919 txq_map &= ~(1 << qindex); 5920 } 5921 5922 if (rxq_map != 0) { 5923 qindex = ffs(rxq_map) - 1; 5924 type = I40E_QUEUE_TYPE_RX; 5925 cur_queue = vf->vsi.first_queue + qindex; 5926 ixl_vf_set_qctl(pf, vector, type, cur_queue, 5927 &last_type, &last_queue); 5928 rxq_map &= ~(1 << qindex); 5929 } 5930 } 5931 5932 if (vector->vector_id == 0) 5933 lnklst_reg = I40E_VPINT_LNKLST0(vf->vf_num); 5934 else 5935 lnklst_reg = IXL_VPINT_LNKLSTN_REG(hw, vector->vector_id, 5936 vf->vf_num); 5937 wr32(hw, lnklst_reg, 5938 (last_queue << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 5939 (last_type << I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 5940 5941 ixl_flush(hw); 5942} 5943 5944static void 5945ixl_vf_config_irq_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5946 uint16_t msg_size) 5947{ 5948 struct i40e_virtchnl_irq_map_info *map; 5949 struct i40e_virtchnl_vector_map *vector; 5950 struct i40e_hw *hw; 5951 int i, largest_txq, largest_rxq; 5952 5953 hw = &pf->hw; 5954 5955 if (msg_size < sizeof(*map)) { 5956 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5957 I40E_ERR_PARAM); 5958 return; 5959 } 5960 5961 map = msg; 5962 if (map->num_vectors == 0) { 5963 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5964 I40E_ERR_PARAM); 5965 return; 5966 } 5967 5968 if (msg_size != sizeof(*map) + map->num_vectors * sizeof(*vector)) { 5969 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5970 I40E_ERR_PARAM); 5971 return; 5972 } 5973 5974 for (i = 0; i < map->num_vectors; i++) { 5975 vector = &map->vecmap[i]; 5976 5977 if ((vector->vector_id >= hw->func_caps.num_msix_vectors_vf) || 5978 vector->vsi_id != vf->vsi.vsi_num) { 5979 i40e_send_vf_nack(pf, vf, 5980 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, I40E_ERR_PARAM); 5981 return; 5982 } 5983 5984 if (vector->rxq_map != 0) { 5985 largest_rxq = fls(vector->rxq_map) - 1; 5986 if (largest_rxq >= vf->vsi.num_queues) { 5987 i40e_send_vf_nack(pf, vf, 5988 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5989 I40E_ERR_PARAM); 5990 return; 5991 } 5992 } 5993 5994 if (vector->txq_map != 0) { 5995 largest_txq = fls(vector->txq_map) - 1; 5996 if (largest_txq >= vf->vsi.num_queues) { 5997 i40e_send_vf_nack(pf, vf, 5998 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5999 I40E_ERR_PARAM); 6000 return; 6001 } 6002 } 6003 6004 if (vector->rxitr_idx > IXL_MAX_ITR_IDX || 6005 vector->txitr_idx > IXL_MAX_ITR_IDX) { 6006 i40e_send_vf_nack(pf, vf, 6007 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 6008 I40E_ERR_PARAM); 6009 return; 6010 } 6011 6012 ixl_vf_config_vector(pf, vf, vector); 6013 } 6014 6015 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP); 6016} 6017 6018static void 6019ixl_vf_enable_queues_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6020 uint16_t msg_size) 6021{ 6022 struct i40e_virtchnl_queue_select *select; 6023 int error; 6024 6025 if (msg_size != sizeof(*select)) { 6026 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6027 I40E_ERR_PARAM); 6028 return; 6029 } 6030 6031 select = msg; 6032 if (select->vsi_id != vf->vsi.vsi_num || 6033 select->rx_queues == 0 || select->tx_queues == 0) { 6034 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6035 I40E_ERR_PARAM); 6036 return; 6037 } 6038 6039 error = ixl_enable_rings(&vf->vsi); 6040 if (error) { 6041 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6042 I40E_ERR_TIMEOUT); 6043 return; 6044 } 6045 6046 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES); 6047} 6048 6049static void 6050ixl_vf_disable_queues_msg(struct ixl_pf *pf, struct ixl_vf *vf, 6051 void *msg, uint16_t msg_size) 6052{ 6053 struct i40e_virtchnl_queue_select *select; 6054 int error; 6055 6056 if (msg_size != sizeof(*select)) { 6057 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6058 I40E_ERR_PARAM); 6059 return; 6060 } 6061 6062 select = msg; 6063 if (select->vsi_id != vf->vsi.vsi_num || 6064 select->rx_queues == 0 || select->tx_queues == 0) { 6065 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6066 I40E_ERR_PARAM); 6067 return; 6068 } 6069 6070 error = ixl_disable_rings(&vf->vsi); 6071 if (error) { 6072 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6073 I40E_ERR_TIMEOUT); 6074 return; 6075 } 6076 6077 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES); 6078} 6079 6080static boolean_t 6081ixl_zero_mac(const uint8_t *addr) 6082{ 6083 uint8_t zero[ETHER_ADDR_LEN] = {0, 0, 0, 0, 0, 0}; 6084 6085 return (cmp_etheraddr(addr, zero)); 6086} 6087 6088static boolean_t 6089ixl_bcast_mac(const uint8_t *addr) 6090{ 6091 6092 return (cmp_etheraddr(addr, ixl_bcast_addr)); 6093} 6094 6095static int 6096ixl_vf_mac_valid(struct ixl_vf *vf, const uint8_t *addr) 6097{ 6098 6099 if (ixl_zero_mac(addr) || ixl_bcast_mac(addr)) 6100 return (EINVAL); 6101 6102 /* 6103 * If the VF is not allowed to change its MAC address, don't let it 6104 * set a MAC filter for an address that is not a multicast address and 6105 * is not its assigned MAC. 6106 */ 6107 if (!(vf->vf_flags & VF_FLAG_SET_MAC_CAP) && 6108 !(ETHER_IS_MULTICAST(addr) || cmp_etheraddr(addr, vf->mac))) 6109 return (EPERM); 6110 6111 return (0); 6112} 6113 6114static void 6115ixl_vf_add_mac_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6116 uint16_t msg_size) 6117{ 6118 struct i40e_virtchnl_ether_addr_list *addr_list; 6119 struct i40e_virtchnl_ether_addr *addr; 6120 struct ixl_vsi *vsi; 6121 int i; 6122 size_t expected_size; 6123 6124 vsi = &vf->vsi; 6125 6126 if (msg_size < sizeof(*addr_list)) { 6127 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6128 I40E_ERR_PARAM); 6129 return; 6130 } 6131 6132 addr_list = msg; 6133 expected_size = sizeof(*addr_list) + 6134 addr_list->num_elements * sizeof(*addr); 6135 6136 if (addr_list->num_elements == 0 || 6137 addr_list->vsi_id != vsi->vsi_num || 6138 msg_size != expected_size) { 6139 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6140 I40E_ERR_PARAM); 6141 return; 6142 } 6143 6144 for (i = 0; i < addr_list->num_elements; i++) { 6145 if (ixl_vf_mac_valid(vf, addr_list->list[i].addr) != 0) { 6146 i40e_send_vf_nack(pf, vf, 6147 I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, I40E_ERR_PARAM); 6148 return; 6149 } 6150 } 6151 6152 for (i = 0; i < addr_list->num_elements; i++) { 6153 addr = &addr_list->list[i]; 6154 ixl_add_filter(vsi, addr->addr, IXL_VLAN_ANY); 6155 } 6156 6157 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS); 6158} 6159 6160static void 6161ixl_vf_del_mac_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6162 uint16_t msg_size) 6163{ 6164 struct i40e_virtchnl_ether_addr_list *addr_list; 6165 struct i40e_virtchnl_ether_addr *addr; 6166 size_t expected_size; 6167 int i; 6168 6169 if (msg_size < sizeof(*addr_list)) { 6170 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6171 I40E_ERR_PARAM); 6172 return; 6173 } 6174 6175 addr_list = msg; 6176 expected_size = sizeof(*addr_list) + 6177 addr_list->num_elements * sizeof(*addr); 6178 6179 if (addr_list->num_elements == 0 || 6180 addr_list->vsi_id != vf->vsi.vsi_num || 6181 msg_size != expected_size) { 6182 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6183 I40E_ERR_PARAM); 6184 return; 6185 } 6186 6187 for (i = 0; i < addr_list->num_elements; i++) { 6188 addr = &addr_list->list[i]; 6189 if (ixl_zero_mac(addr->addr) || ixl_bcast_mac(addr->addr)) { 6190 i40e_send_vf_nack(pf, vf, 6191 I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, I40E_ERR_PARAM); 6192 return; 6193 } 6194 } 6195 6196 for (i = 0; i < addr_list->num_elements; i++) { 6197 addr = &addr_list->list[i]; 6198 ixl_del_filter(&vf->vsi, addr->addr, IXL_VLAN_ANY); 6199 } 6200 6201 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS); 6202} 6203 6204static enum i40e_status_code 6205ixl_vf_enable_vlan_strip(struct ixl_pf *pf, struct ixl_vf *vf) 6206{ 6207 struct i40e_vsi_context vsi_ctx; 6208 6209 vsi_ctx.seid = vf->vsi.seid; 6210 6211 bzero(&vsi_ctx.info, sizeof(vsi_ctx.info)); 6212 vsi_ctx.info.valid_sections = htole16(I40E_AQ_VSI_PROP_VLAN_VALID); 6213 vsi_ctx.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 6214 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 6215 return (i40e_aq_update_vsi_params(&pf->hw, &vsi_ctx, NULL)); 6216} 6217 6218static void 6219ixl_vf_add_vlan_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6220 uint16_t msg_size) 6221{ 6222 struct i40e_virtchnl_vlan_filter_list *filter_list; 6223 enum i40e_status_code code; 6224 size_t expected_size; 6225 int i; 6226 6227 if (msg_size < sizeof(*filter_list)) { 6228 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6229 I40E_ERR_PARAM); 6230 return; 6231 } 6232 6233 filter_list = msg; 6234 expected_size = sizeof(*filter_list) + 6235 filter_list->num_elements * sizeof(uint16_t); 6236 if (filter_list->num_elements == 0 || 6237 filter_list->vsi_id != vf->vsi.vsi_num || 6238 msg_size != expected_size) { 6239 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6240 I40E_ERR_PARAM); 6241 return; 6242 } 6243 6244 if (!(vf->vf_flags & VF_FLAG_VLAN_CAP)) { 6245 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6246 I40E_ERR_PARAM); 6247 return; 6248 } 6249 6250 for (i = 0; i < filter_list->num_elements; i++) { 6251 if (filter_list->vlan_id[i] > EVL_VLID_MASK) { 6252 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6253 I40E_ERR_PARAM); 6254 return; 6255 } 6256 } 6257 6258 code = ixl_vf_enable_vlan_strip(pf, vf); 6259 if (code != I40E_SUCCESS) { 6260 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6261 I40E_ERR_PARAM); 6262 } 6263 6264 for (i = 0; i < filter_list->num_elements; i++) 6265 ixl_add_filter(&vf->vsi, vf->mac, filter_list->vlan_id[i]); 6266 6267 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN); 6268} 6269 6270static void 6271ixl_vf_del_vlan_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6272 uint16_t msg_size) 6273{ 6274 struct i40e_virtchnl_vlan_filter_list *filter_list; 6275 int i; 6276 size_t expected_size; 6277 6278 if (msg_size < sizeof(*filter_list)) { 6279 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN, 6280 I40E_ERR_PARAM); 6281 return; 6282 } 6283 6284 filter_list = msg; 6285 expected_size = sizeof(*filter_list) + 6286 filter_list->num_elements * sizeof(uint16_t); 6287 if (filter_list->num_elements == 0 || 6288 filter_list->vsi_id != vf->vsi.vsi_num || 6289 msg_size != expected_size) { 6290 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN, 6291 I40E_ERR_PARAM); 6292 return; 6293 } 6294 6295 for (i = 0; i < filter_list->num_elements; i++) { 6296 if (filter_list->vlan_id[i] > EVL_VLID_MASK) { 6297 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6298 I40E_ERR_PARAM); 6299 return; 6300 } 6301 } 6302 6303 if (!(vf->vf_flags & VF_FLAG_VLAN_CAP)) { 6304 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6305 I40E_ERR_PARAM); 6306 return; 6307 } 6308 6309 for (i = 0; i < filter_list->num_elements; i++) 6310 ixl_del_filter(&vf->vsi, vf->mac, filter_list->vlan_id[i]); 6311 6312 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN); 6313} 6314 6315static void 6316ixl_vf_config_promisc_msg(struct ixl_pf *pf, struct ixl_vf *vf, 6317 void *msg, uint16_t msg_size) 6318{ 6319 struct i40e_virtchnl_promisc_info *info; 6320 enum i40e_status_code code; 6321 6322 if (msg_size != sizeof(*info)) { 6323 i40e_send_vf_nack(pf, vf, 6324 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6325 return; 6326 } 6327 6328 if (!vf->vf_flags & VF_FLAG_PROMISC_CAP) { 6329 i40e_send_vf_nack(pf, vf, 6330 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6331 return; 6332 } 6333 6334 info = msg; 6335 if (info->vsi_id != vf->vsi.vsi_num) { 6336 i40e_send_vf_nack(pf, vf, 6337 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6338 return; 6339 } 6340 6341 code = i40e_aq_set_vsi_unicast_promiscuous(&pf->hw, info->vsi_id, 6342 info->flags & I40E_FLAG_VF_UNICAST_PROMISC, NULL); 6343 if (code != I40E_SUCCESS) { 6344 i40e_send_vf_nack(pf, vf, 6345 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, code); 6346 return; 6347 } 6348 6349 code = i40e_aq_set_vsi_multicast_promiscuous(&pf->hw, info->vsi_id, 6350 info->flags & I40E_FLAG_VF_MULTICAST_PROMISC, NULL); 6351 if (code != I40E_SUCCESS) { 6352 i40e_send_vf_nack(pf, vf, 6353 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, code); 6354 return; 6355 } 6356 6357 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE); 6358} 6359 6360static void 6361ixl_vf_get_stats_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6362 uint16_t msg_size) 6363{ 6364 struct i40e_virtchnl_queue_select *queue; 6365 6366 if (msg_size != sizeof(*queue)) { 6367 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6368 I40E_ERR_PARAM); 6369 return; 6370 } 6371 6372 queue = msg; 6373 if (queue->vsi_id != vf->vsi.vsi_num) { 6374 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6375 I40E_ERR_PARAM); 6376 return; 6377 } 6378 6379 ixl_update_eth_stats(&vf->vsi); 6380 6381 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6382 I40E_SUCCESS, &vf->vsi.eth_stats, sizeof(vf->vsi.eth_stats)); 6383} 6384 6385static void 6386ixl_handle_vf_msg(struct ixl_pf *pf, struct i40e_arq_event_info *event) 6387{ 6388 struct ixl_vf *vf; 6389 void *msg; 6390 uint16_t vf_num, msg_size; 6391 uint32_t opcode; 6392 6393 vf_num = le16toh(event->desc.retval) - pf->hw.func_caps.vf_base_id; 6394 opcode = le32toh(event->desc.cookie_high); 6395 6396 if (vf_num >= pf->num_vfs) { 6397 device_printf(pf->dev, "Got msg from illegal VF: %d\n", vf_num); 6398 return; 6399 } 6400 6401 vf = &pf->vfs[vf_num]; 6402 msg = event->msg_buf; 6403 msg_size = event->msg_len; 6404 6405 I40E_VC_DEBUG(pf, ixl_vc_opcode_level(opcode), 6406 "Got msg %s(%d) from VF-%d of size %d\n", 6407 ixl_vc_opcode_str(opcode), opcode, vf_num, msg_size); 6408 6409 switch (opcode) { 6410 case I40E_VIRTCHNL_OP_VERSION: 6411 ixl_vf_version_msg(pf, vf, msg, msg_size); 6412 break; 6413 case I40E_VIRTCHNL_OP_RESET_VF: 6414 ixl_vf_reset_msg(pf, vf, msg, msg_size); 6415 break; 6416 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES: 6417 ixl_vf_get_resources_msg(pf, vf, msg, msg_size); 6418 break; 6419 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES: 6420 ixl_vf_config_vsi_msg(pf, vf, msg, msg_size); 6421 break; 6422 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP: 6423 ixl_vf_config_irq_msg(pf, vf, msg, msg_size); 6424 break; 6425 case I40E_VIRTCHNL_OP_ENABLE_QUEUES: 6426 ixl_vf_enable_queues_msg(pf, vf, msg, msg_size); 6427 break; 6428 case I40E_VIRTCHNL_OP_DISABLE_QUEUES: 6429 ixl_vf_disable_queues_msg(pf, vf, msg, msg_size); 6430 break; 6431 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS: 6432 ixl_vf_add_mac_msg(pf, vf, msg, msg_size); 6433 break; 6434 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS: 6435 ixl_vf_del_mac_msg(pf, vf, msg, msg_size); 6436 break; 6437 case I40E_VIRTCHNL_OP_ADD_VLAN: 6438 ixl_vf_add_vlan_msg(pf, vf, msg, msg_size); 6439 break; 6440 case I40E_VIRTCHNL_OP_DEL_VLAN: 6441 ixl_vf_del_vlan_msg(pf, vf, msg, msg_size); 6442 break; 6443 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: 6444 ixl_vf_config_promisc_msg(pf, vf, msg, msg_size); 6445 break; 6446 case I40E_VIRTCHNL_OP_GET_STATS: 6447 ixl_vf_get_stats_msg(pf, vf, msg, msg_size); 6448 break; 6449 6450 /* These two opcodes have been superseded by CONFIG_VSI_QUEUES. */ 6451 case I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE: 6452 case I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE: 6453 default: 6454 i40e_send_vf_nack(pf, vf, opcode, I40E_ERR_NOT_IMPLEMENTED); 6455 break; 6456 } 6457} 6458 6459/* Handle any VFs that have reset themselves via a Function Level Reset(FLR). */ 6460static void 6461ixl_handle_vflr(void *arg, int pending) 6462{ 6463 struct ixl_pf *pf; 6464 struct i40e_hw *hw; 6465 uint16_t global_vf_num; 6466 uint32_t vflrstat_index, vflrstat_mask, vflrstat, icr0; 6467 int i; 6468 6469 pf = arg; 6470 hw = &pf->hw; 6471 6472 IXL_PF_LOCK(pf); 6473 for (i = 0; i < pf->num_vfs; i++) { 6474 global_vf_num = hw->func_caps.vf_base_id + i; 6475 6476 vflrstat_index = IXL_GLGEN_VFLRSTAT_INDEX(global_vf_num); 6477 vflrstat_mask = IXL_GLGEN_VFLRSTAT_MASK(global_vf_num); 6478 vflrstat = rd32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index)); 6479 if (vflrstat & vflrstat_mask) { 6480 wr32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index), 6481 vflrstat_mask); 6482 6483 ixl_reinit_vf(pf, &pf->vfs[i]); 6484 } 6485 } 6486 6487 icr0 = rd32(hw, I40E_PFINT_ICR0_ENA); 6488 icr0 |= I40E_PFINT_ICR0_ENA_VFLR_MASK; 6489 wr32(hw, I40E_PFINT_ICR0_ENA, icr0); 6490 ixl_flush(hw); 6491 6492 IXL_PF_UNLOCK(pf); 6493} 6494 6495static int 6496ixl_adminq_err_to_errno(enum i40e_admin_queue_err err) 6497{ 6498 6499 switch (err) { 6500 case I40E_AQ_RC_EPERM: 6501 return (EPERM); 6502 case I40E_AQ_RC_ENOENT: 6503 return (ENOENT); 6504 case I40E_AQ_RC_ESRCH: 6505 return (ESRCH); 6506 case I40E_AQ_RC_EINTR: 6507 return (EINTR); 6508 case I40E_AQ_RC_EIO: 6509 return (EIO); 6510 case I40E_AQ_RC_ENXIO: 6511 return (ENXIO); 6512 case I40E_AQ_RC_E2BIG: 6513 return (E2BIG); 6514 case I40E_AQ_RC_EAGAIN: 6515 return (EAGAIN); 6516 case I40E_AQ_RC_ENOMEM: 6517 return (ENOMEM); 6518 case I40E_AQ_RC_EACCES: 6519 return (EACCES); 6520 case I40E_AQ_RC_EFAULT: 6521 return (EFAULT); 6522 case I40E_AQ_RC_EBUSY: 6523 return (EBUSY); 6524 case I40E_AQ_RC_EEXIST: 6525 return (EEXIST); 6526 case I40E_AQ_RC_EINVAL: 6527 return (EINVAL); 6528 case I40E_AQ_RC_ENOTTY: 6529 return (ENOTTY); 6530 case I40E_AQ_RC_ENOSPC: 6531 return (ENOSPC); 6532 case I40E_AQ_RC_ENOSYS: 6533 return (ENOSYS); 6534 case I40E_AQ_RC_ERANGE: 6535 return (ERANGE); 6536 case I40E_AQ_RC_EFLUSHED: 6537 return (EINVAL); /* No exact equivalent in errno.h */ 6538 case I40E_AQ_RC_BAD_ADDR: 6539 return (EFAULT); 6540 case I40E_AQ_RC_EMODE: 6541 return (EPERM); 6542 case I40E_AQ_RC_EFBIG: 6543 return (EFBIG); 6544 default: 6545 return (EINVAL); 6546 } 6547} 6548 6549static int 6550ixl_init_iov(device_t dev, uint16_t num_vfs, const nvlist_t *params) 6551{ 6552 struct ixl_pf *pf; 6553 struct i40e_hw *hw; 6554 struct ixl_vsi *pf_vsi; 6555 enum i40e_status_code ret; 6556 int i, error; 6557 6558 pf = device_get_softc(dev); 6559 hw = &pf->hw; 6560 pf_vsi = &pf->vsi; 6561 6562 IXL_PF_LOCK(pf); 6563 pf->vfs = malloc(sizeof(struct ixl_vf) * num_vfs, M_IXL, M_NOWAIT | 6564 M_ZERO); 6565 6566 if (pf->vfs == NULL) { 6567 error = ENOMEM; 6568 goto fail; 6569 } 6570 6571 for (i = 0; i < num_vfs; i++) 6572 sysctl_ctx_init(&pf->vfs[i].ctx); 6573 6574 ret = i40e_aq_add_veb(hw, pf_vsi->uplink_seid, pf_vsi->seid, 6575 1, FALSE, FALSE, &pf->veb_seid, NULL); 6576 if (ret != I40E_SUCCESS) { 6577 error = ixl_adminq_err_to_errno(hw->aq.asq_last_status); 6578 device_printf(dev, "add_veb failed; code=%d error=%d", ret, 6579 error); 6580 goto fail; 6581 } 6582 6583 ixl_configure_msix(pf); 6584 ixl_enable_adminq(hw); 6585 6586 pf->num_vfs = num_vfs; 6587 IXL_PF_UNLOCK(pf); 6588 return (0); 6589 6590fail: 6591 free(pf->vfs, M_IXL); 6592 pf->vfs = NULL; 6593 IXL_PF_UNLOCK(pf); 6594 return (error); 6595} 6596 6597static void 6598ixl_uninit_iov(device_t dev) 6599{ 6600 struct ixl_pf *pf; 6601 struct i40e_hw *hw; 6602 struct ixl_vsi *vsi; 6603 struct ifnet *ifp; 6604 struct ixl_vf *vfs; 6605 int i, num_vfs; 6606 6607 pf = device_get_softc(dev); 6608 hw = &pf->hw; 6609 vsi = &pf->vsi; 6610 ifp = vsi->ifp; 6611 6612 IXL_PF_LOCK(pf); 6613 for (i = 0; i < pf->num_vfs; i++) { 6614 if (pf->vfs[i].vsi.seid != 0) 6615 i40e_aq_delete_element(hw, pf->vfs[i].vsi.seid, NULL); 6616 } 6617 6618 if (pf->veb_seid != 0) { 6619 i40e_aq_delete_element(hw, pf->veb_seid, NULL); 6620 pf->veb_seid = 0; 6621 } 6622 6623 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 6624 ixl_disable_intr(vsi); 6625 6626 vfs = pf->vfs; 6627 num_vfs = pf->num_vfs; 6628 6629 pf->vfs = NULL; 6630 pf->num_vfs = 0; 6631 IXL_PF_UNLOCK(pf); 6632 6633 /* Do this after the unlock as sysctl_ctx_free might sleep. */ 6634 for (i = 0; i < num_vfs; i++) 6635 sysctl_ctx_free(&vfs[i].ctx); 6636 free(vfs, M_IXL); 6637} 6638 6639static int 6640ixl_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 6641{ 6642 char sysctl_name[QUEUE_NAME_LEN]; 6643 struct ixl_pf *pf; 6644 struct ixl_vf *vf; 6645 const void *mac; 6646 size_t size; 6647 int error; 6648 6649 pf = device_get_softc(dev); 6650 vf = &pf->vfs[vfnum]; 6651 6652 IXL_PF_LOCK(pf); 6653 vf->vf_num = vfnum; 6654 6655 vf->vsi.back = pf; 6656 vf->vf_flags = VF_FLAG_ENABLED; 6657 SLIST_INIT(&vf->vsi.ftl); 6658 6659 error = ixl_vf_setup_vsi(pf, vf); 6660 if (error != 0) 6661 goto out; 6662 6663 if (nvlist_exists_binary(params, "mac-addr")) { 6664 mac = nvlist_get_binary(params, "mac-addr", &size); 6665 bcopy(mac, vf->mac, ETHER_ADDR_LEN); 6666 6667 if (nvlist_get_bool(params, "allow-set-mac")) 6668 vf->vf_flags |= VF_FLAG_SET_MAC_CAP; 6669 } else 6670 /* 6671 * If the administrator has not specified a MAC address then 6672 * we must allow the VF to choose one. 6673 */ 6674 vf->vf_flags |= VF_FLAG_SET_MAC_CAP; 6675 6676 if (nvlist_get_bool(params, "mac-anti-spoof")) 6677 vf->vf_flags |= VF_FLAG_MAC_ANTI_SPOOF; 6678 6679 if (nvlist_get_bool(params, "allow-promisc")) 6680 vf->vf_flags |= VF_FLAG_PROMISC_CAP; 6681 6682 vf->vf_flags |= VF_FLAG_VLAN_CAP; 6683 6684 ixl_reset_vf(pf, vf); 6685out: 6686 IXL_PF_UNLOCK(pf); 6687 if (error == 0) { 6688 snprintf(sysctl_name, sizeof(sysctl_name), "vf%d", vfnum); 6689 ixl_add_vsi_sysctls(pf, &vf->vsi, &vf->ctx, sysctl_name); 6690 } 6691 6692 return (error); 6693} 6694#endif /* PCI_IOV */ 6695