1238438Sdteske/*- 2238438Sdteske * Copyright (c) 2004 Texas A&M University 3238438Sdteske * All rights reserved. 4252982Sdteske * 5238438Sdteske * Developer: Wm. Daryl Hawkins 6238438Sdteske * 7238438Sdteske * Redistribution and use in source and binary forms, with or without 8238438Sdteske * modification, are permitted provided that the following conditions 9238438Sdteske * are met: 10238438Sdteske * 1. Redistributions of source code must retain the above copyright 11238438Sdteske * notice, this list of conditions and the following disclaimer. 12238438Sdteske * 2. Redistributions in binary form must reproduce the above copyright 13238438Sdteske * notice, this list of conditions and the following disclaimer in the 14238438Sdteske * documentation and/or other materials provided with the distribution. 15238438Sdteske * 16252987Sdteske * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17238438Sdteske * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18238438Sdteske * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19238438Sdteske * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20240797Sdteske * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21238438Sdteske * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22238438Sdteske * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23238438Sdteske * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24238438Sdteske * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25238438Sdteske * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26238438Sdteske * SUCH DAMAGE. 27238438Sdteske * 28238438Sdteske * $FreeBSD$ 29238438Sdteske */ 30238438Sdteske 31240684Sdteske#ifndef _ICHWD_H_ 32241149Sdteske#define _ICHWD_H_ 33240684Sdteske 34238438Sdteskestruct ichwd_device { 35244675Sdteske uint16_t device; 36244675Sdteske char *desc; 37244675Sdteske unsigned int ich_version; 38244675Sdteske unsigned int tco_version; 39238438Sdteske}; 40238438Sdteske 41238438Sdteskestruct ichwd_softc { 42238438Sdteske device_t device; 43238438Sdteske device_t ich; 44238438Sdteske int ich_version; 45238438Sdteske int tco_version; 46238438Sdteske 47238438Sdteske int active; 48238438Sdteske unsigned int timeout; 49238438Sdteske 50238438Sdteske int smi_enabled; 51238438Sdteske int smi_rid; 52238438Sdteske struct resource *smi_res; 53238438Sdteske 54238438Sdteske int tco_rid; 55241019Sdteske struct resource *tco_res; 56241019Sdteske 57241019Sdteske int gcs_rid; 58241019Sdteske struct resource *gcs_res; 59241019Sdteske 60241019Sdteske eventhandler_tag ev_tag; 61241019Sdteske}; 62241019Sdteske 63241019Sdteske#define VENDORID_INTEL 0x8086 64241019Sdteske#define DEVICEID_BAYTRAIL 0x0f1c 65241019Sdteske#define DEVICEID_CPT0 0x1c40 66238438Sdteske#define DEVICEID_CPT1 0x1c41 67238438Sdteske#define DEVICEID_CPT2 0x1c42 68238438Sdteske#define DEVICEID_CPT3 0x1c43 69238438Sdteske#define DEVICEID_CPT4 0x1c44 70238438Sdteske#define DEVICEID_CPT5 0x1c45 71238438Sdteske#define DEVICEID_CPT6 0x1c46 72238438Sdteske#define DEVICEID_CPT7 0x1c47 73238438Sdteske#define DEVICEID_CPT8 0x1c48 74238438Sdteske#define DEVICEID_CPT9 0x1c49 75238438Sdteske#define DEVICEID_CPT10 0x1c4a 76238438Sdteske#define DEVICEID_CPT11 0x1c4b 77238438Sdteske#define DEVICEID_CPT12 0x1c4c 78238438Sdteske#define DEVICEID_CPT13 0x1c4d 79238438Sdteske#define DEVICEID_CPT14 0x1c4e 80238438Sdteske#define DEVICEID_CPT15 0x1c4f 81238438Sdteske#define DEVICEID_CPT16 0x1c50 82238438Sdteske#define DEVICEID_CPT17 0x1c51 83238438Sdteske#define DEVICEID_CPT18 0x1c52 84238438Sdteske#define DEVICEID_CPT19 0x1c53 85238438Sdteske#define DEVICEID_CPT20 0x1c54 86238438Sdteske#define DEVICEID_CPT21 0x1c55 87238438Sdteske#define DEVICEID_CPT22 0x1c56 88238438Sdteske#define DEVICEID_CPT23 0x1c57 89238438Sdteske#define DEVICEID_CPT24 0x1c58 90238438Sdteske#define DEVICEID_CPT25 0x1c59 91238438Sdteske#define DEVICEID_CPT26 0x1c5a 92238438Sdteske#define DEVICEID_CPT27 0x1c5b 93238438Sdteske#define DEVICEID_CPT28 0x1c5c 94238438Sdteske#define DEVICEID_CPT29 0x1c5d 95238438Sdteske#define DEVICEID_CPT30 0x1c5e 96238438Sdteske#define DEVICEID_CPT31 0x1c5f 97238438Sdteske#define DEVICEID_PATSBURG_LPC1 0x1d40 98238438Sdteske#define DEVICEID_PATSBURG_LPC2 0x1d41 99238438Sdteske#define DEVICEID_PPT0 0x1e40 100238438Sdteske#define DEVICEID_PPT1 0x1e41 101238438Sdteske#define DEVICEID_PPT2 0x1e42 102238438Sdteske#define DEVICEID_PPT3 0x1e43 103238438Sdteske#define DEVICEID_PPT4 0x1e44 104238438Sdteske#define DEVICEID_PPT5 0x1e45 105238438Sdteske#define DEVICEID_PPT6 0x1e46 106238438Sdteske#define DEVICEID_PPT7 0x1e47 107238438Sdteske#define DEVICEID_PPT8 0x1e48 108238438Sdteske#define DEVICEID_PPT9 0x1e49 109238438Sdteske#define DEVICEID_PPT10 0x1e4a 110238438Sdteske#define DEVICEID_PPT11 0x1e4b 111238438Sdteske#define DEVICEID_PPT12 0x1e4c 112238438Sdteske#define DEVICEID_PPT13 0x1e4d 113238438Sdteske#define DEVICEID_PPT14 0x1e4e 114238438Sdteske#define DEVICEID_PPT15 0x1e4f 115238438Sdteske#define DEVICEID_PPT16 0x1e50 116238438Sdteske#define DEVICEID_PPT17 0x1e51 117238438Sdteske#define DEVICEID_PPT18 0x1e52 118238438Sdteske#define DEVICEID_PPT19 0x1e53 119238438Sdteske#define DEVICEID_PPT20 0x1e54 120238438Sdteske#define DEVICEID_PPT21 0x1e55 121258420Sdteske#define DEVICEID_PPT22 0x1e56 122258420Sdteske#define DEVICEID_PPT23 0x1e57 123238438Sdteske#define DEVICEID_PPT24 0x1e58 124238438Sdteske#define DEVICEID_PPT25 0x1e59 125238438Sdteske#define DEVICEID_PPT26 0x1e5a 126238438Sdteske#define DEVICEID_PPT27 0x1e5b 127238438Sdteske#define DEVICEID_PPT28 0x1e5c 128238438Sdteske#define DEVICEID_PPT29 0x1e5d 129238438Sdteske#define DEVICEID_PPT30 0x1e5e 130238438Sdteske#define DEVICEID_PPT31 0x1e5f 131238438Sdteske#define DEVICEID_AVN0 0x1f38 132238438Sdteske#define DEVICEID_AVN1 0x1f39 133238438Sdteske#define DEVICEID_AVN2 0x1f3a 134238438Sdteske#define DEVICEID_AVN3 0x1f3b 135238438Sdteske#define DEVICEID_BRASWELL 0x229c 136238438Sdteske#define DEVICEID_DH89XXCC_LPC 0x2310 137238438Sdteske#define DEVICEID_COLETOCRK_LPC 0x2390 138252178Sdteske#define DEVICEID_82801AA 0x2410 139238438Sdteske#define DEVICEID_82801AB 0x2420 140238438Sdteske#define DEVICEID_82801BA 0x2440 141238438Sdteske#define DEVICEID_82801BAM 0x244c 142238438Sdteske#define DEVICEID_82801CA 0x2480 143238438Sdteske#define DEVICEID_82801CAM 0x248c 144238438Sdteske#define DEVICEID_82801DB 0x24c0 145238438Sdteske#define DEVICEID_82801DBM 0x24cc 146238438Sdteske#define DEVICEID_82801E 0x2450 147238438Sdteske#define DEVICEID_82801EB 0x24dc 148238438Sdteske#define DEVICEID_82801EBR 0x24d0 149241042Sdteske#define DEVICEID_6300ESB 0x25a1 150238438Sdteske#define DEVICEID_82801FBR 0x2640 151240783Sdteske#define DEVICEID_ICH6M 0x2641 152238438Sdteske#define DEVICEID_ICH6W 0x2642 153238438Sdteske#define DEVICEID_63XXESB 0x2670 154238438Sdteske#define DEVICEID_ICH7 0x27b8 155238438Sdteske#define DEVICEID_ICH7DH 0x27b0 156238438Sdteske#define DEVICEID_ICH7M 0x27b9 157238438Sdteske#define DEVICEID_NM10 0x27bc 158238438Sdteske#define DEVICEID_ICH7MDH 0x27bd 159238438Sdteske#define DEVICEID_ICH8 0x2810 160238438Sdteske#define DEVICEID_ICH8DH 0x2812 161238438Sdteske#define DEVICEID_ICH8DO 0x2814 162238438Sdteske#define DEVICEID_ICH8M 0x2815 163238438Sdteske#define DEVICEID_ICH8ME 0x2811 164238438Sdteske#define DEVICEID_ICH9 0x2918 165238438Sdteske#define DEVICEID_ICH9DH 0x2912 166238438Sdteske#define DEVICEID_ICH9DO 0x2914 167238438Sdteske#define DEVICEID_ICH9M 0x2919 168238438Sdteske#define DEVICEID_ICH9ME 0x2917 169238438Sdteske#define DEVICEID_ICH9R 0x2916 170240798Sdteske#define DEVICEID_ICH10 0x3a18 171238438Sdteske#define DEVICEID_ICH10D 0x3a1a 172238438Sdteske#define DEVICEID_ICH10DO 0x3a14 173238438Sdteske#define DEVICEID_ICH10R 0x3a16 174238438Sdteske#define DEVICEID_PCH 0x3b00 175240783Sdteske#define DEVICEID_PCHM 0x3b01 176238438Sdteske#define DEVICEID_P55 0x3b02 177238438Sdteske#define DEVICEID_PM55 0x3b03 178238438Sdteske#define DEVICEID_H55 0x3b06 179240797Sdteske#define DEVICEID_QM57 0x3b07 180238438Sdteske#define DEVICEID_H57 0x3b08 181238438Sdteske#define DEVICEID_HM55 0x3b09 182238438Sdteske#define DEVICEID_Q57 0x3b0a 183238438Sdteske#define DEVICEID_HM57 0x3b0b 184238438Sdteske#define DEVICEID_PCHMSFF 0x3b0d 185238438Sdteske#define DEVICEID_QS57 0x3b0f 186238438Sdteske#define DEVICEID_3400 0x3b12 187238438Sdteske#define DEVICEID_3420 0x3b14 188238438Sdteske#define DEVICEID_3450 0x3b16 189238438Sdteske#define DEVICEID_LPT0 0x8c40 190238438Sdteske#define DEVICEID_LPT1 0x8c41 191238438Sdteske#define DEVICEID_LPT2 0x8c42 192238438Sdteske#define DEVICEID_LPT3 0x8c43 193238438Sdteske#define DEVICEID_LPT4 0x8c44 194238438Sdteske#define DEVICEID_LPT5 0x8c45 195238438Sdteske#define DEVICEID_LPT6 0x8c46 196238438Sdteske#define DEVICEID_LPT7 0x8c47 197238438Sdteske#define DEVICEID_LPT8 0x8c48 198238438Sdteske#define DEVICEID_LPT9 0x8c49 199238438Sdteske#define DEVICEID_LPT10 0x8c4a 200238438Sdteske#define DEVICEID_LPT11 0x8c4b 201238438Sdteske#define DEVICEID_LPT12 0x8c4c 202238438Sdteske#define DEVICEID_LPT13 0x8c4d 203240783Sdteske#define DEVICEID_LPT14 0x8c4e 204238438Sdteske#define DEVICEID_LPT15 0x8c4f 205238438Sdteske#define DEVICEID_LPT16 0x8c50 206238438Sdteske#define DEVICEID_LPT17 0x8c51 207238438Sdteske#define DEVICEID_LPT18 0x8c52 208238438Sdteske#define DEVICEID_LPT19 0x8c53 209238438Sdteske#define DEVICEID_LPT20 0x8c54 210238438Sdteske#define DEVICEID_LPT21 0x8c55 211238438Sdteske#define DEVICEID_LPT22 0x8c56 212238438Sdteske#define DEVICEID_LPT23 0x8c57 213238438Sdteske#define DEVICEID_LPT24 0x8c58 214238438Sdteske#define DEVICEID_LPT25 0x8c59 215238438Sdteske#define DEVICEID_LPT26 0x8c5a 216238438Sdteske#define DEVICEID_LPT27 0x8c5b 217238438Sdteske#define DEVICEID_LPT28 0x8c5c 218238438Sdteske#define DEVICEID_LPT29 0x8c5d 219238438Sdteske#define DEVICEID_LPT30 0x8c5e 220238438Sdteske#define DEVICEID_LPT31 0x8c5f 221252178Sdteske#define DEVICEID_WCPT1 0x8cc1 222238438Sdteske#define DEVICEID_WCPT2 0x8cc2 223238438Sdteske#define DEVICEID_WCPT3 0x8cc3 224238438Sdteske#define DEVICEID_WCPT4 0x8cc4 225238438Sdteske#define DEVICEID_WCPT6 0x8cc6 226238438Sdteske#define DEVICEID_WBG0 0x8d40 227238438Sdteske#define DEVICEID_WBG1 0x8d41 228238438Sdteske#define DEVICEID_WBG2 0x8d42 229238438Sdteske#define DEVICEID_WBG3 0x8d43 230238438Sdteske#define DEVICEID_WBG4 0x8d44 231238438Sdteske#define DEVICEID_WBG5 0x8d45 232238438Sdteske#define DEVICEID_WBG6 0x8d46 233238438Sdteske#define DEVICEID_WBG7 0x8d47 234240783Sdteske#define DEVICEID_WBG8 0x8d48 235238438Sdteske#define DEVICEID_WBG9 0x8d49 236238438Sdteske#define DEVICEID_WBG10 0x8d4a 237238438Sdteske#define DEVICEID_WBG11 0x8d4b 238238438Sdteske#define DEVICEID_WBG12 0x8d4c 239238438Sdteske#define DEVICEID_WBG13 0x8d4d 240238438Sdteske#define DEVICEID_WBG14 0x8d4e 241238438Sdteske#define DEVICEID_WBG15 0x8d4f 242238438Sdteske#define DEVICEID_WBG16 0x8d50 243238438Sdteske#define DEVICEID_WBG17 0x8d51 244238438Sdteske#define DEVICEID_WBG18 0x8d52 245240783Sdteske#define DEVICEID_WBG19 0x8d53 246238438Sdteske#define DEVICEID_WBG20 0x8d54 247238438Sdteske#define DEVICEID_WBG21 0x8d55 248238438Sdteske#define DEVICEID_WBG22 0x8d56 249238438Sdteske#define DEVICEID_WBG23 0x8d57 250238438Sdteske#define DEVICEID_WBG24 0x8d58 251238438Sdteske#define DEVICEID_WBG25 0x8d59 252238438Sdteske#define DEVICEID_WBG26 0x8d5a 253238438Sdteske#define DEVICEID_WBG27 0x8d5b 254238438Sdteske#define DEVICEID_WBG28 0x8d5c 255238438Sdteske#define DEVICEID_WBG29 0x8d5d 256238438Sdteske#define DEVICEID_WBG30 0x8d5e 257238438Sdteske#define DEVICEID_WBG31 0x8d5f 258238438Sdteske#define DEVICEID_LPT_LP0 0x9c40 259238438Sdteske#define DEVICEID_LPT_LP1 0x9c41 260241019Sdteske#define DEVICEID_LPT_LP2 0x9c42 261238438Sdteske#define DEVICEID_LPT_LP3 0x9c43 262238438Sdteske#define DEVICEID_LPT_LP4 0x9c44 263238438Sdteske#define DEVICEID_LPT_LP5 0x9c45 264238438Sdteske#define DEVICEID_LPT_LP6 0x9c46 265238438Sdteske#define DEVICEID_LPT_LP7 0x9c47 266238438Sdteske#define DEVICEID_WCPT_LP1 0x9cc1 267241019Sdteske#define DEVICEID_WCPT_LP2 0x9cc2 268241019Sdteske#define DEVICEID_WCPT_LP3 0x9cc3 269241019Sdteske#define DEVICEID_WCPT_LP5 0x9cc5 270238438Sdteske#define DEVICEID_WCPT_LP6 0x9cc6 271238438Sdteske#define DEVICEID_WCPT_LP7 0x9cc7 272238438Sdteske#define DEVICEID_WCPT_LP9 0x9cc9 273238438Sdteske 274238438Sdteske/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 275240863Sdteske#define ICH_GEN_STA 0xd4 276238438Sdteske#define ICH_GEN_STA_NO_REBOOT 0x02 277238438Sdteske#define ICH_PMBASE 0x40 /* ACPI base address register */ 278238438Sdteske#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 279238438Sdteske 280238438Sdteske/* ICH Chipset Configuration Registers (ICH6 and newer) */ 281238438Sdteske#define ICH_RCBA 0xf0 282238438Sdteske#define ICH_GCS_OFFSET 0x3410 283238438Sdteske#define ICH_GCS_SIZE 0x4 284238438Sdteske#define ICH_GCS_NO_REBOOT 0x20 285238438Sdteske 286238438Sdteske/* SoC Power Management Configuration Registers */ 287238438Sdteske#define ICH_PBASE 0x44 288238438Sdteske#define ICH_PMC_OFFSET 0x08 289238438Sdteske#define ICH_PMC_SIZE 0x4 290238438Sdteske#define ICH_PMC_NO_REBOOT 0x10 291238438Sdteske 292238438Sdteske/* register names and locations (relative to PMBASE) */ 293238438Sdteske#define SMI_BASE 0x30 /* base address for SMI registers */ 294238438Sdteske#define SMI_LEN 0x08 295238438Sdteske#define SMI_EN 0x00 /* SMI Control and Enable Register */ 296238438Sdteske#define SMI_STS 0x04 /* SMI Status Register */ 297238438Sdteske#define TCO_BASE 0x60 /* base address for TCO registers */ 298238438Sdteske#define TCO_LEN 0x20 299238438Sdteske#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 300238438Sdteske#define TCO_TMR1 0x01 /* TCO Timer Initial Value 301238438Sdteske (ICH5 and older, 8 bits) */ 302238438Sdteske#define TCO_TMR2 0x12 /* TCO Timer Initial Value 303238438Sdteske (ICH6 and newer, 16 bits) */ 304238438Sdteske#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 305238438Sdteske#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 306238438Sdteske#define TCO1_STS 0x04 /* TCO Status 1 */ 307238438Sdteske#define TCO2_STS 0x06 /* TCO Status 2 */ 308238438Sdteske#define TCO1_CNT 0x08 /* TCO Control 1 */ 309238438Sdteske#define TCO2_CNT 0x08 /* TCO Control 2 */ 310238438Sdteske#define TCO_MESSAGE1 0x0c /* TCO Message 1 */ 311238438Sdteske#define TCO_MESSAGE2 0x0d /* TCO Message 2 */ 312238438Sdteske 313238438Sdteske/* bit definitions for SMI_EN and SMI_STS */ 314238438Sdteske#define SMI_TCO_EN 0x2000 315238438Sdteske#define SMI_TCO_STS 0x2000 316238438Sdteske#define SMI_GBL_EN 0x0001 317238438Sdteske 318238438Sdteske/* timer value mask for TCO_RLD and TCO_TMR */ 319238438Sdteske#define TCO_TIMER_MASK 0x1f 320238438Sdteske 321238438Sdteske/* status bits for TCO1_STS */ 322238438Sdteske#define TCO_NEWCENTURY 0x80 /* set for RTC year roll over (99 to 00) */ 323238438Sdteske#define TCO_TIMEOUT 0x08 /* timed out */ 324238438Sdteske#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 325238438Sdteske#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 326238438Sdteske 327238438Sdteske/* status bits for TCO2_STS */ 328238438Sdteske#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 329238438Sdteske#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 330238438Sdteske 331238438Sdteske/* control bits for TCO1_CNT */ 332238438Sdteske#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 333238438Sdteske#define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */ 334238438Sdteske#define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */ 335238438Sdteske#define TCO_NMI_NOW 0x0100 /* trigger an NMI */ 336238438Sdteske 337238438Sdteske/* 338238438Sdteske * Masks for the TCO timer value field in TCO_RLD. 339238438Sdteske * If the datasheets are to be believed, the minimum value actually varies 340238438Sdteske * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 341238438Sdteske * I suspect this is a bug in the ICH5 datasheet and that the minimum is 342238438Sdteske * uniformly 2, but I'd rather err on the side of caution. 343238438Sdteske */ 344238438Sdteske#define TCO_RLD_TMR_MIN 0x0004 345238438Sdteske#define TCO_RLD1_TMR_MAX 0x003f 346238438Sdteske#define TCO_RLD2_TMR_MAX 0x03ff 347238438Sdteske 348238438Sdteske/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 349238438Sdteske#define ICHWD_TICK 600000000 350238438Sdteske 351238438Sdteske#endif 352238438Sdteske