1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31#ifndef _ICHWD_H_ 32#define _ICHWD_H_ 33 34struct ichwd_device { 35 uint16_t device; 36 char *desc; 37 unsigned int ich_version; 38 unsigned int tco_version; 39}; 40 41struct ichwd_softc { 42 device_t device; 43 device_t ich; 44 int ich_version; 45 int tco_version; 46 47 int active; 48 unsigned int timeout; 49 50 int smi_enabled; 51 int smi_rid; 52 struct resource *smi_res; 53 54 int tco_rid; 55 struct resource *tco_res; 56 57 int gcs_rid; 58 struct resource *gcs_res; 59 60 eventhandler_tag ev_tag; 61}; 62 63#define VENDORID_INTEL 0x8086 64#define DEVICEID_BAYTRAIL 0x0f1c 65#define DEVICEID_CPT0 0x1c40 66#define DEVICEID_CPT1 0x1c41 67#define DEVICEID_CPT2 0x1c42 68#define DEVICEID_CPT3 0x1c43 69#define DEVICEID_CPT4 0x1c44 70#define DEVICEID_CPT5 0x1c45 71#define DEVICEID_CPT6 0x1c46 72#define DEVICEID_CPT7 0x1c47 73#define DEVICEID_CPT8 0x1c48 74#define DEVICEID_CPT9 0x1c49 75#define DEVICEID_CPT10 0x1c4a 76#define DEVICEID_CPT11 0x1c4b 77#define DEVICEID_CPT12 0x1c4c 78#define DEVICEID_CPT13 0x1c4d 79#define DEVICEID_CPT14 0x1c4e 80#define DEVICEID_CPT15 0x1c4f 81#define DEVICEID_CPT16 0x1c50 82#define DEVICEID_CPT17 0x1c51 83#define DEVICEID_CPT18 0x1c52 84#define DEVICEID_CPT19 0x1c53 85#define DEVICEID_CPT20 0x1c54 86#define DEVICEID_CPT21 0x1c55 87#define DEVICEID_CPT22 0x1c56 88#define DEVICEID_CPT23 0x1c57 89#define DEVICEID_CPT24 0x1c58 90#define DEVICEID_CPT25 0x1c59 91#define DEVICEID_CPT26 0x1c5a 92#define DEVICEID_CPT27 0x1c5b 93#define DEVICEID_CPT28 0x1c5c 94#define DEVICEID_CPT29 0x1c5d 95#define DEVICEID_CPT30 0x1c5e 96#define DEVICEID_CPT31 0x1c5f 97#define DEVICEID_PATSBURG_LPC1 0x1d40 98#define DEVICEID_PATSBURG_LPC2 0x1d41 99#define DEVICEID_PPT0 0x1e40 100#define DEVICEID_PPT1 0x1e41 101#define DEVICEID_PPT2 0x1e42 102#define DEVICEID_PPT3 0x1e43 103#define DEVICEID_PPT4 0x1e44 104#define DEVICEID_PPT5 0x1e45 105#define DEVICEID_PPT6 0x1e46 106#define DEVICEID_PPT7 0x1e47 107#define DEVICEID_PPT8 0x1e48 108#define DEVICEID_PPT9 0x1e49 109#define DEVICEID_PPT10 0x1e4a 110#define DEVICEID_PPT11 0x1e4b 111#define DEVICEID_PPT12 0x1e4c 112#define DEVICEID_PPT13 0x1e4d 113#define DEVICEID_PPT14 0x1e4e 114#define DEVICEID_PPT15 0x1e4f 115#define DEVICEID_PPT16 0x1e50 116#define DEVICEID_PPT17 0x1e51 117#define DEVICEID_PPT18 0x1e52 118#define DEVICEID_PPT19 0x1e53 119#define DEVICEID_PPT20 0x1e54 120#define DEVICEID_PPT21 0x1e55 121#define DEVICEID_PPT22 0x1e56 122#define DEVICEID_PPT23 0x1e57 123#define DEVICEID_PPT24 0x1e58 124#define DEVICEID_PPT25 0x1e59 125#define DEVICEID_PPT26 0x1e5a 126#define DEVICEID_PPT27 0x1e5b 127#define DEVICEID_PPT28 0x1e5c 128#define DEVICEID_PPT29 0x1e5d 129#define DEVICEID_PPT30 0x1e5e 130#define DEVICEID_PPT31 0x1e5f 131#define DEVICEID_AVN0 0x1f38 132#define DEVICEID_AVN1 0x1f39 133#define DEVICEID_AVN2 0x1f3a 134#define DEVICEID_AVN3 0x1f3b 135#define DEVICEID_BRASWELL 0x229c 136#define DEVICEID_DH89XXCC_LPC 0x2310 137#define DEVICEID_COLETOCRK_LPC 0x2390 138#define DEVICEID_82801AA 0x2410 139#define DEVICEID_82801AB 0x2420 140#define DEVICEID_82801BA 0x2440 141#define DEVICEID_82801BAM 0x244c 142#define DEVICEID_82801CA 0x2480 143#define DEVICEID_82801CAM 0x248c 144#define DEVICEID_82801DB 0x24c0 145#define DEVICEID_82801DBM 0x24cc 146#define DEVICEID_82801E 0x2450 147#define DEVICEID_82801EB 0x24dc 148#define DEVICEID_82801EBR 0x24d0 149#define DEVICEID_6300ESB 0x25a1 150#define DEVICEID_82801FBR 0x2640 151#define DEVICEID_ICH6M 0x2641 152#define DEVICEID_ICH6W 0x2642 153#define DEVICEID_63XXESB 0x2670 154#define DEVICEID_ICH7 0x27b8 155#define DEVICEID_ICH7DH 0x27b0 156#define DEVICEID_ICH7M 0x27b9 157#define DEVICEID_NM10 0x27bc 158#define DEVICEID_ICH7MDH 0x27bd 159#define DEVICEID_ICH8 0x2810 160#define DEVICEID_ICH8DH 0x2812 161#define DEVICEID_ICH8DO 0x2814 162#define DEVICEID_ICH8M 0x2815 163#define DEVICEID_ICH8ME 0x2811 164#define DEVICEID_ICH9 0x2918 165#define DEVICEID_ICH9DH 0x2912 166#define DEVICEID_ICH9DO 0x2914 167#define DEVICEID_ICH9M 0x2919 168#define DEVICEID_ICH9ME 0x2917 169#define DEVICEID_ICH9R 0x2916 170#define DEVICEID_ICH10 0x3a18 171#define DEVICEID_ICH10D 0x3a1a 172#define DEVICEID_ICH10DO 0x3a14 173#define DEVICEID_ICH10R 0x3a16 174#define DEVICEID_PCH 0x3b00 175#define DEVICEID_PCHM 0x3b01 176#define DEVICEID_P55 0x3b02 177#define DEVICEID_PM55 0x3b03 178#define DEVICEID_H55 0x3b06 179#define DEVICEID_QM57 0x3b07 180#define DEVICEID_H57 0x3b08 181#define DEVICEID_HM55 0x3b09 182#define DEVICEID_Q57 0x3b0a 183#define DEVICEID_HM57 0x3b0b 184#define DEVICEID_PCHMSFF 0x3b0d 185#define DEVICEID_QS57 0x3b0f 186#define DEVICEID_3400 0x3b12 187#define DEVICEID_3420 0x3b14 188#define DEVICEID_3450 0x3b16 189#define DEVICEID_LPT0 0x8c40 190#define DEVICEID_LPT1 0x8c41 191#define DEVICEID_LPT2 0x8c42 192#define DEVICEID_LPT3 0x8c43 193#define DEVICEID_LPT4 0x8c44 194#define DEVICEID_LPT5 0x8c45 195#define DEVICEID_LPT6 0x8c46 196#define DEVICEID_LPT7 0x8c47 197#define DEVICEID_LPT8 0x8c48 198#define DEVICEID_LPT9 0x8c49 199#define DEVICEID_LPT10 0x8c4a 200#define DEVICEID_LPT11 0x8c4b 201#define DEVICEID_LPT12 0x8c4c 202#define DEVICEID_LPT13 0x8c4d 203#define DEVICEID_LPT14 0x8c4e 204#define DEVICEID_LPT15 0x8c4f 205#define DEVICEID_LPT16 0x8c50 206#define DEVICEID_LPT17 0x8c51 207#define DEVICEID_LPT18 0x8c52 208#define DEVICEID_LPT19 0x8c53 209#define DEVICEID_LPT20 0x8c54 210#define DEVICEID_LPT21 0x8c55 211#define DEVICEID_LPT22 0x8c56 212#define DEVICEID_LPT23 0x8c57 213#define DEVICEID_LPT24 0x8c58 214#define DEVICEID_LPT25 0x8c59 215#define DEVICEID_LPT26 0x8c5a 216#define DEVICEID_LPT27 0x8c5b 217#define DEVICEID_LPT28 0x8c5c 218#define DEVICEID_LPT29 0x8c5d 219#define DEVICEID_LPT30 0x8c5e 220#define DEVICEID_LPT31 0x8c5f 221#define DEVICEID_WCPT1 0x8cc1 222#define DEVICEID_WCPT2 0x8cc2 223#define DEVICEID_WCPT3 0x8cc3 224#define DEVICEID_WCPT4 0x8cc4 225#define DEVICEID_WCPT6 0x8cc6 226#define DEVICEID_WBG0 0x8d40 227#define DEVICEID_WBG1 0x8d41 228#define DEVICEID_WBG2 0x8d42 229#define DEVICEID_WBG3 0x8d43 230#define DEVICEID_WBG4 0x8d44 231#define DEVICEID_WBG5 0x8d45 232#define DEVICEID_WBG6 0x8d46 233#define DEVICEID_WBG7 0x8d47 234#define DEVICEID_WBG8 0x8d48 235#define DEVICEID_WBG9 0x8d49 236#define DEVICEID_WBG10 0x8d4a 237#define DEVICEID_WBG11 0x8d4b 238#define DEVICEID_WBG12 0x8d4c 239#define DEVICEID_WBG13 0x8d4d 240#define DEVICEID_WBG14 0x8d4e 241#define DEVICEID_WBG15 0x8d4f 242#define DEVICEID_WBG16 0x8d50 243#define DEVICEID_WBG17 0x8d51 244#define DEVICEID_WBG18 0x8d52 245#define DEVICEID_WBG19 0x8d53 246#define DEVICEID_WBG20 0x8d54 247#define DEVICEID_WBG21 0x8d55 248#define DEVICEID_WBG22 0x8d56 249#define DEVICEID_WBG23 0x8d57 250#define DEVICEID_WBG24 0x8d58 251#define DEVICEID_WBG25 0x8d59 252#define DEVICEID_WBG26 0x8d5a 253#define DEVICEID_WBG27 0x8d5b 254#define DEVICEID_WBG28 0x8d5c 255#define DEVICEID_WBG29 0x8d5d 256#define DEVICEID_WBG30 0x8d5e 257#define DEVICEID_WBG31 0x8d5f 258#define DEVICEID_LPT_LP0 0x9c40 259#define DEVICEID_LPT_LP1 0x9c41 260#define DEVICEID_LPT_LP2 0x9c42 261#define DEVICEID_LPT_LP3 0x9c43 262#define DEVICEID_LPT_LP4 0x9c44 263#define DEVICEID_LPT_LP5 0x9c45 264#define DEVICEID_LPT_LP6 0x9c46 265#define DEVICEID_LPT_LP7 0x9c47 266#define DEVICEID_WCPT_LP1 0x9cc1 267#define DEVICEID_WCPT_LP2 0x9cc2 268#define DEVICEID_WCPT_LP3 0x9cc3 269#define DEVICEID_WCPT_LP5 0x9cc5 270#define DEVICEID_WCPT_LP6 0x9cc6 271#define DEVICEID_WCPT_LP7 0x9cc7 272#define DEVICEID_WCPT_LP9 0x9cc9 273 274/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 275#define ICH_GEN_STA 0xd4 276#define ICH_GEN_STA_NO_REBOOT 0x02 277#define ICH_PMBASE 0x40 /* ACPI base address register */ 278#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 279 280/* ICH Chipset Configuration Registers (ICH6 and newer) */ 281#define ICH_RCBA 0xf0 282#define ICH_GCS_OFFSET 0x3410 283#define ICH_GCS_SIZE 0x4 284#define ICH_GCS_NO_REBOOT 0x20 285 286/* SoC Power Management Configuration Registers */ 287#define ICH_PBASE 0x44 288#define ICH_PMC_OFFSET 0x08 289#define ICH_PMC_SIZE 0x4 290#define ICH_PMC_NO_REBOOT 0x10 291 292/* register names and locations (relative to PMBASE) */ 293#define SMI_BASE 0x30 /* base address for SMI registers */ 294#define SMI_LEN 0x08 295#define SMI_EN 0x00 /* SMI Control and Enable Register */ 296#define SMI_STS 0x04 /* SMI Status Register */ 297#define TCO_BASE 0x60 /* base address for TCO registers */ 298#define TCO_LEN 0x20 299#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 300#define TCO_TMR1 0x01 /* TCO Timer Initial Value 301 (ICH5 and older, 8 bits) */ 302#define TCO_TMR2 0x12 /* TCO Timer Initial Value 303 (ICH6 and newer, 16 bits) */ 304#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 305#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 306#define TCO1_STS 0x04 /* TCO Status 1 */ 307#define TCO2_STS 0x06 /* TCO Status 2 */ 308#define TCO1_CNT 0x08 /* TCO Control 1 */ 309#define TCO2_CNT 0x08 /* TCO Control 2 */ 310#define TCO_MESSAGE1 0x0c /* TCO Message 1 */ 311#define TCO_MESSAGE2 0x0d /* TCO Message 2 */ 312 313/* bit definitions for SMI_EN and SMI_STS */ 314#define SMI_TCO_EN 0x2000 315#define SMI_TCO_STS 0x2000 316#define SMI_GBL_EN 0x0001 317 318/* timer value mask for TCO_RLD and TCO_TMR */ 319#define TCO_TIMER_MASK 0x1f 320 321/* status bits for TCO1_STS */ 322#define TCO_NEWCENTURY 0x80 /* set for RTC year roll over (99 to 00) */ 323#define TCO_TIMEOUT 0x08 /* timed out */ 324#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 325#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 326 327/* status bits for TCO2_STS */ 328#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 329#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 330 331/* control bits for TCO1_CNT */ 332#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 333#define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */ 334#define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */ 335#define TCO_NMI_NOW 0x0100 /* trigger an NMI */ 336 337/* 338 * Masks for the TCO timer value field in TCO_RLD. 339 * If the datasheets are to be believed, the minimum value actually varies 340 * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 341 * I suspect this is a bug in the ICH5 datasheet and that the minimum is 342 * uniformly 2, but I'd rather err on the side of caution. 343 */ 344#define TCO_RLD_TMR_MIN 0x0004 345#define TCO_RLD1_TMR_MAX 0x003f 346#define TCO_RLD2_TMR_MAX 0x03ff 347 348/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 349#define ICHWD_TICK 600000000 350 351#endif 352