1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD$"); 33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37#include "radeon_family.h" 38 39/* General customization: 40 */ 41 42#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 43 44#define DRIVER_NAME "radeon" 45#define DRIVER_DESC "ATI Radeon" 46#define DRIVER_DATE "20080528" 47 48/* Interface history: 49 * 50 * 1.1 - ?? 51 * 1.2 - Add vertex2 ioctl (keith) 52 * - Add stencil capability to clear ioctl (gareth, keith) 53 * - Increase MAX_TEXTURE_LEVELS (brian) 54 * 1.3 - Add cmdbuf ioctl (keith) 55 * - Add support for new radeon packets (keith) 56 * - Add getparam ioctl (keith) 57 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 58 * 1.4 - Add scratch registers to get_param ioctl. 59 * 1.5 - Add r200 packets to cmdbuf ioctl 60 * - Add r200 function to init ioctl 61 * - Add 'scalar2' instruction to cmdbuf 62 * 1.6 - Add static GART memory manager 63 * Add irq handler (won't be turned on unless X server knows to) 64 * Add irq ioctls and irq_active getparam. 65 * Add wait command for cmdbuf ioctl 66 * Add GART offset query for getparam 67 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 68 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 69 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 70 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 71 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 72 * Add 'GET' queries for starting additional clients on different VT's. 73 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 74 * Add texture rectangle support for r100. 75 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 76 * clients use to tell the DRM where they think the framebuffer is 77 * located in the card's address space 78 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 79 * and GL_EXT_blend_[func|equation]_separate on r200 80 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 81 * (No 3D support yet - just microcode loading). 82 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 83 * - Add hyperz support, add hyperz flags to clear ioctl. 84 * 1.14- Add support for color tiling 85 * - Add R100/R200 surface allocation/free support 86 * 1.15- Add support for texture micro tiling 87 * - Add support for r100 cube maps 88 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 89 * texture filtering on r200 90 * 1.17- Add initial support for R300 (3D). 91 * 1.18- Add support for GL_ATI_fragment_shader, new packets 92 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 93 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 94 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 95 * 1.19- Add support for gart table in FB memory and PCIE r300 96 * 1.20- Add support for r300 texrect 97 * 1.21- Add support for card type getparam 98 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 99 * 1.23- Add new radeon memory map work from benh 100 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 101 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 102 * new packet type) 103 * 1.26- Add support for variable size PCI(E) gart aperture 104 * 1.27- Add support for IGP GART 105 * 1.28- Add support for VBL on CRTC2 106 * 1.29- R500 3D cmd buffer support 107 * 1.30- Add support for occlusion queries 108 * 1.31- Add support for num Z pipes from GET_PARAM 109 * 1.32- fixes for rv740 setup 110 * 1.33- Add r6xx/r7xx const buffer support 111 */ 112#define DRIVER_MAJOR 1 113#define DRIVER_MINOR 33 114#define DRIVER_PATCHLEVEL 0 115 116enum radeon_cp_microcode_version { 117 UCODE_R100, 118 UCODE_R200, 119 UCODE_R300, 120}; 121 122typedef struct drm_radeon_freelist { 123 unsigned int age; 124 struct drm_buf *buf; 125 struct drm_radeon_freelist *next; 126 struct drm_radeon_freelist *prev; 127} drm_radeon_freelist_t; 128 129typedef struct drm_radeon_ring_buffer { 130 u32 *start; 131 u32 *end; 132 int size; 133 int size_l2qw; 134 135 int rptr_update; /* Double Words */ 136 int rptr_update_l2qw; /* log2 Quad Words */ 137 138 int fetch_size; /* Double Words */ 139 int fetch_size_l2ow; /* log2 Oct Words */ 140 141 u32 tail; 142 u32 tail_mask; 143 int space; 144 145 int high_mark; 146} drm_radeon_ring_buffer_t; 147 148typedef struct drm_radeon_depth_clear_t { 149 u32 rb3d_cntl; 150 u32 rb3d_zstencilcntl; 151 u32 se_cntl; 152} drm_radeon_depth_clear_t; 153 154struct drm_radeon_driver_file_fields { 155 int64_t radeon_fb_delta; 156}; 157 158struct mem_block { 159 struct mem_block *next; 160 struct mem_block *prev; 161 int start; 162 int size; 163 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 164}; 165 166struct radeon_surface { 167 int refcount; 168 u32 lower; 169 u32 upper; 170 u32 flags; 171}; 172 173struct radeon_virt_surface { 174 int surface_index; 175 u32 lower; 176 u32 upper; 177 u32 flags; 178 struct drm_file *file_priv; 179#define PCIGART_FILE_PRIV ((void *) -1L) 180}; 181 182#define RADEON_FLUSH_EMITED (1 << 0) 183#define RADEON_PURGE_EMITED (1 << 1) 184 185struct drm_radeon_master_private { 186 drm_local_map_t *sarea; 187 drm_radeon_sarea_t *sarea_priv; 188}; 189 190typedef struct drm_radeon_private { 191 drm_radeon_ring_buffer_t ring; 192 193 u32 fb_location; 194 u32 fb_size; 195 int new_memmap; 196 197 int gart_size; 198 u32 gart_vm_start; 199 unsigned long gart_buffers_offset; 200 201 int cp_mode; 202 int cp_running; 203 204 drm_radeon_freelist_t *head; 205 drm_radeon_freelist_t *tail; 206 int last_buf; 207 int writeback_works; 208 209 int usec_timeout; 210 211 int microcode_version; 212 213 struct { 214 u32 boxes; 215 int freelist_timeouts; 216 int freelist_loops; 217 int requested_bufs; 218 int last_frame_reads; 219 int last_clear_reads; 220 int clears; 221 int texture_uploads; 222 } stats; 223 224 int do_boxes; 225 int page_flipping; 226 227 u32 color_fmt; 228 unsigned int front_offset; 229 unsigned int front_pitch; 230 unsigned int back_offset; 231 unsigned int back_pitch; 232 233 u32 depth_fmt; 234 unsigned int depth_offset; 235 unsigned int depth_pitch; 236 237 u32 front_pitch_offset; 238 u32 back_pitch_offset; 239 u32 depth_pitch_offset; 240 241 drm_radeon_depth_clear_t depth_clear; 242 243 unsigned long ring_offset; 244 unsigned long ring_rptr_offset; 245 unsigned long buffers_offset; 246 unsigned long gart_textures_offset; 247 248 drm_local_map_t *sarea; 249 drm_local_map_t *cp_ring; 250 drm_local_map_t *ring_rptr; 251 drm_local_map_t *gart_textures; 252 253 struct mem_block *gart_heap; 254 struct mem_block *fb_heap; 255 256 /* SW interrupt */ 257 wait_queue_head_t swi_queue; 258 atomic_t swi_emitted; 259 int vblank_crtc; 260 uint32_t irq_enable_reg; 261 uint32_t r500_disp_irq_reg; 262 263 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 264 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 265 266 unsigned long pcigart_offset; 267 unsigned int pcigart_offset_set; 268 struct drm_ati_pcigart_info gart_info; 269 270 u32 scratch_ages[5]; 271 272 int have_z_offset; 273 274 /* starting from here on, data is preserved across an open */ 275 uint32_t flags; /* see radeon_chip_flags */ 276 resource_size_t fb_aper_offset; 277 278 int num_gb_pipes; 279 int num_z_pipes; 280 int track_flush; 281 drm_local_map_t *mmio; 282 283 /* r6xx/r7xx pipe/shader config */ 284 int r600_max_pipes; 285 int r600_max_tile_pipes; 286 int r600_max_simds; 287 int r600_max_backends; 288 int r600_max_gprs; 289 int r600_max_threads; 290 int r600_max_stack_entries; 291 int r600_max_hw_contexts; 292 int r600_max_gs_threads; 293 int r600_sx_max_export_size; 294 int r600_sx_max_export_pos_size; 295 int r600_sx_max_export_smx_size; 296 int r600_sq_num_cf_insts; 297 int r700_sx_num_of_sets; 298 int r700_sc_prim_fifo_size; 299 int r700_sc_hiz_tile_fifo_size; 300 int r700_sc_earlyz_tile_fifo_fize; 301 int r600_group_size; 302 int r600_npipes; 303 int r600_nbanks; 304 305 struct sx cs_mutex; 306 u32 cs_id_scnt; 307 u32 cs_id_wcnt; 308 /* r6xx/r7xx drm blit vertex buffer */ 309 struct drm_buf *blit_vb; 310 311 /* firmware */ 312 const struct firmware *me_fw, *pfp_fw; 313} drm_radeon_private_t; 314 315typedef struct drm_radeon_buf_priv { 316 u32 age; 317} drm_radeon_buf_priv_t; 318 319struct drm_buffer; 320 321typedef struct drm_radeon_kcmd_buffer { 322 int bufsz; 323 struct drm_buffer *buffer; 324 int nbox; 325 struct drm_clip_rect __user *boxes; 326} drm_radeon_kcmd_buffer_t; 327 328extern int radeon_no_wb; 329extern struct drm_ioctl_desc radeon_ioctls[]; 330extern int radeon_max_ioctl; 331#ifdef COMPAT_FREEBSD32 332extern struct drm_ioctl_desc radeon_compat_ioctls[]; 333extern int radeon_num_compat_ioctls; 334#endif 335 336extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); 337extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); 338 339#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) 340#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 341 342/* Check whether the given hardware address is inside the framebuffer or the 343 * GART area. 344 */ 345static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 346 u64 off) 347{ 348 u32 fb_start = dev_priv->fb_location; 349 u32 fb_end = fb_start + dev_priv->fb_size - 1; 350 u32 gart_start = dev_priv->gart_vm_start; 351 u32 gart_end = gart_start + dev_priv->gart_size - 1; 352 353 return ((off >= fb_start && off <= fb_end) || 354 (off >= gart_start && off <= gart_end)); 355} 356 357/* radeon_state.c */ 358extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf); 359 360 /* radeon_cp.c */ 361extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 362extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 363extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 364extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 365extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 366extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 367extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 368extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 369extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 370extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 371extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 372extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 373 374extern void radeon_freelist_reset(struct drm_device * dev); 375extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 376 377extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 378 379extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 380 381extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 382extern int radeon_presetup(struct drm_device *dev); 383extern int radeon_driver_postcleanup(struct drm_device *dev); 384 385extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 386extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 387extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 388extern void radeon_mem_takedown(struct mem_block **heap); 389extern void radeon_mem_release(struct drm_file *file_priv, 390 struct mem_block *heap); 391 392extern void radeon_enable_bm(struct drm_radeon_private *dev_priv); 393extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); 394extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); 395 396 /* radeon_irq.c */ 397extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 398extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 399extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 400 401extern void radeon_do_release(struct drm_device * dev); 402extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 403extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 404extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 405extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 406extern void radeon_driver_irq_preinstall(struct drm_device * dev); 407extern int radeon_driver_irq_postinstall(struct drm_device *dev); 408extern void radeon_driver_irq_uninstall(struct drm_device * dev); 409extern void radeon_enable_interrupt(struct drm_device *dev); 410extern int radeon_vblank_crtc_get(struct drm_device *dev); 411extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 412 413extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 414extern int radeon_driver_unload(struct drm_device *dev); 415extern int radeon_driver_firstopen(struct drm_device *dev); 416extern void radeon_driver_preclose(struct drm_device *dev, 417 struct drm_file *file_priv); 418extern void radeon_driver_postclose(struct drm_device *dev, 419 struct drm_file *file_priv); 420extern void radeon_driver_lastclose(struct drm_device * dev); 421extern int radeon_driver_open(struct drm_device *dev, 422 struct drm_file *file_priv); 423extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 424 unsigned long arg); 425extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 426 unsigned long arg); 427 428extern int radeon_master_create(struct drm_device *dev, struct drm_master *master); 429extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); 430extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master); 431/* r300_cmdbuf.c */ 432extern void r300_init_reg_flags(struct drm_device *dev); 433 434extern int r300_do_cp_cmdbuf(struct drm_device *dev, 435 struct drm_file *file_priv, 436 drm_radeon_kcmd_buffer_t *cmdbuf); 437 438/* r600_cp.c */ 439extern int r600_do_engine_reset(struct drm_device *dev); 440extern int r600_do_cleanup_cp(struct drm_device *dev); 441extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 442 struct drm_file *file_priv); 443extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); 444extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 445extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 446extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 447extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 448extern int r600_cp_dispatch_indirect(struct drm_device *dev, 449 struct drm_buf *buf, int start, int end); 450extern int r600_page_table_init(struct drm_device *dev); 451extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 452extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 453extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv); 454extern int r600_cp_dispatch_texture(struct drm_device *dev, 455 struct drm_file *file_priv, 456 drm_radeon_texture_t *tex, 457 drm_radeon_tex_image_t *image); 458/* r600_blit.c */ 459extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv); 460extern void r600_done_blit_copy(struct drm_device *dev); 461extern void r600_blit_copy(struct drm_device *dev, 462 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 463 int size_bytes); 464extern void r600_blit_swap(struct drm_device *dev, 465 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 466 int sx, int sy, int dx, int dy, 467 int w, int h, int src_pitch, int dst_pitch, int cpp); 468 469/* atpx handler */ 470#if defined(CONFIG_VGA_SWITCHEROO) 471void radeon_register_atpx_handler(void); 472void radeon_unregister_atpx_handler(void); 473#else 474static inline void radeon_register_atpx_handler(void) {} 475static inline void radeon_unregister_atpx_handler(void) {} 476#endif 477 478/* Flags for stats.boxes 479 */ 480#define RADEON_BOX_DMA_IDLE 0x1 481#define RADEON_BOX_RING_FULL 0x2 482#define RADEON_BOX_FLIP 0x4 483#define RADEON_BOX_WAIT_IDLE 0x8 484#define RADEON_BOX_TEXTURE_LOAD 0x10 485 486/* Register definitions, register access macros and drmAddMap constants 487 * for Radeon kernel driver. 488 */ 489#define RADEON_MM_INDEX 0x0000 490#define RADEON_MM_DATA 0x0004 491 492#define RADEON_AGP_COMMAND 0x0f60 493#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 494# define RADEON_AGP_ENABLE (1<<8) 495#define RADEON_AUX_SCISSOR_CNTL 0x26f0 496# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 497# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 498# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 499# define RADEON_SCISSOR_0_ENABLE (1 << 28) 500# define RADEON_SCISSOR_1_ENABLE (1 << 29) 501# define RADEON_SCISSOR_2_ENABLE (1 << 30) 502 503/* 504 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 505 * don't have an explicit bus mastering disable bit. It's handled 506 * by the PCI D-states. PMI_BM_DIS disables D-state bus master 507 * handling, not bus mastering itself. 508 */ 509#define RADEON_BUS_CNTL 0x0030 510/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 511# define RADEON_BUS_MASTER_DIS (1 << 6) 512/* rs600/rs690/rs740 */ 513# define RS600_BUS_MASTER_DIS (1 << 14) 514# define RS600_MSI_REARM (1 << 20) 515/* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 516 517#define RADEON_BUS_CNTL1 0x0034 518# define RADEON_PMI_BM_DIS (1 << 2) 519# define RADEON_PMI_INT_DIS (1 << 3) 520 521#define RV370_BUS_CNTL 0x004c 522# define RV370_PMI_BM_DIS (1 << 5) 523# define RV370_PMI_INT_DIS (1 << 6) 524 525#define RADEON_MSI_REARM_EN 0x0160 526/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 527# define RV370_MSI_REARM_EN (1 << 0) 528 529#define RADEON_CLOCK_CNTL_DATA 0x000c 530# define RADEON_PLL_WR_EN (1 << 7) 531#define RADEON_CLOCK_CNTL_INDEX 0x0008 532#define RADEON_CONFIG_APER_SIZE 0x0108 533#define RADEON_CONFIG_MEMSIZE 0x00f8 534#define RADEON_CRTC_OFFSET 0x0224 535#define RADEON_CRTC_OFFSET_CNTL 0x0228 536# define RADEON_CRTC_TILE_EN (1 << 15) 537# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 538#define RADEON_CRTC2_OFFSET 0x0324 539#define RADEON_CRTC2_OFFSET_CNTL 0x0328 540 541#define RADEON_PCIE_INDEX 0x0030 542#define RADEON_PCIE_DATA 0x0034 543#define RADEON_PCIE_TX_GART_CNTL 0x10 544# define RADEON_PCIE_TX_GART_EN (1 << 0) 545# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 546# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 547# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 548# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 549# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 550# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 551# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 552#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 553#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 554#define RADEON_PCIE_TX_GART_BASE 0x13 555#define RADEON_PCIE_TX_GART_START_LO 0x14 556#define RADEON_PCIE_TX_GART_START_HI 0x15 557#define RADEON_PCIE_TX_GART_END_LO 0x16 558#define RADEON_PCIE_TX_GART_END_HI 0x17 559 560#define RS480_NB_MC_INDEX 0x168 561# define RS480_NB_MC_IND_WR_EN (1 << 8) 562#define RS480_NB_MC_DATA 0x16c 563 564#define RS690_MC_INDEX 0x78 565# define RS690_MC_INDEX_MASK 0x1ff 566# define RS690_MC_INDEX_WR_EN (1 << 9) 567# define RS690_MC_INDEX_WR_ACK 0x7f 568#define RS690_MC_DATA 0x7c 569 570/* MC indirect registers */ 571#define RS480_MC_MISC_CNTL 0x18 572# define RS480_DISABLE_GTW (1 << 1) 573/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 574# define RS480_GART_INDEX_REG_EN (1 << 12) 575# define RS690_BLOCK_GFX_D3_EN (1 << 14) 576#define RS480_K8_FB_LOCATION 0x1e 577#define RS480_GART_FEATURE_ID 0x2b 578# define RS480_HANG_EN (1 << 11) 579# define RS480_TLB_ENABLE (1 << 18) 580# define RS480_P2P_ENABLE (1 << 19) 581# define RS480_GTW_LAC_EN (1 << 25) 582# define RS480_2LEVEL_GART (0 << 30) 583# define RS480_1LEVEL_GART (1 << 30) 584# define RS480_PDC_EN (1U << 31) 585#define RS480_GART_BASE 0x2c 586#define RS480_GART_CACHE_CNTRL 0x2e 587# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 588#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 589# define RS480_GART_EN (1 << 0) 590# define RS480_VA_SIZE_32MB (0 << 1) 591# define RS480_VA_SIZE_64MB (1 << 1) 592# define RS480_VA_SIZE_128MB (2 << 1) 593# define RS480_VA_SIZE_256MB (3 << 1) 594# define RS480_VA_SIZE_512MB (4 << 1) 595# define RS480_VA_SIZE_1GB (5 << 1) 596# define RS480_VA_SIZE_2GB (6 << 1) 597#define RS480_AGP_MODE_CNTL 0x39 598# define RS480_POST_GART_Q_SIZE (1 << 18) 599# define RS480_NONGART_SNOOP (1 << 19) 600# define RS480_AGP_RD_BUF_SIZE (1 << 20) 601# define RS480_REQ_TYPE_SNOOP_SHIFT 22 602# define RS480_REQ_TYPE_SNOOP_MASK 0x3 603# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 604#define RS480_MC_MISC_UMA_CNTL 0x5f 605#define RS480_MC_MCLK_CNTL 0x7a 606#define RS480_MC_UMA_DUALCH_CNTL 0x86 607 608#define RS690_MC_FB_LOCATION 0x100 609#define RS690_MC_AGP_LOCATION 0x101 610#define RS690_MC_AGP_BASE 0x102 611#define RS690_MC_AGP_BASE_2 0x103 612 613#define RS600_MC_INDEX 0x70 614# define RS600_MC_ADDR_MASK 0xffff 615# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 616# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 617# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 618# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 619# define RS600_MC_IND_AIC_RBS (1 << 20) 620# define RS600_MC_IND_CITF_ARB0 (1 << 21) 621# define RS600_MC_IND_CITF_ARB1 (1 << 22) 622# define RS600_MC_IND_WR_EN (1 << 23) 623#define RS600_MC_DATA 0x74 624 625#define RS600_MC_STATUS 0x0 626# define RS600_MC_IDLE (1 << 1) 627#define RS600_MC_FB_LOCATION 0x4 628#define RS600_MC_AGP_LOCATION 0x5 629#define RS600_AGP_BASE 0x6 630#define RS600_AGP_BASE_2 0x7 631#define RS600_MC_CNTL1 0x9 632# define RS600_ENABLE_PAGE_TABLES (1 << 26) 633#define RS600_MC_PT0_CNTL 0x100 634# define RS600_ENABLE_PT (1 << 0) 635# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 636# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 637# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 638# define RS600_INVALIDATE_L2_CACHE (1 << 29) 639#define RS600_MC_PT0_CONTEXT0_CNTL 0x102 640# define RS600_ENABLE_PAGE_TABLE (1 << 0) 641# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 642#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 643#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 644#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 645#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 646#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 647#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 648#define RS600_MC_PT0_CLIENT0_CNTL 0x16c 649# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 650# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 651# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 652# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 653# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 654# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 655# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 656# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 657# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 658# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 659# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 660# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 661# define RS600_INVALIDATE_L1_TLB (1 << 20) 662 663#define R520_MC_IND_INDEX 0x70 664#define R520_MC_IND_WR_EN (1 << 24) 665#define R520_MC_IND_DATA 0x74 666 667#define RV515_MC_FB_LOCATION 0x01 668#define RV515_MC_AGP_LOCATION 0x02 669#define RV515_MC_AGP_BASE 0x03 670#define RV515_MC_AGP_BASE_2 0x04 671 672#define R520_MC_FB_LOCATION 0x04 673#define R520_MC_AGP_LOCATION 0x05 674#define R520_MC_AGP_BASE 0x06 675#define R520_MC_AGP_BASE_2 0x07 676 677#define RADEON_MPP_TB_CONFIG 0x01c0 678#define RADEON_MEM_CNTL 0x0140 679#define RADEON_MEM_SDRAM_MODE_REG 0x0158 680#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 681#define RS480_AGP_BASE_2 0x0164 682#define RADEON_AGP_BASE 0x0170 683 684/* pipe config regs */ 685#define R400_GB_PIPE_SELECT 0x402c 686#define RV530_GB_PIPE_SELECT2 0x4124 687#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 688#define R300_GB_TILE_CONFIG 0x4018 689# define R300_ENABLE_TILING (1 << 0) 690# define R300_PIPE_COUNT_RV350 (0 << 1) 691# define R300_PIPE_COUNT_R300 (3 << 1) 692# define R300_PIPE_COUNT_R420_3P (6 << 1) 693# define R300_PIPE_COUNT_R420 (7 << 1) 694# define R300_TILE_SIZE_8 (0 << 4) 695# define R300_TILE_SIZE_16 (1 << 4) 696# define R300_TILE_SIZE_32 (2 << 4) 697# define R300_SUBPIXEL_1_12 (0 << 16) 698# define R300_SUBPIXEL_1_16 (1 << 16) 699#define R300_DST_PIPE_CONFIG 0x170c 700# define R300_PIPE_AUTO_CONFIG (1U << 31) 701#define R300_RB2D_DSTCACHE_MODE 0x3428 702# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 703# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 704 705#define RADEON_RB3D_COLOROFFSET 0x1c40 706#define RADEON_RB3D_COLORPITCH 0x1c48 707 708#define RADEON_SRC_X_Y 0x1590 709 710#define RADEON_DP_GUI_MASTER_CNTL 0x146c 711# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 712# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 713# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 714# define RADEON_GMC_BRUSH_NONE (15 << 4) 715# define RADEON_GMC_DST_16BPP (4 << 8) 716# define RADEON_GMC_DST_24BPP (5 << 8) 717# define RADEON_GMC_DST_32BPP (6 << 8) 718# define RADEON_GMC_DST_DATATYPE_SHIFT 8 719# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 720# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 721# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 722# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 723# define RADEON_GMC_WR_MSK_DIS (1 << 30) 724# define RADEON_ROP3_S 0x00cc0000 725# define RADEON_ROP3_P 0x00f00000 726#define RADEON_DP_WRITE_MASK 0x16cc 727#define RADEON_SRC_PITCH_OFFSET 0x1428 728#define RADEON_DST_PITCH_OFFSET 0x142c 729#define RADEON_DST_PITCH_OFFSET_C 0x1c80 730# define RADEON_DST_TILE_LINEAR (0 << 30) 731# define RADEON_DST_TILE_MACRO (1 << 30) 732# define RADEON_DST_TILE_MICRO (2U << 30) 733# define RADEON_DST_TILE_BOTH (3U << 30) 734 735#define RADEON_SCRATCH_REG0 0x15e0 736#define RADEON_SCRATCH_REG1 0x15e4 737#define RADEON_SCRATCH_REG2 0x15e8 738#define RADEON_SCRATCH_REG3 0x15ec 739#define RADEON_SCRATCH_REG4 0x15f0 740#define RADEON_SCRATCH_REG5 0x15f4 741#define RADEON_SCRATCH_UMSK 0x0770 742#define RADEON_SCRATCH_ADDR 0x0774 743 744#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 745 746extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); 747 748#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) 749 750#define R600_SCRATCH_REG0 0x8500 751#define R600_SCRATCH_REG1 0x8504 752#define R600_SCRATCH_REG2 0x8508 753#define R600_SCRATCH_REG3 0x850c 754#define R600_SCRATCH_REG4 0x8510 755#define R600_SCRATCH_REG5 0x8514 756#define R600_SCRATCH_REG6 0x8518 757#define R600_SCRATCH_REG7 0x851c 758#define R600_SCRATCH_UMSK 0x8540 759#define R600_SCRATCH_ADDR 0x8544 760 761#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) 762 763#define RADEON_GEN_INT_CNTL 0x0040 764# define RADEON_CRTC_VBLANK_MASK (1 << 0) 765# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 766# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 767# define RADEON_SW_INT_ENABLE (1 << 25) 768 769#define RADEON_GEN_INT_STATUS 0x0044 770# define RADEON_CRTC_VBLANK_STAT (1 << 0) 771# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 772# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 773# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 774# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 775# define RADEON_SW_INT_TEST (1 << 25) 776# define RADEON_SW_INT_TEST_ACK (1 << 25) 777# define RADEON_SW_INT_FIRE (1 << 26) 778# define R500_DISPLAY_INT_STATUS (1 << 0) 779 780#define RADEON_HOST_PATH_CNTL 0x0130 781# define RADEON_HDP_SOFT_RESET (1 << 26) 782# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 783# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 784 785#define RADEON_ISYNC_CNTL 0x1724 786# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 787# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 788# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 789# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 790# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 791# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 792 793#define RADEON_RBBM_GUICNTL 0x172c 794# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 795# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 796# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 797# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 798 799#define RADEON_MC_AGP_LOCATION 0x014c 800#define RADEON_MC_FB_LOCATION 0x0148 801#define RADEON_MCLK_CNTL 0x0012 802# define RADEON_FORCEON_MCLKA (1 << 16) 803# define RADEON_FORCEON_MCLKB (1 << 17) 804# define RADEON_FORCEON_YCLKA (1 << 18) 805# define RADEON_FORCEON_YCLKB (1 << 19) 806# define RADEON_FORCEON_MC (1 << 20) 807# define RADEON_FORCEON_AIC (1 << 21) 808 809#define RADEON_PP_BORDER_COLOR_0 0x1d40 810#define RADEON_PP_BORDER_COLOR_1 0x1d44 811#define RADEON_PP_BORDER_COLOR_2 0x1d48 812#define RADEON_PP_CNTL 0x1c38 813# define RADEON_SCISSOR_ENABLE (1 << 1) 814#define RADEON_PP_LUM_MATRIX 0x1d00 815#define RADEON_PP_MISC 0x1c14 816#define RADEON_PP_ROT_MATRIX_0 0x1d58 817#define RADEON_PP_TXFILTER_0 0x1c54 818#define RADEON_PP_TXOFFSET_0 0x1c5c 819#define RADEON_PP_TXFILTER_1 0x1c6c 820#define RADEON_PP_TXFILTER_2 0x1c84 821 822#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 823#define R300_DSTCACHE_CTLSTAT 0x1714 824# define R300_RB2D_DC_FLUSH (3 << 0) 825# define R300_RB2D_DC_FREE (3 << 2) 826# define R300_RB2D_DC_FLUSH_ALL 0xf 827# define R300_RB2D_DC_BUSY (1U << 31) 828#define RADEON_RB3D_CNTL 0x1c3c 829# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 830# define RADEON_PLANE_MASK_ENABLE (1 << 1) 831# define RADEON_DITHER_ENABLE (1 << 2) 832# define RADEON_ROUND_ENABLE (1 << 3) 833# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 834# define RADEON_DITHER_INIT (1 << 5) 835# define RADEON_ROP_ENABLE (1 << 6) 836# define RADEON_STENCIL_ENABLE (1 << 7) 837# define RADEON_Z_ENABLE (1 << 8) 838# define RADEON_ZBLOCK16 (1 << 15) 839#define RADEON_RB3D_DEPTHOFFSET 0x1c24 840#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 841#define RADEON_RB3D_DEPTHPITCH 0x1c28 842#define RADEON_RB3D_PLANEMASK 0x1d84 843#define RADEON_RB3D_STENCILREFMASK 0x1d7c 844#define RADEON_RB3D_ZCACHE_MODE 0x3250 845#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 846# define RADEON_RB3D_ZC_FLUSH (1 << 0) 847# define RADEON_RB3D_ZC_FREE (1 << 2) 848# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 849# define RADEON_RB3D_ZC_BUSY (1U << 31) 850#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 851# define R300_ZC_FLUSH (1 << 0) 852# define R300_ZC_FREE (1 << 1) 853# define R300_ZC_BUSY (1U << 31) 854#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 855# define RADEON_RB3D_DC_FLUSH (3 << 0) 856# define RADEON_RB3D_DC_FREE (3 << 2) 857# define RADEON_RB3D_DC_FLUSH_ALL 0xf 858# define RADEON_RB3D_DC_BUSY (1U << 31) 859#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 860# define R300_RB3D_DC_FLUSH (2 << 0) 861# define R300_RB3D_DC_FREE (2 << 2) 862# define R300_RB3D_DC_FINISH (1 << 4) 863#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 864# define RADEON_Z_TEST_MASK (7 << 4) 865# define RADEON_Z_TEST_ALWAYS (7 << 4) 866# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 867# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 868# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 869# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 870# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 871# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 872# define RADEON_FORCE_Z_DIRTY (1 << 29) 873# define RADEON_Z_WRITE_ENABLE (1 << 30) 874# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31) 875#define RADEON_RBBM_SOFT_RESET 0x00f0 876# define RADEON_SOFT_RESET_CP (1 << 0) 877# define RADEON_SOFT_RESET_HI (1 << 1) 878# define RADEON_SOFT_RESET_SE (1 << 2) 879# define RADEON_SOFT_RESET_RE (1 << 3) 880# define RADEON_SOFT_RESET_PP (1 << 4) 881# define RADEON_SOFT_RESET_E2 (1 << 5) 882# define RADEON_SOFT_RESET_RB (1 << 6) 883# define RADEON_SOFT_RESET_HDP (1 << 7) 884/* 885 * 6:0 Available slots in the FIFO 886 * 8 Host Interface active 887 * 9 CP request active 888 * 10 FIFO request active 889 * 11 Host Interface retry active 890 * 12 CP retry active 891 * 13 FIFO retry active 892 * 14 FIFO pipeline busy 893 * 15 Event engine busy 894 * 16 CP command stream busy 895 * 17 2D engine busy 896 * 18 2D portion of render backend busy 897 * 20 3D setup engine busy 898 * 26 GA engine busy 899 * 27 CBA 2D engine busy 900 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 901 * command stream queue not empty or Ring Buffer not empty 902 */ 903#define RADEON_RBBM_STATUS 0x0e40 904/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 905/* #define RADEON_RBBM_STATUS 0x1740 */ 906/* bits 6:0 are dword slots available in the cmd fifo */ 907# define RADEON_RBBM_FIFOCNT_MASK 0x007f 908# define RADEON_HIRQ_ON_RBB (1 << 8) 909# define RADEON_CPRQ_ON_RBB (1 << 9) 910# define RADEON_CFRQ_ON_RBB (1 << 10) 911# define RADEON_HIRQ_IN_RTBUF (1 << 11) 912# define RADEON_CPRQ_IN_RTBUF (1 << 12) 913# define RADEON_CFRQ_IN_RTBUF (1 << 13) 914# define RADEON_PIPE_BUSY (1 << 14) 915# define RADEON_ENG_EV_BUSY (1 << 15) 916# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 917# define RADEON_E2_BUSY (1 << 17) 918# define RADEON_RB2D_BUSY (1 << 18) 919# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 920# define RADEON_VAP_BUSY (1 << 20) 921# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 922# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 923# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 924# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 925# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 926# define RADEON_GA_BUSY (1 << 26) 927# define RADEON_CBA2D_BUSY (1 << 27) 928# define RADEON_RBBM_ACTIVE (1U << 31) 929#define RADEON_RE_LINE_PATTERN 0x1cd0 930#define RADEON_RE_MISC 0x26c4 931#define RADEON_RE_TOP_LEFT 0x26c0 932#define RADEON_RE_WIDTH_HEIGHT 0x1c44 933#define RADEON_RE_STIPPLE_ADDR 0x1cc8 934#define RADEON_RE_STIPPLE_DATA 0x1ccc 935 936#define RADEON_SCISSOR_TL_0 0x1cd8 937#define RADEON_SCISSOR_BR_0 0x1cdc 938#define RADEON_SCISSOR_TL_1 0x1ce0 939#define RADEON_SCISSOR_BR_1 0x1ce4 940#define RADEON_SCISSOR_TL_2 0x1ce8 941#define RADEON_SCISSOR_BR_2 0x1cec 942#define RADEON_SE_COORD_FMT 0x1c50 943#define RADEON_SE_CNTL 0x1c4c 944# define RADEON_FFACE_CULL_CW (0 << 0) 945# define RADEON_BFACE_SOLID (3 << 1) 946# define RADEON_FFACE_SOLID (3 << 3) 947# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 948# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 949# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 950# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 951# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 952# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 953# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 954# define RADEON_FOG_SHADE_FLAT (1 << 14) 955# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 956# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 957# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 958# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 959# define RADEON_ROUND_MODE_TRUNC (0 << 28) 960# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 961#define RADEON_SE_CNTL_STATUS 0x2140 962#define RADEON_SE_LINE_WIDTH 0x1db8 963#define RADEON_SE_VPORT_XSCALE 0x1d98 964#define RADEON_SE_ZBIAS_FACTOR 0x1db0 965#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 966#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 967#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 968# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 969# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 970#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 971#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 972# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 973#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 974#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 975#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 976#define RADEON_SURFACE_CNTL 0x0b00 977# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 978# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 979# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 980# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 981# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 982# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 983# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 984# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 985# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 986#define RADEON_SURFACE0_INFO 0x0b0c 987# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 988# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 989# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 990# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 991# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 992# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 993#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 994#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 995# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 996#define RADEON_SURFACE1_INFO 0x0b1c 997#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 998#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 999#define RADEON_SURFACE2_INFO 0x0b2c 1000#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1001#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1002#define RADEON_SURFACE3_INFO 0x0b3c 1003#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1004#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1005#define RADEON_SURFACE4_INFO 0x0b4c 1006#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1007#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1008#define RADEON_SURFACE5_INFO 0x0b5c 1009#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1010#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1011#define RADEON_SURFACE6_INFO 0x0b6c 1012#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1013#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1014#define RADEON_SURFACE7_INFO 0x0b7c 1015#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1016#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1017#define RADEON_SW_SEMAPHORE 0x013c 1018 1019#define RADEON_WAIT_UNTIL 0x1720 1020# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1021# define RADEON_WAIT_2D_IDLE (1 << 14) 1022# define RADEON_WAIT_3D_IDLE (1 << 15) 1023# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1024# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1025# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1026 1027#define RADEON_RB3D_ZMASKOFFSET 0x3234 1028#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1029# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1030# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1031 1032/* CP registers */ 1033#define RADEON_CP_ME_RAM_ADDR 0x07d4 1034#define RADEON_CP_ME_RAM_RADDR 0x07d8 1035#define RADEON_CP_ME_RAM_DATAH 0x07dc 1036#define RADEON_CP_ME_RAM_DATAL 0x07e0 1037 1038#define RADEON_CP_RB_BASE 0x0700 1039#define RADEON_CP_RB_CNTL 0x0704 1040# define RADEON_BUF_SWAP_32BIT (2 << 16) 1041# define RADEON_RB_NO_UPDATE (1 << 27) 1042# define RADEON_RB_RPTR_WR_ENA (1U << 31) 1043#define RADEON_CP_RB_RPTR_ADDR 0x070c 1044#define RADEON_CP_RB_RPTR 0x0710 1045#define RADEON_CP_RB_WPTR 0x0714 1046 1047#define RADEON_CP_RB_WPTR_DELAY 0x0718 1048# define RADEON_PRE_WRITE_TIMER_SHIFT 0 1049# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 1050 1051#define RADEON_CP_IB_BASE 0x0738 1052 1053#define RADEON_CP_CSQ_CNTL 0x0740 1054# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1055# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1056# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1057# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1058# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1059# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1060# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1061 1062#define R300_CP_RESYNC_ADDR 0x0778 1063#define R300_CP_RESYNC_DATA 0x077c 1064 1065#define RADEON_AIC_CNTL 0x01d0 1066# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1067# define RS400_MSI_REARM (1 << 3) 1068#define RADEON_AIC_STAT 0x01d4 1069#define RADEON_AIC_PT_BASE 0x01d8 1070#define RADEON_AIC_LO_ADDR 0x01dc 1071#define RADEON_AIC_HI_ADDR 0x01e0 1072#define RADEON_AIC_TLB_ADDR 0x01e4 1073#define RADEON_AIC_TLB_DATA 0x01e8 1074 1075/* CP command packets */ 1076#define RADEON_CP_PACKET0 0x00000000 1077# define RADEON_ONE_REG_WR (1 << 15) 1078#define RADEON_CP_PACKET1 0x40000000 1079#define RADEON_CP_PACKET2 0x80000000 1080#define RADEON_CP_PACKET3 0xC0000000 1081# define RADEON_CP_NOP 0x00001000 1082# define RADEON_CP_NEXT_CHAR 0x00001900 1083# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1084# define RADEON_CP_SET_SCISSORS 0x00001E00 1085 /* GEN_INDX_PRIM is unsupported starting with R300 */ 1086# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 1087# define RADEON_WAIT_FOR_IDLE 0x00002600 1088# define RADEON_3D_DRAW_VBUF 0x00002800 1089# define RADEON_3D_DRAW_IMMD 0x00002900 1090# define RADEON_3D_DRAW_INDX 0x00002A00 1091# define RADEON_CP_LOAD_PALETTE 0x00002C00 1092# define RADEON_3D_LOAD_VBPNTR 0x00002F00 1093# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1094# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1095# define RADEON_3D_CLEAR_ZMASK 0x00003200 1096# define RADEON_CP_INDX_BUFFER 0x00003300 1097# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1098# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1099# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1100# define RADEON_3D_CLEAR_HIZ 0x00003700 1101# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 1102# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 1103# define RADEON_CNTL_PAINT_MULTI 0x00009A00 1104# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1105# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1106 1107# define R600_IT_INDIRECT_BUFFER_END 0x00001700 1108# define R600_IT_SET_PREDICATION 0x00002000 1109# define R600_IT_REG_RMW 0x00002100 1110# define R600_IT_COND_EXEC 0x00002200 1111# define R600_IT_PRED_EXEC 0x00002300 1112# define R600_IT_START_3D_CMDBUF 0x00002400 1113# define R600_IT_DRAW_INDEX_2 0x00002700 1114# define R600_IT_CONTEXT_CONTROL 0x00002800 1115# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900 1116# define R600_IT_INDEX_TYPE 0x00002A00 1117# define R600_IT_DRAW_INDEX 0x00002B00 1118# define R600_IT_DRAW_INDEX_AUTO 0x00002D00 1119# define R600_IT_DRAW_INDEX_IMMD 0x00002E00 1120# define R600_IT_NUM_INSTANCES 0x00002F00 1121# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400 1122# define R600_IT_INDIRECT_BUFFER_MP 0x00003800 1123# define R600_IT_MEM_SEMAPHORE 0x00003900 1124# define R600_IT_MPEG_INDEX 0x00003A00 1125# define R600_IT_WAIT_REG_MEM 0x00003C00 1126# define R600_IT_MEM_WRITE 0x00003D00 1127# define R600_IT_INDIRECT_BUFFER 0x00003200 1128# define R600_IT_SURFACE_SYNC 0x00004300 1129# define R600_CB0_DEST_BASE_ENA (1 << 6) 1130# define R600_TC_ACTION_ENA (1 << 23) 1131# define R600_VC_ACTION_ENA (1 << 24) 1132# define R600_CB_ACTION_ENA (1 << 25) 1133# define R600_DB_ACTION_ENA (1 << 26) 1134# define R600_SH_ACTION_ENA (1 << 27) 1135# define R600_SMX_ACTION_ENA (1 << 28) 1136# define R600_IT_ME_INITIALIZE 0x00004400 1137# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1138# define R600_IT_COND_WRITE 0x00004500 1139# define R600_IT_EVENT_WRITE 0x00004600 1140# define R600_IT_EVENT_WRITE_EOP 0x00004700 1141# define R600_IT_ONE_REG_WRITE 0x00005700 1142# define R600_IT_SET_CONFIG_REG 0x00006800 1143# define R600_SET_CONFIG_REG_OFFSET 0x00008000 1144# define R600_SET_CONFIG_REG_END 0x0000ac00 1145# define R600_IT_SET_CONTEXT_REG 0x00006900 1146# define R600_SET_CONTEXT_REG_OFFSET 0x00028000 1147# define R600_SET_CONTEXT_REG_END 0x00029000 1148# define R600_IT_SET_ALU_CONST 0x00006A00 1149# define R600_SET_ALU_CONST_OFFSET 0x00030000 1150# define R600_SET_ALU_CONST_END 0x00032000 1151# define R600_IT_SET_BOOL_CONST 0x00006B00 1152# define R600_SET_BOOL_CONST_OFFSET 0x0003e380 1153# define R600_SET_BOOL_CONST_END 0x00040000 1154# define R600_IT_SET_LOOP_CONST 0x00006C00 1155# define R600_SET_LOOP_CONST_OFFSET 0x0003e200 1156# define R600_SET_LOOP_CONST_END 0x0003e380 1157# define R600_IT_SET_RESOURCE 0x00006D00 1158# define R600_SET_RESOURCE_OFFSET 0x00038000 1159# define R600_SET_RESOURCE_END 0x0003c000 1160# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0 1161# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1 1162# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2 1163# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3 1164# define R600_IT_SET_SAMPLER 0x00006E00 1165# define R600_SET_SAMPLER_OFFSET 0x0003c000 1166# define R600_SET_SAMPLER_END 0x0003cff0 1167# define R600_IT_SET_CTL_CONST 0x00006F00 1168# define R600_SET_CTL_CONST_OFFSET 0x0003cff0 1169# define R600_SET_CTL_CONST_END 0x0003e200 1170# define R600_IT_SURFACE_BASE_UPDATE 0x00007300 1171 1172#define RADEON_CP_PACKET_MASK 0xC0000000 1173#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1174#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1175#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 1176#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 1177 1178#define RADEON_VTX_Z_PRESENT (1U << 31) 1179#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 1180 1181#define RADEON_PRIM_TYPE_NONE (0 << 0) 1182#define RADEON_PRIM_TYPE_POINT (1 << 0) 1183#define RADEON_PRIM_TYPE_LINE (2 << 0) 1184#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 1185#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 1186#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 1187#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 1188#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1189#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1190#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1191#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1192#define RADEON_PRIM_TYPE_MASK 0xf 1193#define RADEON_PRIM_WALK_IND (1 << 4) 1194#define RADEON_PRIM_WALK_LIST (2 << 4) 1195#define RADEON_PRIM_WALK_RING (3 << 4) 1196#define RADEON_COLOR_ORDER_BGRA (0 << 6) 1197#define RADEON_COLOR_ORDER_RGBA (1 << 6) 1198#define RADEON_MAOS_ENABLE (1 << 7) 1199#define RADEON_VTX_FMT_R128_MODE (0 << 8) 1200#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1201#define RADEON_NUM_VERTICES_SHIFT 16 1202 1203#define RADEON_COLOR_FORMAT_CI8 2 1204#define RADEON_COLOR_FORMAT_ARGB1555 3 1205#define RADEON_COLOR_FORMAT_RGB565 4 1206#define RADEON_COLOR_FORMAT_ARGB8888 6 1207#define RADEON_COLOR_FORMAT_RGB332 7 1208#define RADEON_COLOR_FORMAT_RGB8 9 1209#define RADEON_COLOR_FORMAT_ARGB4444 15 1210 1211#define RADEON_TXFORMAT_I8 0 1212#define RADEON_TXFORMAT_AI88 1 1213#define RADEON_TXFORMAT_RGB332 2 1214#define RADEON_TXFORMAT_ARGB1555 3 1215#define RADEON_TXFORMAT_RGB565 4 1216#define RADEON_TXFORMAT_ARGB4444 5 1217#define RADEON_TXFORMAT_ARGB8888 6 1218#define RADEON_TXFORMAT_RGBA8888 7 1219#define RADEON_TXFORMAT_Y8 8 1220#define RADEON_TXFORMAT_VYUY422 10 1221#define RADEON_TXFORMAT_YVYU422 11 1222#define RADEON_TXFORMAT_DXT1 12 1223#define RADEON_TXFORMAT_DXT23 14 1224#define RADEON_TXFORMAT_DXT45 15 1225 1226#define R200_PP_TXCBLEND_0 0x2f00 1227#define R200_PP_TXCBLEND_1 0x2f10 1228#define R200_PP_TXCBLEND_2 0x2f20 1229#define R200_PP_TXCBLEND_3 0x2f30 1230#define R200_PP_TXCBLEND_4 0x2f40 1231#define R200_PP_TXCBLEND_5 0x2f50 1232#define R200_PP_TXCBLEND_6 0x2f60 1233#define R200_PP_TXCBLEND_7 0x2f70 1234#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1235#define R200_PP_TFACTOR_0 0x2ee0 1236#define R200_SE_VTX_FMT_0 0x2088 1237#define R200_SE_VAP_CNTL 0x2080 1238#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1239#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1240#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1241#define R200_PP_TXFILTER_5 0x2ca0 1242#define R200_PP_TXFILTER_4 0x2c80 1243#define R200_PP_TXFILTER_3 0x2c60 1244#define R200_PP_TXFILTER_2 0x2c40 1245#define R200_PP_TXFILTER_1 0x2c20 1246#define R200_PP_TXFILTER_0 0x2c00 1247#define R200_PP_TXOFFSET_5 0x2d78 1248#define R200_PP_TXOFFSET_4 0x2d60 1249#define R200_PP_TXOFFSET_3 0x2d48 1250#define R200_PP_TXOFFSET_2 0x2d30 1251#define R200_PP_TXOFFSET_1 0x2d18 1252#define R200_PP_TXOFFSET_0 0x2d00 1253 1254#define R200_PP_CUBIC_FACES_0 0x2c18 1255#define R200_PP_CUBIC_FACES_1 0x2c38 1256#define R200_PP_CUBIC_FACES_2 0x2c58 1257#define R200_PP_CUBIC_FACES_3 0x2c78 1258#define R200_PP_CUBIC_FACES_4 0x2c98 1259#define R200_PP_CUBIC_FACES_5 0x2cb8 1260#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1261#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1262#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1263#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1264#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1265#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1266#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1267#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1268#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1269#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1270#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1271#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1272#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1273#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1274#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1275#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1276#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1277#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1278#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1279#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1280#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1281#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1282#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1283#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1284#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1285#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1286#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1287#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1288#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1289#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1290 1291#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1292#define R200_SE_VTE_CNTL 0x20b0 1293#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1294#define R200_PP_TAM_DEBUG3 0x2d9c 1295#define R200_PP_CNTL_X 0x2cc4 1296#define R200_SE_VAP_CNTL_STATUS 0x2140 1297#define R200_RE_SCISSOR_TL_0 0x1cd8 1298#define R200_RE_SCISSOR_TL_1 0x1ce0 1299#define R200_RE_SCISSOR_TL_2 0x1ce8 1300#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1301#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1302#define R200_SE_VTX_STATE_CNTL 0x2180 1303#define R200_RE_POINTSIZE 0x2648 1304#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1305 1306#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1307#define RADEON_PP_TEX_SIZE_1 0x1d0c 1308#define RADEON_PP_TEX_SIZE_2 0x1d14 1309 1310#define RADEON_PP_CUBIC_FACES_0 0x1d24 1311#define RADEON_PP_CUBIC_FACES_1 0x1d28 1312#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1313#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1314#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1315#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1316 1317#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1318 1319#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1320#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1321#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1322#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1323#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1324#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1325#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1326#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1327#define R200_3D_DRAW_IMMD_2 0xC0003500 1328#define R200_SE_VTX_FMT_1 0x208c 1329#define R200_RE_CNTL 0x1c50 1330 1331#define R200_RB3D_BLENDCOLOR 0x3218 1332 1333#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1334 1335#define R200_PP_TRI_PERF 0x2cf8 1336 1337#define R200_PP_AFS_0 0x2f80 1338#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1339 1340#define R200_VAP_PVS_CNTL_1 0x22D0 1341 1342#define RADEON_CRTC_CRNT_FRAME 0x0214 1343#define RADEON_CRTC2_CRNT_FRAME 0x0314 1344 1345#define R500_D1CRTC_STATUS 0x609c 1346#define R500_D2CRTC_STATUS 0x689c 1347#define R500_CRTC_V_BLANK (1<<0) 1348 1349#define R500_D1CRTC_FRAME_COUNT 0x60a4 1350#define R500_D2CRTC_FRAME_COUNT 0x68a4 1351 1352#define R500_D1MODE_V_COUNTER 0x6530 1353#define R500_D2MODE_V_COUNTER 0x6d30 1354 1355#define R500_D1MODE_VBLANK_STATUS 0x6534 1356#define R500_D2MODE_VBLANK_STATUS 0x6d34 1357#define R500_VBLANK_OCCURED (1<<0) 1358#define R500_VBLANK_ACK (1<<4) 1359#define R500_VBLANK_STAT (1<<12) 1360#define R500_VBLANK_INT (1<<16) 1361 1362#define R500_DxMODE_INT_MASK 0x6540 1363#define R500_D1MODE_INT_MASK (1<<0) 1364#define R500_D2MODE_INT_MASK (1<<8) 1365 1366#define R500_DISP_INTERRUPT_STATUS 0x7edc 1367#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1368#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1369 1370/* R6xx/R7xx registers */ 1371#define R600_MC_VM_FB_LOCATION 0x2180 1372#define R600_MC_VM_AGP_TOP 0x2184 1373#define R600_MC_VM_AGP_BOT 0x2188 1374#define R600_MC_VM_AGP_BASE 0x218c 1375#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1376#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1377#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1378 1379#define R700_MC_VM_FB_LOCATION 0x2024 1380#define R700_MC_VM_AGP_TOP 0x2028 1381#define R700_MC_VM_AGP_BOT 0x202c 1382#define R700_MC_VM_AGP_BASE 0x2030 1383#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1384#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1385#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1386 1387#define R600_MCD_RD_A_CNTL 0x219c 1388#define R600_MCD_RD_B_CNTL 0x21a0 1389 1390#define R600_MCD_WR_A_CNTL 0x21a4 1391#define R600_MCD_WR_B_CNTL 0x21a8 1392 1393#define R600_MCD_RD_SYS_CNTL 0x2200 1394#define R600_MCD_WR_SYS_CNTL 0x2214 1395 1396#define R600_MCD_RD_GFX_CNTL 0x21fc 1397#define R600_MCD_RD_HDP_CNTL 0x2204 1398#define R600_MCD_RD_PDMA_CNTL 0x2208 1399#define R600_MCD_RD_SEM_CNTL 0x220c 1400#define R600_MCD_WR_GFX_CNTL 0x2210 1401#define R600_MCD_WR_HDP_CNTL 0x2218 1402#define R600_MCD_WR_PDMA_CNTL 0x221c 1403#define R600_MCD_WR_SEM_CNTL 0x2220 1404 1405# define R600_MCD_L1_TLB (1 << 0) 1406# define R600_MCD_L1_FRAG_PROC (1 << 1) 1407# define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1408 1409# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1410# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1411# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1412# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1413# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1414 1415# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1416# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1417 1418# define R600_MCD_SEMAPHORE_MODE (1 << 10) 1419# define R600_MCD_WAIT_L2_QUERY (1 << 11) 1420# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1421# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1422 1423#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1424#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1425#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1426 1427#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1428#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1429#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1430#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1431 1432# define R700_ENABLE_L1_TLB (1 << 0) 1433# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1434# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1435# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1436# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1437# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1438 1439#define R700_MC_ARB_RAMCFG 0x2760 1440# define R700_NOOFBANK_SHIFT 0 1441# define R700_NOOFBANK_MASK 0x3 1442# define R700_NOOFRANK_SHIFT 2 1443# define R700_NOOFRANK_MASK 0x1 1444# define R700_NOOFROWS_SHIFT 3 1445# define R700_NOOFROWS_MASK 0x7 1446# define R700_NOOFCOLS_SHIFT 6 1447# define R700_NOOFCOLS_MASK 0x3 1448# define R700_CHANSIZE_SHIFT 8 1449# define R700_CHANSIZE_MASK 0x1 1450# define R700_BURSTLENGTH_SHIFT 9 1451# define R700_BURSTLENGTH_MASK 0x1 1452#define R600_RAMCFG 0x2408 1453# define R600_NOOFBANK_SHIFT 0 1454# define R600_NOOFBANK_MASK 0x1 1455# define R600_NOOFRANK_SHIFT 1 1456# define R600_NOOFRANK_MASK 0x1 1457# define R600_NOOFROWS_SHIFT 2 1458# define R600_NOOFROWS_MASK 0x7 1459# define R600_NOOFCOLS_SHIFT 5 1460# define R600_NOOFCOLS_MASK 0x3 1461# define R600_CHANSIZE_SHIFT 7 1462# define R600_CHANSIZE_MASK 0x1 1463# define R600_BURSTLENGTH_SHIFT 8 1464# define R600_BURSTLENGTH_MASK 0x1 1465 1466#define R600_VM_L2_CNTL 0x1400 1467# define R600_VM_L2_CACHE_EN (1 << 0) 1468# define R600_VM_L2_FRAG_PROC (1 << 1) 1469# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1470# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1471# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1472 1473#define R600_VM_L2_CNTL2 0x1404 1474# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1475# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1476#define R600_VM_L2_CNTL3 0x1408 1477# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1478# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1479# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1480# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1481# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1482 1483#define R600_VM_L2_STATUS 0x140c 1484 1485#define R600_VM_CONTEXT0_CNTL 0x1410 1486# define R600_VM_ENABLE_CONTEXT (1 << 0) 1487# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1488 1489#define R600_VM_CONTEXT0_CNTL2 0x1430 1490#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1491#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1492#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1493#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1494#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1495#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1496 1497#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1498#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1499#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1500 1501#define R600_HDP_HOST_PATH_CNTL 0x2c00 1502 1503#define R600_GRBM_CNTL 0x8000 1504# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1505 1506#define R600_GRBM_STATUS 0x8010 1507# define R600_CMDFIFO_AVAIL_MASK 0x1f 1508# define R700_CMDFIFO_AVAIL_MASK 0xf 1509# define R600_GUI_ACTIVE (1U << 31) 1510#define R600_GRBM_STATUS2 0x8014 1511#define R600_GRBM_SOFT_RESET 0x8020 1512# define R600_SOFT_RESET_CP (1 << 0) 1513#define R600_WAIT_UNTIL 0x8040 1514 1515#define R600_CP_SEM_WAIT_TIMER 0x85bc 1516#define R600_CP_ME_CNTL 0x86d8 1517# define R600_CP_ME_HALT (1 << 28) 1518#define R600_CP_QUEUE_THRESHOLDS 0x8760 1519# define R600_ROQ_IB1_START(x) ((x) << 0) 1520# define R600_ROQ_IB2_START(x) ((x) << 8) 1521#define R600_CP_MEQ_THRESHOLDS 0x8764 1522# define R700_STQ_SPLIT(x) ((x) << 0) 1523# define R600_MEQ_END(x) ((x) << 16) 1524# define R600_ROQ_END(x) ((x) << 24) 1525#define R600_CP_PERFMON_CNTL 0x87fc 1526#define R600_CP_RB_BASE 0xc100 1527#define R600_CP_RB_CNTL 0xc104 1528# define R600_RB_BUFSZ(x) ((x) << 0) 1529# define R600_RB_BLKSZ(x) ((x) << 8) 1530# define R600_BUF_SWAP_32BIT (2 << 16) 1531# define R600_RB_NO_UPDATE (1 << 27) 1532# define R600_RB_RPTR_WR_ENA (1U << 31) 1533#define R600_CP_RB_RPTR_WR 0xc108 1534#define R600_CP_RB_RPTR_ADDR 0xc10c 1535#define R600_CP_RB_RPTR_ADDR_HI 0xc110 1536#define R600_CP_RB_WPTR 0xc114 1537#define R600_CP_RB_WPTR_ADDR 0xc118 1538#define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1539#define R600_CP_RB_RPTR 0x8700 1540#define R600_CP_RB_WPTR_DELAY 0x8704 1541#define R600_CP_PFP_UCODE_ADDR 0xc150 1542#define R600_CP_PFP_UCODE_DATA 0xc154 1543#define R600_CP_ME_RAM_RADDR 0xc158 1544#define R600_CP_ME_RAM_WADDR 0xc15c 1545#define R600_CP_ME_RAM_DATA 0xc160 1546#define R600_CP_DEBUG 0xc1fc 1547 1548#define R600_PA_CL_ENHANCE 0x8a14 1549# define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1550# define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1551#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1552#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1553#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1554# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1555# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1556#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1557#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1558#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1559#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1560# define R600_S0_X(x) ((x) << 0) 1561# define R600_S0_Y(x) ((x) << 4) 1562# define R600_S1_X(x) ((x) << 8) 1563# define R600_S1_Y(x) ((x) << 12) 1564# define R600_S2_X(x) ((x) << 16) 1565# define R600_S2_Y(x) ((x) << 20) 1566# define R600_S3_X(x) ((x) << 24) 1567# define R600_S3_Y(x) ((x) << 28) 1568# define R600_S4_X(x) ((x) << 0) 1569# define R600_S4_Y(x) ((x) << 4) 1570# define R600_S5_X(x) ((x) << 8) 1571# define R600_S5_Y(x) ((x) << 12) 1572# define R600_S6_X(x) ((x) << 16) 1573# define R600_S6_Y(x) ((x) << 20) 1574# define R600_S7_X(x) ((x) << 24) 1575# define R600_S7_Y(x) ((x) << 28) 1576#define R600_PA_SC_FIFO_SIZE 0x8bd0 1577# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1578# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1579# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1580#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1581# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1582# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1583# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1584#define R600_PA_SC_ENHANCE 0x8bf0 1585# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1586# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1587#define R600_PA_SC_CLIPRECT_RULE 0x2820c 1588#define R700_PA_SC_EDGERULE 0x28230 1589#define R600_PA_SC_LINE_STIPPLE 0x28a0c 1590#define R600_PA_SC_MODE_CNTL 0x28a4c 1591#define R600_PA_SC_AA_CONFIG 0x28c04 1592 1593#define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1594# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1595# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1596# define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1597#define R600_SX_DEBUG_1 0x9054 1598# define R600_SMX_EVENT_RELEASE (1 << 0) 1599# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1600#define R700_SX_DEBUG_1 0x9058 1601# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1602#define R600_SX_MISC 0x28350 1603 1604#define R600_DB_DEBUG 0x9830 1605# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) 1606#define R600_DB_WATERMARKS 0x9838 1607# define R600_DEPTH_FREE(x) ((x) << 0) 1608# define R600_DEPTH_FLUSH(x) ((x) << 5) 1609# define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1610# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1611#define R700_DB_DEBUG3 0x98b0 1612# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1613#define RV700_DB_DEBUG4 0x9b8c 1614# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1615 1616#define R600_VGT_CACHE_INVALIDATION 0x88c4 1617# define R600_CACHE_INVALIDATION(x) ((x) << 0) 1618# define R600_VC_ONLY 0 1619# define R600_TC_ONLY 1 1620# define R600_VC_AND_TC 2 1621# define R700_AUTO_INVLD_EN(x) ((x) << 6) 1622# define R700_NO_AUTO 0 1623# define R700_ES_AUTO 1 1624# define R700_GS_AUTO 2 1625# define R700_ES_AND_GS_AUTO 3 1626#define R600_VGT_GS_PER_ES 0x88c8 1627#define R600_VGT_ES_PER_GS 0x88cc 1628#define R600_VGT_GS_PER_VS 0x88e8 1629#define R600_VGT_GS_VERTEX_REUSE 0x88d4 1630#define R600_VGT_NUM_INSTANCES 0x8974 1631#define R600_VGT_STRMOUT_EN 0x28ab0 1632#define R600_VGT_EVENT_INITIATOR 0x28a90 1633# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1634#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1635# define R600_VTX_REUSE_DEPTH_MASK 0xff 1636#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1637# define R600_DEALLOC_DIST_MASK 0x7f 1638 1639#define R600_CB_COLOR0_BASE 0x28040 1640#define R600_CB_COLOR1_BASE 0x28044 1641#define R600_CB_COLOR2_BASE 0x28048 1642#define R600_CB_COLOR3_BASE 0x2804c 1643#define R600_CB_COLOR4_BASE 0x28050 1644#define R600_CB_COLOR5_BASE 0x28054 1645#define R600_CB_COLOR6_BASE 0x28058 1646#define R600_CB_COLOR7_BASE 0x2805c 1647#define R600_CB_COLOR7_FRAG 0x280fc 1648 1649#define R600_CB_COLOR0_SIZE 0x28060 1650#define R600_CB_COLOR0_VIEW 0x28080 1651#define R600_CB_COLOR0_INFO 0x280a0 1652#define R600_CB_COLOR0_TILE 0x280c0 1653#define R600_CB_COLOR0_FRAG 0x280e0 1654#define R600_CB_COLOR0_MASK 0x28100 1655 1656#define AVIVO_D1MODE_VLINE_START_END 0x6538 1657#define AVIVO_D2MODE_VLINE_START_END 0x6d38 1658#define R600_CP_COHER_BASE 0x85f8 1659#define R600_DB_DEPTH_BASE 0x2800c 1660#define R600_SQ_PGM_START_FS 0x28894 1661#define R600_SQ_PGM_START_ES 0x28880 1662#define R600_SQ_PGM_START_VS 0x28858 1663#define R600_SQ_PGM_RESOURCES_VS 0x28868 1664#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0 1665#define R600_SQ_PGM_START_GS 0x2886c 1666#define R600_SQ_PGM_START_PS 0x28840 1667#define R600_SQ_PGM_RESOURCES_PS 0x28850 1668#define R600_SQ_PGM_EXPORTS_PS 0x28854 1669#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc 1670#define R600_VGT_DMA_BASE 0x287e8 1671#define R600_VGT_DMA_BASE_HI 0x287e4 1672#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10 1673#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14 1674#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18 1675#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c 1676#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44 1677#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48 1678#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c 1679#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50 1680#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8 1681#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8 1682#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8 1683#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08 1684#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc 1685#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec 1686#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc 1687#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c 1688 1689#define R600_VGT_PRIMITIVE_TYPE 0x8958 1690 1691#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030 1692#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240 1693#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204 1694 1695#define R600_TC_CNTL 0x9608 1696# define R600_TC_L2_SIZE(x) ((x) << 5) 1697# define R600_L2_DISABLE_LATE_HIT (1 << 9) 1698 1699#define R600_ARB_POP 0x2418 1700# define R600_ENABLE_TC128 (1 << 30) 1701#define R600_ARB_GDEC_RD_CNTL 0x246c 1702 1703#define R600_TA_CNTL_AUX 0x9508 1704# define R600_DISABLE_CUBE_WRAP (1 << 0) 1705# define R600_DISABLE_CUBE_ANISO (1 << 1) 1706# define R700_GETLOD_SELECT(x) ((x) << 2) 1707# define R600_SYNC_GRADIENT (1 << 24) 1708# define R600_SYNC_WALKER (1 << 25) 1709# define R600_SYNC_ALIGNER (1 << 26) 1710# define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1711# define R600_BILINEAR_PRECISION_8_BIT (1U << 31) 1712 1713#define R700_TCP_CNTL 0x9610 1714 1715#define R600_SMX_DC_CTL0 0xa020 1716# define R700_USE_HASH_FUNCTION (1 << 0) 1717# define R700_CACHE_DEPTH(x) ((x) << 1) 1718# define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1719# define R700_STALL_ON_EVENT (1 << 11) 1720#define R700_SMX_EVENT_CTL 0xa02c 1721# define R700_ES_FLUSH_CTL(x) ((x) << 0) 1722# define R700_GS_FLUSH_CTL(x) ((x) << 3) 1723# define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1724# define R700_SYNC_FLUSH_CTL (1 << 8) 1725 1726#define R600_SQ_CONFIG 0x8c00 1727# define R600_VC_ENABLE (1 << 0) 1728# define R600_EXPORT_SRC_C (1 << 1) 1729# define R600_DX9_CONSTS (1 << 2) 1730# define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1731# define R600_DX10_CLAMP (1 << 4) 1732# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1733# define R600_PS_PRIO(x) ((x) << 24) 1734# define R600_VS_PRIO(x) ((x) << 26) 1735# define R600_GS_PRIO(x) ((x) << 28) 1736# define R600_ES_PRIO(x) ((x) << 30) 1737#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1738# define R600_NUM_PS_GPRS(x) ((x) << 0) 1739# define R600_NUM_VS_GPRS(x) ((x) << 16) 1740# define R700_DYN_GPR_ENABLE (1 << 27) 1741# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1742#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1743# define R600_NUM_GS_GPRS(x) ((x) << 0) 1744# define R600_NUM_ES_GPRS(x) ((x) << 16) 1745#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1746# define R600_NUM_PS_THREADS(x) ((x) << 0) 1747# define R600_NUM_VS_THREADS(x) ((x) << 8) 1748# define R600_NUM_GS_THREADS(x) ((x) << 16) 1749# define R600_NUM_ES_THREADS(x) ((x) << 24) 1750#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1751# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1752# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1753#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1754# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1755# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1756#define R600_SQ_MS_FIFO_SIZES 0x8cf0 1757# define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1758# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1759# define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1760# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1761#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1762# define R700_SIMDA_RING0(x) ((x) << 0) 1763# define R700_SIMDA_RING1(x) ((x) << 8) 1764# define R700_SIMDB_RING0(x) ((x) << 16) 1765# define R700_SIMDB_RING1(x) ((x) << 24) 1766#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1767#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1768#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1769#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1770#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1771#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1772#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1773 1774#define R600_SPI_PS_IN_CONTROL_0 0x286cc 1775# define R600_NUM_INTERP(x) ((x) << 0) 1776# define R600_POSITION_ENA (1 << 8) 1777# define R600_POSITION_CENTROID (1 << 9) 1778# define R600_POSITION_ADDR(x) ((x) << 10) 1779# define R600_PARAM_GEN(x) ((x) << 15) 1780# define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1781# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1782# define R600_PERSP_GRADIENT_ENA (1 << 28) 1783# define R600_LINEAR_GRADIENT_ENA (1 << 29) 1784# define R600_POSITION_SAMPLE (1 << 30) 1785# define R600_BARYC_AT_SAMPLE_ENA (1U << 31) 1786#define R600_SPI_PS_IN_CONTROL_1 0x286d0 1787# define R600_GEN_INDEX_PIX (1 << 0) 1788# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1789# define R600_FRONT_FACE_ENA (1 << 8) 1790# define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1791# define R600_FRONT_FACE_ALL_BITS (1 << 11) 1792# define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1793# define R600_FOG_ADDR(x) ((x) << 17) 1794# define R600_FIXED_PT_POSITION_ENA (1 << 24) 1795# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1796# define R700_POSITION_ULC (1 << 30) 1797#define R600_SPI_INPUT_Z 0x286d8 1798 1799#define R600_SPI_CONFIG_CNTL 0x9100 1800# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1801# define R600_DISABLE_INTERP_1 (1 << 5) 1802#define R600_SPI_CONFIG_CNTL_1 0x913c 1803# define R600_VTX_DONE_DELAY(x) ((x) << 0) 1804# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1805 1806#define R600_GB_TILING_CONFIG 0x98f0 1807# define R600_PIPE_TILING(x) ((x) << 1) 1808# define R600_BANK_TILING(x) ((x) << 4) 1809# define R600_GROUP_SIZE(x) ((x) << 6) 1810# define R600_ROW_TILING(x) ((x) << 8) 1811# define R600_BANK_SWAPS(x) ((x) << 11) 1812# define R600_SAMPLE_SPLIT(x) ((x) << 14) 1813# define R600_BACKEND_MAP(x) ((x) << 16) 1814#define R600_DCP_TILING_CONFIG 0x6ca0 1815#define R600_HDP_TILING_CONFIG 0x2f3c 1816 1817#define R600_CC_RB_BACKEND_DISABLE 0x98f4 1818#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1819# define R600_BACKEND_DISABLE(x) ((x) << 16) 1820 1821#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1822#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1823# define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1824# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1825# define R600_INACTIVE_SIMDS(x) ((x) << 16) 1826# define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1827 1828#define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1829#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1830#define R700_CGTS_TCC_DISABLE 0x9148 1831#define R700_CGTS_USER_TCC_DISABLE 0x914c 1832 1833/* Constants */ 1834#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1835 1836#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1837#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1838#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1839#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1840#define RADEON_LAST_DISPATCH 1 1841 1842#define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1843#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1844#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1845#define R600_LAST_SWI_REG R600_SCRATCH_REG3 1846 1847#define RADEON_MAX_VB_AGE 0x7fffffff 1848#define RADEON_MAX_VB_VERTS (0xffff) 1849 1850#define RADEON_RING_HIGH_MARK 128 1851 1852#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1853 1854#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1855#define RADEON_WRITE(reg, val) \ 1856do { \ 1857 if (reg < 0x10000) { \ 1858 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ 1859 } else { \ 1860 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ 1861 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ 1862 } \ 1863} while (0) 1864#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1865#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1866 1867#define RADEON_WRITE_PLL(addr, val) \ 1868do { \ 1869 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1870 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1871 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1872} while (0) 1873 1874#define RADEON_WRITE_PCIE(addr, val) \ 1875do { \ 1876 RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1877 ((addr) & 0xff)); \ 1878 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1879} while (0) 1880 1881#define R500_WRITE_MCIND(addr, val) \ 1882do { \ 1883 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1884 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1885 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1886} while (0) 1887 1888#define RS480_WRITE_MCIND(addr, val) \ 1889do { \ 1890 RADEON_WRITE(RS480_NB_MC_INDEX, \ 1891 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1892 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1893 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1894} while (0) 1895 1896#define RS690_WRITE_MCIND(addr, val) \ 1897do { \ 1898 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1899 RADEON_WRITE(RS690_MC_DATA, val); \ 1900 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1901} while (0) 1902 1903#define RS600_WRITE_MCIND(addr, val) \ 1904do { \ 1905 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1906 RADEON_WRITE(RS600_MC_DATA, val); \ 1907} while (0) 1908 1909#define IGP_WRITE_MCIND(addr, val) \ 1910do { \ 1911 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1912 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1913 RS690_WRITE_MCIND(addr, val); \ 1914 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1915 RS600_WRITE_MCIND(addr, val); \ 1916 else \ 1917 RS480_WRITE_MCIND(addr, val); \ 1918} while (0) 1919 1920#define CP_PACKET0( reg, n ) \ 1921 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1922#define CP_PACKET0_TABLE( reg, n ) \ 1923 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1924#define CP_PACKET1( reg0, reg1 ) \ 1925 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1926#define CP_PACKET2() \ 1927 (RADEON_CP_PACKET2) 1928#define CP_PACKET3( pkt, n ) \ 1929 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1930 1931/* ================================================================ 1932 * Engine control helper macros 1933 */ 1934 1935#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1937 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1938 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1939} while (0) 1940 1941#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1943 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1944 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1945} while (0) 1946 1947#define RADEON_WAIT_UNTIL_IDLE() do { \ 1948 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1949 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1950 RADEON_WAIT_3D_IDLECLEAN | \ 1951 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1952} while (0) 1953 1954#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1955 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1956 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1957} while (0) 1958 1959#define RADEON_FLUSH_CACHE() do { \ 1960 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1961 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1962 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1963 } else { \ 1964 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1965 OUT_RING(R300_RB3D_DC_FLUSH); \ 1966 } \ 1967} while (0) 1968 1969#define RADEON_PURGE_CACHE() do { \ 1970 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1971 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1972 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1973 } else { \ 1974 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1975 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1976 } \ 1977} while (0) 1978 1979#define RADEON_FLUSH_ZCACHE() do { \ 1980 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1981 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1982 OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1983 } else { \ 1984 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1985 OUT_RING(R300_ZC_FLUSH); \ 1986 } \ 1987} while (0) 1988 1989#define RADEON_PURGE_ZCACHE() do { \ 1990 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1991 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1992 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1993 } else { \ 1994 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1995 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1996 } \ 1997} while (0) 1998 1999/* ================================================================ 2000 * Misc helper macros 2001 */ 2002 2003/* Perfbox functionality only. 2004 */ 2005#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 2006do { \ 2007 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 2008 u32 head = GET_RING_HEAD( dev_priv ); \ 2009 if (head == dev_priv->ring.tail) \ 2010 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 2011 } \ 2012} while (0) 2013 2014#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 2015do { \ 2016 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \ 2017 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \ 2018 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 2019 int __ret; \ 2020 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 2021 __ret = r600_do_cp_idle(dev_priv); \ 2022 else \ 2023 __ret = radeon_do_cp_idle(dev_priv); \ 2024 if ( __ret ) return __ret; \ 2025 sarea_priv->last_dispatch = 0; \ 2026 radeon_freelist_reset( dev ); \ 2027 } \ 2028} while (0) 2029 2030#define RADEON_DISPATCH_AGE( age ) do { \ 2031 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 2032 OUT_RING( age ); \ 2033} while (0) 2034 2035#define RADEON_FRAME_AGE( age ) do { \ 2036 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 2037 OUT_RING( age ); \ 2038} while (0) 2039 2040#define RADEON_CLEAR_AGE( age ) do { \ 2041 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 2042 OUT_RING( age ); \ 2043} while (0) 2044 2045#define R600_DISPATCH_AGE(age) do { \ 2046 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2047 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2048 OUT_RING(age); \ 2049} while (0) 2050 2051#define R600_FRAME_AGE(age) do { \ 2052 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2053 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2054 OUT_RING(age); \ 2055} while (0) 2056 2057#define R600_CLEAR_AGE(age) do { \ 2058 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2059 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2060 OUT_RING(age); \ 2061} while (0) 2062 2063/* ================================================================ 2064 * Ring control 2065 */ 2066 2067#define RADEON_VERBOSE 0 2068 2069#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 2070 2071#define RADEON_RING_ALIGN 16 2072 2073#define BEGIN_RING( n ) do { \ 2074 if ( RADEON_VERBOSE ) { \ 2075 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 2076 } \ 2077 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \ 2078 _align_nr += n; \ 2079 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \ 2080 COMMIT_RING(); \ 2081 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \ 2082 } \ 2083 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 2084 ring = dev_priv->ring.start; \ 2085 write = dev_priv->ring.tail; \ 2086 mask = dev_priv->ring.tail_mask; \ 2087} while (0) 2088 2089#define ADVANCE_RING() do { \ 2090 if ( RADEON_VERBOSE ) { \ 2091 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 2092 write, dev_priv->ring.tail ); \ 2093 } \ 2094 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 2095 DRM_ERROR( \ 2096 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 2097 ((dev_priv->ring.tail + _nr) & mask), \ 2098 write, __LINE__); \ 2099 } else \ 2100 dev_priv->ring.tail = write; \ 2101} while (0) 2102 2103extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 2104 2105#define COMMIT_RING() do { \ 2106 radeon_commit_ring(dev_priv); \ 2107 } while(0) 2108 2109#define OUT_RING( x ) do { \ 2110 if ( RADEON_VERBOSE ) { \ 2111 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2112 (unsigned int)(x), write ); \ 2113 } \ 2114 ring[write++] = (x); \ 2115 write &= mask; \ 2116} while (0) 2117 2118#define OUT_RING_REG( reg, val ) do { \ 2119 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2120 OUT_RING( val ); \ 2121} while (0) 2122 2123#define OUT_RING_TABLE( tab, sz ) do { \ 2124 int _size = (sz); \ 2125 int *_tab = (int *)(tab); \ 2126 \ 2127 if (write + _size > mask) { \ 2128 int _i = (mask+1) - write; \ 2129 _size -= _i; \ 2130 while (_i > 0 ) { \ 2131 *(int *)(ring + write) = *_tab++; \ 2132 write++; \ 2133 _i--; \ 2134 } \ 2135 write = 0; \ 2136 _tab += _i; \ 2137 } \ 2138 while (_size > 0) { \ 2139 *(ring + write) = *_tab++; \ 2140 write++; \ 2141 _size--; \ 2142 } \ 2143 write &= mask; \ 2144} while (0) 2145 2146/** 2147 * Copy given number of dwords from drm buffer to the ring buffer. 2148 */ 2149#define OUT_RING_DRM_BUFFER(buf, sz) do { \ 2150 int _size = (sz) * 4; \ 2151 struct drm_buffer *_buf = (buf); \ 2152 int _part_size; \ 2153 while (_size > 0) { \ 2154 _part_size = _size; \ 2155 \ 2156 if (write + _part_size/4 > mask) \ 2157 _part_size = ((mask + 1) - write)*4; \ 2158 \ 2159 if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \ 2160 _part_size = PAGE_SIZE - drm_buffer_index(_buf);\ 2161 \ 2162 \ 2163 \ 2164 memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \ 2165 [drm_buffer_index(_buf)], _part_size); \ 2166 \ 2167 _size -= _part_size; \ 2168 write = (write + _part_size/4) & mask; \ 2169 drm_buffer_advance(_buf, _part_size); \ 2170 } \ 2171} while (0) 2172 2173 2174#endif /* __RADEON_DRV_H__ */ 2175