nid.h revision 261455
1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef NI_H 25#define NI_H 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/nid.h 261455 2014-02-04 03:36:42Z eadler $"); 29 30#define CAYMAN_MAX_SH_GPRS 256 31#define CAYMAN_MAX_TEMP_GPRS 16 32#define CAYMAN_MAX_SH_THREADS 256 33#define CAYMAN_MAX_SH_STACK_ENTRIES 4096 34#define CAYMAN_MAX_FRC_EOV_CNT 16384 35#define CAYMAN_MAX_BACKENDS 8 36#define CAYMAN_MAX_BACKENDS_MASK 0xFF 37#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 38#define CAYMAN_MAX_SIMDS 16 39#define CAYMAN_MAX_SIMDS_MASK 0xFFFF 40#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 41#define CAYMAN_MAX_PIPES 8 42#define CAYMAN_MAX_PIPES_MASK 0xFF 43#define CAYMAN_MAX_LDS_NUM 0xFFFF 44#define CAYMAN_MAX_TCC 16 45#define CAYMAN_MAX_TCC_MASK 0xFF 46 47#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 48#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 49 50#define DMIF_ADDR_CONFIG 0xBD4 51#define SRBM_GFX_CNTL 0x0E44 52#define RINGID(x) (((x) & 0x3) << 0) 53#define VMID(x) (((x) & 0x7) << 0) 54#define SRBM_STATUS 0x0E50 55 56#define SRBM_SOFT_RESET 0x0E60 57#define SOFT_RESET_BIF (1 << 1) 58#define SOFT_RESET_CG (1 << 2) 59#define SOFT_RESET_DC (1 << 5) 60#define SOFT_RESET_DMA1 (1 << 6) 61#define SOFT_RESET_GRBM (1 << 8) 62#define SOFT_RESET_HDP (1 << 9) 63#define SOFT_RESET_IH (1 << 10) 64#define SOFT_RESET_MC (1 << 11) 65#define SOFT_RESET_RLC (1 << 13) 66#define SOFT_RESET_ROM (1 << 14) 67#define SOFT_RESET_SEM (1 << 15) 68#define SOFT_RESET_VMC (1 << 17) 69#define SOFT_RESET_DMA (1 << 20) 70#define SOFT_RESET_TST (1 << 21) 71#define SOFT_RESET_REGBB (1 << 22) 72#define SOFT_RESET_ORB (1 << 23) 73 74#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 75#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 76#define RESPONSE_TYPE_MASK 0x000000F0 77#define RESPONSE_TYPE_SHIFT 4 78#define VM_L2_CNTL 0x1400 79#define ENABLE_L2_CACHE (1 << 0) 80#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 81#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 82#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 83#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 84#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 85/* CONTEXT1_IDENTITY_ACCESS_MODE 86 * 0 physical = logical 87 * 1 logical via context1 page table 88 * 2 inside identity aperture use translation, outside physical = logical 89 * 3 inside identity aperture physical = logical, outside use translation 90 */ 91#define VM_L2_CNTL2 0x1404 92#define INVALIDATE_ALL_L1_TLBS (1 << 0) 93#define INVALIDATE_L2_CACHE (1 << 1) 94#define VM_L2_CNTL3 0x1408 95#define BANK_SELECT(x) ((x) << 0) 96#define CACHE_UPDATE_MODE(x) ((x) << 6) 97#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 98#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 99#define VM_L2_STATUS 0x140C 100#define L2_BUSY (1 << 0) 101#define VM_CONTEXT0_CNTL 0x1410 102#define ENABLE_CONTEXT (1 << 0) 103#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 104#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 105#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 106#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 107#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 108#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 109#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 110#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 111#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 112#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 113#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 114#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 115#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 116#define VM_CONTEXT1_CNTL 0x1414 117#define VM_CONTEXT0_CNTL2 0x1430 118#define VM_CONTEXT1_CNTL2 0x1434 119#define VM_INVALIDATE_REQUEST 0x1478 120#define VM_INVALIDATE_RESPONSE 0x147c 121#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 122#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 123#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 124#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 125#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 126 127#define MC_SHARED_CHMAP 0x2004 128#define NOOFCHAN_SHIFT 12 129#define NOOFCHAN_MASK 0x00003000 130#define MC_SHARED_CHREMAP 0x2008 131 132#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 133#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 134#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 135#define MC_VM_MX_L1_TLB_CNTL 0x2064 136#define ENABLE_L1_TLB (1 << 0) 137#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 138#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 139#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 140#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 141#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 142#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 143#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 144#define FUS_MC_VM_FB_OFFSET 0x2068 145 146#define MC_SHARED_BLACKOUT_CNTL 0x20ac 147#define MC_ARB_RAMCFG 0x2760 148#define NOOFBANK_SHIFT 0 149#define NOOFBANK_MASK 0x00000003 150#define NOOFRANK_SHIFT 2 151#define NOOFRANK_MASK 0x00000004 152#define NOOFROWS_SHIFT 3 153#define NOOFROWS_MASK 0x00000038 154#define NOOFCOLS_SHIFT 6 155#define NOOFCOLS_MASK 0x000000C0 156#define CHANSIZE_SHIFT 8 157#define CHANSIZE_MASK 0x00000100 158#define BURSTLENGTH_SHIFT 9 159#define BURSTLENGTH_MASK 0x00000200 160#define CHANSIZE_OVERRIDE (1 << 11) 161#define MC_SEQ_SUP_CNTL 0x28c8 162#define RUN_MASK (1 << 0) 163#define MC_SEQ_SUP_PGM 0x28cc 164#define MC_IO_PAD_CNTL_D0 0x29d0 165#define MEM_FALL_OUT_CMD (1 << 8) 166#define MC_SEQ_MISC0 0x2a00 167#define MC_SEQ_MISC0_GDDR5_SHIFT 28 168#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 169#define MC_SEQ_MISC0_GDDR5_VALUE 5 170#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 171#define MC_SEQ_IO_DEBUG_DATA 0x2a48 172 173#define HDP_HOST_PATH_CNTL 0x2C00 174#define HDP_NONSURFACE_BASE 0x2C04 175#define HDP_NONSURFACE_INFO 0x2C08 176#define HDP_NONSURFACE_SIZE 0x2C0C 177#define HDP_ADDR_CONFIG 0x2F48 178#define HDP_MISC_CNTL 0x2F4C 179#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 180 181#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 182#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 183#define CGTS_SYS_TCC_DISABLE 0x3F90 184#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 185 186#define RLC_GFX_INDEX 0x3FC4 187 188#define CONFIG_MEMSIZE 0x5428 189 190#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 191#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 192 193#define GRBM_CNTL 0x8000 194#define GRBM_READ_TIMEOUT(x) ((x) << 0) 195#define GRBM_STATUS 0x8010 196#define CMDFIFO_AVAIL_MASK 0x0000000F 197#define RING2_RQ_PENDING (1 << 4) 198#define SRBM_RQ_PENDING (1 << 5) 199#define RING1_RQ_PENDING (1 << 6) 200#define CF_RQ_PENDING (1 << 7) 201#define PF_RQ_PENDING (1 << 8) 202#define GDS_DMA_RQ_PENDING (1 << 9) 203#define GRBM_EE_BUSY (1 << 10) 204#define SX_CLEAN (1 << 11) 205#define DB_CLEAN (1 << 12) 206#define CB_CLEAN (1 << 13) 207#define TA_BUSY (1 << 14) 208#define GDS_BUSY (1 << 15) 209#define VGT_BUSY_NO_DMA (1 << 16) 210#define VGT_BUSY (1 << 17) 211#define IA_BUSY_NO_DMA (1 << 18) 212#define IA_BUSY (1 << 19) 213#define SX_BUSY (1 << 20) 214#define SH_BUSY (1 << 21) 215#define SPI_BUSY (1 << 22) 216#define SC_BUSY (1 << 24) 217#define PA_BUSY (1 << 25) 218#define DB_BUSY (1 << 26) 219#define CP_COHERENCY_BUSY (1 << 28) 220#define CP_BUSY (1 << 29) 221#define CB_BUSY (1 << 30) 222#define GUI_ACTIVE (1U << 31) 223#define GRBM_STATUS_SE0 0x8014 224#define GRBM_STATUS_SE1 0x8018 225#define SE_SX_CLEAN (1 << 0) 226#define SE_DB_CLEAN (1 << 1) 227#define SE_CB_CLEAN (1 << 2) 228#define SE_VGT_BUSY (1 << 23) 229#define SE_PA_BUSY (1 << 24) 230#define SE_TA_BUSY (1 << 25) 231#define SE_SX_BUSY (1 << 26) 232#define SE_SPI_BUSY (1 << 27) 233#define SE_SH_BUSY (1 << 28) 234#define SE_SC_BUSY (1 << 29) 235#define SE_DB_BUSY (1 << 30) 236#define SE_CB_BUSY (1U << 31) 237#define GRBM_SOFT_RESET 0x8020 238#define SOFT_RESET_CP (1 << 0) 239#define SOFT_RESET_CB (1 << 1) 240#define SOFT_RESET_DB (1 << 3) 241#define SOFT_RESET_GDS (1 << 4) 242#define SOFT_RESET_PA (1 << 5) 243#define SOFT_RESET_SC (1 << 6) 244#define SOFT_RESET_SPI (1 << 8) 245#define SOFT_RESET_SH (1 << 9) 246#define SOFT_RESET_SX (1 << 10) 247#define SOFT_RESET_TC (1 << 11) 248#define SOFT_RESET_TA (1 << 12) 249#define SOFT_RESET_VGT (1 << 14) 250#define SOFT_RESET_IA (1 << 15) 251 252#define GRBM_GFX_INDEX 0x802C 253#define INSTANCE_INDEX(x) ((x) << 0) 254#define SE_INDEX(x) ((x) << 16) 255#define INSTANCE_BROADCAST_WRITES (1 << 30) 256#define SE_BROADCAST_WRITES (1U << 31) 257 258#define SCRATCH_REG0 0x8500 259#define SCRATCH_REG1 0x8504 260#define SCRATCH_REG2 0x8508 261#define SCRATCH_REG3 0x850C 262#define SCRATCH_REG4 0x8510 263#define SCRATCH_REG5 0x8514 264#define SCRATCH_REG6 0x8518 265#define SCRATCH_REG7 0x851C 266#define SCRATCH_UMSK 0x8540 267#define SCRATCH_ADDR 0x8544 268#define CP_SEM_WAIT_TIMER 0x85BC 269#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 270#define CP_COHER_CNTL2 0x85E8 271#define CP_STALLED_STAT1 0x8674 272#define CP_STALLED_STAT2 0x8678 273#define CP_BUSY_STAT 0x867C 274#define CP_STAT 0x8680 275#define CP_ME_CNTL 0x86D8 276#define CP_ME_HALT (1 << 28) 277#define CP_PFP_HALT (1 << 26) 278#define CP_RB2_RPTR 0x86f8 279#define CP_RB1_RPTR 0x86fc 280#define CP_RB0_RPTR 0x8700 281#define CP_RB_WPTR_DELAY 0x8704 282#define CP_MEQ_THRESHOLDS 0x8764 283#define MEQ1_START(x) ((x) << 0) 284#define MEQ2_START(x) ((x) << 8) 285#define CP_PERFMON_CNTL 0x87FC 286 287#define VGT_CACHE_INVALIDATION 0x88C4 288#define CACHE_INVALIDATION(x) ((x) << 0) 289#define VC_ONLY 0 290#define TC_ONLY 1 291#define VC_AND_TC 2 292#define AUTO_INVLD_EN(x) ((x) << 6) 293#define NO_AUTO 0 294#define ES_AUTO 1 295#define GS_AUTO 2 296#define ES_AND_GS_AUTO 3 297#define VGT_GS_VERTEX_REUSE 0x88D4 298 299#define CC_GC_SHADER_PIPE_CONFIG 0x8950 300#define GC_USER_SHADER_PIPE_CONFIG 0x8954 301#define INACTIVE_QD_PIPES(x) ((x) << 8) 302#define INACTIVE_QD_PIPES_MASK 0x0000FF00 303#define INACTIVE_QD_PIPES_SHIFT 8 304#define INACTIVE_SIMDS(x) ((x) << 16) 305#define INACTIVE_SIMDS_MASK 0xFFFF0000 306#define INACTIVE_SIMDS_SHIFT 16 307 308#define VGT_PRIMITIVE_TYPE 0x8958 309#define VGT_NUM_INSTANCES 0x8974 310#define VGT_TF_RING_SIZE 0x8988 311#define VGT_OFFCHIP_LDS_BASE 0x89b4 312 313#define PA_SC_LINE_STIPPLE_STATE 0x8B10 314#define PA_CL_ENHANCE 0x8A14 315#define CLIP_VTX_REORDER_ENA (1 << 0) 316#define NUM_CLIP_SEQ(x) ((x) << 1) 317#define PA_SC_FIFO_SIZE 0x8BCC 318#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 319#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 320#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 321#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 322#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 323#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 324 325#define SQ_CONFIG 0x8C00 326#define VC_ENABLE (1 << 0) 327#define EXPORT_SRC_C (1 << 1) 328#define GFX_PRIO(x) ((x) << 2) 329#define CS1_PRIO(x) ((x) << 4) 330#define CS2_PRIO(x) ((x) << 6) 331#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 332#define NUM_PS_GPRS(x) ((x) << 0) 333#define NUM_VS_GPRS(x) ((x) << 16) 334#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 335#define SQ_ESGS_RING_SIZE 0x8c44 336#define SQ_GSVS_RING_SIZE 0x8c4c 337#define SQ_ESTMP_RING_BASE 0x8c50 338#define SQ_ESTMP_RING_SIZE 0x8c54 339#define SQ_GSTMP_RING_BASE 0x8c58 340#define SQ_GSTMP_RING_SIZE 0x8c5c 341#define SQ_VSTMP_RING_BASE 0x8c60 342#define SQ_VSTMP_RING_SIZE 0x8c64 343#define SQ_PSTMP_RING_BASE 0x8c68 344#define SQ_PSTMP_RING_SIZE 0x8c6c 345#define SQ_MS_FIFO_SIZES 0x8CF0 346#define CACHE_FIFO_SIZE(x) ((x) << 0) 347#define FETCH_FIFO_HIWATER(x) ((x) << 8) 348#define DONE_FIFO_HIWATER(x) ((x) << 16) 349#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 350#define SQ_LSTMP_RING_BASE 0x8e10 351#define SQ_LSTMP_RING_SIZE 0x8e14 352#define SQ_HSTMP_RING_BASE 0x8e18 353#define SQ_HSTMP_RING_SIZE 0x8e1c 354#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 355#define DYN_GPR_ENABLE (1 << 8) 356#define SQ_CONST_MEM_BASE 0x8df8 357 358#define SX_EXPORT_BUFFER_SIZES 0x900C 359#define COLOR_BUFFER_SIZE(x) ((x) << 0) 360#define POSITION_BUFFER_SIZE(x) ((x) << 8) 361#define SMX_BUFFER_SIZE(x) ((x) << 16) 362#define SX_DEBUG_1 0x9058 363#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 364 365#define SPI_CONFIG_CNTL 0x9100 366#define GPR_WRITE_PRIORITY(x) ((x) << 0) 367#define SPI_CONFIG_CNTL_1 0x913C 368#define VTX_DONE_DELAY(x) ((x) << 0) 369#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 370#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 371 372#define CGTS_TCC_DISABLE 0x9148 373#define CGTS_USER_TCC_DISABLE 0x914C 374#define TCC_DISABLE_MASK 0xFFFF0000 375#define TCC_DISABLE_SHIFT 16 376#define CGTS_SM_CTRL_REG 0x9150 377#define OVERRIDE (1 << 21) 378 379#define TA_CNTL_AUX 0x9508 380#define DISABLE_CUBE_WRAP (1 << 0) 381#define DISABLE_CUBE_ANISO (1 << 1) 382 383#define TCP_CHAN_STEER_LO 0x960c 384#define TCP_CHAN_STEER_HI 0x9610 385 386#define CC_RB_BACKEND_DISABLE 0x98F4 387#define BACKEND_DISABLE(x) ((x) << 16) 388#define GB_ADDR_CONFIG 0x98F8 389#define NUM_PIPES(x) ((x) << 0) 390#define NUM_PIPES_MASK 0x00000007 391#define NUM_PIPES_SHIFT 0 392#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 393#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 394#define PIPE_INTERLEAVE_SIZE_SHIFT 4 395#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 396#define NUM_SHADER_ENGINES(x) ((x) << 12) 397#define NUM_SHADER_ENGINES_MASK 0x00003000 398#define NUM_SHADER_ENGINES_SHIFT 12 399#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 400#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 401#define SHADER_ENGINE_TILE_SIZE_SHIFT 16 402#define NUM_GPUS(x) ((x) << 20) 403#define NUM_GPUS_MASK 0x00700000 404#define NUM_GPUS_SHIFT 20 405#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 406#define MULTI_GPU_TILE_SIZE_MASK 0x03000000 407#define MULTI_GPU_TILE_SIZE_SHIFT 24 408#define ROW_SIZE(x) ((x) << 28) 409#define ROW_SIZE_MASK 0x30000000 410#define ROW_SIZE_SHIFT 28 411#define NUM_LOWER_PIPES(x) ((x) << 30) 412#define NUM_LOWER_PIPES_MASK 0x40000000 413#define NUM_LOWER_PIPES_SHIFT 30 414#define GB_BACKEND_MAP 0x98FC 415 416#define CB_PERF_CTR0_SEL_0 0x9A20 417#define CB_PERF_CTR0_SEL_1 0x9A24 418#define CB_PERF_CTR1_SEL_0 0x9A28 419#define CB_PERF_CTR1_SEL_1 0x9A2C 420#define CB_PERF_CTR2_SEL_0 0x9A30 421#define CB_PERF_CTR2_SEL_1 0x9A34 422#define CB_PERF_CTR3_SEL_0 0x9A38 423#define CB_PERF_CTR3_SEL_1 0x9A3C 424 425#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 426#define BACKEND_DISABLE_MASK 0x00FF0000 427#define BACKEND_DISABLE_SHIFT 16 428 429#define SMX_DC_CTL0 0xA020 430#define USE_HASH_FUNCTION (1 << 0) 431#define NUMBER_OF_SETS(x) ((x) << 1) 432#define FLUSH_ALL_ON_EVENT (1 << 10) 433#define STALL_ON_EVENT (1 << 11) 434#define SMX_EVENT_CTL 0xA02C 435#define ES_FLUSH_CTL(x) ((x) << 0) 436#define GS_FLUSH_CTL(x) ((x) << 3) 437#define ACK_FLUSH_CTL(x) ((x) << 6) 438#define SYNC_FLUSH_CTL (1 << 8) 439 440#define CP_RB0_BASE 0xC100 441#define CP_RB0_CNTL 0xC104 442#define RB_BUFSZ(x) ((x) << 0) 443#define RB_BLKSZ(x) ((x) << 8) 444#define RB_NO_UPDATE (1 << 27) 445#define RB_RPTR_WR_ENA (1U << 31) 446#define BUF_SWAP_32BIT (2 << 16) 447#define CP_RB0_RPTR_ADDR 0xC10C 448#define CP_RB0_RPTR_ADDR_HI 0xC110 449#define CP_RB0_WPTR 0xC114 450 451#define CP_INT_CNTL 0xC124 452# define CNTX_BUSY_INT_ENABLE (1 << 19) 453# define CNTX_EMPTY_INT_ENABLE (1 << 20) 454# define TIME_STAMP_INT_ENABLE (1 << 26) 455 456#define CP_RB1_BASE 0xC180 457#define CP_RB1_CNTL 0xC184 458#define CP_RB1_RPTR_ADDR 0xC188 459#define CP_RB1_RPTR_ADDR_HI 0xC18C 460#define CP_RB1_WPTR 0xC190 461#define CP_RB2_BASE 0xC194 462#define CP_RB2_CNTL 0xC198 463#define CP_RB2_RPTR_ADDR 0xC19C 464#define CP_RB2_RPTR_ADDR_HI 0xC1A0 465#define CP_RB2_WPTR 0xC1A4 466#define CP_PFP_UCODE_ADDR 0xC150 467#define CP_PFP_UCODE_DATA 0xC154 468#define CP_ME_RAM_RADDR 0xC158 469#define CP_ME_RAM_WADDR 0xC15C 470#define CP_ME_RAM_DATA 0xC160 471#define CP_DEBUG 0xC1FC 472 473#define VGT_EVENT_INITIATOR 0x28a90 474# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 475# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 476 477/* 478 * PM4 479 */ 480#define PACKET_TYPE0 0 481#define PACKET_TYPE1 1 482#define PACKET_TYPE2 2 483#define PACKET_TYPE3 3 484 485#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 486#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 487#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 488#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 489#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 490 (((reg) >> 2) & 0xFFFF) | \ 491 ((n) & 0x3FFF) << 16) 492#define CP_PACKET2 0x80000000 493#define PACKET2_PAD_SHIFT 0 494#define PACKET2_PAD_MASK (0x3fffffff << 0) 495 496#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 497 498#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 499 (((op) & 0xFF) << 8) | \ 500 ((n) & 0x3FFF) << 16) 501 502/* Packet 3 types */ 503#define PACKET3_NOP 0x10 504#define PACKET3_SET_BASE 0x11 505#define PACKET3_CLEAR_STATE 0x12 506#define PACKET3_INDEX_BUFFER_SIZE 0x13 507#define PACKET3_DEALLOC_STATE 0x14 508#define PACKET3_DISPATCH_DIRECT 0x15 509#define PACKET3_DISPATCH_INDIRECT 0x16 510#define PACKET3_INDIRECT_BUFFER_END 0x17 511#define PACKET3_MODE_CONTROL 0x18 512#define PACKET3_SET_PREDICATION 0x20 513#define PACKET3_REG_RMW 0x21 514#define PACKET3_COND_EXEC 0x22 515#define PACKET3_PRED_EXEC 0x23 516#define PACKET3_DRAW_INDIRECT 0x24 517#define PACKET3_DRAW_INDEX_INDIRECT 0x25 518#define PACKET3_INDEX_BASE 0x26 519#define PACKET3_DRAW_INDEX_2 0x27 520#define PACKET3_CONTEXT_CONTROL 0x28 521#define PACKET3_DRAW_INDEX_OFFSET 0x29 522#define PACKET3_INDEX_TYPE 0x2A 523#define PACKET3_DRAW_INDEX 0x2B 524#define PACKET3_DRAW_INDEX_AUTO 0x2D 525#define PACKET3_DRAW_INDEX_IMMD 0x2E 526#define PACKET3_NUM_INSTANCES 0x2F 527#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 528#define PACKET3_INDIRECT_BUFFER 0x32 529#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 530#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 531#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 532#define PACKET3_WRITE_DATA 0x37 533#define PACKET3_MEM_SEMAPHORE 0x39 534#define PACKET3_MPEG_INDEX 0x3A 535#define PACKET3_WAIT_REG_MEM 0x3C 536#define PACKET3_MEM_WRITE 0x3D 537#define PACKET3_PFP_SYNC_ME 0x42 538#define PACKET3_SURFACE_SYNC 0x43 539# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 540# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 541# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 542# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 543# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 544# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 545# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 546# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 547# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 548# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 549# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 550# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 551# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 552# define PACKET3_FULL_CACHE_ENA (1 << 20) 553# define PACKET3_TC_ACTION_ENA (1 << 23) 554# define PACKET3_CB_ACTION_ENA (1 << 25) 555# define PACKET3_DB_ACTION_ENA (1 << 26) 556# define PACKET3_SH_ACTION_ENA (1 << 27) 557# define PACKET3_SX_ACTION_ENA (1 << 28) 558#define PACKET3_ME_INITIALIZE 0x44 559#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 560#define PACKET3_COND_WRITE 0x45 561#define PACKET3_EVENT_WRITE 0x46 562#define EVENT_TYPE(x) ((x) << 0) 563#define EVENT_INDEX(x) ((x) << 8) 564 /* 0 - any non-TS event 565 * 1 - ZPASS_DONE 566 * 2 - SAMPLE_PIPELINESTAT 567 * 3 - SAMPLE_STREAMOUTSTAT* 568 * 4 - *S_PARTIAL_FLUSH 569 * 5 - TS events 570 */ 571#define PACKET3_EVENT_WRITE_EOP 0x47 572#define DATA_SEL(x) ((x) << 29) 573 /* 0 - discard 574 * 1 - send low 32bit data 575 * 2 - send 64bit data 576 * 3 - send 64bit counter value 577 */ 578#define INT_SEL(x) ((x) << 24) 579 /* 0 - none 580 * 1 - interrupt only (DATA_SEL = 0) 581 * 2 - interrupt when data write is confirmed 582 */ 583#define PACKET3_EVENT_WRITE_EOS 0x48 584#define PACKET3_PREAMBLE_CNTL 0x4A 585# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 586# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 587#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 588#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 589#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 590#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 591#define PACKET3_ONE_REG_WRITE 0x57 592#define PACKET3_SET_CONFIG_REG 0x68 593#define PACKET3_SET_CONFIG_REG_START 0x00008000 594#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 595#define PACKET3_SET_CONTEXT_REG 0x69 596#define PACKET3_SET_CONTEXT_REG_START 0x00028000 597#define PACKET3_SET_CONTEXT_REG_END 0x00029000 598#define PACKET3_SET_ALU_CONST 0x6A 599/* alu const buffers only; no reg file */ 600#define PACKET3_SET_BOOL_CONST 0x6B 601#define PACKET3_SET_BOOL_CONST_START 0x0003a500 602#define PACKET3_SET_BOOL_CONST_END 0x0003a518 603#define PACKET3_SET_LOOP_CONST 0x6C 604#define PACKET3_SET_LOOP_CONST_START 0x0003a200 605#define PACKET3_SET_LOOP_CONST_END 0x0003a500 606#define PACKET3_SET_RESOURCE 0x6D 607#define PACKET3_SET_RESOURCE_START 0x00030000 608#define PACKET3_SET_RESOURCE_END 0x00038000 609#define PACKET3_SET_SAMPLER 0x6E 610#define PACKET3_SET_SAMPLER_START 0x0003c000 611#define PACKET3_SET_SAMPLER_END 0x0003c600 612#define PACKET3_SET_CTL_CONST 0x6F 613#define PACKET3_SET_CTL_CONST_START 0x0003cff0 614#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 615#define PACKET3_SET_RESOURCE_OFFSET 0x70 616#define PACKET3_SET_ALU_CONST_VS 0x71 617#define PACKET3_SET_ALU_CONST_DI 0x72 618#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 619#define PACKET3_SET_RESOURCE_INDIRECT 0x74 620#define PACKET3_SET_APPEND_CNT 0x75 621#define PACKET3_ME_WRITE 0x7A 622 623/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 624#define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 625#define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 626 627#define DMA_RB_CNTL 0xd000 628# define DMA_RB_ENABLE (1 << 0) 629# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 630# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 631# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 632# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 633# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 634#define DMA_RB_BASE 0xd004 635#define DMA_RB_RPTR 0xd008 636#define DMA_RB_WPTR 0xd00c 637 638#define DMA_RB_RPTR_ADDR_HI 0xd01c 639#define DMA_RB_RPTR_ADDR_LO 0xd020 640 641#define DMA_IB_CNTL 0xd024 642# define DMA_IB_ENABLE (1 << 0) 643# define DMA_IB_SWAP_ENABLE (1 << 4) 644# define CMD_VMID_FORCE (1U << 31) 645#define DMA_IB_RPTR 0xd028 646#define DMA_CNTL 0xd02c 647# define TRAP_ENABLE (1 << 0) 648# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 649# define SEM_WAIT_INT_ENABLE (1 << 2) 650# define DATA_SWAP_ENABLE (1 << 3) 651# define FENCE_SWAP_ENABLE (1 << 4) 652# define CTXEMPTY_INT_ENABLE (1 << 28) 653#define DMA_STATUS_REG 0xd034 654# define DMA_IDLE (1 << 0) 655#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 656#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 657#define DMA_TILING_CONFIG 0xd0b8 658#define DMA_MODE 0xd0bc 659 660#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 661 (((t) & 0x1) << 23) | \ 662 (((s) & 0x1) << 22) | \ 663 (((n) & 0xFFFFF) << 0)) 664 665#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 666 (((vmid) & 0xF) << 20) | \ 667 (((n) & 0xFFFFF) << 0)) 668 669/* async DMA Packet types */ 670#define DMA_PACKET_WRITE 0x2 671#define DMA_PACKET_COPY 0x3 672#define DMA_PACKET_INDIRECT_BUFFER 0x4 673#define DMA_PACKET_SEMAPHORE 0x5 674#define DMA_PACKET_FENCE 0x6 675#define DMA_PACKET_TRAP 0x7 676#define DMA_PACKET_SRBM_WRITE 0x9 677#define DMA_PACKET_CONSTANT_FILL 0xd 678#define DMA_PACKET_NOP 0xf 679 680#endif 681