1/*
2 * $FreeBSD$
3 */
4
5#ifndef _INTEL_RINGBUFFER_H_
6#define _INTEL_RINGBUFFER_H_
7
8struct  intel_hw_status_page {
9	u32		*page_addr;
10	unsigned int	gfx_addr;
11	struct		drm_i915_gem_object *obj;
12};
13
14#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
15#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
16
17#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
18#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
19
20#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
21#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
22
23#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
24#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
25
26#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
27#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
28
29#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
30#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
31#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
32
33struct  intel_ring_buffer {
34	const char	*name;
35	enum intel_ring_id {
36		RCS = 0x0,
37		VCS,
38		BCS,
39	} id;
40#define I915_NUM_RINGS 3
41	u32		mmio_base;
42	void		*virtual_start;
43	struct		drm_device *dev;
44	struct		drm_i915_gem_object *obj;
45
46	u32		head;
47	u32		tail;
48	int		space;
49	int		size;
50	int		effective_size;
51	struct intel_hw_status_page status_page;
52
53	/** We track the position of the requests in the ring buffer, and
54	 * when each is retired we increment last_retired_head as the GPU
55	 * must have finished processing the request and so we know we
56	 * can advance the ringbuffer up to that position.
57	 *
58	 * last_retired_head is set to -1 after the value is consumed so
59	 * we can detect new retirements.
60	 */
61	u32		last_retired_head;
62
63	u32		irq_refcount;
64	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
65	u32		trace_irq_seqno;
66	u32		sync_seqno[I915_NUM_RINGS-1];
67	bool		(*irq_get)(struct intel_ring_buffer *ring);
68	void		(*irq_put)(struct intel_ring_buffer *ring);
69
70	int		(*init)(struct intel_ring_buffer *ring);
71
72	void		(*write_tail)(struct intel_ring_buffer *ring,
73				      uint32_t value);
74	int		(*flush)(struct intel_ring_buffer *ring,
75				  uint32_t	invalidate_domains,
76				  uint32_t	flush_domains);
77	int		(*add_request)(struct intel_ring_buffer *ring,
78				       uint32_t *seqno);
79	uint32_t	(*get_seqno)(struct intel_ring_buffer *ring);
80	int		(*dispatch_execbuffer)(struct intel_ring_buffer *ring,
81					       uint32_t offset, uint32_t length);
82	void		(*cleanup)(struct intel_ring_buffer *ring);
83	int		(*sync_to)(struct intel_ring_buffer *ring,
84				   struct intel_ring_buffer *to,
85				   u32 seqno);
86
87	u32		semaphore_register[3]; /*our mbox written by others */
88	u32		signal_mbox[2]; /* mboxes this ring signals to */
89
90	/**
91	 * List of objects currently involved in rendering from the
92	 * ringbuffer.
93	 *
94	 * Includes buffers having the contents of their GPU caches
95	 * flushed, not necessarily primitives.  last_rendering_seqno
96	 * represents when the rendering involved will be completed.
97	 *
98	 * A reference is held on the buffer while on this list.
99	 */
100	struct list_head active_list;
101
102	/**
103	 * List of breadcrumbs associated with GPU requests currently
104	 * outstanding.
105	 */
106	struct list_head request_list;
107
108	/**
109	 * List of objects currently pending a GPU write flush.
110	 *
111	 * All elements on this list will belong to either the
112	 * active_list or flushing_list, last_rendering_seqno can
113	 * be used to differentiate between the two elements.
114	 */
115	struct list_head gpu_write_list;
116
117	/**
118	 * Do we have some not yet emitted requests outstanding?
119	 */
120	u32 outstanding_lazy_request;
121
122	/**
123	 * Do an explicit TLB flush before MI_SET_CONTEXT
124	 */
125	bool itlb_before_ctx_switch;
126	struct i915_hw_context *default_context;
127	struct drm_i915_gem_object *last_context_obj;
128
129	drm_local_map_t map;
130
131	void *private;
132};
133
134static inline bool
135intel_ring_initialized(struct intel_ring_buffer *ring)
136{
137	return ring->obj != NULL;
138}
139
140static inline unsigned
141intel_ring_flag(struct intel_ring_buffer *ring)
142{
143	return 1 << ring->id;
144}
145
146static inline uint32_t
147intel_ring_sync_index(struct intel_ring_buffer *ring,
148		      struct intel_ring_buffer *other)
149{
150	int idx;
151
152	/*
153	 * cs -> 0 = vcs, 1 = bcs
154	 * vcs -> 0 = bcs, 1 = cs,
155	 * bcs -> 0 = cs, 1 = vcs.
156	 */
157
158	idx = (other - ring) - 1;
159	if (idx < 0)
160		idx += I915_NUM_RINGS;
161
162	return idx;
163}
164
165static inline uint32_t
166intel_read_status_page(struct intel_ring_buffer *ring, int reg)
167{
168
169	/* Ensure that the compiler doesn't optimize away the load. */
170	__compiler_membar();
171	return (atomic_load_acq_32(ring->status_page.page_addr + reg));
172}
173
174void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
175
176int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
177static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
178{
179
180	return (intel_wait_ring_buffer(ring, ring->size - 8));
181}
182
183int intel_ring_begin(struct intel_ring_buffer *ring, int n);
184
185static inline void intel_ring_emit(struct intel_ring_buffer *ring,
186				   uint32_t data)
187{
188	*(volatile uint32_t *)((char *)ring->virtual_start +
189	    ring->tail) = data;
190	ring->tail += 4;
191}
192
193void intel_ring_advance(struct intel_ring_buffer *ring);
194
195uint32_t intel_ring_get_seqno(struct intel_ring_buffer *ring);
196
197int intel_init_render_ring_buffer(struct drm_device *dev);
198int intel_init_bsd_ring_buffer(struct drm_device *dev);
199int intel_init_blt_ring_buffer(struct drm_device *dev);
200
201u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
202void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
203
204static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
205{
206	return ring->tail;
207}
208
209void i915_trace_irq_get(struct intel_ring_buffer *ring, uint32_t seqno);
210
211/* DRI warts */
212int intel_render_ring_init_dri(struct drm_device *dev, uint64_t start,
213    uint32_t size);
214
215#endif /* _INTEL_RINGBUFFER_H_ */
216