1/*- 2 * Copyright (c) 2012-2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t4fw_interface.h 353418 2019-10-10 23:27:02Z np $ 27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37enum fw_retval { 38 FW_SUCCESS = 0, /* completed sucessfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */ 77}; 78 79/****************************************************************************** 80 * M E M O R Y T Y P E s 81 ******************************/ 82 83enum fw_memtype { 84 FW_MEMTYPE_EDC0 = 0x0, 85 FW_MEMTYPE_EDC1 = 0x1, 86 FW_MEMTYPE_EXTMEM = 0x2, 87 FW_MEMTYPE_FLASH = 0x4, 88 FW_MEMTYPE_INTERNAL = 0x5, 89 FW_MEMTYPE_EXTMEM1 = 0x6, 90 FW_MEMTYPE_HMA = 0x7, 91}; 92 93/****************************************************************************** 94 * W O R K R E Q U E S T s 95 ********************************/ 96 97enum fw_wr_opcodes { 98 FW_FRAG_WR = 0x1d, 99 FW_FILTER_WR = 0x02, 100 FW_ULPTX_WR = 0x04, 101 FW_TP_WR = 0x05, 102 FW_ETH_TX_PKT_WR = 0x08, 103 FW_ETH_TX_PKT2_WR = 0x44, 104 FW_ETH_TX_PKTS_WR = 0x09, 105 FW_ETH_TX_PKTS2_WR = 0x78, 106 FW_ETH_TX_EO_WR = 0x1c, 107 FW_EQ_FLUSH_WR = 0x1b, 108 FW_OFLD_CONNECTION_WR = 0x2f, 109 FW_FLOWC_WR = 0x0a, 110 FW_OFLD_TX_DATA_WR = 0x0b, 111 FW_CMD_WR = 0x10, 112 FW_ETH_TX_PKT_VM_WR = 0x11, 113 FW_ETH_TX_PKTS_VM_WR = 0x12, 114 FW_RI_RES_WR = 0x0c, 115 FW_RI_RDMA_WRITE_WR = 0x14, 116 FW_RI_SEND_WR = 0x15, 117 FW_RI_RDMA_READ_WR = 0x16, 118 FW_RI_RECV_WR = 0x17, 119 FW_RI_BIND_MW_WR = 0x18, 120 FW_RI_FR_NSMR_WR = 0x19, 121 FW_RI_FR_NSMR_TPTE_WR = 0x20, 122 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 123 FW_RI_INV_LSTAG_WR = 0x1a, 124 FW_RI_SEND_IMMEDIATE_WR = 0x15, 125 FW_RI_ATOMIC_WR = 0x16, 126 FW_RI_WR = 0x0d, 127 FW_CHNET_IFCONF_WR = 0x6b, 128 FW_RDEV_WR = 0x38, 129 FW_FOISCSI_NODE_WR = 0x60, 130 FW_FOISCSI_CTRL_WR = 0x6a, 131 FW_FOISCSI_CHAP_WR = 0x6c, 132 FW_FCOE_ELS_CT_WR = 0x30, 133 FW_SCSI_WRITE_WR = 0x31, 134 FW_SCSI_READ_WR = 0x32, 135 FW_SCSI_CMD_WR = 0x33, 136 FW_SCSI_ABRT_CLS_WR = 0x34, 137 FW_SCSI_TGT_ACC_WR = 0x35, 138 FW_SCSI_TGT_XMIT_WR = 0x36, 139 FW_SCSI_TGT_RSP_WR = 0x37, 140 FW_POFCOE_TCB_WR = 0x42, 141 FW_POFCOE_ULPTX_WR = 0x43, 142 FW_ISCSI_TX_DATA_WR = 0x45, 143 FW_PTP_TX_PKT_WR = 0x46, 144 FW_TLSTX_DATA_WR = 0x68, 145 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 146 FW_COISCSI_TGT_WR = 0x70, 147 FW_COISCSI_TGT_CONN_WR = 0x71, 148 FW_COISCSI_TGT_XMIT_WR = 0x72, 149 FW_COISCSI_STATS_WR = 0x73, 150 FW_ISNS_WR = 0x75, 151 FW_ISNS_XMIT_WR = 0x76, 152 FW_FILTER2_WR = 0x77, 153 FW_LASTC2E_WR = 0x80 154}; 155 156/* 157 * Generic work request header flit0 158 */ 159struct fw_wr_hdr { 160 __be32 hi; 161 __be32 lo; 162}; 163 164/* work request opcode (hi) 165 */ 166#define S_FW_WR_OP 24 167#define M_FW_WR_OP 0xff 168#define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 169#define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 170 171/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 172 */ 173#define S_FW_WR_ATOMIC 23 174#define M_FW_WR_ATOMIC 0x1 175#define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 176#define G_FW_WR_ATOMIC(x) \ 177 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 178#define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 179 180/* flush flag (hi) - firmware flushes flushable work request buffered 181 * in the flow context. 182 */ 183#define S_FW_WR_FLUSH 22 184#define M_FW_WR_FLUSH 0x1 185#define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 186#define G_FW_WR_FLUSH(x) \ 187 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 188#define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 189 190/* completion flag (hi) - firmware generates a cpl_fw6_ack 191 */ 192#define S_FW_WR_COMPL 21 193#define M_FW_WR_COMPL 0x1 194#define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 195#define G_FW_WR_COMPL(x) \ 196 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 197#define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 198 199 200/* work request immediate data lengh (hi) 201 */ 202#define S_FW_WR_IMMDLEN 0 203#define M_FW_WR_IMMDLEN 0xff 204#define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 205#define G_FW_WR_IMMDLEN(x) \ 206 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 207 208/* egress queue status update to associated ingress queue entry (lo) 209 */ 210#define S_FW_WR_EQUIQ 31 211#define M_FW_WR_EQUIQ 0x1 212#define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 213#define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 214#define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 215 216/* egress queue status update to egress queue status entry (lo) 217 */ 218#define S_FW_WR_EQUEQ 30 219#define M_FW_WR_EQUEQ 0x1 220#define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 221#define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 222#define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 223 224/* flow context identifier (lo) 225 */ 226#define S_FW_WR_FLOWID 8 227#define M_FW_WR_FLOWID 0xfffff 228#define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 229#define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 230 231/* length in units of 16-bytes (lo) 232 */ 233#define S_FW_WR_LEN16 0 234#define M_FW_WR_LEN16 0xff 235#define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 236#define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 237 238struct fw_frag_wr { 239 __be32 op_to_fragoff16; 240 __be32 flowid_len16; 241 __be64 r4; 242}; 243 244#define S_FW_FRAG_WR_EOF 15 245#define M_FW_FRAG_WR_EOF 0x1 246#define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 247#define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 248#define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 249 250#define S_FW_FRAG_WR_FRAGOFF16 8 251#define M_FW_FRAG_WR_FRAGOFF16 0x7f 252#define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 253#define G_FW_FRAG_WR_FRAGOFF16(x) \ 254 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 255 256/* valid filter configurations for compressed tuple 257 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 258 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 259 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 260 * OV - Outer VLAN/VNIC_ID, 261*/ 262#define HW_TPL_FR_MT_M_E_P_FC 0x3C3 263#define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 264#define HW_TPL_FR_MT_M_IV_P_FC 0x38B 265#define HW_TPL_FR_MT_M_OV_P_FC 0x387 266#define HW_TPL_FR_MT_E_PR_T 0x370 267#define HW_TPL_FR_MT_E_PR_P_FC 0X363 268#define HW_TPL_FR_MT_E_T_P_FC 0X353 269#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 270#define HW_TPL_FR_MT_PR_OV_P_FC 0X327 271#define HW_TPL_FR_MT_T_IV_P_FC 0X31B 272#define HW_TPL_FR_MT_T_OV_P_FC 0X317 273#define HW_TPL_FR_M_E_PR_FC 0X2E1 274#define HW_TPL_FR_M_E_T_FC 0X2D1 275#define HW_TPL_FR_M_PR_IV_FC 0X2A9 276#define HW_TPL_FR_M_PR_OV_FC 0X2A5 277#define HW_TPL_FR_M_T_IV_FC 0X299 278#define HW_TPL_FR_M_T_OV_FC 0X295 279#define HW_TPL_FR_E_PR_T_P 0X272 280#define HW_TPL_FR_E_PR_T_FC 0X271 281#define HW_TPL_FR_E_IV_FC 0X249 282#define HW_TPL_FR_E_OV_FC 0X245 283#define HW_TPL_FR_PR_T_IV_FC 0X239 284#define HW_TPL_FR_PR_T_OV_FC 0X235 285#define HW_TPL_FR_IV_OV_FC 0X20D 286#define HW_TPL_MT_M_E_PR 0X1E0 287#define HW_TPL_MT_M_E_T 0X1D0 288#define HW_TPL_MT_E_PR_T_FC 0X171 289#define HW_TPL_MT_E_IV 0X148 290#define HW_TPL_MT_E_OV 0X144 291#define HW_TPL_MT_PR_T_IV 0X138 292#define HW_TPL_MT_PR_T_OV 0X134 293#define HW_TPL_M_E_PR_P 0X0E2 294#define HW_TPL_M_E_T_P 0X0D2 295#define HW_TPL_E_PR_T_P_FC 0X073 296#define HW_TPL_E_IV_P 0X04A 297#define HW_TPL_E_OV_P 0X046 298#define HW_TPL_PR_T_IV_P 0X03A 299#define HW_TPL_PR_T_OV_P 0X036 300 301/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 302enum fw_filter_wr_cookie { 303 FW_FILTER_WR_SUCCESS, 304 FW_FILTER_WR_FLT_ADDED, 305 FW_FILTER_WR_FLT_DELETED, 306 FW_FILTER_WR_SMT_TBL_FULL, 307 FW_FILTER_WR_EINVAL, 308}; 309 310enum fw_filter_wr_nat_mode { 311 FW_FILTER_WR_NATMODE_NONE = 0, 312 FW_FILTER_WR_NATMODE_DIP , 313 FW_FILTER_WR_NATMODE_DIPDP, 314 FW_FILTER_WR_NATMODE_DIPDPSIP, 315 FW_FILTER_WR_NATMODE_DIPDPSP, 316 FW_FILTER_WR_NATMODE_SIPSP, 317 FW_FILTER_WR_NATMODE_DIPSIPSP, 318 FW_FILTER_WR_NATMODE_FOURTUPLE, 319}; 320 321struct fw_filter_wr { 322 __be32 op_pkd; 323 __be32 len16_pkd; 324 __be64 r3; 325 __be32 tid_to_iq; 326 __be32 del_filter_to_l2tix; 327 __be16 ethtype; 328 __be16 ethtypem; 329 __u8 frag_to_ovlan_vldm; 330 __u8 smac_sel; 331 __be16 rx_chan_rx_rpl_iq; 332 __be32 maci_to_matchtypem; 333 __u8 ptcl; 334 __u8 ptclm; 335 __u8 ttyp; 336 __u8 ttypm; 337 __be16 ivlan; 338 __be16 ivlanm; 339 __be16 ovlan; 340 __be16 ovlanm; 341 __u8 lip[16]; 342 __u8 lipm[16]; 343 __u8 fip[16]; 344 __u8 fipm[16]; 345 __be16 lp; 346 __be16 lpm; 347 __be16 fp; 348 __be16 fpm; 349 __be16 r7; 350 __u8 sma[6]; 351}; 352 353struct fw_filter2_wr { 354 __be32 op_pkd; 355 __be32 len16_pkd; 356 __be64 r3; 357 __be32 tid_to_iq; 358 __be32 del_filter_to_l2tix; 359 __be16 ethtype; 360 __be16 ethtypem; 361 __u8 frag_to_ovlan_vldm; 362 __u8 smac_sel; 363 __be16 rx_chan_rx_rpl_iq; 364 __be32 maci_to_matchtypem; 365 __u8 ptcl; 366 __u8 ptclm; 367 __u8 ttyp; 368 __u8 ttypm; 369 __be16 ivlan; 370 __be16 ivlanm; 371 __be16 ovlan; 372 __be16 ovlanm; 373 __u8 lip[16]; 374 __u8 lipm[16]; 375 __u8 fip[16]; 376 __u8 fipm[16]; 377 __be16 lp; 378 __be16 lpm; 379 __be16 fp; 380 __be16 fpm; 381 __be16 r7; 382 __u8 sma[6]; 383 __be16 r8; 384 __u8 filter_type_swapmac; 385 __u8 natmode_to_ulp_type; 386 __be16 newlport; 387 __be16 newfport; 388 __u8 newlip[16]; 389 __u8 newfip[16]; 390 __be32 natseqcheck; 391 __be32 r9; 392 __be64 r10; 393 __be64 r11; 394 __be64 r12; 395 __be64 r13; 396}; 397 398#define S_FW_FILTER_WR_TID 12 399#define M_FW_FILTER_WR_TID 0xfffff 400#define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 401#define G_FW_FILTER_WR_TID(x) \ 402 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 403 404#define S_FW_FILTER_WR_RQTYPE 11 405#define M_FW_FILTER_WR_RQTYPE 0x1 406#define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 407#define G_FW_FILTER_WR_RQTYPE(x) \ 408 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 409#define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 410 411#define S_FW_FILTER_WR_NOREPLY 10 412#define M_FW_FILTER_WR_NOREPLY 0x1 413#define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 414#define G_FW_FILTER_WR_NOREPLY(x) \ 415 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 416#define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 417 418#define S_FW_FILTER_WR_IQ 0 419#define M_FW_FILTER_WR_IQ 0x3ff 420#define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 421#define G_FW_FILTER_WR_IQ(x) \ 422 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 423 424#define S_FW_FILTER_WR_DEL_FILTER 31 425#define M_FW_FILTER_WR_DEL_FILTER 0x1 426#define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 427#define G_FW_FILTER_WR_DEL_FILTER(x) \ 428 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 429#define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 430 431#define S_FW_FILTER2_WR_DROP_ENCAP 30 432#define M_FW_FILTER2_WR_DROP_ENCAP 0x1 433#define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 434#define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 435 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 436#define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 437 438#define S_FW_FILTER2_WR_TX_LOOP 29 439#define M_FW_FILTER2_WR_TX_LOOP 0x1 440#define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 441#define G_FW_FILTER2_WR_TX_LOOP(x) \ 442 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 443#define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 444 445#define S_FW_FILTER_WR_RPTTID 25 446#define M_FW_FILTER_WR_RPTTID 0x1 447#define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 448#define G_FW_FILTER_WR_RPTTID(x) \ 449 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 450#define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 451 452#define S_FW_FILTER_WR_DROP 24 453#define M_FW_FILTER_WR_DROP 0x1 454#define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 455#define G_FW_FILTER_WR_DROP(x) \ 456 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 457#define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 458 459#define S_FW_FILTER_WR_DIRSTEER 23 460#define M_FW_FILTER_WR_DIRSTEER 0x1 461#define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 462#define G_FW_FILTER_WR_DIRSTEER(x) \ 463 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 464#define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 465 466#define S_FW_FILTER_WR_MASKHASH 22 467#define M_FW_FILTER_WR_MASKHASH 0x1 468#define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 469#define G_FW_FILTER_WR_MASKHASH(x) \ 470 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 471#define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 472 473#define S_FW_FILTER_WR_DIRSTEERHASH 21 474#define M_FW_FILTER_WR_DIRSTEERHASH 0x1 475#define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 476#define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 477 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 478#define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 479 480#define S_FW_FILTER_WR_LPBK 20 481#define M_FW_FILTER_WR_LPBK 0x1 482#define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 483#define G_FW_FILTER_WR_LPBK(x) \ 484 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 485#define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 486 487#define S_FW_FILTER_WR_DMAC 19 488#define M_FW_FILTER_WR_DMAC 0x1 489#define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 490#define G_FW_FILTER_WR_DMAC(x) \ 491 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 492#define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 493 494#define S_FW_FILTER_WR_SMAC 18 495#define M_FW_FILTER_WR_SMAC 0x1 496#define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 497#define G_FW_FILTER_WR_SMAC(x) \ 498 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 499#define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 500 501#define S_FW_FILTER_WR_INSVLAN 17 502#define M_FW_FILTER_WR_INSVLAN 0x1 503#define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 504#define G_FW_FILTER_WR_INSVLAN(x) \ 505 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 506#define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 507 508#define S_FW_FILTER_WR_RMVLAN 16 509#define M_FW_FILTER_WR_RMVLAN 0x1 510#define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 511#define G_FW_FILTER_WR_RMVLAN(x) \ 512 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 513#define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 514 515#define S_FW_FILTER_WR_HITCNTS 15 516#define M_FW_FILTER_WR_HITCNTS 0x1 517#define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 518#define G_FW_FILTER_WR_HITCNTS(x) \ 519 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 520#define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 521 522#define S_FW_FILTER_WR_TXCHAN 13 523#define M_FW_FILTER_WR_TXCHAN 0x3 524#define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 525#define G_FW_FILTER_WR_TXCHAN(x) \ 526 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 527 528#define S_FW_FILTER_WR_PRIO 12 529#define M_FW_FILTER_WR_PRIO 0x1 530#define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 531#define G_FW_FILTER_WR_PRIO(x) \ 532 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 533#define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 534 535#define S_FW_FILTER_WR_L2TIX 0 536#define M_FW_FILTER_WR_L2TIX 0xfff 537#define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 538#define G_FW_FILTER_WR_L2TIX(x) \ 539 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 540 541#define S_FW_FILTER_WR_FRAG 7 542#define M_FW_FILTER_WR_FRAG 0x1 543#define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 544#define G_FW_FILTER_WR_FRAG(x) \ 545 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 546#define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 547 548#define S_FW_FILTER_WR_FRAGM 6 549#define M_FW_FILTER_WR_FRAGM 0x1 550#define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 551#define G_FW_FILTER_WR_FRAGM(x) \ 552 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 553#define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 554 555#define S_FW_FILTER_WR_IVLAN_VLD 5 556#define M_FW_FILTER_WR_IVLAN_VLD 0x1 557#define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 558#define G_FW_FILTER_WR_IVLAN_VLD(x) \ 559 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 560#define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 561 562#define S_FW_FILTER_WR_OVLAN_VLD 4 563#define M_FW_FILTER_WR_OVLAN_VLD 0x1 564#define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 565#define G_FW_FILTER_WR_OVLAN_VLD(x) \ 566 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 567#define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 568 569#define S_FW_FILTER_WR_IVLAN_VLDM 3 570#define M_FW_FILTER_WR_IVLAN_VLDM 0x1 571#define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 572#define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 573 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 574#define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 575 576#define S_FW_FILTER_WR_OVLAN_VLDM 2 577#define M_FW_FILTER_WR_OVLAN_VLDM 0x1 578#define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 579#define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 580 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 581#define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 582 583#define S_FW_FILTER_WR_RX_CHAN 15 584#define M_FW_FILTER_WR_RX_CHAN 0x1 585#define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 586#define G_FW_FILTER_WR_RX_CHAN(x) \ 587 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 588#define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 589 590#define S_FW_FILTER_WR_RX_RPL_IQ 0 591#define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 592#define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 593#define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 594 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 595 596#define S_FW_FILTER2_WR_FILTER_TYPE 1 597#define M_FW_FILTER2_WR_FILTER_TYPE 0x1 598#define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 599#define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 600 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 601#define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 602 603#define S_FW_FILTER2_WR_SWAPMAC 0 604#define M_FW_FILTER2_WR_SWAPMAC 0x1 605#define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 606#define G_FW_FILTER2_WR_SWAPMAC(x) \ 607 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 608#define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 609 610#define S_FW_FILTER2_WR_NATMODE 5 611#define M_FW_FILTER2_WR_NATMODE 0x7 612#define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 613#define G_FW_FILTER2_WR_NATMODE(x) \ 614 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 615 616#define S_FW_FILTER2_WR_NATFLAGCHECK 4 617#define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 618#define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 619#define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 620 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 621#define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 622 623#define S_FW_FILTER2_WR_ULP_TYPE 0 624#define M_FW_FILTER2_WR_ULP_TYPE 0xf 625#define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 626#define G_FW_FILTER2_WR_ULP_TYPE(x) \ 627 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 628 629#define S_FW_FILTER_WR_MACI 23 630#define M_FW_FILTER_WR_MACI 0x1ff 631#define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 632#define G_FW_FILTER_WR_MACI(x) \ 633 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 634 635#define S_FW_FILTER_WR_MACIM 14 636#define M_FW_FILTER_WR_MACIM 0x1ff 637#define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 638#define G_FW_FILTER_WR_MACIM(x) \ 639 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 640 641#define S_FW_FILTER_WR_FCOE 13 642#define M_FW_FILTER_WR_FCOE 0x1 643#define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 644#define G_FW_FILTER_WR_FCOE(x) \ 645 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 646#define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 647 648#define S_FW_FILTER_WR_FCOEM 12 649#define M_FW_FILTER_WR_FCOEM 0x1 650#define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 651#define G_FW_FILTER_WR_FCOEM(x) \ 652 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 653#define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 654 655#define S_FW_FILTER_WR_PORT 9 656#define M_FW_FILTER_WR_PORT 0x7 657#define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 658#define G_FW_FILTER_WR_PORT(x) \ 659 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 660 661#define S_FW_FILTER_WR_PORTM 6 662#define M_FW_FILTER_WR_PORTM 0x7 663#define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 664#define G_FW_FILTER_WR_PORTM(x) \ 665 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 666 667#define S_FW_FILTER_WR_MATCHTYPE 3 668#define M_FW_FILTER_WR_MATCHTYPE 0x7 669#define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 670#define G_FW_FILTER_WR_MATCHTYPE(x) \ 671 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 672 673#define S_FW_FILTER_WR_MATCHTYPEM 0 674#define M_FW_FILTER_WR_MATCHTYPEM 0x7 675#define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 676#define G_FW_FILTER_WR_MATCHTYPEM(x) \ 677 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 678 679struct fw_ulptx_wr { 680 __be32 op_to_compl; 681 __be32 flowid_len16; 682 __u64 cookie; 683}; 684 685/* flag for packet type - control packet (0), data packet (1) 686 */ 687#define S_FW_ULPTX_WR_DATA 28 688#define M_FW_ULPTX_WR_DATA 0x1 689#define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 690#define G_FW_ULPTX_WR_DATA(x) \ 691 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 692#define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 693 694struct fw_tp_wr { 695 __be32 op_to_immdlen; 696 __be32 flowid_len16; 697 __u64 cookie; 698}; 699 700struct fw_eth_tx_pkt_wr { 701 __be32 op_immdlen; 702 __be32 equiq_to_len16; 703 __be64 r3; 704}; 705 706#define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 707#define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 708#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 709#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 710 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 711 712struct fw_eth_tx_pkt2_wr { 713 __be32 op_immdlen; 714 __be32 equiq_to_len16; 715 __be32 r3; 716 __be32 L4ChkDisable_to_IpHdrLen; 717}; 718 719#define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 720#define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 721#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 722#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 723 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 724 725#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 726#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 727#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 728 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 729#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 730 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 731 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 732#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 733 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 734 735#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 736#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 737#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 738 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 739#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 740 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 741 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 742#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 743 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 744 745#define S_FW_ETH_TX_PKT2_WR_IVLAN 28 746#define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 747#define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 748#define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 749 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 750#define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 751 752#define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 753#define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 754#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 755#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 756 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 757 758#define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 759#define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 760#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 761#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 762 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 763 764#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 765#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 766#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 767#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 768 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 769 770struct fw_eth_tx_pkts_wr { 771 __be32 op_pkd; 772 __be32 equiq_to_len16; 773 __be32 r3; 774 __be16 plen; 775 __u8 npkt; 776 __u8 type; 777}; 778 779#define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 780#define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 781#define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 782#define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 783 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 784 785struct fw_eth_tx_pkt_ptp_wr { 786 __be32 op_immdlen; 787 __be32 equiq_to_len16; 788 __be64 r3; 789}; 790 791enum fw_eth_tx_eo_type { 792 FW_ETH_TX_EO_TYPE_UDPSEG, 793 FW_ETH_TX_EO_TYPE_TCPSEG, 794 FW_ETH_TX_EO_TYPE_NVGRESEG, 795 FW_ETH_TX_EO_TYPE_VXLANSEG, 796 FW_ETH_TX_EO_TYPE_GENEVESEG, 797}; 798 799struct fw_eth_tx_eo_wr { 800 __be32 op_immdlen; 801 __be32 equiq_to_len16; 802 __be64 r3; 803 union fw_eth_tx_eo { 804 struct fw_eth_tx_eo_udpseg { 805 __u8 type; 806 __u8 ethlen; 807 __be16 iplen; 808 __u8 udplen; 809 __u8 rtplen; 810 __be16 r4; 811 __be16 mss; 812 __be16 schedpktsize; 813 __be32 plen; 814 } udpseg; 815 struct fw_eth_tx_eo_tcpseg { 816 __u8 type; 817 __u8 ethlen; 818 __be16 iplen; 819 __u8 tcplen; 820 __u8 tsclk_tsoff; 821 __be16 r4; 822 __be16 mss; 823 __be16 r5; 824 __be32 plen; 825 } tcpseg; 826 struct fw_eth_tx_eo_nvgreseg { 827 __u8 type; 828 __u8 iphdroffout; 829 __be16 grehdroff; 830 __be16 iphdroffin; 831 __be16 tcphdroffin; 832 __be16 mss; 833 __be16 r4; 834 __be32 plen; 835 } nvgreseg; 836 struct fw_eth_tx_eo_vxlanseg { 837 __u8 type; 838 __u8 iphdroffout; 839 __be16 vxlanhdroff; 840 __be16 iphdroffin; 841 __be16 tcphdroffin; 842 __be16 mss; 843 __be16 r4; 844 __be32 plen; 845 846 } vxlanseg; 847 struct fw_eth_tx_eo_geneveseg { 848 __u8 type; 849 __u8 iphdroffout; 850 __be16 genevehdroff; 851 __be16 iphdroffin; 852 __be16 tcphdroffin; 853 __be16 mss; 854 __be16 r4; 855 __be32 plen; 856 } geneveseg; 857 } u; 858}; 859 860#define S_FW_ETH_TX_EO_WR_IMMDLEN 0 861#define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 862#define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 863#define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 864 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 865 866#define S_FW_ETH_TX_EO_WR_TSCLK 6 867#define M_FW_ETH_TX_EO_WR_TSCLK 0x3 868#define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 869#define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 870 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 871 872#define S_FW_ETH_TX_EO_WR_TSOFF 0 873#define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 874#define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 875#define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 876 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 877 878struct fw_eq_flush_wr { 879 __u8 opcode; 880 __u8 r1[3]; 881 __be32 equiq_to_len16; 882 __be64 r3; 883}; 884 885struct fw_ofld_connection_wr { 886 __be32 op_compl; 887 __be32 len16_pkd; 888 __u64 cookie; 889 __be64 r2; 890 __be64 r3; 891 struct fw_ofld_connection_le { 892 __be32 version_cpl; 893 __be32 filter; 894 __be32 r1; 895 __be16 lport; 896 __be16 pport; 897 union fw_ofld_connection_leip { 898 struct fw_ofld_connection_le_ipv4 { 899 __be32 pip; 900 __be32 lip; 901 __be64 r0; 902 __be64 r1; 903 __be64 r2; 904 } ipv4; 905 struct fw_ofld_connection_le_ipv6 { 906 __be64 pip_hi; 907 __be64 pip_lo; 908 __be64 lip_hi; 909 __be64 lip_lo; 910 } ipv6; 911 } u; 912 } le; 913 struct fw_ofld_connection_tcb { 914 __be32 t_state_to_astid; 915 __be16 cplrxdataack_cplpassacceptrpl; 916 __be16 rcv_adv; 917 __be32 rcv_nxt; 918 __be32 tx_max; 919 __be64 opt0; 920 __be32 opt2; 921 __be32 r1; 922 __be64 r2; 923 __be64 r3; 924 } tcb; 925}; 926 927#define S_FW_OFLD_CONNECTION_WR_VERSION 31 928#define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 929#define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 930 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 931#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 932 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 933 M_FW_OFLD_CONNECTION_WR_VERSION) 934#define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 935 936#define S_FW_OFLD_CONNECTION_WR_CPL 30 937#define M_FW_OFLD_CONNECTION_WR_CPL 0x1 938#define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 939#define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 940 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 941#define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 942 943#define S_FW_OFLD_CONNECTION_WR_T_STATE 28 944#define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 945#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 946 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 947#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 948 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 949 M_FW_OFLD_CONNECTION_WR_T_STATE) 950 951#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 952#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 953#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 954 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 955#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 956 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 957 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 958 959#define S_FW_OFLD_CONNECTION_WR_ASTID 0 960#define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 961#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 962 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 963#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 964 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 965 966#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 967#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 968#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 969 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 970#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 971 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 972 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 973#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 974 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 975 976#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 977#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 978#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 979 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 980#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 981 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 982 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 983#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 984 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 985 986enum fw_flowc_mnem_tcpstate { 987 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 988 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 989 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 990 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 991 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 992 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 993 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 994 * will resend FIN - equiv ESTAB 995 */ 996 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 997 * will resend FIN but have 998 * received FIN 999 */ 1000 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 1001 * will resend FIN but have 1002 * received FIN 1003 */ 1004 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 1005 * waiting for FIN 1006 */ 1007 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 1008}; 1009 1010enum fw_flowc_mnem_eostate { 1011 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 1012 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 1013 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 1014 * outstanding payload 1015 */ 1016 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1017 * discarding outstanding payload 1018 */ 1019}; 1020 1021enum fw_flowc_mnem { 1022 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1023 FW_FLOWC_MNEM_CH = 1, 1024 FW_FLOWC_MNEM_PORT = 2, 1025 FW_FLOWC_MNEM_IQID = 3, 1026 FW_FLOWC_MNEM_SNDNXT = 4, 1027 FW_FLOWC_MNEM_RCVNXT = 5, 1028 FW_FLOWC_MNEM_SNDBUF = 6, 1029 FW_FLOWC_MNEM_MSS = 7, 1030 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1031 FW_FLOWC_MNEM_TCPSTATE = 9, 1032 FW_FLOWC_MNEM_EOSTATE = 10, 1033 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1034 FW_FLOWC_MNEM_DCBPRIO = 12, 1035 FW_FLOWC_MNEM_SND_SCALE = 13, 1036 FW_FLOWC_MNEM_RCV_SCALE = 14, 1037 FW_FLOWC_MNEM_ULP_MODE = 15, 1038 FW_FLOWC_MNEM_MAX = 16, 1039}; 1040 1041struct fw_flowc_mnemval { 1042 __u8 mnemonic; 1043 __u8 r4[3]; 1044 __be32 val; 1045}; 1046 1047struct fw_flowc_wr { 1048 __be32 op_to_nparams; 1049 __be32 flowid_len16; 1050#ifndef C99_NOT_SUPPORTED 1051 struct fw_flowc_mnemval mnemval[0]; 1052#endif 1053}; 1054 1055#define S_FW_FLOWC_WR_NPARAMS 0 1056#define M_FW_FLOWC_WR_NPARAMS 0xff 1057#define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1058#define G_FW_FLOWC_WR_NPARAMS(x) \ 1059 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1060 1061struct fw_ofld_tx_data_wr { 1062 __be32 op_to_immdlen; 1063 __be32 flowid_len16; 1064 __be32 plen; 1065 __be32 lsodisable_to_flags; 1066}; 1067 1068#define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1069#define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1070#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1071 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1072#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1073 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1074 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1075#define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1076 1077#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1078#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1079#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1080 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1081#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1082 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1083#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1084 1085#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1086#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1087#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1088 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1089#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1090 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1091 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1092#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1093 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1094 1095#define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1096#define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1097#define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1098#define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1099 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1100 1101 1102/* Use fw_ofld_tx_data_wr structure */ 1103#define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1104#define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1105#define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1106 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1107#define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1108 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1109 1110#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1111#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1112#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1113 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1114#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1115 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1116 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1117#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1118 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1119 1120#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1121#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1122#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1123 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1124#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1125 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1126 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1127#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1128 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1129 1130#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1131#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1132#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1133 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1134#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1135 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1136 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1137#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1138 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1139 1140#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1141#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1142#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1143 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1144#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1145 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1146 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1147#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1148 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1149 1150#define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1151#define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1152#define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1153 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1154#define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1155 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1156 1157struct fw_cmd_wr { 1158 __be32 op_dma; 1159 __be32 len16_pkd; 1160 __be64 cookie_daddr; 1161}; 1162 1163#define S_FW_CMD_WR_DMA 17 1164#define M_FW_CMD_WR_DMA 0x1 1165#define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1166#define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1167#define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1168 1169struct fw_eth_tx_pkt_vm_wr { 1170 __be32 op_immdlen; 1171 __be32 equiq_to_len16; 1172 __be32 r3[2]; 1173 __u8 ethmacdst[6]; 1174 __u8 ethmacsrc[6]; 1175 __be16 ethtype; 1176 __be16 vlantci; 1177}; 1178 1179struct fw_eth_tx_pkts_vm_wr { 1180 __be32 op_pkd; 1181 __be32 equiq_to_len16; 1182 __be32 r3; 1183 __be16 plen; 1184 __u8 npkt; 1185 __u8 r4; 1186 __u8 ethmacdst[6]; 1187 __u8 ethmacsrc[6]; 1188 __be16 ethtype; 1189 __be16 vlantci; 1190}; 1191 1192/****************************************************************************** 1193 * R I W O R K R E Q U E S T s 1194 **************************************/ 1195 1196enum fw_ri_wr_opcode { 1197 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1198 FW_RI_READ_REQ = 0x1, 1199 FW_RI_READ_RESP = 0x2, 1200 FW_RI_SEND = 0x3, 1201 FW_RI_SEND_WITH_INV = 0x4, 1202 FW_RI_SEND_WITH_SE = 0x5, 1203 FW_RI_SEND_WITH_SE_INV = 0x6, 1204 FW_RI_TERMINATE = 0x7, 1205 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1206 FW_RI_BIND_MW = 0x9, 1207 FW_RI_FAST_REGISTER = 0xa, 1208 FW_RI_LOCAL_INV = 0xb, 1209 FW_RI_QP_MODIFY = 0xc, 1210 FW_RI_BYPASS = 0xd, 1211 FW_RI_RECEIVE = 0xe, 1212#if 0 1213 FW_RI_SEND_IMMEDIATE = 0x8, 1214 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1215 FW_RI_ATOMIC_REQUEST = 0xa, 1216 FW_RI_ATOMIC_RESPONSE = 0xb, 1217 1218 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1219 FW_RI_FAST_REGISTER = 0xd, 1220 FW_RI_LOCAL_INV = 0xe, 1221#endif 1222 FW_RI_SGE_EC_CR_RETURN = 0xf, 1223 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1224}; 1225 1226enum fw_ri_wr_flags { 1227 FW_RI_COMPLETION_FLAG = 0x01, 1228 FW_RI_NOTIFICATION_FLAG = 0x02, 1229 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1230 FW_RI_READ_FENCE_FLAG = 0x08, 1231 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1232 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1233 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 1234}; 1235 1236enum fw_ri_mpa_attrs { 1237 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1238 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1239 FW_RI_MPA_CRC_ENABLE = 0x04, 1240 FW_RI_MPA_IETF_ENABLE = 0x08 1241}; 1242 1243enum fw_ri_qp_caps { 1244 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1245 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1246 FW_RI_QP_BIND_ENABLE = 0x04, 1247 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1248 FW_RI_QP_STAG0_ENABLE = 0x10, 1249 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1250}; 1251 1252enum fw_ri_addr_type { 1253 FW_RI_ZERO_BASED_TO = 0x00, 1254 FW_RI_VA_BASED_TO = 0x01 1255}; 1256 1257enum fw_ri_mem_perms { 1258 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1259 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1260 FW_RI_MEM_ACCESS_REM = 0x03, 1261 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1262 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1263 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1264}; 1265 1266enum fw_ri_stag_type { 1267 FW_RI_STAG_NSMR = 0x00, 1268 FW_RI_STAG_SMR = 0x01, 1269 FW_RI_STAG_MW = 0x02, 1270 FW_RI_STAG_MW_RELAXED = 0x03 1271}; 1272 1273enum fw_ri_data_op { 1274 FW_RI_DATA_IMMD = 0x81, 1275 FW_RI_DATA_DSGL = 0x82, 1276 FW_RI_DATA_ISGL = 0x83 1277}; 1278 1279enum fw_ri_sgl_depth { 1280 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1281 FW_RI_SGL_DEPTH_MAX_RQ = 4 1282}; 1283 1284enum fw_ri_cqe_err { 1285 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1286 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1287 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1288 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1289 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1290 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1291 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1292 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1293 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1294 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1295 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1296 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1297 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1298 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1299 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1300 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1301 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1302 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1303 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1304 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1305 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1306 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1307 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1308 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1309 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1310 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1311 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1312 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1313 1314}; 1315 1316struct fw_ri_dsge_pair { 1317 __be32 len[2]; 1318 __be64 addr[2]; 1319}; 1320 1321struct fw_ri_dsgl { 1322 __u8 op; 1323 __u8 r1; 1324 __be16 nsge; 1325 __be32 len0; 1326 __be64 addr0; 1327#ifndef C99_NOT_SUPPORTED 1328 struct fw_ri_dsge_pair sge[0]; 1329#endif 1330}; 1331 1332struct fw_ri_sge { 1333 __be32 stag; 1334 __be32 len; 1335 __be64 to; 1336}; 1337 1338struct fw_ri_isgl { 1339 __u8 op; 1340 __u8 r1; 1341 __be16 nsge; 1342 __be32 r2; 1343#ifndef C99_NOT_SUPPORTED 1344 struct fw_ri_sge sge[0]; 1345#endif 1346}; 1347 1348struct fw_ri_immd { 1349 __u8 op; 1350 __u8 r1; 1351 __be16 r2; 1352 __be32 immdlen; 1353#ifndef C99_NOT_SUPPORTED 1354 __u8 data[0]; 1355#endif 1356}; 1357 1358struct fw_ri_tpte { 1359 __be32 valid_to_pdid; 1360 __be32 locread_to_qpid; 1361 __be32 nosnoop_pbladdr; 1362 __be32 len_lo; 1363 __be32 va_hi; 1364 __be32 va_lo_fbo; 1365 __be32 dca_mwbcnt_pstag; 1366 __be32 len_hi; 1367}; 1368 1369#define S_FW_RI_TPTE_VALID 31 1370#define M_FW_RI_TPTE_VALID 0x1 1371#define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1372#define G_FW_RI_TPTE_VALID(x) \ 1373 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1374#define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1375 1376#define S_FW_RI_TPTE_STAGKEY 23 1377#define M_FW_RI_TPTE_STAGKEY 0xff 1378#define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1379#define G_FW_RI_TPTE_STAGKEY(x) \ 1380 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1381 1382#define S_FW_RI_TPTE_STAGSTATE 22 1383#define M_FW_RI_TPTE_STAGSTATE 0x1 1384#define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1385#define G_FW_RI_TPTE_STAGSTATE(x) \ 1386 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1387#define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1388 1389#define S_FW_RI_TPTE_STAGTYPE 20 1390#define M_FW_RI_TPTE_STAGTYPE 0x3 1391#define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1392#define G_FW_RI_TPTE_STAGTYPE(x) \ 1393 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1394 1395#define S_FW_RI_TPTE_PDID 0 1396#define M_FW_RI_TPTE_PDID 0xfffff 1397#define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1398#define G_FW_RI_TPTE_PDID(x) \ 1399 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1400 1401#define S_FW_RI_TPTE_PERM 28 1402#define M_FW_RI_TPTE_PERM 0xf 1403#define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1404#define G_FW_RI_TPTE_PERM(x) \ 1405 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1406 1407#define S_FW_RI_TPTE_REMINVDIS 27 1408#define M_FW_RI_TPTE_REMINVDIS 0x1 1409#define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1410#define G_FW_RI_TPTE_REMINVDIS(x) \ 1411 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1412#define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1413 1414#define S_FW_RI_TPTE_ADDRTYPE 26 1415#define M_FW_RI_TPTE_ADDRTYPE 1 1416#define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1417#define G_FW_RI_TPTE_ADDRTYPE(x) \ 1418 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1419#define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1420 1421#define S_FW_RI_TPTE_MWBINDEN 25 1422#define M_FW_RI_TPTE_MWBINDEN 0x1 1423#define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1424#define G_FW_RI_TPTE_MWBINDEN(x) \ 1425 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1426#define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1427 1428#define S_FW_RI_TPTE_PS 20 1429#define M_FW_RI_TPTE_PS 0x1f 1430#define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1431#define G_FW_RI_TPTE_PS(x) \ 1432 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1433 1434#define S_FW_RI_TPTE_QPID 0 1435#define M_FW_RI_TPTE_QPID 0xfffff 1436#define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1437#define G_FW_RI_TPTE_QPID(x) \ 1438 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1439 1440#define S_FW_RI_TPTE_NOSNOOP 31 1441#define M_FW_RI_TPTE_NOSNOOP 0x1 1442#define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1443#define G_FW_RI_TPTE_NOSNOOP(x) \ 1444 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1445#define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1446 1447#define S_FW_RI_TPTE_PBLADDR 0 1448#define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1449#define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1450#define G_FW_RI_TPTE_PBLADDR(x) \ 1451 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1452 1453#define S_FW_RI_TPTE_DCA 24 1454#define M_FW_RI_TPTE_DCA 0x1f 1455#define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1456#define G_FW_RI_TPTE_DCA(x) \ 1457 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1458 1459#define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1460#define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1461#define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1462 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1463#define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1464 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1465 1466enum fw_ri_cqe_rxtx { 1467 FW_RI_CQE_RXTX_RX = 0x0, 1468 FW_RI_CQE_RXTX_TX = 0x1, 1469}; 1470 1471struct fw_ri_cqe { 1472 union fw_ri_rxtx { 1473 struct fw_ri_scqe { 1474 __be32 qpid_n_stat_rxtx_type; 1475 __be32 plen; 1476 __be32 stag; 1477 __be32 wrid; 1478 } scqe; 1479 struct fw_ri_rcqe { 1480 __be32 qpid_n_stat_rxtx_type; 1481 __be32 plen; 1482 __be32 stag; 1483 __be32 msn; 1484 } rcqe; 1485 struct fw_ri_rcqe_imm { 1486 __be32 qpid_n_stat_rxtx_type; 1487 __be32 plen; 1488 __be32 mo; 1489 __be32 msn; 1490 __u64 imm_data; 1491 } imm_data_rcqe; 1492 } u; 1493}; 1494 1495#define S_FW_RI_CQE_QPID 12 1496#define M_FW_RI_CQE_QPID 0xfffff 1497#define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1498#define G_FW_RI_CQE_QPID(x) \ 1499 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1500 1501#define S_FW_RI_CQE_NOTIFY 10 1502#define M_FW_RI_CQE_NOTIFY 0x1 1503#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1504#define G_FW_RI_CQE_NOTIFY(x) \ 1505 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1506 1507#define S_FW_RI_CQE_STATUS 5 1508#define M_FW_RI_CQE_STATUS 0x1f 1509#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1510#define G_FW_RI_CQE_STATUS(x) \ 1511 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1512 1513 1514#define S_FW_RI_CQE_RXTX 4 1515#define M_FW_RI_CQE_RXTX 0x1 1516#define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1517#define G_FW_RI_CQE_RXTX(x) \ 1518 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1519 1520#define S_FW_RI_CQE_TYPE 0 1521#define M_FW_RI_CQE_TYPE 0xf 1522#define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1523#define G_FW_RI_CQE_TYPE(x) \ 1524 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1525 1526enum fw_ri_res_type { 1527 FW_RI_RES_TYPE_SQ, 1528 FW_RI_RES_TYPE_RQ, 1529 FW_RI_RES_TYPE_CQ, 1530 FW_RI_RES_TYPE_SRQ, 1531}; 1532 1533enum fw_ri_res_op { 1534 FW_RI_RES_OP_WRITE, 1535 FW_RI_RES_OP_RESET, 1536}; 1537 1538struct fw_ri_res { 1539 union fw_ri_restype { 1540 struct fw_ri_res_sqrq { 1541 __u8 restype; 1542 __u8 op; 1543 __be16 r3; 1544 __be32 eqid; 1545 __be32 r4[2]; 1546 __be32 fetchszm_to_iqid; 1547 __be32 dcaen_to_eqsize; 1548 __be64 eqaddr; 1549 } sqrq; 1550 struct fw_ri_res_cq { 1551 __u8 restype; 1552 __u8 op; 1553 __be16 r3; 1554 __be32 iqid; 1555 __be32 r4[2]; 1556 __be32 iqandst_to_iqandstindex; 1557 __be16 iqdroprss_to_iqesize; 1558 __be16 iqsize; 1559 __be64 iqaddr; 1560 __be32 iqns_iqro; 1561 __be32 r6_lo; 1562 __be64 r7; 1563 } cq; 1564 struct fw_ri_res_srq { 1565 __u8 restype; 1566 __u8 op; 1567 __be16 r3; 1568 __be32 eqid; 1569 __be32 r4[2]; 1570 __be32 fetchszm_to_iqid; 1571 __be32 dcaen_to_eqsize; 1572 __be64 eqaddr; 1573 __be32 srqid; 1574 __be32 pdid; 1575 __be32 hwsrqsize; 1576 __be32 hwsrqaddr; 1577 } srq; 1578 } u; 1579}; 1580 1581struct fw_ri_res_wr { 1582 __be32 op_nres; 1583 __be32 len16_pkd; 1584 __u64 cookie; 1585#ifndef C99_NOT_SUPPORTED 1586 struct fw_ri_res res[0]; 1587#endif 1588}; 1589 1590#define S_FW_RI_RES_WR_VFN 8 1591#define M_FW_RI_RES_WR_VFN 0xff 1592#define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1593#define G_FW_RI_RES_WR_VFN(x) \ 1594 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1595 1596#define S_FW_RI_RES_WR_NRES 0 1597#define M_FW_RI_RES_WR_NRES 0xff 1598#define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1599#define G_FW_RI_RES_WR_NRES(x) \ 1600 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1601 1602#define S_FW_RI_RES_WR_FETCHSZM 26 1603#define M_FW_RI_RES_WR_FETCHSZM 0x1 1604#define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1605#define G_FW_RI_RES_WR_FETCHSZM(x) \ 1606 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1607#define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1608 1609#define S_FW_RI_RES_WR_STATUSPGNS 25 1610#define M_FW_RI_RES_WR_STATUSPGNS 0x1 1611#define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1612#define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1613 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1614#define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1615 1616#define S_FW_RI_RES_WR_STATUSPGRO 24 1617#define M_FW_RI_RES_WR_STATUSPGRO 0x1 1618#define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1619#define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1620 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1621#define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1622 1623#define S_FW_RI_RES_WR_FETCHNS 23 1624#define M_FW_RI_RES_WR_FETCHNS 0x1 1625#define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1626#define G_FW_RI_RES_WR_FETCHNS(x) \ 1627 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1628#define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1629 1630#define S_FW_RI_RES_WR_FETCHRO 22 1631#define M_FW_RI_RES_WR_FETCHRO 0x1 1632#define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1633#define G_FW_RI_RES_WR_FETCHRO(x) \ 1634 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1635#define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1636 1637#define S_FW_RI_RES_WR_HOSTFCMODE 20 1638#define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1639#define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1640#define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1641 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1642 1643#define S_FW_RI_RES_WR_CPRIO 19 1644#define M_FW_RI_RES_WR_CPRIO 0x1 1645#define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1646#define G_FW_RI_RES_WR_CPRIO(x) \ 1647 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1648#define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1649 1650#define S_FW_RI_RES_WR_ONCHIP 18 1651#define M_FW_RI_RES_WR_ONCHIP 0x1 1652#define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1653#define G_FW_RI_RES_WR_ONCHIP(x) \ 1654 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1655#define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1656 1657#define S_FW_RI_RES_WR_PCIECHN 16 1658#define M_FW_RI_RES_WR_PCIECHN 0x3 1659#define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1660#define G_FW_RI_RES_WR_PCIECHN(x) \ 1661 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1662 1663#define S_FW_RI_RES_WR_IQID 0 1664#define M_FW_RI_RES_WR_IQID 0xffff 1665#define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1666#define G_FW_RI_RES_WR_IQID(x) \ 1667 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1668 1669#define S_FW_RI_RES_WR_DCAEN 31 1670#define M_FW_RI_RES_WR_DCAEN 0x1 1671#define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1672#define G_FW_RI_RES_WR_DCAEN(x) \ 1673 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1674#define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1675 1676#define S_FW_RI_RES_WR_DCACPU 26 1677#define M_FW_RI_RES_WR_DCACPU 0x1f 1678#define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1679#define G_FW_RI_RES_WR_DCACPU(x) \ 1680 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1681 1682#define S_FW_RI_RES_WR_FBMIN 23 1683#define M_FW_RI_RES_WR_FBMIN 0x7 1684#define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1685#define G_FW_RI_RES_WR_FBMIN(x) \ 1686 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1687 1688#define S_FW_RI_RES_WR_FBMAX 20 1689#define M_FW_RI_RES_WR_FBMAX 0x7 1690#define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1691#define G_FW_RI_RES_WR_FBMAX(x) \ 1692 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1693 1694#define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1695#define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1696#define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1697#define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1698 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1699#define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1700 1701#define S_FW_RI_RES_WR_CIDXFTHRESH 16 1702#define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1703#define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1704#define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1705 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1706 1707#define S_FW_RI_RES_WR_EQSIZE 0 1708#define M_FW_RI_RES_WR_EQSIZE 0xffff 1709#define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1710#define G_FW_RI_RES_WR_EQSIZE(x) \ 1711 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1712 1713#define S_FW_RI_RES_WR_IQANDST 15 1714#define M_FW_RI_RES_WR_IQANDST 0x1 1715#define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1716#define G_FW_RI_RES_WR_IQANDST(x) \ 1717 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1718#define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1719 1720#define S_FW_RI_RES_WR_IQANUS 14 1721#define M_FW_RI_RES_WR_IQANUS 0x1 1722#define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1723#define G_FW_RI_RES_WR_IQANUS(x) \ 1724 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1725#define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1726 1727#define S_FW_RI_RES_WR_IQANUD 12 1728#define M_FW_RI_RES_WR_IQANUD 0x3 1729#define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1730#define G_FW_RI_RES_WR_IQANUD(x) \ 1731 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1732 1733#define S_FW_RI_RES_WR_IQANDSTINDEX 0 1734#define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1735#define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1736#define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1737 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1738 1739#define S_FW_RI_RES_WR_IQDROPRSS 15 1740#define M_FW_RI_RES_WR_IQDROPRSS 0x1 1741#define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1742#define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1743 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1744#define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1745 1746#define S_FW_RI_RES_WR_IQGTSMODE 14 1747#define M_FW_RI_RES_WR_IQGTSMODE 0x1 1748#define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1749#define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1750 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1751#define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1752 1753#define S_FW_RI_RES_WR_IQPCIECH 12 1754#define M_FW_RI_RES_WR_IQPCIECH 0x3 1755#define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1756#define G_FW_RI_RES_WR_IQPCIECH(x) \ 1757 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1758 1759#define S_FW_RI_RES_WR_IQDCAEN 11 1760#define M_FW_RI_RES_WR_IQDCAEN 0x1 1761#define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1762#define G_FW_RI_RES_WR_IQDCAEN(x) \ 1763 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1764#define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1765 1766#define S_FW_RI_RES_WR_IQDCACPU 6 1767#define M_FW_RI_RES_WR_IQDCACPU 0x1f 1768#define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1769#define G_FW_RI_RES_WR_IQDCACPU(x) \ 1770 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1771 1772#define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1773#define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1774#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1775 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1776#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1777 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1778 1779#define S_FW_RI_RES_WR_IQO 3 1780#define M_FW_RI_RES_WR_IQO 0x1 1781#define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1782#define G_FW_RI_RES_WR_IQO(x) \ 1783 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1784#define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1785 1786#define S_FW_RI_RES_WR_IQCPRIO 2 1787#define M_FW_RI_RES_WR_IQCPRIO 0x1 1788#define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1789#define G_FW_RI_RES_WR_IQCPRIO(x) \ 1790 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1791#define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1792 1793#define S_FW_RI_RES_WR_IQESIZE 0 1794#define M_FW_RI_RES_WR_IQESIZE 0x3 1795#define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1796#define G_FW_RI_RES_WR_IQESIZE(x) \ 1797 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1798 1799#define S_FW_RI_RES_WR_IQNS 31 1800#define M_FW_RI_RES_WR_IQNS 0x1 1801#define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1802#define G_FW_RI_RES_WR_IQNS(x) \ 1803 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1804#define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1805 1806#define S_FW_RI_RES_WR_IQRO 30 1807#define M_FW_RI_RES_WR_IQRO 0x1 1808#define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1809#define G_FW_RI_RES_WR_IQRO(x) \ 1810 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1811#define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1812 1813struct fw_ri_rdma_write_wr { 1814 __u8 opcode; 1815 __u8 flags; 1816 __u16 wrid; 1817 __u8 r1[3]; 1818 __u8 len16; 1819 __u64 immd_data; 1820 __be32 plen; 1821 __be32 stag_sink; 1822 __be64 to_sink; 1823#ifndef C99_NOT_SUPPORTED 1824 union { 1825 struct fw_ri_immd immd_src[0]; 1826 struct fw_ri_isgl isgl_src[0]; 1827 } u; 1828#endif 1829}; 1830 1831struct fw_ri_send_wr { 1832 __u8 opcode; 1833 __u8 flags; 1834 __u16 wrid; 1835 __u8 r1[3]; 1836 __u8 len16; 1837 __be32 sendop_pkd; 1838 __be32 stag_inv; 1839 __be32 plen; 1840 __be32 r3; 1841 __be64 r4; 1842#ifndef C99_NOT_SUPPORTED 1843 union { 1844 struct fw_ri_immd immd_src[0]; 1845 struct fw_ri_isgl isgl_src[0]; 1846 } u; 1847#endif 1848}; 1849 1850#define S_FW_RI_SEND_WR_SENDOP 0 1851#define M_FW_RI_SEND_WR_SENDOP 0xf 1852#define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1853#define G_FW_RI_SEND_WR_SENDOP(x) \ 1854 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1855 1856struct fw_ri_rdma_write_cmpl_wr { 1857 __u8 opcode; 1858 __u8 flags; 1859 __u16 wrid; 1860 __u8 r1[3]; 1861 __u8 len16; 1862 __u8 r2; 1863 __u8 flags_send; 1864 __u16 wrid_send; 1865 __be32 stag_inv; 1866 __be32 plen; 1867 __be32 stag_sink; 1868 __be64 to_sink; 1869 union fw_ri_cmpl { 1870 struct fw_ri_immd_cmpl { 1871 __u8 op; 1872 __u8 r1[6]; 1873 __u8 immdlen; 1874 __u8 data[16]; 1875 } immd_src; 1876 struct fw_ri_isgl isgl_src; 1877 } u_cmpl; 1878 __be64 r3; 1879#ifndef C99_NOT_SUPPORTED 1880 union fw_ri_write { 1881 struct fw_ri_immd immd_src[0]; 1882 struct fw_ri_isgl isgl_src[0]; 1883 } u; 1884#endif 1885}; 1886 1887struct fw_ri_rdma_read_wr { 1888 __u8 opcode; 1889 __u8 flags; 1890 __u16 wrid; 1891 __u8 r1[3]; 1892 __u8 len16; 1893 __be64 r2; 1894 __be32 stag_sink; 1895 __be32 to_sink_hi; 1896 __be32 to_sink_lo; 1897 __be32 plen; 1898 __be32 stag_src; 1899 __be32 to_src_hi; 1900 __be32 to_src_lo; 1901 __be32 r5; 1902}; 1903 1904struct fw_ri_recv_wr { 1905 __u8 opcode; 1906 __u8 r1; 1907 __u16 wrid; 1908 __u8 r2[3]; 1909 __u8 len16; 1910 struct fw_ri_isgl isgl; 1911}; 1912 1913struct fw_ri_bind_mw_wr { 1914 __u8 opcode; 1915 __u8 flags; 1916 __u16 wrid; 1917 __u8 r1[3]; 1918 __u8 len16; 1919 __u8 qpbinde_to_dcacpu; 1920 __u8 pgsz_shift; 1921 __u8 addr_type; 1922 __u8 mem_perms; 1923 __be32 stag_mr; 1924 __be32 stag_mw; 1925 __be32 r3; 1926 __be64 len_mw; 1927 __be64 va_fbo; 1928 __be64 r4; 1929}; 1930 1931#define S_FW_RI_BIND_MW_WR_QPBINDE 6 1932#define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1933#define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1934#define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1935 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1936#define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1937 1938#define S_FW_RI_BIND_MW_WR_NS 5 1939#define M_FW_RI_BIND_MW_WR_NS 0x1 1940#define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1941#define G_FW_RI_BIND_MW_WR_NS(x) \ 1942 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1943#define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1944 1945#define S_FW_RI_BIND_MW_WR_DCACPU 0 1946#define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1947#define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1948#define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1949 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1950 1951struct fw_ri_fr_nsmr_wr { 1952 __u8 opcode; 1953 __u8 flags; 1954 __u16 wrid; 1955 __u8 r1[3]; 1956 __u8 len16; 1957 __u8 qpbinde_to_dcacpu; 1958 __u8 pgsz_shift; 1959 __u8 addr_type; 1960 __u8 mem_perms; 1961 __be32 stag; 1962 __be32 len_hi; 1963 __be32 len_lo; 1964 __be32 va_hi; 1965 __be32 va_lo_fbo; 1966}; 1967 1968#define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1969#define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1970#define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1971#define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1972 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1973#define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1974 1975#define S_FW_RI_FR_NSMR_WR_NS 5 1976#define M_FW_RI_FR_NSMR_WR_NS 0x1 1977#define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1978#define G_FW_RI_FR_NSMR_WR_NS(x) \ 1979 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1980#define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1981 1982#define S_FW_RI_FR_NSMR_WR_DCACPU 0 1983#define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1984#define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1985#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1986 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1987 1988struct fw_ri_fr_nsmr_tpte_wr { 1989 __u8 opcode; 1990 __u8 flags; 1991 __u16 wrid; 1992 __u8 r1[3]; 1993 __u8 len16; 1994 __be32 r2; 1995 __be32 stag; 1996 struct fw_ri_tpte tpte; 1997 __be64 pbl[2]; 1998}; 1999 2000struct fw_ri_inv_lstag_wr { 2001 __u8 opcode; 2002 __u8 flags; 2003 __u16 wrid; 2004 __u8 r1[3]; 2005 __u8 len16; 2006 __be32 r2; 2007 __be32 stag_inv; 2008}; 2009 2010struct fw_ri_send_immediate_wr { 2011 __u8 opcode; 2012 __u8 flags; 2013 __u16 wrid; 2014 __u8 r1[3]; 2015 __u8 len16; 2016 __be32 sendimmop_pkd; 2017 __be32 r3; 2018 __be32 plen; 2019 __be32 r4; 2020 __be64 r5; 2021#ifndef C99_NOT_SUPPORTED 2022 struct fw_ri_immd immd_src[0]; 2023#endif 2024}; 2025 2026#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 2027#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 2028#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2029 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2030#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2031 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2032 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2033 2034enum fw_ri_atomic_op { 2035 FW_RI_ATOMIC_OP_FETCHADD, 2036 FW_RI_ATOMIC_OP_SWAP, 2037 FW_RI_ATOMIC_OP_CMDSWAP, 2038}; 2039 2040struct fw_ri_atomic_wr { 2041 __u8 opcode; 2042 __u8 flags; 2043 __u16 wrid; 2044 __u8 r1[3]; 2045 __u8 len16; 2046 __be32 atomicop_pkd; 2047 __be64 r3; 2048 __be32 aopcode_pkd; 2049 __be32 reqid; 2050 __be32 stag; 2051 __be32 to_hi; 2052 __be32 to_lo; 2053 __be32 addswap_data_hi; 2054 __be32 addswap_data_lo; 2055 __be32 addswap_mask_hi; 2056 __be32 addswap_mask_lo; 2057 __be32 compare_data_hi; 2058 __be32 compare_data_lo; 2059 __be32 compare_mask_hi; 2060 __be32 compare_mask_lo; 2061 __be32 r5; 2062}; 2063 2064#define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2065#define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2066#define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2067#define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2068 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2069 2070#define S_FW_RI_ATOMIC_WR_AOPCODE 0 2071#define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2072#define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2073#define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2074 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2075 2076enum fw_ri_type { 2077 FW_RI_TYPE_INIT, 2078 FW_RI_TYPE_FINI, 2079 FW_RI_TYPE_TERMINATE 2080}; 2081 2082enum fw_ri_init_p2ptype { 2083 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2084 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2085 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2086 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2087 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2088 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2089 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2090}; 2091 2092enum fw_ri_init_rqeqid_srq { 2093 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 2094}; 2095 2096struct fw_ri_wr { 2097 __be32 op_compl; 2098 __be32 flowid_len16; 2099 __u64 cookie; 2100 union fw_ri { 2101 struct fw_ri_init { 2102 __u8 type; 2103 __u8 mpareqbit_p2ptype; 2104 __u8 r4[2]; 2105 __u8 mpa_attrs; 2106 __u8 qp_caps; 2107 __be16 nrqe; 2108 __be32 pdid; 2109 __be32 qpid; 2110 __be32 sq_eqid; 2111 __be32 rq_eqid; 2112 __be32 scqid; 2113 __be32 rcqid; 2114 __be32 ord_max; 2115 __be32 ird_max; 2116 __be32 iss; 2117 __be32 irs; 2118 __be32 hwrqsize; 2119 __be32 hwrqaddr; 2120 __be64 r5; 2121 union fw_ri_init_p2p { 2122 struct fw_ri_rdma_write_wr write; 2123 struct fw_ri_rdma_read_wr read; 2124 struct fw_ri_send_wr send; 2125 } u; 2126 } init; 2127 struct fw_ri_fini { 2128 __u8 type; 2129 __u8 r3[7]; 2130 __be64 r4; 2131 } fini; 2132 struct fw_ri_terminate { 2133 __u8 type; 2134 __u8 r3[3]; 2135 __be32 immdlen; 2136 __u8 termmsg[40]; 2137 } terminate; 2138 } u; 2139}; 2140 2141#define S_FW_RI_WR_MPAREQBIT 7 2142#define M_FW_RI_WR_MPAREQBIT 0x1 2143#define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2144#define G_FW_RI_WR_MPAREQBIT(x) \ 2145 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2146#define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2147 2148#define S_FW_RI_WR_0BRRBIT 6 2149#define M_FW_RI_WR_0BRRBIT 0x1 2150#define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2151#define G_FW_RI_WR_0BRRBIT(x) \ 2152 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2153#define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2154 2155#define S_FW_RI_WR_P2PTYPE 0 2156#define M_FW_RI_WR_P2PTYPE 0xf 2157#define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2158#define G_FW_RI_WR_P2PTYPE(x) \ 2159 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2160 2161/****************************************************************************** 2162 * F O i S C S I W O R K R E Q U E S T s 2163 *********************************************/ 2164 2165#define FW_FOISCSI_NAME_MAX_LEN 224 2166#define FW_FOISCSI_ALIAS_MAX_LEN 224 2167#define FW_FOISCSI_KEY_MAX_LEN 64 2168#define FW_FOISCSI_VAL_MAX_LEN 256 2169#define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2170#define FW_FOISCSI_INIT_NODE_MAX 8 2171 2172enum fw_chnet_ifconf_wr_subop { 2173 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2174 2175 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2176 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2177 2178 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2179 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2180 2181 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2182 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2183 2184 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2185 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2186 2187 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2188 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2189 2190 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2191 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2192 2193 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2194 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2195 2196 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2197 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2198 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2199 2200 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4, 2201 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6, 2202 2203 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2204}; 2205 2206struct fw_chnet_ifconf_wr { 2207 __be32 op_compl; 2208 __be32 flowid_len16; 2209 __u64 cookie; 2210 __be32 if_flowid; 2211 __u8 idx; 2212 __u8 subop; 2213 __u8 retval; 2214 __u8 r2; 2215 union { 2216 __be64 r3; 2217 struct fw_chnet_ifconf_ping { 2218 __be16 ping_time; 2219 __u8 ping_rsptype; 2220 __u8 ping_param_rspcode_to_fin_bit; 2221 __u8 ping_pktsize; 2222 __u8 ping_ttl; 2223 __be16 ping_seq; 2224 } ping; 2225 struct fw_chnet_ifconf_mac { 2226 __u8 peer_mac[6]; 2227 __u8 smac_idx; 2228 } mac; 2229 } u; 2230 struct fw_chnet_ifconf_params { 2231 __be32 r0; 2232 __be16 vlanid; 2233 __be16 mtu; 2234 union fw_chnet_ifconf_addr_type { 2235 struct fw_chnet_ifconf_ipv4 { 2236 __be32 addr; 2237 __be32 mask; 2238 __be32 router; 2239 __be32 r0; 2240 __be64 r1; 2241 } ipv4; 2242 struct fw_chnet_ifconf_ipv6 { 2243 __u8 prefix_len; 2244 __u8 r0; 2245 __be16 r1; 2246 __be32 r2; 2247 __be64 addr_hi; 2248 __be64 addr_lo; 2249 __be64 router_hi; 2250 __be64 router_lo; 2251 } ipv6; 2252 } in_attr; 2253 } param; 2254}; 2255 2256#define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1 2257#define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1 2258#define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2259 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT) 2260#define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2261 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \ 2262 M_FW_CHNET_IFCONF_WR_PING_MACBIT) 2263#define F_FW_CHNET_IFCONF_WR_PING_MACBIT \ 2264 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U) 2265 2266#define S_FW_CHNET_IFCONF_WR_FIN_BIT 0 2267#define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1 2268#define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT) 2269#define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \ 2270 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT) 2271#define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U) 2272 2273enum fw_foiscsi_node_type { 2274 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2275 FW_FOISCSI_NODE_TYPE_TARGET, 2276}; 2277 2278enum fw_foiscsi_session_type { 2279 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2280 FW_FOISCSI_SESSION_TYPE_NORMAL, 2281}; 2282 2283enum fw_foiscsi_auth_policy { 2284 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2285 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2286}; 2287 2288enum fw_foiscsi_auth_method { 2289 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2290 FW_FOISCSI_AUTH_METHOD_CHAP, 2291 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2292 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2293}; 2294 2295enum fw_foiscsi_digest_type { 2296 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2297 FW_FOISCSI_DIGEST_TYPE_CRC32, 2298 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2299 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2300}; 2301 2302enum fw_foiscsi_wr_subop { 2303 FW_FOISCSI_WR_SUBOP_ADD = 1, 2304 FW_FOISCSI_WR_SUBOP_DEL = 2, 2305 FW_FOISCSI_WR_SUBOP_MOD = 4, 2306}; 2307 2308enum fw_coiscsi_stats_wr_subop { 2309 FW_COISCSI_WR_SUBOP_TOT = 1, 2310 FW_COISCSI_WR_SUBOP_MAX = 2, 2311 FW_COISCSI_WR_SUBOP_CUR = 3, 2312 FW_COISCSI_WR_SUBOP_CLR = 4, 2313}; 2314 2315enum fw_foiscsi_ctrl_state { 2316 FW_FOISCSI_CTRL_STATE_FREE = 0, 2317 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2318 FW_FOISCSI_CTRL_STATE_FAILED, 2319 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2320 FW_FOISCSI_CTRL_STATE_REDIRECT, 2321}; 2322 2323struct fw_rdev_wr { 2324 __be32 op_to_immdlen; 2325 __be32 alloc_to_len16; 2326 __be64 cookie; 2327 __u8 protocol; 2328 __u8 event_cause; 2329 __u8 cur_state; 2330 __u8 prev_state; 2331 __be32 flags_to_assoc_flowid; 2332 union rdev_entry { 2333 struct fcoe_rdev_entry { 2334 __be32 flowid; 2335 __u8 protocol; 2336 __u8 event_cause; 2337 __u8 flags; 2338 __u8 rjt_reason; 2339 __u8 cur_login_st; 2340 __u8 prev_login_st; 2341 __be16 rcv_fr_sz; 2342 __u8 rd_xfer_rdy_to_rport_type; 2343 __u8 vft_to_qos; 2344 __u8 org_proc_assoc_to_acc_rsp_code; 2345 __u8 enh_disc_to_tgt; 2346 __u8 wwnn[8]; 2347 __u8 wwpn[8]; 2348 __be16 iqid; 2349 __u8 fc_oui[3]; 2350 __u8 r_id[3]; 2351 } fcoe_rdev; 2352 struct iscsi_rdev_entry { 2353 __be32 flowid; 2354 __u8 protocol; 2355 __u8 event_cause; 2356 __u8 flags; 2357 __u8 r3; 2358 __be16 iscsi_opts; 2359 __be16 tcp_opts; 2360 __be16 ip_opts; 2361 __be16 max_rcv_len; 2362 __be16 max_snd_len; 2363 __be16 first_brst_len; 2364 __be16 max_brst_len; 2365 __be16 r4; 2366 __be16 def_time2wait; 2367 __be16 def_time2ret; 2368 __be16 nop_out_intrvl; 2369 __be16 non_scsi_to; 2370 __be16 isid; 2371 __be16 tsid; 2372 __be16 port; 2373 __be16 tpgt; 2374 __u8 r5[6]; 2375 __be16 iqid; 2376 } iscsi_rdev; 2377 } u; 2378}; 2379 2380#define S_FW_RDEV_WR_IMMDLEN 0 2381#define M_FW_RDEV_WR_IMMDLEN 0xff 2382#define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2383#define G_FW_RDEV_WR_IMMDLEN(x) \ 2384 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2385 2386#define S_FW_RDEV_WR_ALLOC 31 2387#define M_FW_RDEV_WR_ALLOC 0x1 2388#define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2389#define G_FW_RDEV_WR_ALLOC(x) \ 2390 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2391#define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2392 2393#define S_FW_RDEV_WR_FREE 30 2394#define M_FW_RDEV_WR_FREE 0x1 2395#define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2396#define G_FW_RDEV_WR_FREE(x) \ 2397 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2398#define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2399 2400#define S_FW_RDEV_WR_MODIFY 29 2401#define M_FW_RDEV_WR_MODIFY 0x1 2402#define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2403#define G_FW_RDEV_WR_MODIFY(x) \ 2404 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2405#define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2406 2407#define S_FW_RDEV_WR_FLOWID 8 2408#define M_FW_RDEV_WR_FLOWID 0xfffff 2409#define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2410#define G_FW_RDEV_WR_FLOWID(x) \ 2411 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2412 2413#define S_FW_RDEV_WR_LEN16 0 2414#define M_FW_RDEV_WR_LEN16 0xff 2415#define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2416#define G_FW_RDEV_WR_LEN16(x) \ 2417 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2418 2419#define S_FW_RDEV_WR_FLAGS 24 2420#define M_FW_RDEV_WR_FLAGS 0xff 2421#define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2422#define G_FW_RDEV_WR_FLAGS(x) \ 2423 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2424 2425#define S_FW_RDEV_WR_GET_NEXT 20 2426#define M_FW_RDEV_WR_GET_NEXT 0xf 2427#define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2428#define G_FW_RDEV_WR_GET_NEXT(x) \ 2429 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2430 2431#define S_FW_RDEV_WR_ASSOC_FLOWID 0 2432#define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2433#define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2434#define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2435 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2436 2437#define S_FW_RDEV_WR_RJT 7 2438#define M_FW_RDEV_WR_RJT 0x1 2439#define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2440#define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2441#define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2442 2443#define S_FW_RDEV_WR_REASON 0 2444#define M_FW_RDEV_WR_REASON 0x7f 2445#define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2446#define G_FW_RDEV_WR_REASON(x) \ 2447 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2448 2449#define S_FW_RDEV_WR_RD_XFER_RDY 7 2450#define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2451#define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2452#define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2453 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2454#define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2455 2456#define S_FW_RDEV_WR_WR_XFER_RDY 6 2457#define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2458#define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2459#define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2460 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2461#define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2462 2463#define S_FW_RDEV_WR_FC_SP 5 2464#define M_FW_RDEV_WR_FC_SP 0x1 2465#define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2466#define G_FW_RDEV_WR_FC_SP(x) \ 2467 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2468#define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2469 2470#define S_FW_RDEV_WR_RPORT_TYPE 0 2471#define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2472#define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2473#define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2474 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2475 2476#define S_FW_RDEV_WR_VFT 7 2477#define M_FW_RDEV_WR_VFT 0x1 2478#define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2479#define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2480#define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2481 2482#define S_FW_RDEV_WR_NPIV 6 2483#define M_FW_RDEV_WR_NPIV 0x1 2484#define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2485#define G_FW_RDEV_WR_NPIV(x) \ 2486 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2487#define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2488 2489#define S_FW_RDEV_WR_CLASS 4 2490#define M_FW_RDEV_WR_CLASS 0x3 2491#define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2492#define G_FW_RDEV_WR_CLASS(x) \ 2493 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2494 2495#define S_FW_RDEV_WR_SEQ_DEL 3 2496#define M_FW_RDEV_WR_SEQ_DEL 0x1 2497#define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2498#define G_FW_RDEV_WR_SEQ_DEL(x) \ 2499 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2500#define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2501 2502#define S_FW_RDEV_WR_PRIO_PREEMP 2 2503#define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2504#define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2505#define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2506 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2507#define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2508 2509#define S_FW_RDEV_WR_PREF 1 2510#define M_FW_RDEV_WR_PREF 0x1 2511#define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2512#define G_FW_RDEV_WR_PREF(x) \ 2513 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2514#define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2515 2516#define S_FW_RDEV_WR_QOS 0 2517#define M_FW_RDEV_WR_QOS 0x1 2518#define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2519#define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2520#define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2521 2522#define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2523#define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2524#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2525#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2526 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2527#define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2528 2529#define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2530#define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2531#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2532#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2533 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2534#define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2535 2536#define S_FW_RDEV_WR_IMAGE_PAIR 5 2537#define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2538#define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2539#define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2540 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2541#define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2542 2543#define S_FW_RDEV_WR_ACC_RSP_CODE 0 2544#define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2545#define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2546#define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2547 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2548 2549#define S_FW_RDEV_WR_ENH_DISC 7 2550#define M_FW_RDEV_WR_ENH_DISC 0x1 2551#define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2552#define G_FW_RDEV_WR_ENH_DISC(x) \ 2553 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2554#define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2555 2556#define S_FW_RDEV_WR_REC 6 2557#define M_FW_RDEV_WR_REC 0x1 2558#define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2559#define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2560#define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2561 2562#define S_FW_RDEV_WR_TASK_RETRY_ID 5 2563#define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2564#define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2565#define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2566 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2567#define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2568 2569#define S_FW_RDEV_WR_RETRY 4 2570#define M_FW_RDEV_WR_RETRY 0x1 2571#define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2572#define G_FW_RDEV_WR_RETRY(x) \ 2573 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2574#define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2575 2576#define S_FW_RDEV_WR_CONF_CMPL 3 2577#define M_FW_RDEV_WR_CONF_CMPL 0x1 2578#define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2579#define G_FW_RDEV_WR_CONF_CMPL(x) \ 2580 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2581#define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2582 2583#define S_FW_RDEV_WR_DATA_OVLY 2 2584#define M_FW_RDEV_WR_DATA_OVLY 0x1 2585#define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2586#define G_FW_RDEV_WR_DATA_OVLY(x) \ 2587 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2588#define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2589 2590#define S_FW_RDEV_WR_INI 1 2591#define M_FW_RDEV_WR_INI 0x1 2592#define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2593#define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2594#define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2595 2596#define S_FW_RDEV_WR_TGT 0 2597#define M_FW_RDEV_WR_TGT 0x1 2598#define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2599#define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2600#define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2601 2602struct fw_foiscsi_node_wr { 2603 __be32 op_to_immdlen; 2604 __be32 no_sess_recv_to_len16; 2605 __u64 cookie; 2606 __u8 subop; 2607 __u8 status; 2608 __u8 alias_len; 2609 __u8 iqn_len; 2610 __be32 node_flowid; 2611 __be16 nodeid; 2612 __be16 login_retry; 2613 __be16 retry_timeout; 2614 __be16 r3; 2615 __u8 iqn[224]; 2616 __u8 alias[224]; 2617 __be32 isid_tval_to_isid_cval; 2618}; 2619 2620#define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2621#define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2622#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2623#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2624 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2625 2626#define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28 2627#define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1 2628#define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2629 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2630#define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2631 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \ 2632 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2633#define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \ 2634 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U) 2635 2636#define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30 2637#define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3 2638#define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2639 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL) 2640#define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2641 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL) 2642 2643#define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24 2644#define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f 2645#define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2646 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL) 2647#define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2648 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL) 2649 2650#define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8 2651#define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff 2652#define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2653 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL) 2654#define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2655 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL) 2656 2657#define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0 2658#define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff 2659#define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2660 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL) 2661#define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2662 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL) 2663 2664struct fw_foiscsi_ctrl_wr { 2665 __be32 op_to_no_fin; 2666 __be32 flowid_len16; 2667 __u64 cookie; 2668 __u8 subop; 2669 __u8 status; 2670 __u8 ctrl_state; 2671 __u8 io_state; 2672 __be32 node_id; 2673 __be32 ctrl_id; 2674 __be32 io_id; 2675 struct fw_foiscsi_sess_attr { 2676 __be32 sess_type_to_erl; 2677 __be16 max_conn; 2678 __be16 max_r2t; 2679 __be16 time2wait; 2680 __be16 time2retain; 2681 __be32 max_burst; 2682 __be32 first_burst; 2683 __be32 r1; 2684 } sess_attr; 2685 struct fw_foiscsi_conn_attr { 2686 __be32 hdigest_to_tcp_ws_en; 2687 __be32 max_rcv_dsl; 2688 __be32 ping_tmo; 2689 __be16 dst_port; 2690 __be16 src_port; 2691 union fw_foiscsi_conn_attr_addr { 2692 struct fw_foiscsi_conn_attr_ipv6 { 2693 __be64 dst_addr[2]; 2694 __be64 src_addr[2]; 2695 } ipv6_addr; 2696 struct fw_foiscsi_conn_attr_ipv4 { 2697 __be32 dst_addr; 2698 __be32 src_addr; 2699 } ipv4_addr; 2700 } u; 2701 } conn_attr; 2702 __u8 tgt_name_len; 2703 __u8 r3[7]; 2704 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2705}; 2706 2707#define S_FW_FOISCSI_CTRL_WR_PORTID 1 2708#define M_FW_FOISCSI_CTRL_WR_PORTID 0x7 2709#define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID) 2710#define G_FW_FOISCSI_CTRL_WR_PORTID(x) \ 2711 (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID) 2712 2713#define S_FW_FOISCSI_CTRL_WR_NO_FIN 0 2714#define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1 2715#define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN) 2716#define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \ 2717 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN) 2718#define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U) 2719 2720#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2721#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2722#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2723 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2724#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2725 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2726 2727#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2728#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2729#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2730 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2731#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2732 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2733 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2734#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2735 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2736 2737#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2738#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2739#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2740 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2741#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2742 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2743 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2744#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2745 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2746 2747#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2748#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2749#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2750 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2751#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2752 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2753 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2754#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2755 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2756 2757#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2758#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2759#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2760 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2761#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2762 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2763 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2764#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2765 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2766 2767#define S_FW_FOISCSI_CTRL_WR_ERL 24 2768#define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2769#define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2770#define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2771 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2772 2773#define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2774#define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2775#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2776#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2777 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2778 2779#define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2780#define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2781#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2782#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2783 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2784 2785#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2786#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2787#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2788 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2789#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2790 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2791 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2792 2793#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2794#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2795#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2796 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2797#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2798 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2799 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2800 2801#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2802#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2803#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2804 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2805#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2806 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2807 2808#define S_FW_FOISCSI_CTRL_WR_IPV6 20 2809#define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2810#define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2811#define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2812 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2813#define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2814 2815#define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16 2816#define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf 2817#define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2818 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2819#define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2820 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2821 2822#define S_FW_FOISCSI_CTRL_WR_TCP_WS 12 2823#define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf 2824#define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS) 2825#define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \ 2826 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS) 2827 2828#define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11 2829#define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1 2830#define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2831 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2832#define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2833 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2834#define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U) 2835 2836struct fw_foiscsi_chap_wr { 2837 __be32 op_to_kv_flag; 2838 __be32 flowid_len16; 2839 __u64 cookie; 2840 __u8 status; 2841 union fw_foiscsi_len { 2842 struct fw_foiscsi_chap_lens { 2843 __u8 id_len; 2844 __u8 sec_len; 2845 } chapl; 2846 struct fw_foiscsi_vend_kv_lens { 2847 __u8 key_len; 2848 __u8 val_len; 2849 } vend_kvl; 2850 } lenu; 2851 __u8 node_type; 2852 __be16 node_id; 2853 __u8 r3[2]; 2854 union fw_foiscsi_chap_vend { 2855 struct fw_foiscsi_chap { 2856 __u8 chap_id[224]; 2857 __u8 chap_sec[128]; 2858 } chap; 2859 struct fw_foiscsi_vend_kv { 2860 __u8 vend_key[64]; 2861 __u8 vend_val[256]; 2862 } vend_kv; 2863 } u; 2864}; 2865 2866#define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20 2867#define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1 2868#define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG) 2869#define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \ 2870 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG) 2871#define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U) 2872 2873/****************************************************************************** 2874 * C O i S C S I W O R K R E Q U E S T S 2875 ********************************************/ 2876 2877enum fw_chnet_addr_type { 2878 FW_CHNET_ADDD_TYPE_NONE = 0, 2879 FW_CHNET_ADDR_TYPE_IPV4, 2880 FW_CHNET_ADDR_TYPE_IPV6, 2881}; 2882 2883enum fw_msg_wr_type { 2884 FW_MSG_WR_TYPE_RPL = 0, 2885 FW_MSG_WR_TYPE_ERR, 2886 FW_MSG_WR_TYPE_PLD, 2887}; 2888 2889struct fw_coiscsi_tgt_wr { 2890 __be32 op_compl; 2891 __be32 flowid_len16; 2892 __u64 cookie; 2893 __u8 subop; 2894 __u8 status; 2895 __be16 r4; 2896 __be32 flags; 2897 struct fw_coiscsi_tgt_conn_attr { 2898 __be32 in_tid; 2899 __be16 in_port; 2900 __u8 in_type; 2901 __u8 r6; 2902 union fw_coiscsi_tgt_conn_attr_addr { 2903 struct fw_coiscsi_tgt_conn_attr_in_addr { 2904 __be32 addr; 2905 __be32 r7; 2906 __be32 r8[2]; 2907 } in_addr; 2908 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2909 __be64 addr[2]; 2910 } in_addr6; 2911 } u; 2912 } conn_attr; 2913}; 2914 2915#define S_FW_COISCSI_TGT_WR_PORTID 0 2916#define M_FW_COISCSI_TGT_WR_PORTID 0x7 2917#define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID) 2918#define G_FW_COISCSI_TGT_WR_PORTID(x) \ 2919 (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID) 2920 2921struct fw_coiscsi_tgt_conn_wr { 2922 __be32 op_compl; 2923 __be32 flowid_len16; 2924 __u64 cookie; 2925 __u8 subop; 2926 __u8 status; 2927 __be16 iq_id; 2928 __be32 in_stid; 2929 __be32 io_id; 2930 __be32 flags_fin; 2931 union { 2932 struct fw_coiscsi_tgt_conn_tcp { 2933 __be16 in_sport; 2934 __be16 in_dport; 2935 __u8 wscale_wsen; 2936 __u8 r4[3]; 2937 union fw_coiscsi_tgt_conn_tcp_addr { 2938 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2939 __be32 saddr; 2940 __be32 daddr; 2941 } in_addr; 2942 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2943 __be64 saddr[2]; 2944 __be64 daddr[2]; 2945 } in_addr6; 2946 } u; 2947 } conn_tcp; 2948 struct fw_coiscsi_tgt_conn_stats { 2949 __be32 ddp_reqs; 2950 __be32 ddp_cmpls; 2951 __be16 ddp_aborts; 2952 __be16 ddp_bps; 2953 } stats; 2954 } u; 2955 struct fw_coiscsi_tgt_conn_iscsi { 2956 __be32 hdigest_to_ddp_pgsz; 2957 __be32 tgt_id; 2958 __be16 max_r2t; 2959 __be16 r5; 2960 __be32 max_burst; 2961 __be32 max_rdsl; 2962 __be32 max_tdsl; 2963 __be32 cur_sn; 2964 __be32 r6; 2965 } conn_iscsi; 2966}; 2967 2968#define S_FW_COISCSI_TGT_CONN_WR_PORTID 0 2969#define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7 2970#define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 2971 ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID) 2972#define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 2973 (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \ 2974 M_FW_COISCSI_TGT_CONN_WR_PORTID) 2975 2976#define S_FW_COISCSI_TGT_CONN_WR_FIN 0 2977#define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1 2978#define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN) 2979#define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \ 2980 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN) 2981#define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U) 2982 2983#define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1 2984#define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf 2985#define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2986 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE) 2987#define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2988 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \ 2989 M_FW_COISCSI_TGT_CONN_WR_WSCALE) 2990 2991#define S_FW_COISCSI_TGT_CONN_WR_WSEN 0 2992#define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1 2993#define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 2994 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN) 2995#define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 2996 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN) 2997#define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U) 2998 2999struct fw_coiscsi_tgt_xmit_wr { 3000 __be32 op_to_immdlen; 3001 union { 3002 struct cmpl_stat { 3003 __be32 cmpl_status_pkd; 3004 } cs; 3005 struct flowid_len { 3006 __be32 flowid_len16; 3007 } fllen; 3008 } u; 3009 __u64 cookie; 3010 __be16 iq_id; 3011 __be16 r3; 3012 __be32 pz_off; 3013 __be32 t_xfer_len; 3014 union { 3015 __be32 tag; 3016 __be32 datasn; 3017 __be32 ddp_status; 3018 } cu; 3019}; 3020 3021#define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23 3022#define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1 3023#define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3024 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST) 3025#define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3026 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST) 3027#define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U) 3028 3029#define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22 3030#define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1 3031#define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3032 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST) 3033#define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3034 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST) 3035#define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U) 3036 3037#define S_FW_COISCSI_TGT_XMIT_WR_DDP 20 3038#define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1 3039#define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP) 3040#define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \ 3041 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP) 3042#define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U) 3043 3044#define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19 3045#define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1 3046#define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3047 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT) 3048#define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3049 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT) 3050#define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U) 3051 3052#define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18 3053#define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1 3054#define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3055 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL) 3056#define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3057 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL) 3058#define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U) 3059 3060#define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16 3061#define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3 3062#define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3063 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3064#define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3065 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \ 3066 M_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3067 3068#define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15 3069#define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1 3070#define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3071 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3072#define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3073 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \ 3074 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3075#define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \ 3076 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U) 3077 3078#define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0 3079#define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff 3080#define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3081 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3082#define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3083 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \ 3084 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3085 3086#define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8 3087#define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff 3088#define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3089 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3090#define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3091 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \ 3092 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3093 3094struct fw_coiscsi_stats_wr { 3095 __be32 op_compl; 3096 __be32 flowid_len16; 3097 __u64 cookie; 3098 __u8 subop; 3099 __u8 status; 3100 union fw_coiscsi_stats { 3101 struct fw_coiscsi_resource { 3102 __u8 num_ipv4_tgt; 3103 __u8 num_ipv6_tgt; 3104 __be16 num_l2t_entries; 3105 __be16 num_csocks; 3106 __be16 num_tasks; 3107 __be16 num_ppods_zone[11]; 3108 __be32 num_bufll64; 3109 __u8 r2[12]; 3110 } rsrc; 3111 } u; 3112}; 3113 3114#define S_FW_COISCSI_STATS_WR_PORTID 0 3115#define M_FW_COISCSI_STATS_WR_PORTID 0x7 3116#define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID) 3117#define G_FW_COISCSI_STATS_WR_PORTID(x) \ 3118 (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID) 3119 3120struct fw_isns_wr { 3121 __be32 op_compl; 3122 __be32 flowid_len16; 3123 __u64 cookie; 3124 __u8 subop; 3125 __u8 status; 3126 __be16 iq_id; 3127 __be16 vlanid; 3128 __be16 r4; 3129 struct fw_tcp_conn_attr { 3130 __be32 in_tid; 3131 __be16 in_port; 3132 __u8 in_type; 3133 __u8 r6; 3134 union fw_tcp_conn_attr_addr { 3135 struct fw_tcp_conn_attr_in_addr { 3136 __be32 addr; 3137 __be32 r7; 3138 __be32 r8[2]; 3139 } in_addr; 3140 struct fw_tcp_conn_attr_in_addr6 { 3141 __be64 addr[2]; 3142 } in_addr6; 3143 } u; 3144 } conn_attr; 3145}; 3146 3147#define S_FW_ISNS_WR_PORTID 0 3148#define M_FW_ISNS_WR_PORTID 0x7 3149#define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID) 3150#define G_FW_ISNS_WR_PORTID(x) \ 3151 (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID) 3152 3153struct fw_isns_xmit_wr { 3154 __be32 op_to_immdlen; 3155 __be32 flowid_len16; 3156 __u64 cookie; 3157 __be16 iq_id; 3158 __be16 r4; 3159 __be32 xfer_len; 3160 __be64 r5; 3161}; 3162 3163#define S_FW_ISNS_XMIT_WR_IMMDLEN 0 3164#define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 3165#define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 3166#define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 3167 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 3168 3169/****************************************************************************** 3170 * F O F C O E W O R K R E Q U E S T s 3171 *******************************************/ 3172 3173struct fw_fcoe_els_ct_wr { 3174 __be32 op_immdlen; 3175 __be32 flowid_len16; 3176 __be64 cookie; 3177 __be16 iqid; 3178 __u8 tmo_val; 3179 __u8 els_ct_type; 3180 __u8 ctl_pri; 3181 __u8 cp_en_class; 3182 __be16 xfer_cnt; 3183 __u8 fl_to_sp; 3184 __u8 l_id[3]; 3185 __u8 r5; 3186 __u8 r_id[3]; 3187 __be64 rsp_dmaaddr; 3188 __be32 rsp_dmalen; 3189 __be32 r6; 3190}; 3191 3192#define S_FW_FCOE_ELS_CT_WR_OPCODE 24 3193#define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 3194#define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 3195#define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 3196 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 3197 3198#define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 3199#define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 3200#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 3201#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 3202 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 3203 3204#define S_FW_FCOE_ELS_CT_WR_FLOWID 8 3205#define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 3206#define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 3207#define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 3208 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 3209 3210#define S_FW_FCOE_ELS_CT_WR_LEN16 0 3211#define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 3212#define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 3213#define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 3214 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 3215 3216#define S_FW_FCOE_ELS_CT_WR_CP_EN 6 3217#define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 3218#define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 3219#define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 3220 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 3221 3222#define S_FW_FCOE_ELS_CT_WR_CLASS 4 3223#define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 3224#define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 3225#define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 3226 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 3227 3228#define S_FW_FCOE_ELS_CT_WR_FL 2 3229#define M_FW_FCOE_ELS_CT_WR_FL 0x1 3230#define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 3231#define G_FW_FCOE_ELS_CT_WR_FL(x) \ 3232 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 3233#define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 3234 3235#define S_FW_FCOE_ELS_CT_WR_NPIV 1 3236#define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 3237#define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 3238#define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 3239 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 3240#define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 3241 3242#define S_FW_FCOE_ELS_CT_WR_SP 0 3243#define M_FW_FCOE_ELS_CT_WR_SP 0x1 3244#define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 3245#define G_FW_FCOE_ELS_CT_WR_SP(x) \ 3246 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 3247#define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 3248 3249/****************************************************************************** 3250 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 3251 *****************************************************************************/ 3252 3253struct fw_scsi_write_wr { 3254 __be32 op_immdlen; 3255 __be32 flowid_len16; 3256 __be64 cookie; 3257 __be16 iqid; 3258 __u8 tmo_val; 3259 __u8 use_xfer_cnt; 3260 union fw_scsi_write_priv { 3261 struct fcoe_write_priv { 3262 __u8 ctl_pri; 3263 __u8 cp_en_class; 3264 __u8 r3_lo[2]; 3265 } fcoe; 3266 struct iscsi_write_priv { 3267 __u8 r3[4]; 3268 } iscsi; 3269 } u; 3270 __be32 xfer_cnt; 3271 __be32 ini_xfer_cnt; 3272 __be64 rsp_dmaaddr; 3273 __be32 rsp_dmalen; 3274 __be32 r4; 3275}; 3276 3277#define S_FW_SCSI_WRITE_WR_OPCODE 24 3278#define M_FW_SCSI_WRITE_WR_OPCODE 0xff 3279#define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 3280#define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 3281 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 3282 3283#define S_FW_SCSI_WRITE_WR_IMMDLEN 0 3284#define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 3285#define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 3286#define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 3287 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 3288 3289#define S_FW_SCSI_WRITE_WR_FLOWID 8 3290#define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 3291#define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 3292#define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 3293 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 3294 3295#define S_FW_SCSI_WRITE_WR_LEN16 0 3296#define M_FW_SCSI_WRITE_WR_LEN16 0xff 3297#define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 3298#define G_FW_SCSI_WRITE_WR_LEN16(x) \ 3299 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 3300 3301#define S_FW_SCSI_WRITE_WR_CP_EN 6 3302#define M_FW_SCSI_WRITE_WR_CP_EN 0x3 3303#define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 3304#define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 3305 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 3306 3307#define S_FW_SCSI_WRITE_WR_CLASS 4 3308#define M_FW_SCSI_WRITE_WR_CLASS 0x3 3309#define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 3310#define G_FW_SCSI_WRITE_WR_CLASS(x) \ 3311 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 3312 3313struct fw_scsi_read_wr { 3314 __be32 op_immdlen; 3315 __be32 flowid_len16; 3316 __be64 cookie; 3317 __be16 iqid; 3318 __u8 tmo_val; 3319 __u8 use_xfer_cnt; 3320 union fw_scsi_read_priv { 3321 struct fcoe_read_priv { 3322 __u8 ctl_pri; 3323 __u8 cp_en_class; 3324 __u8 r3_lo[2]; 3325 } fcoe; 3326 struct iscsi_read_priv { 3327 __u8 r3[4]; 3328 } iscsi; 3329 } u; 3330 __be32 xfer_cnt; 3331 __be32 ini_xfer_cnt; 3332 __be64 rsp_dmaaddr; 3333 __be32 rsp_dmalen; 3334 __be32 r4; 3335}; 3336 3337#define S_FW_SCSI_READ_WR_OPCODE 24 3338#define M_FW_SCSI_READ_WR_OPCODE 0xff 3339#define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 3340#define G_FW_SCSI_READ_WR_OPCODE(x) \ 3341 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 3342 3343#define S_FW_SCSI_READ_WR_IMMDLEN 0 3344#define M_FW_SCSI_READ_WR_IMMDLEN 0xff 3345#define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 3346#define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 3347 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 3348 3349#define S_FW_SCSI_READ_WR_FLOWID 8 3350#define M_FW_SCSI_READ_WR_FLOWID 0xfffff 3351#define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 3352#define G_FW_SCSI_READ_WR_FLOWID(x) \ 3353 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 3354 3355#define S_FW_SCSI_READ_WR_LEN16 0 3356#define M_FW_SCSI_READ_WR_LEN16 0xff 3357#define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 3358#define G_FW_SCSI_READ_WR_LEN16(x) \ 3359 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 3360 3361#define S_FW_SCSI_READ_WR_CP_EN 6 3362#define M_FW_SCSI_READ_WR_CP_EN 0x3 3363#define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 3364#define G_FW_SCSI_READ_WR_CP_EN(x) \ 3365 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3366 3367#define S_FW_SCSI_READ_WR_CLASS 4 3368#define M_FW_SCSI_READ_WR_CLASS 0x3 3369#define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3370#define G_FW_SCSI_READ_WR_CLASS(x) \ 3371 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 3372 3373struct fw_scsi_cmd_wr { 3374 __be32 op_immdlen; 3375 __be32 flowid_len16; 3376 __be64 cookie; 3377 __be16 iqid; 3378 __u8 tmo_val; 3379 __u8 r3; 3380 union fw_scsi_cmd_priv { 3381 struct fcoe_cmd_priv { 3382 __u8 ctl_pri; 3383 __u8 cp_en_class; 3384 __u8 r4_lo[2]; 3385 } fcoe; 3386 struct iscsi_cmd_priv { 3387 __u8 r4[4]; 3388 } iscsi; 3389 } u; 3390 __u8 r5[8]; 3391 __be64 rsp_dmaaddr; 3392 __be32 rsp_dmalen; 3393 __be32 r6; 3394}; 3395 3396#define S_FW_SCSI_CMD_WR_OPCODE 24 3397#define M_FW_SCSI_CMD_WR_OPCODE 0xff 3398#define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 3399#define G_FW_SCSI_CMD_WR_OPCODE(x) \ 3400 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 3401 3402#define S_FW_SCSI_CMD_WR_IMMDLEN 0 3403#define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 3404#define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 3405#define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 3406 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 3407 3408#define S_FW_SCSI_CMD_WR_FLOWID 8 3409#define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 3410#define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 3411#define G_FW_SCSI_CMD_WR_FLOWID(x) \ 3412 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 3413 3414#define S_FW_SCSI_CMD_WR_LEN16 0 3415#define M_FW_SCSI_CMD_WR_LEN16 0xff 3416#define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 3417#define G_FW_SCSI_CMD_WR_LEN16(x) \ 3418 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 3419 3420#define S_FW_SCSI_CMD_WR_CP_EN 6 3421#define M_FW_SCSI_CMD_WR_CP_EN 0x3 3422#define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 3423#define G_FW_SCSI_CMD_WR_CP_EN(x) \ 3424 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 3425 3426#define S_FW_SCSI_CMD_WR_CLASS 4 3427#define M_FW_SCSI_CMD_WR_CLASS 0x3 3428#define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 3429#define G_FW_SCSI_CMD_WR_CLASS(x) \ 3430 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 3431 3432struct fw_scsi_abrt_cls_wr { 3433 __be32 op_immdlen; 3434 __be32 flowid_len16; 3435 __be64 cookie; 3436 __be16 iqid; 3437 __u8 tmo_val; 3438 __u8 sub_opcode_to_chk_all_io; 3439 __u8 r3[4]; 3440 __be64 t_cookie; 3441}; 3442 3443#define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3444#define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3445#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3446#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3447 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3448 3449#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3450#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3451#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3452 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3453#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3454 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3455 3456#define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3457#define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3458#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3459#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3460 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3461 3462#define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3463#define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3464#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3465#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3466 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3467 3468#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3469#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3470#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3471 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3472#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3473 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3474 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3475 3476#define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3477#define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3478#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3479#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3480 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3481#define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3482 3483#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3484#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3485#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3486 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3487#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3488 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3489 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3490#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3491 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3492 3493struct fw_scsi_tgt_acc_wr { 3494 __be32 op_immdlen; 3495 __be32 flowid_len16; 3496 __be64 cookie; 3497 __be16 iqid; 3498 __u8 r3; 3499 __u8 use_burst_len; 3500 union fw_scsi_tgt_acc_priv { 3501 struct fcoe_tgt_acc_priv { 3502 __u8 ctl_pri; 3503 __u8 cp_en_class; 3504 __u8 r4_lo[2]; 3505 } fcoe; 3506 struct iscsi_tgt_acc_priv { 3507 __u8 r4[4]; 3508 } iscsi; 3509 } u; 3510 __be32 burst_len; 3511 __be32 rel_off; 3512 __be64 r5; 3513 __be32 r6; 3514 __be32 tot_xfer_len; 3515}; 3516 3517#define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3518#define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3519#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3520#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3521 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3522 3523#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3524#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3525#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3526#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3527 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3528 3529#define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3530#define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3531#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3532#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3533 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3534 3535#define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3536#define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3537#define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3538#define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3539 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3540 3541#define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3542#define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3543#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3544#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3545 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3546 3547#define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3548#define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3549#define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3550#define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3551 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3552 3553struct fw_scsi_tgt_xmit_wr { 3554 __be32 op_immdlen; 3555 __be32 flowid_len16; 3556 __be64 cookie; 3557 __be16 iqid; 3558 __u8 auto_rsp; 3559 __u8 use_xfer_cnt; 3560 union fw_scsi_tgt_xmit_priv { 3561 struct fcoe_tgt_xmit_priv { 3562 __u8 ctl_pri; 3563 __u8 cp_en_class; 3564 __u8 r3_lo[2]; 3565 } fcoe; 3566 struct iscsi_tgt_xmit_priv { 3567 __u8 r3[4]; 3568 } iscsi; 3569 } u; 3570 __be32 xfer_cnt; 3571 __be32 r4; 3572 __be64 r5; 3573 __be32 r6; 3574 __be32 tot_xfer_len; 3575}; 3576 3577#define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3578#define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3579#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3580#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3581 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3582 3583#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3584#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3585#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3586 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3587#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3588 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3589 3590#define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3591#define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3592#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3593#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3594 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3595 3596#define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3597#define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3598#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3599#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3600 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3601 3602#define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3603#define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3604#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3605#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3606 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3607 3608#define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3609#define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3610#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3611#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3612 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3613 3614struct fw_scsi_tgt_rsp_wr { 3615 __be32 op_immdlen; 3616 __be32 flowid_len16; 3617 __be64 cookie; 3618 __be16 iqid; 3619 __u8 r3[2]; 3620 union fw_scsi_tgt_rsp_priv { 3621 struct fcoe_tgt_rsp_priv { 3622 __u8 ctl_pri; 3623 __u8 cp_en_class; 3624 __u8 r4_lo[2]; 3625 } fcoe; 3626 struct iscsi_tgt_rsp_priv { 3627 __u8 r4[4]; 3628 } iscsi; 3629 } u; 3630 __u8 r5[8]; 3631}; 3632 3633#define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3634#define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3635#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3636#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3637 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3638 3639#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3640#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3641#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3642#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3643 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3644 3645#define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3646#define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3647#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3648#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3649 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3650 3651#define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3652#define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3653#define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3654#define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3655 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3656 3657#define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3658#define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3659#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3660#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3661 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3662 3663#define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3664#define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3665#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3666#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3667 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3668 3669struct fw_pofcoe_tcb_wr { 3670 __be32 op_compl; 3671 __be32 equiq_to_len16; 3672 __be32 r4; 3673 __be32 xfer_len; 3674 __be32 tid_to_port; 3675 __be16 x_id; 3676 __be16 vlan_id; 3677 __be64 cookie; 3678 __be32 s_id; 3679 __be32 d_id; 3680 __be32 tag; 3681 __be16 r6; 3682 __be16 iqid; 3683}; 3684 3685#define S_FW_POFCOE_TCB_WR_TID 12 3686#define M_FW_POFCOE_TCB_WR_TID 0xfffff 3687#define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3688#define G_FW_POFCOE_TCB_WR_TID(x) \ 3689 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3690 3691#define S_FW_POFCOE_TCB_WR_ALLOC 4 3692#define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3693#define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3694#define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3695 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3696#define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3697 3698#define S_FW_POFCOE_TCB_WR_FREE 3 3699#define M_FW_POFCOE_TCB_WR_FREE 0x1 3700#define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3701#define G_FW_POFCOE_TCB_WR_FREE(x) \ 3702 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3703#define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3704 3705#define S_FW_POFCOE_TCB_WR_PORT 0 3706#define M_FW_POFCOE_TCB_WR_PORT 0x7 3707#define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3708#define G_FW_POFCOE_TCB_WR_PORT(x) \ 3709 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3710 3711struct fw_pofcoe_ulptx_wr { 3712 __be32 op_pkd; 3713 __be32 equiq_to_len16; 3714 __u64 cookie; 3715}; 3716 3717/******************************************************************* 3718 * T10 DIF related definition 3719 *******************************************************************/ 3720struct fw_tx_pi_header { 3721 __be16 op_to_inline; 3722 __u8 pi_interval_tag_type; 3723 __u8 num_pi; 3724 __be32 pi_start4_pi_end4; 3725 __u8 tag_gen_enabled_pkd; 3726 __u8 num_pi_dsg; 3727 __be16 app_tag; 3728 __be32 ref_tag; 3729}; 3730 3731#define S_FW_TX_PI_HEADER_OP 8 3732#define M_FW_TX_PI_HEADER_OP 0xff 3733#define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3734#define G_FW_TX_PI_HEADER_OP(x) \ 3735 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3736 3737#define S_FW_TX_PI_HEADER_ULPTXMORE 7 3738#define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3739#define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3740#define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3741 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3742#define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3743 3744#define S_FW_TX_PI_HEADER_PI_CONTROL 4 3745#define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3746#define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3747#define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3748 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3749 3750#define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3751#define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3752#define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3753#define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3754 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3755#define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3756 3757#define S_FW_TX_PI_HEADER_VALIDATE 1 3758#define M_FW_TX_PI_HEADER_VALIDATE 0x1 3759#define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3760#define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3761 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3762#define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3763 3764#define S_FW_TX_PI_HEADER_INLINE 0 3765#define M_FW_TX_PI_HEADER_INLINE 0x1 3766#define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3767#define G_FW_TX_PI_HEADER_INLINE(x) \ 3768 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3769#define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3770 3771#define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3772#define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3773#define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3774 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3775#define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3776 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3777#define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3778 3779#define S_FW_TX_PI_HEADER_TAG_TYPE 5 3780#define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3781#define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3782#define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3783 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3784 3785#define S_FW_TX_PI_HEADER_PI_START4 22 3786#define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3787#define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3788#define G_FW_TX_PI_HEADER_PI_START4(x) \ 3789 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3790 3791#define S_FW_TX_PI_HEADER_PI_END4 0 3792#define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3793#define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3794#define G_FW_TX_PI_HEADER_PI_END4(x) \ 3795 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3796 3797#define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3798#define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3799#define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3800 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3801#define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3802 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3803 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3804 3805enum fw_pi_error_type { 3806 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3807}; 3808 3809struct fw_pi_error { 3810 __be32 err_type_pkd; 3811 __be32 flowid_len16; 3812 __be16 r2; 3813 __be16 app_tag; 3814 __be32 ref_tag; 3815 __be32 pisc[4]; 3816}; 3817 3818#define S_FW_PI_ERROR_ERR_TYPE 24 3819#define M_FW_PI_ERROR_ERR_TYPE 0xff 3820#define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3821#define G_FW_PI_ERROR_ERR_TYPE(x) \ 3822 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3823 3824struct fw_tlstx_data_wr { 3825 __be32 op_to_immdlen; 3826 __be32 flowid_len16; 3827 __be32 plen; 3828 __be32 lsodisable_to_flags; 3829 __be32 r5; 3830 __be32 ctxloc_to_exp; 3831 __be16 mfs; 3832 __be16 adjustedplen_pkd; 3833 __be16 expinplenmax_pkd; 3834 __u8 pdusinplenmax_pkd; 3835 __u8 r10; 3836}; 3837 3838#define S_FW_TLSTX_DATA_WR_OPCODE 24 3839#define M_FW_TLSTX_DATA_WR_OPCODE 0xff 3840#define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 3841#define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 3842 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 3843 3844#define S_FW_TLSTX_DATA_WR_COMPL 21 3845#define M_FW_TLSTX_DATA_WR_COMPL 0x1 3846#define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3847#define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3848 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3849#define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3850 3851#define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3852#define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3853#define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3854#define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3855 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3856 3857#define S_FW_TLSTX_DATA_WR_FLOWID 8 3858#define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3859#define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3860#define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3861 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3862 3863#define S_FW_TLSTX_DATA_WR_LEN16 0 3864#define M_FW_TLSTX_DATA_WR_LEN16 0xff 3865#define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3866#define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3867 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3868 3869#define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3870#define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3871#define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3872 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3873#define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3874 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3875#define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3876 3877#define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3878#define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3879#define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3880#define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3881 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3882#define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3883 3884#define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3885#define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3886#define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3887 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3888#define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3889 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3890 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3891#define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3892 3893#define S_FW_TLSTX_DATA_WR_FLAGS 0 3894#define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3895#define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3896#define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3897 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3898 3899#define S_FW_TLSTX_DATA_WR_CTXLOC 30 3900#define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3901#define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3902#define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3903 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3904 3905#define S_FW_TLSTX_DATA_WR_IVDSGL 29 3906#define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3907#define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3908#define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3909 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3910#define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3911 3912#define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3913#define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3914#define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3915#define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3916 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3917 3918#define S_FW_TLSTX_DATA_WR_NUMIVS 14 3919#define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3920#define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3921#define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3922 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3923 3924#define S_FW_TLSTX_DATA_WR_EXP 0 3925#define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3926#define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3927#define G_FW_TLSTX_DATA_WR_EXP(x) \ 3928 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3929 3930#define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 3931#define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 3932#define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3933 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3934#define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3935 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 3936 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3937 3938#define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 3939#define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 3940#define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3941 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3942#define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3943 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 3944 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3945 3946#define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 3947#define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 3948#define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3949 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3950#define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3951 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 3952 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3953 3954struct fw_crypto_lookaside_wr { 3955 __be32 op_to_cctx_size; 3956 __be32 len16_pkd; 3957 __be32 session_id; 3958 __be32 rx_chid_to_rx_q_id; 3959 __be32 key_addr; 3960 __be32 pld_size_hash_size; 3961 __be64 cookie; 3962}; 3963 3964#define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3965#define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3966#define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3967 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3968#define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3969 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 3970 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3971 3972#define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 3973#define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 3974#define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3975 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3976#define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3977 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 3978 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3979#define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 3980 3981#define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 3982#define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 3983#define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3984 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3985#define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3986 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 3987 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3988 3989#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 3990#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 3991#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3992 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3993#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3994 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 3995 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3996 3997#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 3998#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 3999#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4000 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4001#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4002 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 4003 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4004 4005#define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 4006#define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 4007#define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4008 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4009#define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4010 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 4011 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4012 4013#define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 4014#define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 4015#define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4016 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4017#define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4018 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 4019 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4020 4021#define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 4022#define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 4023#define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4024 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 4025#define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4026 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 4027 4028#define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 4029#define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 4030#define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4031 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4032#define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4033 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 4034 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4035 4036#define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 4037#define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 4038#define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4039 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4040#define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4041 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4042 4043#define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4044#define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4045#define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4046 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4047#define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4048 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4049 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4050 4051#define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4052#define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4053#define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4054 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4055#define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4056 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4057 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4058 4059#define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4060#define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4061#define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4062 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4063#define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4064 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4065 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4066 4067#define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4068#define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4069#define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4070 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4071#define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4072 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4073 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4074 4075#define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4076#define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4077#define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4078 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4079#define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4080 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 4081 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4082 4083/****************************************************************************** 4084 * C O M M A N D s 4085 *********************/ 4086 4087/* 4088 * The maximum length of time, in miliseconds, that we expect any firmware 4089 * command to take to execute and return a reply to the host. The RESET 4090 * and INITIALIZE commands can take a fair amount of time to execute but 4091 * most execute in far less time than this maximum. This constant is used 4092 * by host software to determine how long to wait for a firmware command 4093 * reply before declaring the firmware as dead/unreachable ... 4094 */ 4095#define FW_CMD_MAX_TIMEOUT 10000 4096 4097/* 4098 * If a host driver does a HELLO and discovers that there's already a MASTER 4099 * selected, we may have to wait for that MASTER to finish issuing RESET, 4100 * configuration and INITIALIZE commands. Also, there's a possibility that 4101 * our own HELLO may get lost if it happens right as the MASTER is issuign a 4102 * RESET command, so we need to be willing to make a few retries of our HELLO. 4103 */ 4104#define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 4105#define FW_CMD_HELLO_RETRIES 3 4106 4107enum fw_cmd_opcodes { 4108 FW_LDST_CMD = 0x01, 4109 FW_RESET_CMD = 0x03, 4110 FW_HELLO_CMD = 0x04, 4111 FW_BYE_CMD = 0x05, 4112 FW_INITIALIZE_CMD = 0x06, 4113 FW_CAPS_CONFIG_CMD = 0x07, 4114 FW_PARAMS_CMD = 0x08, 4115 FW_PFVF_CMD = 0x09, 4116 FW_IQ_CMD = 0x10, 4117 FW_EQ_MNGT_CMD = 0x11, 4118 FW_EQ_ETH_CMD = 0x12, 4119 FW_EQ_CTRL_CMD = 0x13, 4120 FW_EQ_OFLD_CMD = 0x21, 4121 FW_VI_CMD = 0x14, 4122 FW_VI_MAC_CMD = 0x15, 4123 FW_VI_RXMODE_CMD = 0x16, 4124 FW_VI_ENABLE_CMD = 0x17, 4125 FW_VI_STATS_CMD = 0x1a, 4126 FW_ACL_MAC_CMD = 0x18, 4127 FW_ACL_VLAN_CMD = 0x19, 4128 FW_PORT_CMD = 0x1b, 4129 FW_PORT_STATS_CMD = 0x1c, 4130 FW_PORT_LB_STATS_CMD = 0x1d, 4131 FW_PORT_TRACE_CMD = 0x1e, 4132 FW_PORT_TRACE_MMAP_CMD = 0x1f, 4133 FW_RSS_IND_TBL_CMD = 0x20, 4134 FW_RSS_GLB_CONFIG_CMD = 0x22, 4135 FW_RSS_VI_CONFIG_CMD = 0x23, 4136 FW_SCHED_CMD = 0x24, 4137 FW_DEVLOG_CMD = 0x25, 4138 FW_WATCHDOG_CMD = 0x27, 4139 FW_CLIP_CMD = 0x28, 4140 FW_CHNET_IFACE_CMD = 0x26, 4141 FW_FCOE_RES_INFO_CMD = 0x31, 4142 FW_FCOE_LINK_CMD = 0x32, 4143 FW_FCOE_VNP_CMD = 0x33, 4144 FW_FCOE_SPARAMS_CMD = 0x35, 4145 FW_FCOE_STATS_CMD = 0x37, 4146 FW_FCOE_FCF_CMD = 0x38, 4147 FW_DCB_IEEE_CMD = 0x3a, 4148 FW_DIAG_CMD = 0x3d, 4149 FW_PTP_CMD = 0x3e, 4150 FW_HMA_CMD = 0x3f, 4151 FW_LASTC2E_CMD = 0x40, 4152 FW_ERROR_CMD = 0x80, 4153 FW_DEBUG_CMD = 0x81, 4154}; 4155 4156enum fw_cmd_cap { 4157 FW_CMD_CAP_PF = 0x01, 4158 FW_CMD_CAP_DMAQ = 0x02, 4159 FW_CMD_CAP_PORT = 0x04, 4160 FW_CMD_CAP_PORTPROMISC = 0x08, 4161 FW_CMD_CAP_PORTSTATS = 0x10, 4162 FW_CMD_CAP_VF = 0x80, 4163}; 4164 4165/* 4166 * Generic command header flit0 4167 */ 4168struct fw_cmd_hdr { 4169 __be32 hi; 4170 __be32 lo; 4171}; 4172 4173#define S_FW_CMD_OP 24 4174#define M_FW_CMD_OP 0xff 4175#define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4176#define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4177 4178#define S_FW_CMD_REQUEST 23 4179#define M_FW_CMD_REQUEST 0x1 4180#define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4181#define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4182#define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4183 4184#define S_FW_CMD_READ 22 4185#define M_FW_CMD_READ 0x1 4186#define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4187#define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4188#define F_FW_CMD_READ V_FW_CMD_READ(1U) 4189 4190#define S_FW_CMD_WRITE 21 4191#define M_FW_CMD_WRITE 0x1 4192#define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4193#define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4194#define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4195 4196#define S_FW_CMD_EXEC 20 4197#define M_FW_CMD_EXEC 0x1 4198#define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4199#define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4200#define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4201 4202#define S_FW_CMD_RAMASK 20 4203#define M_FW_CMD_RAMASK 0xf 4204#define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4205#define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4206 4207#define S_FW_CMD_RETVAL 8 4208#define M_FW_CMD_RETVAL 0xff 4209#define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4210#define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4211 4212#define S_FW_CMD_LEN16 0 4213#define M_FW_CMD_LEN16 0xff 4214#define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4215#define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4216 4217#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 4218 4219/* 4220 * address spaces 4221 */ 4222enum fw_ldst_addrspc { 4223 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 4224 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 4225 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 4226 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 4227 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4228 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 4229 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4230 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4231 FW_LDST_ADDRSPC_MDIO = 0x0018, 4232 FW_LDST_ADDRSPC_MPS = 0x0020, 4233 FW_LDST_ADDRSPC_FUNC = 0x0028, 4234 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4235 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 4236 FW_LDST_ADDRSPC_LE = 0x0030, 4237 FW_LDST_ADDRSPC_I2C = 0x0038, 4238 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4239 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4240 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4241 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 4242}; 4243 4244/* 4245 * MDIO VSC8634 register access control field 4246 */ 4247enum fw_ldst_mdio_vsc8634_aid { 4248 FW_LDST_MDIO_VS_STANDARD, 4249 FW_LDST_MDIO_VS_EXTENDED, 4250 FW_LDST_MDIO_VS_GPIO 4251}; 4252 4253enum fw_ldst_mps_fid { 4254 FW_LDST_MPS_ATRB, 4255 FW_LDST_MPS_RPLC 4256}; 4257 4258enum fw_ldst_func_access_ctl { 4259 FW_LDST_FUNC_ACC_CTL_VIID, 4260 FW_LDST_FUNC_ACC_CTL_FID 4261}; 4262 4263enum fw_ldst_func_mod_index { 4264 FW_LDST_FUNC_MPS 4265}; 4266 4267struct fw_ldst_cmd { 4268 __be32 op_to_addrspace; 4269 __be32 cycles_to_len16; 4270 union fw_ldst { 4271 struct fw_ldst_addrval { 4272 __be32 addr; 4273 __be32 val; 4274 } addrval; 4275 struct fw_ldst_idctxt { 4276 __be32 physid; 4277 __be32 msg_ctxtflush; 4278 __be32 ctxt_data7; 4279 __be32 ctxt_data6; 4280 __be32 ctxt_data5; 4281 __be32 ctxt_data4; 4282 __be32 ctxt_data3; 4283 __be32 ctxt_data2; 4284 __be32 ctxt_data1; 4285 __be32 ctxt_data0; 4286 } idctxt; 4287 struct fw_ldst_mdio { 4288 __be16 paddr_mmd; 4289 __be16 raddr; 4290 __be16 vctl; 4291 __be16 rval; 4292 } mdio; 4293 struct fw_ldst_cim_rq { 4294 __u8 req_first64[8]; 4295 __u8 req_second64[8]; 4296 __u8 resp_first64[8]; 4297 __u8 resp_second64[8]; 4298 __be32 r3[2]; 4299 } cim_rq; 4300 union fw_ldst_mps { 4301 struct fw_ldst_mps_rplc { 4302 __be16 fid_idx; 4303 __be16 rplcpf_pkd; 4304 __be32 rplc255_224; 4305 __be32 rplc223_192; 4306 __be32 rplc191_160; 4307 __be32 rplc159_128; 4308 __be32 rplc127_96; 4309 __be32 rplc95_64; 4310 __be32 rplc63_32; 4311 __be32 rplc31_0; 4312 } rplc; 4313 struct fw_ldst_mps_atrb { 4314 __be16 fid_mpsid; 4315 __be16 r2[3]; 4316 __be32 r3[2]; 4317 __be32 r4; 4318 __be32 atrb; 4319 __be16 vlan[16]; 4320 } atrb; 4321 } mps; 4322 struct fw_ldst_func { 4323 __u8 access_ctl; 4324 __u8 mod_index; 4325 __be16 ctl_id; 4326 __be32 offset; 4327 __be64 data0; 4328 __be64 data1; 4329 } func; 4330 struct fw_ldst_pcie { 4331 __u8 ctrl_to_fn; 4332 __u8 bnum; 4333 __u8 r; 4334 __u8 ext_r; 4335 __u8 select_naccess; 4336 __u8 pcie_fn; 4337 __be16 nset_pkd; 4338 __be32 data[12]; 4339 } pcie; 4340 struct fw_ldst_i2c_deprecated { 4341 __u8 pid_pkd; 4342 __u8 base; 4343 __u8 boffset; 4344 __u8 data; 4345 __be32 r9; 4346 } i2c_deprecated; 4347 struct fw_ldst_i2c { 4348 __u8 pid; 4349 __u8 did; 4350 __u8 boffset; 4351 __u8 blen; 4352 __be32 r9; 4353 __u8 data[48]; 4354 } i2c; 4355 struct fw_ldst_le { 4356 __be32 index; 4357 __be32 r9; 4358 __u8 val[33]; 4359 __u8 r11[7]; 4360 } le; 4361 } u; 4362}; 4363 4364#define S_FW_LDST_CMD_ADDRSPACE 0 4365#define M_FW_LDST_CMD_ADDRSPACE 0xff 4366#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4367#define G_FW_LDST_CMD_ADDRSPACE(x) \ 4368 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4369 4370#define S_FW_LDST_CMD_CYCLES 16 4371#define M_FW_LDST_CMD_CYCLES 0xffff 4372#define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4373#define G_FW_LDST_CMD_CYCLES(x) \ 4374 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4375 4376#define S_FW_LDST_CMD_MSG 31 4377#define M_FW_LDST_CMD_MSG 0x1 4378#define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4379#define G_FW_LDST_CMD_MSG(x) \ 4380 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4381#define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4382 4383#define S_FW_LDST_CMD_CTXTFLUSH 30 4384#define M_FW_LDST_CMD_CTXTFLUSH 0x1 4385#define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4386#define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4387 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4388#define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4389 4390#define S_FW_LDST_CMD_PADDR 8 4391#define M_FW_LDST_CMD_PADDR 0x1f 4392#define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4393#define G_FW_LDST_CMD_PADDR(x) \ 4394 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4395 4396#define S_FW_LDST_CMD_MMD 0 4397#define M_FW_LDST_CMD_MMD 0x1f 4398#define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4399#define G_FW_LDST_CMD_MMD(x) \ 4400 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4401 4402#define S_FW_LDST_CMD_FID 15 4403#define M_FW_LDST_CMD_FID 0x1 4404#define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4405#define G_FW_LDST_CMD_FID(x) \ 4406 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4407#define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4408 4409#define S_FW_LDST_CMD_IDX 0 4410#define M_FW_LDST_CMD_IDX 0x7fff 4411#define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4412#define G_FW_LDST_CMD_IDX(x) \ 4413 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4414 4415#define S_FW_LDST_CMD_RPLCPF 0 4416#define M_FW_LDST_CMD_RPLCPF 0xff 4417#define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4418#define G_FW_LDST_CMD_RPLCPF(x) \ 4419 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4420 4421#define S_FW_LDST_CMD_MPSID 0 4422#define M_FW_LDST_CMD_MPSID 0x7fff 4423#define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4424#define G_FW_LDST_CMD_MPSID(x) \ 4425 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4426 4427#define S_FW_LDST_CMD_CTRL 7 4428#define M_FW_LDST_CMD_CTRL 0x1 4429#define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4430#define G_FW_LDST_CMD_CTRL(x) \ 4431 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4432#define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4433 4434#define S_FW_LDST_CMD_LC 4 4435#define M_FW_LDST_CMD_LC 0x1 4436#define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4437#define G_FW_LDST_CMD_LC(x) \ 4438 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4439#define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4440 4441#define S_FW_LDST_CMD_AI 3 4442#define M_FW_LDST_CMD_AI 0x1 4443#define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4444#define G_FW_LDST_CMD_AI(x) \ 4445 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4446#define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4447 4448#define S_FW_LDST_CMD_FN 0 4449#define M_FW_LDST_CMD_FN 0x7 4450#define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4451#define G_FW_LDST_CMD_FN(x) \ 4452 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4453 4454#define S_FW_LDST_CMD_SELECT 4 4455#define M_FW_LDST_CMD_SELECT 0xf 4456#define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4457#define G_FW_LDST_CMD_SELECT(x) \ 4458 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4459 4460#define S_FW_LDST_CMD_NACCESS 0 4461#define M_FW_LDST_CMD_NACCESS 0xf 4462#define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4463#define G_FW_LDST_CMD_NACCESS(x) \ 4464 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4465 4466#define S_FW_LDST_CMD_NSET 14 4467#define M_FW_LDST_CMD_NSET 0x3 4468#define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4469#define G_FW_LDST_CMD_NSET(x) \ 4470 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4471 4472#define S_FW_LDST_CMD_PID 6 4473#define M_FW_LDST_CMD_PID 0x3 4474#define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4475#define G_FW_LDST_CMD_PID(x) \ 4476 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 4477 4478struct fw_reset_cmd { 4479 __be32 op_to_write; 4480 __be32 retval_len16; 4481 __be32 val; 4482 __be32 halt_pkd; 4483}; 4484 4485#define S_FW_RESET_CMD_HALT 31 4486#define M_FW_RESET_CMD_HALT 0x1 4487#define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4488#define G_FW_RESET_CMD_HALT(x) \ 4489 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4490#define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 4491 4492enum { 4493 FW_HELLO_CMD_STAGE_OS = 0, 4494 FW_HELLO_CMD_STAGE_PREOS0 = 1, 4495 FW_HELLO_CMD_STAGE_PREOS1 = 2, 4496 FW_HELLO_CMD_STAGE_POSTOS = 3, 4497}; 4498 4499struct fw_hello_cmd { 4500 __be32 op_to_write; 4501 __be32 retval_len16; 4502 __be32 err_to_clearinit; 4503 __be32 fwrev; 4504}; 4505 4506#define S_FW_HELLO_CMD_ERR 31 4507#define M_FW_HELLO_CMD_ERR 0x1 4508#define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4509#define G_FW_HELLO_CMD_ERR(x) \ 4510 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4511#define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4512 4513#define S_FW_HELLO_CMD_INIT 30 4514#define M_FW_HELLO_CMD_INIT 0x1 4515#define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4516#define G_FW_HELLO_CMD_INIT(x) \ 4517 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4518#define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4519 4520#define S_FW_HELLO_CMD_MASTERDIS 29 4521#define M_FW_HELLO_CMD_MASTERDIS 0x1 4522#define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4523#define G_FW_HELLO_CMD_MASTERDIS(x) \ 4524 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4525#define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4526 4527#define S_FW_HELLO_CMD_MASTERFORCE 28 4528#define M_FW_HELLO_CMD_MASTERFORCE 0x1 4529#define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4530#define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4531 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4532#define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4533 4534#define S_FW_HELLO_CMD_MBMASTER 24 4535#define M_FW_HELLO_CMD_MBMASTER 0xf 4536#define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4537#define G_FW_HELLO_CMD_MBMASTER(x) \ 4538 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4539 4540#define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4541#define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4542#define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4543#define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4544 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4545#define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4546 4547#define S_FW_HELLO_CMD_MBASYNCNOT 20 4548#define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4549#define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4550#define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4551 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4552 4553#define S_FW_HELLO_CMD_STAGE 17 4554#define M_FW_HELLO_CMD_STAGE 0x7 4555#define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4556#define G_FW_HELLO_CMD_STAGE(x) \ 4557 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4558 4559#define S_FW_HELLO_CMD_CLEARINIT 16 4560#define M_FW_HELLO_CMD_CLEARINIT 0x1 4561#define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4562#define G_FW_HELLO_CMD_CLEARINIT(x) \ 4563 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4564#define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 4565 4566struct fw_bye_cmd { 4567 __be32 op_to_write; 4568 __be32 retval_len16; 4569 __be64 r3; 4570}; 4571 4572struct fw_initialize_cmd { 4573 __be32 op_to_write; 4574 __be32 retval_len16; 4575 __be64 r3; 4576}; 4577 4578enum fw_caps_config_hm { 4579 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4580 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4581 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4582 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4583 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4584 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4585 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4586 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4587 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4588 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4589 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4590 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4591 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4592 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4593 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4594 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4595 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4596 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4597 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4598 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4599 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4600 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4601 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4602 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4603}; 4604 4605/* 4606 * The VF Register Map. 4607 * 4608 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4609 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4610 * the Slice to Module Map Table (see below) in the Physical Function Register 4611 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4612 * and Offset registers in the PF Register Map. The MBDATA base address is 4613 * quite constrained as it determines the Mailbox Data addresses for both PFs 4614 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4615 * overlapping other registers. 4616 */ 4617#define FW_T4VF_SGE_BASE_ADDR 0x0000 4618#define FW_T4VF_MPS_BASE_ADDR 0x0100 4619#define FW_T4VF_PL_BASE_ADDR 0x0200 4620#define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4621#define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4622#define FW_T4VF_CIM_BASE_ADDR 0x0300 4623 4624#define FW_T4VF_REGMAP_START 0x0000 4625#define FW_T4VF_REGMAP_SIZE 0x0400 4626 4627enum fw_caps_config_nbm { 4628 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4629 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4630}; 4631 4632enum fw_caps_config_link { 4633 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4634 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4635 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4636}; 4637 4638enum fw_caps_config_switch { 4639 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4640 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4641}; 4642 4643enum fw_caps_config_nic { 4644 FW_CAPS_CONFIG_NIC = 0x00000001, 4645 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4646 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4647 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4648 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4649 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4650 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4651}; 4652 4653enum fw_caps_config_toe { 4654 FW_CAPS_CONFIG_TOE = 0x00000001, 4655}; 4656 4657enum fw_caps_config_rdma { 4658 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4659 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4660}; 4661 4662enum fw_caps_config_iscsi { 4663 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4664 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4665 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4666 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4667 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4668 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4669 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4670 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4671 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4672}; 4673 4674enum fw_caps_config_crypto { 4675 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4676 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 4677 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, 4678}; 4679 4680enum fw_caps_config_fcoe { 4681 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4682 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4683 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4684 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4685 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4686}; 4687 4688enum fw_memtype_cf { 4689 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4690 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4691 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4692 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4693 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4694 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4695}; 4696 4697struct fw_caps_config_cmd { 4698 __be32 op_to_write; 4699 __be32 cfvalid_to_len16; 4700 __be32 r2; 4701 __be32 hwmbitmap; 4702 __be16 nbmcaps; 4703 __be16 linkcaps; 4704 __be16 switchcaps; 4705 __be16 r3; 4706 __be16 niccaps; 4707 __be16 toecaps; 4708 __be16 rdmacaps; 4709 __be16 cryptocaps; 4710 __be16 iscsicaps; 4711 __be16 fcoecaps; 4712 __be32 cfcsum; 4713 __be32 finiver; 4714 __be32 finicsum; 4715}; 4716 4717#define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4718#define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4719#define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4720#define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4721 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4722#define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4723 4724#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4725#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4726#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4727 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4728#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4729 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4730 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4731 4732#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4733#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4734#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4735 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4736#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4737 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4738 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4739 4740/* 4741 * params command mnemonics 4742 */ 4743enum fw_params_mnem { 4744 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4745 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4746 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4747 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4748 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4749 FW_PARAMS_MNEM_LAST 4750}; 4751 4752/* 4753 * device parameters 4754 */ 4755enum fw_params_param_dev { 4756 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4757 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4758 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4759 * allocated by the device's 4760 * Lookup Engine 4761 */ 4762 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4763 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4764 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4765 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4766 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4767 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4768 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4769 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4770 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4771 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4772 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4773 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4774 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4775 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4776 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4777 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4778 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4779 */ 4780 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4781 */ 4782 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4783 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4784 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4785 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4786 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4787 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4788 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4789 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 4790 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 4791 4792 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 4793 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4794 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 4795 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 4796 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 4797 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 4798 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 4799 FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25, 4800 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26, 4801}; 4802 4803/* 4804 * dev bypass parameters; actions and modes 4805 */ 4806enum fw_params_param_dev_bypass { 4807 4808 /* actions 4809 */ 4810 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4811 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4812 4813 /* modes 4814 */ 4815 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4816 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4817 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4818}; 4819 4820enum fw_params_param_dev_phyfw { 4821 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4822 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4823}; 4824 4825enum fw_params_param_dev_diag { 4826 FW_PARAM_DEV_DIAG_TMP = 0x00, 4827 FW_PARAM_DEV_DIAG_VDD = 0x01, 4828 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 4829}; 4830 4831enum fw_params_param_dev_fwcache { 4832 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4833 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4834}; 4835 4836/* 4837 * physical and virtual function parameters 4838 */ 4839enum fw_params_param_pfvf { 4840 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4841 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4842 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4843 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4844 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4845 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4846 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4847 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4848 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4849 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4850 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4851 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4852 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4853 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4854 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4855 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4856 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4857 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4858 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4859 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4860 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4861 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4862 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4863 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4864 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4865 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4866 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4867 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4868 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4869 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4870 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4871 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4872 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4873 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4874 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4875 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4876 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4877 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4878 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4879 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4880 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4881 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4882 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4883 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4884 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4885 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4886 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4887 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4888 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 4889 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 4890 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 4891 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 4892 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 4893 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 4894}; 4895 4896/* 4897 * dma queue parameters 4898 */ 4899enum fw_params_param_dmaq { 4900 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4901 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4902 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4903 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4904 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4905 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4906 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4907 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4908 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4909 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4910 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4911}; 4912 4913/* 4914 * chnet parameters 4915 */ 4916enum fw_params_param_chnet { 4917 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4918}; 4919 4920enum fw_params_param_chnet_flags { 4921 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4922 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4923 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4924}; 4925 4926#define S_FW_PARAMS_MNEM 24 4927#define M_FW_PARAMS_MNEM 0xff 4928#define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4929#define G_FW_PARAMS_MNEM(x) \ 4930 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4931 4932#define S_FW_PARAMS_PARAM_X 16 4933#define M_FW_PARAMS_PARAM_X 0xff 4934#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4935#define G_FW_PARAMS_PARAM_X(x) \ 4936 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4937 4938#define S_FW_PARAMS_PARAM_Y 8 4939#define M_FW_PARAMS_PARAM_Y 0xff 4940#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4941#define G_FW_PARAMS_PARAM_Y(x) \ 4942 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4943 4944#define S_FW_PARAMS_PARAM_Z 0 4945#define M_FW_PARAMS_PARAM_Z 0xff 4946#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4947#define G_FW_PARAMS_PARAM_Z(x) \ 4948 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4949 4950#define S_FW_PARAMS_PARAM_XYZ 0 4951#define M_FW_PARAMS_PARAM_XYZ 0xffffff 4952#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4953#define G_FW_PARAMS_PARAM_XYZ(x) \ 4954 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4955 4956#define S_FW_PARAMS_PARAM_YZ 0 4957#define M_FW_PARAMS_PARAM_YZ 0xffff 4958#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4959#define G_FW_PARAMS_PARAM_YZ(x) \ 4960 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4961 4962#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4963#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4964#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4965 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4966#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4967 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4968 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4969 4970#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4971#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4972#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4973 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4974#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4975 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4976 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4977 4978#define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4979#define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4980#define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4981 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4982#define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4983 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4984 4985#define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 4986#define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 4987#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4988 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4989#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4990 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 4991 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4992 4993#define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 4994#define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 4995#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4996 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 4997#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4998 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 4999 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 5000 5001struct fw_params_cmd { 5002 __be32 op_to_vfn; 5003 __be32 retval_len16; 5004 struct fw_params_param { 5005 __be32 mnem; 5006 __be32 val; 5007 } param[7]; 5008}; 5009 5010#define S_FW_PARAMS_CMD_PFN 8 5011#define M_FW_PARAMS_CMD_PFN 0x7 5012#define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 5013#define G_FW_PARAMS_CMD_PFN(x) \ 5014 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 5015 5016#define S_FW_PARAMS_CMD_VFN 0 5017#define M_FW_PARAMS_CMD_VFN 0xff 5018#define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 5019#define G_FW_PARAMS_CMD_VFN(x) \ 5020 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 5021 5022struct fw_pfvf_cmd { 5023 __be32 op_to_vfn; 5024 __be32 retval_len16; 5025 __be32 niqflint_niq; 5026 __be32 type_to_neq; 5027 __be32 tc_to_nexactf; 5028 __be32 r_caps_to_nethctrl; 5029 __be16 nricq; 5030 __be16 nriqp; 5031 __be32 r4; 5032}; 5033 5034#define S_FW_PFVF_CMD_PFN 8 5035#define M_FW_PFVF_CMD_PFN 0x7 5036#define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 5037#define G_FW_PFVF_CMD_PFN(x) \ 5038 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 5039 5040#define S_FW_PFVF_CMD_VFN 0 5041#define M_FW_PFVF_CMD_VFN 0xff 5042#define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 5043#define G_FW_PFVF_CMD_VFN(x) \ 5044 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 5045 5046#define S_FW_PFVF_CMD_NIQFLINT 20 5047#define M_FW_PFVF_CMD_NIQFLINT 0xfff 5048#define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 5049#define G_FW_PFVF_CMD_NIQFLINT(x) \ 5050 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 5051 5052#define S_FW_PFVF_CMD_NIQ 0 5053#define M_FW_PFVF_CMD_NIQ 0xfffff 5054#define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 5055#define G_FW_PFVF_CMD_NIQ(x) \ 5056 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 5057 5058#define S_FW_PFVF_CMD_TYPE 31 5059#define M_FW_PFVF_CMD_TYPE 0x1 5060#define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 5061#define G_FW_PFVF_CMD_TYPE(x) \ 5062 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 5063#define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 5064 5065#define S_FW_PFVF_CMD_CMASK 24 5066#define M_FW_PFVF_CMD_CMASK 0xf 5067#define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 5068#define G_FW_PFVF_CMD_CMASK(x) \ 5069 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 5070 5071#define S_FW_PFVF_CMD_PMASK 20 5072#define M_FW_PFVF_CMD_PMASK 0xf 5073#define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 5074#define G_FW_PFVF_CMD_PMASK(x) \ 5075 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 5076 5077#define S_FW_PFVF_CMD_NEQ 0 5078#define M_FW_PFVF_CMD_NEQ 0xfffff 5079#define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 5080#define G_FW_PFVF_CMD_NEQ(x) \ 5081 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 5082 5083#define S_FW_PFVF_CMD_TC 24 5084#define M_FW_PFVF_CMD_TC 0xff 5085#define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 5086#define G_FW_PFVF_CMD_TC(x) \ 5087 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 5088 5089#define S_FW_PFVF_CMD_NVI 16 5090#define M_FW_PFVF_CMD_NVI 0xff 5091#define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 5092#define G_FW_PFVF_CMD_NVI(x) \ 5093 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 5094 5095#define S_FW_PFVF_CMD_NEXACTF 0 5096#define M_FW_PFVF_CMD_NEXACTF 0xffff 5097#define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 5098#define G_FW_PFVF_CMD_NEXACTF(x) \ 5099 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 5100 5101#define S_FW_PFVF_CMD_R_CAPS 24 5102#define M_FW_PFVF_CMD_R_CAPS 0xff 5103#define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 5104#define G_FW_PFVF_CMD_R_CAPS(x) \ 5105 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 5106 5107#define S_FW_PFVF_CMD_WX_CAPS 16 5108#define M_FW_PFVF_CMD_WX_CAPS 0xff 5109#define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 5110#define G_FW_PFVF_CMD_WX_CAPS(x) \ 5111 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 5112 5113#define S_FW_PFVF_CMD_NETHCTRL 0 5114#define M_FW_PFVF_CMD_NETHCTRL 0xffff 5115#define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 5116#define G_FW_PFVF_CMD_NETHCTRL(x) \ 5117 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 5118 5119/* 5120 * ingress queue type; the first 1K ingress queues can have associated 0, 5121 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 5122 * capabilities 5123 */ 5124enum fw_iq_type { 5125 FW_IQ_TYPE_FL_INT_CAP, 5126 FW_IQ_TYPE_NO_FL_INT_CAP, 5127 FW_IQ_TYPE_VF_CQ 5128}; 5129 5130enum fw_iq_iqtype { 5131 FW_IQ_IQTYPE_OTHER, 5132 FW_IQ_IQTYPE_NIC, 5133 FW_IQ_IQTYPE_OFLD, 5134}; 5135 5136struct fw_iq_cmd { 5137 __be32 op_to_vfn; 5138 __be32 alloc_to_len16; 5139 __be16 physiqid; 5140 __be16 iqid; 5141 __be16 fl0id; 5142 __be16 fl1id; 5143 __be32 type_to_iqandstindex; 5144 __be16 iqdroprss_to_iqesize; 5145 __be16 iqsize; 5146 __be64 iqaddr; 5147 __be32 iqns_to_fl0congen; 5148 __be16 fl0dcaen_to_fl0cidxfthresh; 5149 __be16 fl0size; 5150 __be64 fl0addr; 5151 __be32 fl1cngchmap_to_fl1congen; 5152 __be16 fl1dcaen_to_fl1cidxfthresh; 5153 __be16 fl1size; 5154 __be64 fl1addr; 5155}; 5156 5157#define S_FW_IQ_CMD_PFN 8 5158#define M_FW_IQ_CMD_PFN 0x7 5159#define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 5160#define G_FW_IQ_CMD_PFN(x) \ 5161 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 5162 5163#define S_FW_IQ_CMD_VFN 0 5164#define M_FW_IQ_CMD_VFN 0xff 5165#define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 5166#define G_FW_IQ_CMD_VFN(x) \ 5167 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 5168 5169#define S_FW_IQ_CMD_ALLOC 31 5170#define M_FW_IQ_CMD_ALLOC 0x1 5171#define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 5172#define G_FW_IQ_CMD_ALLOC(x) \ 5173 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 5174#define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 5175 5176#define S_FW_IQ_CMD_FREE 30 5177#define M_FW_IQ_CMD_FREE 0x1 5178#define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 5179#define G_FW_IQ_CMD_FREE(x) \ 5180 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 5181#define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 5182 5183#define S_FW_IQ_CMD_MODIFY 29 5184#define M_FW_IQ_CMD_MODIFY 0x1 5185#define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 5186#define G_FW_IQ_CMD_MODIFY(x) \ 5187 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 5188#define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 5189 5190#define S_FW_IQ_CMD_IQSTART 28 5191#define M_FW_IQ_CMD_IQSTART 0x1 5192#define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 5193#define G_FW_IQ_CMD_IQSTART(x) \ 5194 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 5195#define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5196 5197#define S_FW_IQ_CMD_IQSTOP 27 5198#define M_FW_IQ_CMD_IQSTOP 0x1 5199#define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5200#define G_FW_IQ_CMD_IQSTOP(x) \ 5201 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5202#define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5203 5204#define S_FW_IQ_CMD_TYPE 29 5205#define M_FW_IQ_CMD_TYPE 0x7 5206#define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5207#define G_FW_IQ_CMD_TYPE(x) \ 5208 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5209 5210#define S_FW_IQ_CMD_IQASYNCH 28 5211#define M_FW_IQ_CMD_IQASYNCH 0x1 5212#define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5213#define G_FW_IQ_CMD_IQASYNCH(x) \ 5214 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5215#define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5216 5217#define S_FW_IQ_CMD_VIID 16 5218#define M_FW_IQ_CMD_VIID 0xfff 5219#define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5220#define G_FW_IQ_CMD_VIID(x) \ 5221 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5222 5223#define S_FW_IQ_CMD_IQANDST 15 5224#define M_FW_IQ_CMD_IQANDST 0x1 5225#define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5226#define G_FW_IQ_CMD_IQANDST(x) \ 5227 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5228#define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5229 5230#define S_FW_IQ_CMD_IQANUS 14 5231#define M_FW_IQ_CMD_IQANUS 0x1 5232#define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5233#define G_FW_IQ_CMD_IQANUS(x) \ 5234 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5235#define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5236 5237#define S_FW_IQ_CMD_IQANUD 12 5238#define M_FW_IQ_CMD_IQANUD 0x3 5239#define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5240#define G_FW_IQ_CMD_IQANUD(x) \ 5241 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5242 5243#define S_FW_IQ_CMD_IQANDSTINDEX 0 5244#define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5245#define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5246#define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5247 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5248 5249#define S_FW_IQ_CMD_IQDROPRSS 15 5250#define M_FW_IQ_CMD_IQDROPRSS 0x1 5251#define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5252#define G_FW_IQ_CMD_IQDROPRSS(x) \ 5253 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5254#define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5255 5256#define S_FW_IQ_CMD_IQGTSMODE 14 5257#define M_FW_IQ_CMD_IQGTSMODE 0x1 5258#define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5259#define G_FW_IQ_CMD_IQGTSMODE(x) \ 5260 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5261#define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5262 5263#define S_FW_IQ_CMD_IQPCIECH 12 5264#define M_FW_IQ_CMD_IQPCIECH 0x3 5265#define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5266#define G_FW_IQ_CMD_IQPCIECH(x) \ 5267 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5268 5269#define S_FW_IQ_CMD_IQDCAEN 11 5270#define M_FW_IQ_CMD_IQDCAEN 0x1 5271#define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5272#define G_FW_IQ_CMD_IQDCAEN(x) \ 5273 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5274#define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5275 5276#define S_FW_IQ_CMD_IQDCACPU 6 5277#define M_FW_IQ_CMD_IQDCACPU 0x1f 5278#define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5279#define G_FW_IQ_CMD_IQDCACPU(x) \ 5280 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5281 5282#define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5283#define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5284#define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5285#define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5286 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5287 5288#define S_FW_IQ_CMD_IQO 3 5289#define M_FW_IQ_CMD_IQO 0x1 5290#define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5291#define G_FW_IQ_CMD_IQO(x) \ 5292 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5293#define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5294 5295#define S_FW_IQ_CMD_IQCPRIO 2 5296#define M_FW_IQ_CMD_IQCPRIO 0x1 5297#define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5298#define G_FW_IQ_CMD_IQCPRIO(x) \ 5299 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5300#define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5301 5302#define S_FW_IQ_CMD_IQESIZE 0 5303#define M_FW_IQ_CMD_IQESIZE 0x3 5304#define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5305#define G_FW_IQ_CMD_IQESIZE(x) \ 5306 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5307 5308#define S_FW_IQ_CMD_IQNS 31 5309#define M_FW_IQ_CMD_IQNS 0x1 5310#define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5311#define G_FW_IQ_CMD_IQNS(x) \ 5312 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5313#define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5314 5315#define S_FW_IQ_CMD_IQRO 30 5316#define M_FW_IQ_CMD_IQRO 0x1 5317#define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5318#define G_FW_IQ_CMD_IQRO(x) \ 5319 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5320#define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5321 5322#define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5323#define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5324#define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5325#define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5326 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5327 5328#define S_FW_IQ_CMD_IQFLINTCONGEN 27 5329#define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5330#define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5331#define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5332 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5333#define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5334 5335#define S_FW_IQ_CMD_IQFLINTISCSIC 26 5336#define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5337#define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5338#define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5339 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5340#define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5341 5342#define S_FW_IQ_CMD_IQTYPE 24 5343#define M_FW_IQ_CMD_IQTYPE 0x3 5344#define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 5345#define G_FW_IQ_CMD_IQTYPE(x) \ 5346 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE) 5347 5348#define S_FW_IQ_CMD_FL0CNGCHMAP 20 5349#define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5350#define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5351#define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5352 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5353 5354#define S_FW_IQ_CMD_FL0CONGDROP 16 5355#define M_FW_IQ_CMD_FL0CONGDROP 0x1 5356#define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5357#define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5358 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5359#define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5360 5361#define S_FW_IQ_CMD_FL0CACHELOCK 15 5362#define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5363#define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5364#define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5365 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5366#define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5367 5368#define S_FW_IQ_CMD_FL0DBP 14 5369#define M_FW_IQ_CMD_FL0DBP 0x1 5370#define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5371#define G_FW_IQ_CMD_FL0DBP(x) \ 5372 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5373#define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5374 5375#define S_FW_IQ_CMD_FL0DATANS 13 5376#define M_FW_IQ_CMD_FL0DATANS 0x1 5377#define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5378#define G_FW_IQ_CMD_FL0DATANS(x) \ 5379 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5380#define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5381 5382#define S_FW_IQ_CMD_FL0DATARO 12 5383#define M_FW_IQ_CMD_FL0DATARO 0x1 5384#define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5385#define G_FW_IQ_CMD_FL0DATARO(x) \ 5386 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5387#define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5388 5389#define S_FW_IQ_CMD_FL0CONGCIF 11 5390#define M_FW_IQ_CMD_FL0CONGCIF 0x1 5391#define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5392#define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5393 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5394#define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5395 5396#define S_FW_IQ_CMD_FL0ONCHIP 10 5397#define M_FW_IQ_CMD_FL0ONCHIP 0x1 5398#define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5399#define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5400 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5401#define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5402 5403#define S_FW_IQ_CMD_FL0STATUSPGNS 9 5404#define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5405#define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5406#define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5407 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5408#define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5409 5410#define S_FW_IQ_CMD_FL0STATUSPGRO 8 5411#define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5412#define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5413#define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5414 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5415#define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5416 5417#define S_FW_IQ_CMD_FL0FETCHNS 7 5418#define M_FW_IQ_CMD_FL0FETCHNS 0x1 5419#define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5420#define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5421 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5422#define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5423 5424#define S_FW_IQ_CMD_FL0FETCHRO 6 5425#define M_FW_IQ_CMD_FL0FETCHRO 0x1 5426#define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5427#define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5428 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5429#define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5430 5431#define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5432#define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5433#define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5434#define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5435 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5436 5437#define S_FW_IQ_CMD_FL0CPRIO 3 5438#define M_FW_IQ_CMD_FL0CPRIO 0x1 5439#define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5440#define G_FW_IQ_CMD_FL0CPRIO(x) \ 5441 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5442#define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5443 5444#define S_FW_IQ_CMD_FL0PADEN 2 5445#define M_FW_IQ_CMD_FL0PADEN 0x1 5446#define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5447#define G_FW_IQ_CMD_FL0PADEN(x) \ 5448 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5449#define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5450 5451#define S_FW_IQ_CMD_FL0PACKEN 1 5452#define M_FW_IQ_CMD_FL0PACKEN 0x1 5453#define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5454#define G_FW_IQ_CMD_FL0PACKEN(x) \ 5455 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5456#define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5457 5458#define S_FW_IQ_CMD_FL0CONGEN 0 5459#define M_FW_IQ_CMD_FL0CONGEN 0x1 5460#define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5461#define G_FW_IQ_CMD_FL0CONGEN(x) \ 5462 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5463#define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5464 5465#define S_FW_IQ_CMD_FL0DCAEN 15 5466#define M_FW_IQ_CMD_FL0DCAEN 0x1 5467#define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5468#define G_FW_IQ_CMD_FL0DCAEN(x) \ 5469 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5470#define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5471 5472#define S_FW_IQ_CMD_FL0DCACPU 10 5473#define M_FW_IQ_CMD_FL0DCACPU 0x1f 5474#define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5475#define G_FW_IQ_CMD_FL0DCACPU(x) \ 5476 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5477 5478#define S_FW_IQ_CMD_FL0FBMIN 7 5479#define M_FW_IQ_CMD_FL0FBMIN 0x7 5480#define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5481#define G_FW_IQ_CMD_FL0FBMIN(x) \ 5482 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5483 5484#define S_FW_IQ_CMD_FL0FBMAX 4 5485#define M_FW_IQ_CMD_FL0FBMAX 0x7 5486#define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5487#define G_FW_IQ_CMD_FL0FBMAX(x) \ 5488 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5489 5490#define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5491#define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5492#define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5493#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5494 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5495#define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5496 5497#define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5498#define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5499#define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5500#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5501 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5502 5503#define S_FW_IQ_CMD_FL1CNGCHMAP 20 5504#define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5505#define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5506#define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5507 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5508 5509#define S_FW_IQ_CMD_FL1CONGDROP 16 5510#define M_FW_IQ_CMD_FL1CONGDROP 0x1 5511#define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5512#define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5513 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5514#define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5515 5516#define S_FW_IQ_CMD_FL1CACHELOCK 15 5517#define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5518#define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5519#define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5520 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5521#define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5522 5523#define S_FW_IQ_CMD_FL1DBP 14 5524#define M_FW_IQ_CMD_FL1DBP 0x1 5525#define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5526#define G_FW_IQ_CMD_FL1DBP(x) \ 5527 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5528#define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5529 5530#define S_FW_IQ_CMD_FL1DATANS 13 5531#define M_FW_IQ_CMD_FL1DATANS 0x1 5532#define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5533#define G_FW_IQ_CMD_FL1DATANS(x) \ 5534 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5535#define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5536 5537#define S_FW_IQ_CMD_FL1DATARO 12 5538#define M_FW_IQ_CMD_FL1DATARO 0x1 5539#define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5540#define G_FW_IQ_CMD_FL1DATARO(x) \ 5541 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5542#define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5543 5544#define S_FW_IQ_CMD_FL1CONGCIF 11 5545#define M_FW_IQ_CMD_FL1CONGCIF 0x1 5546#define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5547#define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5548 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5549#define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5550 5551#define S_FW_IQ_CMD_FL1ONCHIP 10 5552#define M_FW_IQ_CMD_FL1ONCHIP 0x1 5553#define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5554#define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5555 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5556#define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5557 5558#define S_FW_IQ_CMD_FL1STATUSPGNS 9 5559#define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5560#define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5561#define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5562 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5563#define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5564 5565#define S_FW_IQ_CMD_FL1STATUSPGRO 8 5566#define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5567#define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5568#define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5569 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5570#define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5571 5572#define S_FW_IQ_CMD_FL1FETCHNS 7 5573#define M_FW_IQ_CMD_FL1FETCHNS 0x1 5574#define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5575#define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5576 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5577#define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5578 5579#define S_FW_IQ_CMD_FL1FETCHRO 6 5580#define M_FW_IQ_CMD_FL1FETCHRO 0x1 5581#define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5582#define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5583 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5584#define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5585 5586#define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5587#define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5588#define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5589#define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5590 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5591 5592#define S_FW_IQ_CMD_FL1CPRIO 3 5593#define M_FW_IQ_CMD_FL1CPRIO 0x1 5594#define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5595#define G_FW_IQ_CMD_FL1CPRIO(x) \ 5596 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5597#define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5598 5599#define S_FW_IQ_CMD_FL1PADEN 2 5600#define M_FW_IQ_CMD_FL1PADEN 0x1 5601#define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5602#define G_FW_IQ_CMD_FL1PADEN(x) \ 5603 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5604#define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5605 5606#define S_FW_IQ_CMD_FL1PACKEN 1 5607#define M_FW_IQ_CMD_FL1PACKEN 0x1 5608#define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5609#define G_FW_IQ_CMD_FL1PACKEN(x) \ 5610 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5611#define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5612 5613#define S_FW_IQ_CMD_FL1CONGEN 0 5614#define M_FW_IQ_CMD_FL1CONGEN 0x1 5615#define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5616#define G_FW_IQ_CMD_FL1CONGEN(x) \ 5617 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5618#define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5619 5620#define S_FW_IQ_CMD_FL1DCAEN 15 5621#define M_FW_IQ_CMD_FL1DCAEN 0x1 5622#define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5623#define G_FW_IQ_CMD_FL1DCAEN(x) \ 5624 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5625#define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5626 5627#define S_FW_IQ_CMD_FL1DCACPU 10 5628#define M_FW_IQ_CMD_FL1DCACPU 0x1f 5629#define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5630#define G_FW_IQ_CMD_FL1DCACPU(x) \ 5631 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5632 5633#define S_FW_IQ_CMD_FL1FBMIN 7 5634#define M_FW_IQ_CMD_FL1FBMIN 0x7 5635#define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5636#define G_FW_IQ_CMD_FL1FBMIN(x) \ 5637 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5638 5639#define S_FW_IQ_CMD_FL1FBMAX 4 5640#define M_FW_IQ_CMD_FL1FBMAX 0x7 5641#define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5642#define G_FW_IQ_CMD_FL1FBMAX(x) \ 5643 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5644 5645#define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5646#define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5647#define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5648#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5649 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5650#define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5651 5652#define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5653#define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5654#define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5655#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5656 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5657 5658struct fw_eq_mngt_cmd { 5659 __be32 op_to_vfn; 5660 __be32 alloc_to_len16; 5661 __be32 cmpliqid_eqid; 5662 __be32 physeqid_pkd; 5663 __be32 fetchszm_to_iqid; 5664 __be32 dcaen_to_eqsize; 5665 __be64 eqaddr; 5666}; 5667 5668#define S_FW_EQ_MNGT_CMD_PFN 8 5669#define M_FW_EQ_MNGT_CMD_PFN 0x7 5670#define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5671#define G_FW_EQ_MNGT_CMD_PFN(x) \ 5672 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5673 5674#define S_FW_EQ_MNGT_CMD_VFN 0 5675#define M_FW_EQ_MNGT_CMD_VFN 0xff 5676#define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5677#define G_FW_EQ_MNGT_CMD_VFN(x) \ 5678 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5679 5680#define S_FW_EQ_MNGT_CMD_ALLOC 31 5681#define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5682#define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5683#define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5684 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5685#define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5686 5687#define S_FW_EQ_MNGT_CMD_FREE 30 5688#define M_FW_EQ_MNGT_CMD_FREE 0x1 5689#define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5690#define G_FW_EQ_MNGT_CMD_FREE(x) \ 5691 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5692#define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5693 5694#define S_FW_EQ_MNGT_CMD_MODIFY 29 5695#define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5696#define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5697#define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5698 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5699#define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5700 5701#define S_FW_EQ_MNGT_CMD_EQSTART 28 5702#define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5703#define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5704#define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5705 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5706#define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5707 5708#define S_FW_EQ_MNGT_CMD_EQSTOP 27 5709#define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5710#define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5711#define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5712 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5713#define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5714 5715#define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5716#define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5717#define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5718#define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5719 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5720 5721#define S_FW_EQ_MNGT_CMD_EQID 0 5722#define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5723#define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5724#define G_FW_EQ_MNGT_CMD_EQID(x) \ 5725 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5726 5727#define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5728#define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5729#define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5730#define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5731 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5732 5733#define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5734#define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5735#define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5736#define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5737 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5738#define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5739 5740#define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5741#define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5742#define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5743#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5744 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5745#define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5746 5747#define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5748#define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5749#define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5750#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5751 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5752#define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5753 5754#define S_FW_EQ_MNGT_CMD_FETCHNS 23 5755#define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5756#define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5757#define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5758 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5759#define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5760 5761#define S_FW_EQ_MNGT_CMD_FETCHRO 22 5762#define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5763#define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5764#define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5765 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5766#define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5767 5768#define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5769#define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5770#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5771#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5772 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5773 5774#define S_FW_EQ_MNGT_CMD_CPRIO 19 5775#define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5776#define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5777#define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5778 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5779#define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5780 5781#define S_FW_EQ_MNGT_CMD_ONCHIP 18 5782#define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5783#define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5784#define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5785 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5786#define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5787 5788#define S_FW_EQ_MNGT_CMD_PCIECHN 16 5789#define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5790#define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5791#define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5792 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5793 5794#define S_FW_EQ_MNGT_CMD_IQID 0 5795#define M_FW_EQ_MNGT_CMD_IQID 0xffff 5796#define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5797#define G_FW_EQ_MNGT_CMD_IQID(x) \ 5798 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5799 5800#define S_FW_EQ_MNGT_CMD_DCAEN 31 5801#define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5802#define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5803#define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5804 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5805#define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5806 5807#define S_FW_EQ_MNGT_CMD_DCACPU 26 5808#define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5809#define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5810#define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5811 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5812 5813#define S_FW_EQ_MNGT_CMD_FBMIN 23 5814#define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5815#define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5816#define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5817 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5818 5819#define S_FW_EQ_MNGT_CMD_FBMAX 20 5820#define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5821#define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5822#define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5823 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5824 5825#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5826#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5827#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5828 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5829#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5830 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5831#define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5832 5833#define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5834#define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5835#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5836#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5837 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5838 5839#define S_FW_EQ_MNGT_CMD_EQSIZE 0 5840#define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5841#define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5842#define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5843 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5844 5845struct fw_eq_eth_cmd { 5846 __be32 op_to_vfn; 5847 __be32 alloc_to_len16; 5848 __be32 eqid_pkd; 5849 __be32 physeqid_pkd; 5850 __be32 fetchszm_to_iqid; 5851 __be32 dcaen_to_eqsize; 5852 __be64 eqaddr; 5853 __be32 autoequiqe_to_viid; 5854 __be32 r8_lo; 5855 __be64 r9; 5856}; 5857 5858#define S_FW_EQ_ETH_CMD_PFN 8 5859#define M_FW_EQ_ETH_CMD_PFN 0x7 5860#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5861#define G_FW_EQ_ETH_CMD_PFN(x) \ 5862 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5863 5864#define S_FW_EQ_ETH_CMD_VFN 0 5865#define M_FW_EQ_ETH_CMD_VFN 0xff 5866#define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5867#define G_FW_EQ_ETH_CMD_VFN(x) \ 5868 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5869 5870#define S_FW_EQ_ETH_CMD_ALLOC 31 5871#define M_FW_EQ_ETH_CMD_ALLOC 0x1 5872#define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5873#define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5874 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5875#define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5876 5877#define S_FW_EQ_ETH_CMD_FREE 30 5878#define M_FW_EQ_ETH_CMD_FREE 0x1 5879#define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5880#define G_FW_EQ_ETH_CMD_FREE(x) \ 5881 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5882#define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5883 5884#define S_FW_EQ_ETH_CMD_MODIFY 29 5885#define M_FW_EQ_ETH_CMD_MODIFY 0x1 5886#define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5887#define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5888 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5889#define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5890 5891#define S_FW_EQ_ETH_CMD_EQSTART 28 5892#define M_FW_EQ_ETH_CMD_EQSTART 0x1 5893#define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5894#define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5895 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5896#define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5897 5898#define S_FW_EQ_ETH_CMD_EQSTOP 27 5899#define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5900#define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5901#define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5902 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5903#define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5904 5905#define S_FW_EQ_ETH_CMD_EQID 0 5906#define M_FW_EQ_ETH_CMD_EQID 0xfffff 5907#define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5908#define G_FW_EQ_ETH_CMD_EQID(x) \ 5909 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5910 5911#define S_FW_EQ_ETH_CMD_PHYSEQID 0 5912#define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5913#define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5914#define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5915 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5916 5917#define S_FW_EQ_ETH_CMD_FETCHSZM 26 5918#define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5919#define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5920#define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5921 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5922#define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5923 5924#define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5925#define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5926#define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5927#define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5928 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5929#define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5930 5931#define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5932#define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5933#define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5934#define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5935 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5936#define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5937 5938#define S_FW_EQ_ETH_CMD_FETCHNS 23 5939#define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5940#define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5941#define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5942 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5943#define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5944 5945#define S_FW_EQ_ETH_CMD_FETCHRO 22 5946#define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5947#define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5948#define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5949 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5950#define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5951 5952#define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5953#define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5954#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5955#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5956 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5957 5958#define S_FW_EQ_ETH_CMD_CPRIO 19 5959#define M_FW_EQ_ETH_CMD_CPRIO 0x1 5960#define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5961#define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5962 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5963#define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5964 5965#define S_FW_EQ_ETH_CMD_ONCHIP 18 5966#define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5967#define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5968#define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5969 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5970#define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5971 5972#define S_FW_EQ_ETH_CMD_PCIECHN 16 5973#define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5974#define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5975#define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5976 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5977 5978#define S_FW_EQ_ETH_CMD_IQID 0 5979#define M_FW_EQ_ETH_CMD_IQID 0xffff 5980#define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5981#define G_FW_EQ_ETH_CMD_IQID(x) \ 5982 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5983 5984#define S_FW_EQ_ETH_CMD_DCAEN 31 5985#define M_FW_EQ_ETH_CMD_DCAEN 0x1 5986#define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5987#define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5988 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5989#define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5990 5991#define S_FW_EQ_ETH_CMD_DCACPU 26 5992#define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5993#define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5994#define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5995 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5996 5997#define S_FW_EQ_ETH_CMD_FBMIN 23 5998#define M_FW_EQ_ETH_CMD_FBMIN 0x7 5999#define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 6000#define G_FW_EQ_ETH_CMD_FBMIN(x) \ 6001 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 6002 6003#define S_FW_EQ_ETH_CMD_FBMAX 20 6004#define M_FW_EQ_ETH_CMD_FBMAX 0x7 6005#define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 6006#define G_FW_EQ_ETH_CMD_FBMAX(x) \ 6007 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 6008 6009#define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 6010#define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 6011#define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6012#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 6013 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6014#define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 6015 6016#define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 6017#define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 6018#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 6019#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 6020 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 6021 6022#define S_FW_EQ_ETH_CMD_EQSIZE 0 6023#define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 6024#define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 6025#define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 6026 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 6027 6028#define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 6029#define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 6030#define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 6031#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 6032 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 6033#define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 6034 6035#define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 6036#define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 6037#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 6038#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 6039 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 6040#define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 6041 6042#define S_FW_EQ_ETH_CMD_VIID 16 6043#define M_FW_EQ_ETH_CMD_VIID 0xfff 6044#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 6045#define G_FW_EQ_ETH_CMD_VIID(x) \ 6046 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 6047 6048struct fw_eq_ctrl_cmd { 6049 __be32 op_to_vfn; 6050 __be32 alloc_to_len16; 6051 __be32 cmpliqid_eqid; 6052 __be32 physeqid_pkd; 6053 __be32 fetchszm_to_iqid; 6054 __be32 dcaen_to_eqsize; 6055 __be64 eqaddr; 6056}; 6057 6058#define S_FW_EQ_CTRL_CMD_PFN 8 6059#define M_FW_EQ_CTRL_CMD_PFN 0x7 6060#define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 6061#define G_FW_EQ_CTRL_CMD_PFN(x) \ 6062 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 6063 6064#define S_FW_EQ_CTRL_CMD_VFN 0 6065#define M_FW_EQ_CTRL_CMD_VFN 0xff 6066#define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 6067#define G_FW_EQ_CTRL_CMD_VFN(x) \ 6068 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 6069 6070#define S_FW_EQ_CTRL_CMD_ALLOC 31 6071#define M_FW_EQ_CTRL_CMD_ALLOC 0x1 6072#define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 6073#define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 6074 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 6075#define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 6076 6077#define S_FW_EQ_CTRL_CMD_FREE 30 6078#define M_FW_EQ_CTRL_CMD_FREE 0x1 6079#define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 6080#define G_FW_EQ_CTRL_CMD_FREE(x) \ 6081 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 6082#define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 6083 6084#define S_FW_EQ_CTRL_CMD_MODIFY 29 6085#define M_FW_EQ_CTRL_CMD_MODIFY 0x1 6086#define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 6087#define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 6088 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 6089#define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 6090 6091#define S_FW_EQ_CTRL_CMD_EQSTART 28 6092#define M_FW_EQ_CTRL_CMD_EQSTART 0x1 6093#define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 6094#define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 6095 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 6096#define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 6097 6098#define S_FW_EQ_CTRL_CMD_EQSTOP 27 6099#define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 6100#define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 6101#define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 6102 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 6103#define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 6104 6105#define S_FW_EQ_CTRL_CMD_CMPLIQID 20 6106#define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 6107#define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 6108#define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 6109 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 6110 6111#define S_FW_EQ_CTRL_CMD_EQID 0 6112#define M_FW_EQ_CTRL_CMD_EQID 0xfffff 6113#define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 6114#define G_FW_EQ_CTRL_CMD_EQID(x) \ 6115 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 6116 6117#define S_FW_EQ_CTRL_CMD_PHYSEQID 0 6118#define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 6119#define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 6120#define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 6121 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 6122 6123#define S_FW_EQ_CTRL_CMD_FETCHSZM 26 6124#define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 6125#define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 6126#define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 6127 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 6128#define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 6129 6130#define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 6131#define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 6132#define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 6133#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 6134 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 6135#define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 6136 6137#define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 6138#define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 6139#define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 6140#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 6141 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 6142#define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 6143 6144#define S_FW_EQ_CTRL_CMD_FETCHNS 23 6145#define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 6146#define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 6147#define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 6148 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 6149#define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 6150 6151#define S_FW_EQ_CTRL_CMD_FETCHRO 22 6152#define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 6153#define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 6154#define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 6155 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 6156#define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 6157 6158#define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 6159#define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 6160#define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 6161#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 6162 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 6163 6164#define S_FW_EQ_CTRL_CMD_CPRIO 19 6165#define M_FW_EQ_CTRL_CMD_CPRIO 0x1 6166#define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 6167#define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 6168 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 6169#define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 6170 6171#define S_FW_EQ_CTRL_CMD_ONCHIP 18 6172#define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 6173#define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 6174#define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 6175 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 6176#define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 6177 6178#define S_FW_EQ_CTRL_CMD_PCIECHN 16 6179#define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 6180#define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 6181#define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 6182 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 6183 6184#define S_FW_EQ_CTRL_CMD_IQID 0 6185#define M_FW_EQ_CTRL_CMD_IQID 0xffff 6186#define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 6187#define G_FW_EQ_CTRL_CMD_IQID(x) \ 6188 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 6189 6190#define S_FW_EQ_CTRL_CMD_DCAEN 31 6191#define M_FW_EQ_CTRL_CMD_DCAEN 0x1 6192#define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 6193#define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 6194 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 6195#define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 6196 6197#define S_FW_EQ_CTRL_CMD_DCACPU 26 6198#define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 6199#define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 6200#define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 6201 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6202 6203#define S_FW_EQ_CTRL_CMD_FBMIN 23 6204#define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6205#define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6206#define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6207 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6208 6209#define S_FW_EQ_CTRL_CMD_FBMAX 20 6210#define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6211#define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6212#define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6213 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6214 6215#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6216#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6217#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6218 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6219#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6220 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6221#define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6222 6223#define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6224#define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6225#define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6226#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6227 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6228 6229#define S_FW_EQ_CTRL_CMD_EQSIZE 0 6230#define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6231#define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6232#define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6233 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 6234 6235struct fw_eq_ofld_cmd { 6236 __be32 op_to_vfn; 6237 __be32 alloc_to_len16; 6238 __be32 eqid_pkd; 6239 __be32 physeqid_pkd; 6240 __be32 fetchszm_to_iqid; 6241 __be32 dcaen_to_eqsize; 6242 __be64 eqaddr; 6243}; 6244 6245#define S_FW_EQ_OFLD_CMD_PFN 8 6246#define M_FW_EQ_OFLD_CMD_PFN 0x7 6247#define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6248#define G_FW_EQ_OFLD_CMD_PFN(x) \ 6249 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6250 6251#define S_FW_EQ_OFLD_CMD_VFN 0 6252#define M_FW_EQ_OFLD_CMD_VFN 0xff 6253#define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6254#define G_FW_EQ_OFLD_CMD_VFN(x) \ 6255 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6256 6257#define S_FW_EQ_OFLD_CMD_ALLOC 31 6258#define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6259#define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6260#define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6261 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6262#define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6263 6264#define S_FW_EQ_OFLD_CMD_FREE 30 6265#define M_FW_EQ_OFLD_CMD_FREE 0x1 6266#define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6267#define G_FW_EQ_OFLD_CMD_FREE(x) \ 6268 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6269#define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6270 6271#define S_FW_EQ_OFLD_CMD_MODIFY 29 6272#define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6273#define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6274#define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6275 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6276#define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6277 6278#define S_FW_EQ_OFLD_CMD_EQSTART 28 6279#define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6280#define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6281#define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6282 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6283#define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6284 6285#define S_FW_EQ_OFLD_CMD_EQSTOP 27 6286#define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6287#define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6288#define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6289 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6290#define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6291 6292#define S_FW_EQ_OFLD_CMD_EQID 0 6293#define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6294#define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6295#define G_FW_EQ_OFLD_CMD_EQID(x) \ 6296 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6297 6298#define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6299#define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6300#define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6301#define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6302 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6303 6304#define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6305#define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6306#define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6307#define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6308 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6309#define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6310 6311#define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6312#define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6313#define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6314#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6315 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6316#define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6317 6318#define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6319#define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6320#define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6321#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6322 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6323#define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6324 6325#define S_FW_EQ_OFLD_CMD_FETCHNS 23 6326#define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6327#define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6328#define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6329 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6330#define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6331 6332#define S_FW_EQ_OFLD_CMD_FETCHRO 22 6333#define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6334#define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6335#define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6336 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6337#define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6338 6339#define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6340#define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6341#define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6342#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6343 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6344 6345#define S_FW_EQ_OFLD_CMD_CPRIO 19 6346#define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6347#define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6348#define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6349 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6350#define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6351 6352#define S_FW_EQ_OFLD_CMD_ONCHIP 18 6353#define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6354#define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6355#define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6356 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6357#define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6358 6359#define S_FW_EQ_OFLD_CMD_PCIECHN 16 6360#define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6361#define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6362#define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6363 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6364 6365#define S_FW_EQ_OFLD_CMD_IQID 0 6366#define M_FW_EQ_OFLD_CMD_IQID 0xffff 6367#define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6368#define G_FW_EQ_OFLD_CMD_IQID(x) \ 6369 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6370 6371#define S_FW_EQ_OFLD_CMD_DCAEN 31 6372#define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6373#define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6374#define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6375 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6376#define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6377 6378#define S_FW_EQ_OFLD_CMD_DCACPU 26 6379#define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6380#define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6381#define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6382 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6383 6384#define S_FW_EQ_OFLD_CMD_FBMIN 23 6385#define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6386#define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6387#define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6388 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6389 6390#define S_FW_EQ_OFLD_CMD_FBMAX 20 6391#define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6392#define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6393#define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6394 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6395 6396#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6397#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6398#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6399 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6400#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6401 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6402#define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6403 6404#define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6405#define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6406#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6407#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6408 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6409 6410#define S_FW_EQ_OFLD_CMD_EQSIZE 0 6411#define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6412#define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6413#define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6414 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6415 6416/* Macros for VIID parsing: 6417 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6418#define S_FW_VIID_PFN 8 6419#define M_FW_VIID_PFN 0x7 6420#define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6421#define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6422 6423#define S_FW_VIID_VIVLD 7 6424#define M_FW_VIID_VIVLD 0x1 6425#define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6426#define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6427 6428#define S_FW_VIID_VIN 0 6429#define M_FW_VIID_VIN 0x7F 6430#define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6431#define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 6432 6433/* Macros for VIID parsing: 6434 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */ 6435#define S_FW_256VIID_PFN 9 6436#define M_FW_256VIID_PFN 0x7 6437#define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN) 6438#define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN) 6439 6440#define S_FW_256VIID_VIVLD 8 6441#define M_FW_256VIID_VIVLD 0x1 6442#define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD) 6443#define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD) 6444 6445#define S_FW_256VIID_VIN 0 6446#define M_FW_256VIID_VIN 0xFF 6447#define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN) 6448#define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN) 6449 6450enum fw_vi_func { 6451 FW_VI_FUNC_ETH, 6452 FW_VI_FUNC_OFLD, 6453 FW_VI_FUNC_IWARP, 6454 FW_VI_FUNC_OPENISCSI, 6455 FW_VI_FUNC_OPENFCOE, 6456 FW_VI_FUNC_FOISCSI, 6457 FW_VI_FUNC_FOFCOE, 6458 FW_VI_FUNC_FW, 6459}; 6460 6461struct fw_vi_cmd { 6462 __be32 op_to_vfn; 6463 __be32 alloc_to_len16; 6464 __be16 type_to_viid; 6465 __u8 mac[6]; 6466 __u8 portid_pkd; 6467 __u8 nmac; 6468 __u8 nmac0[6]; 6469 __be16 norss_rsssize; 6470 __u8 nmac1[6]; 6471 __be16 idsiiq_pkd; 6472 __u8 nmac2[6]; 6473 __be16 idseiq_pkd; 6474 __u8 nmac3[6]; 6475 __be64 r9; 6476 __be64 r10; 6477}; 6478 6479#define S_FW_VI_CMD_PFN 8 6480#define M_FW_VI_CMD_PFN 0x7 6481#define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6482#define G_FW_VI_CMD_PFN(x) \ 6483 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6484 6485#define S_FW_VI_CMD_VFN 0 6486#define M_FW_VI_CMD_VFN 0xff 6487#define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6488#define G_FW_VI_CMD_VFN(x) \ 6489 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6490 6491#define S_FW_VI_CMD_ALLOC 31 6492#define M_FW_VI_CMD_ALLOC 0x1 6493#define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6494#define G_FW_VI_CMD_ALLOC(x) \ 6495 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6496#define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6497 6498#define S_FW_VI_CMD_FREE 30 6499#define M_FW_VI_CMD_FREE 0x1 6500#define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6501#define G_FW_VI_CMD_FREE(x) \ 6502 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6503#define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6504 6505#define S_FW_VI_CMD_TYPE 15 6506#define M_FW_VI_CMD_TYPE 0x1 6507#define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6508#define G_FW_VI_CMD_TYPE(x) \ 6509 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6510#define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6511 6512#define S_FW_VI_CMD_FUNC 12 6513#define M_FW_VI_CMD_FUNC 0x7 6514#define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6515#define G_FW_VI_CMD_FUNC(x) \ 6516 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6517 6518#define S_FW_VI_CMD_VIID 0 6519#define M_FW_VI_CMD_VIID 0xfff 6520#define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6521#define G_FW_VI_CMD_VIID(x) \ 6522 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6523 6524#define S_FW_VI_CMD_PORTID 4 6525#define M_FW_VI_CMD_PORTID 0xf 6526#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6527#define G_FW_VI_CMD_PORTID(x) \ 6528 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6529 6530#define S_FW_VI_CMD_NORSS 11 6531#define M_FW_VI_CMD_NORSS 0x1 6532#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6533#define G_FW_VI_CMD_NORSS(x) \ 6534 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6535#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6536 6537#define S_FW_VI_CMD_RSSSIZE 0 6538#define M_FW_VI_CMD_RSSSIZE 0x7ff 6539#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6540#define G_FW_VI_CMD_RSSSIZE(x) \ 6541 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6542 6543#define S_FW_VI_CMD_IDSIIQ 0 6544#define M_FW_VI_CMD_IDSIIQ 0x3ff 6545#define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6546#define G_FW_VI_CMD_IDSIIQ(x) \ 6547 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6548 6549#define S_FW_VI_CMD_IDSEIQ 0 6550#define M_FW_VI_CMD_IDSEIQ 0x3ff 6551#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6552#define G_FW_VI_CMD_IDSEIQ(x) \ 6553 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 6554 6555/* Special VI_MAC command index ids */ 6556#define FW_VI_MAC_ADD_MAC 0x3FF 6557#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6558#define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6559#define FW_VI_MAC_ID_BASED_FREE 0x3FC 6560 6561enum fw_vi_mac_smac { 6562 FW_VI_MAC_MPS_TCAM_ENTRY, 6563 FW_VI_MAC_MPS_TCAM_ONLY, 6564 FW_VI_MAC_SMT_ONLY, 6565 FW_VI_MAC_SMT_AND_MPSTCAM 6566}; 6567 6568enum fw_vi_mac_result { 6569 FW_VI_MAC_R_SUCCESS, 6570 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 6571 FW_VI_MAC_R_SMAC_FAIL, 6572 FW_VI_MAC_R_F_ACL_CHECK 6573}; 6574 6575enum fw_vi_mac_entry_types { 6576 FW_VI_MAC_TYPE_EXACTMAC, 6577 FW_VI_MAC_TYPE_HASHVEC, 6578 FW_VI_MAC_TYPE_RAW, 6579 FW_VI_MAC_TYPE_EXACTMAC_VNI, 6580}; 6581 6582struct fw_vi_mac_cmd { 6583 __be32 op_to_viid; 6584 __be32 freemacs_to_len16; 6585 union fw_vi_mac { 6586 struct fw_vi_mac_exact { 6587 __be16 valid_to_idx; 6588 __u8 macaddr[6]; 6589 } exact[7]; 6590 struct fw_vi_mac_hash { 6591 __be64 hashvec; 6592 } hash; 6593 struct fw_vi_mac_raw { 6594 __be32 raw_idx_pkd; 6595 __be32 data0_pkd; 6596 __be32 data1[2]; 6597 __be64 data0m_pkd; 6598 __be32 data1m[2]; 6599 } raw; 6600 struct fw_vi_mac_vni { 6601 __be16 valid_to_idx; 6602 __u8 macaddr[6]; 6603 __be16 r7; 6604 __u8 macaddr_mask[6]; 6605 __be32 lookup_type_to_vni; 6606 __be32 vni_mask_pkd; 6607 } exact_vni[2]; 6608 } u; 6609}; 6610 6611#define S_FW_VI_MAC_CMD_VIID 0 6612#define M_FW_VI_MAC_CMD_VIID 0xfff 6613#define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6614#define G_FW_VI_MAC_CMD_VIID(x) \ 6615 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6616 6617#define S_FW_VI_MAC_CMD_FREEMACS 31 6618#define M_FW_VI_MAC_CMD_FREEMACS 0x1 6619#define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6620#define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6621 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6622#define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6623 6624#define S_FW_VI_MAC_CMD_IS_SMAC 30 6625#define M_FW_VI_MAC_CMD_IS_SMAC 0x1 6626#define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC) 6627#define G_FW_VI_MAC_CMD_IS_SMAC(x) \ 6628 (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC) 6629#define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U) 6630 6631#define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6632#define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6633#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6634#define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6635 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6636 6637#define S_FW_VI_MAC_CMD_HASHUNIEN 22 6638#define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6639#define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6640#define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6641 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6642#define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6643 6644#define S_FW_VI_MAC_CMD_VALID 15 6645#define M_FW_VI_MAC_CMD_VALID 0x1 6646#define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6647#define G_FW_VI_MAC_CMD_VALID(x) \ 6648 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6649#define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6650 6651#define S_FW_VI_MAC_CMD_PRIO 12 6652#define M_FW_VI_MAC_CMD_PRIO 0x7 6653#define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6654#define G_FW_VI_MAC_CMD_PRIO(x) \ 6655 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6656 6657#define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6658#define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6659#define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6660#define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6661 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6662 6663#define S_FW_VI_MAC_CMD_IDX 0 6664#define M_FW_VI_MAC_CMD_IDX 0x3ff 6665#define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6666#define G_FW_VI_MAC_CMD_IDX(x) \ 6667 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6668 6669#define S_FW_VI_MAC_CMD_RAW_IDX 16 6670#define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6671#define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6672#define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6673 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6674 6675#define S_FW_VI_MAC_CMD_DATA0 0 6676#define M_FW_VI_MAC_CMD_DATA0 0xffff 6677#define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6678#define G_FW_VI_MAC_CMD_DATA0(x) \ 6679 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6680 6681#define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 6682#define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 6683#define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 6684#define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 6685 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 6686#define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 6687 6688#define S_FW_VI_MAC_CMD_DIP_HIT 30 6689#define M_FW_VI_MAC_CMD_DIP_HIT 0x1 6690#define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 6691#define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 6692 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 6693#define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 6694 6695#define S_FW_VI_MAC_CMD_VNI 0 6696#define M_FW_VI_MAC_CMD_VNI 0xffffff 6697#define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 6698#define G_FW_VI_MAC_CMD_VNI(x) \ 6699 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 6700 6701/* Extracting loopback port number passed from driver. 6702 * as a part of fw_vi_mac_vni For non loopback entries 6703 * ignore the field and update port number from flowc. 6704 * Fw will ignore if physical port number received. 6705 * expected range (4-7). 6706 */ 6707 6708#define S_FW_VI_MAC_CMD_PORT 24 6709#define M_FW_VI_MAC_CMD_PORT 0x7 6710#define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT) 6711#define G_FW_VI_MAC_CMD_PORT(x) \ 6712 (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT) 6713 6714#define S_FW_VI_MAC_CMD_VNI_MASK 0 6715#define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 6716#define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 6717#define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 6718 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 6719 6720/* T4 max MTU supported */ 6721#define T4_MAX_MTU_SUPPORTED 9600 6722#define FW_RXMODE_MTU_NO_CHG 65535 6723 6724struct fw_vi_rxmode_cmd { 6725 __be32 op_to_viid; 6726 __be32 retval_len16; 6727 __be32 mtu_to_vlanexen; 6728 __be32 r4_lo; 6729}; 6730 6731#define S_FW_VI_RXMODE_CMD_VIID 0 6732#define M_FW_VI_RXMODE_CMD_VIID 0xfff 6733#define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6734#define G_FW_VI_RXMODE_CMD_VIID(x) \ 6735 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6736 6737#define S_FW_VI_RXMODE_CMD_MTU 16 6738#define M_FW_VI_RXMODE_CMD_MTU 0xffff 6739#define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6740#define G_FW_VI_RXMODE_CMD_MTU(x) \ 6741 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6742 6743#define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6744#define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6745#define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6746#define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6747 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6748 6749#define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6750#define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6751#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6752 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6753#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6754 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6755 6756#define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6757#define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6758#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6759 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6760#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6761 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6762 6763#define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6764#define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6765#define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6766#define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6767 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6768 6769struct fw_vi_enable_cmd { 6770 __be32 op_to_viid; 6771 __be32 ien_to_len16; 6772 __be16 blinkdur; 6773 __be16 r3; 6774 __be32 r4; 6775}; 6776 6777#define S_FW_VI_ENABLE_CMD_VIID 0 6778#define M_FW_VI_ENABLE_CMD_VIID 0xfff 6779#define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6780#define G_FW_VI_ENABLE_CMD_VIID(x) \ 6781 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6782 6783#define S_FW_VI_ENABLE_CMD_IEN 31 6784#define M_FW_VI_ENABLE_CMD_IEN 0x1 6785#define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6786#define G_FW_VI_ENABLE_CMD_IEN(x) \ 6787 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6788#define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6789 6790#define S_FW_VI_ENABLE_CMD_EEN 30 6791#define M_FW_VI_ENABLE_CMD_EEN 0x1 6792#define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6793#define G_FW_VI_ENABLE_CMD_EEN(x) \ 6794 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6795#define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6796 6797#define S_FW_VI_ENABLE_CMD_LED 29 6798#define M_FW_VI_ENABLE_CMD_LED 0x1 6799#define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6800#define G_FW_VI_ENABLE_CMD_LED(x) \ 6801 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6802#define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6803 6804#define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6805#define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6806#define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6807#define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6808 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6809#define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6810 6811/* VI VF stats offset definitions */ 6812#define VI_VF_NUM_STATS 16 6813enum fw_vi_stats_vf_index { 6814 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6815 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6816 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6817 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6818 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6819 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6820 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6821 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6822 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6823 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6824 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6825 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6826 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6827 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6828 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6829 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6830}; 6831 6832/* VI PF stats offset definitions */ 6833#define VI_PF_NUM_STATS 17 6834enum fw_vi_stats_pf_index { 6835 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6836 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6837 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6838 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6839 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6840 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6841 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6842 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6843 FW_VI_PF_STAT_RX_BYTES_IX, 6844 FW_VI_PF_STAT_RX_FRAMES_IX, 6845 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6846 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6847 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6848 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6849 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6850 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6851 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6852}; 6853 6854struct fw_vi_stats_cmd { 6855 __be32 op_to_viid; 6856 __be32 retval_len16; 6857 union fw_vi_stats { 6858 struct fw_vi_stats_ctl { 6859 __be16 nstats_ix; 6860 __be16 r6; 6861 __be32 r7; 6862 __be64 stat0; 6863 __be64 stat1; 6864 __be64 stat2; 6865 __be64 stat3; 6866 __be64 stat4; 6867 __be64 stat5; 6868 } ctl; 6869 struct fw_vi_stats_pf { 6870 __be64 tx_bcast_bytes; 6871 __be64 tx_bcast_frames; 6872 __be64 tx_mcast_bytes; 6873 __be64 tx_mcast_frames; 6874 __be64 tx_ucast_bytes; 6875 __be64 tx_ucast_frames; 6876 __be64 tx_offload_bytes; 6877 __be64 tx_offload_frames; 6878 __be64 rx_pf_bytes; 6879 __be64 rx_pf_frames; 6880 __be64 rx_bcast_bytes; 6881 __be64 rx_bcast_frames; 6882 __be64 rx_mcast_bytes; 6883 __be64 rx_mcast_frames; 6884 __be64 rx_ucast_bytes; 6885 __be64 rx_ucast_frames; 6886 __be64 rx_err_frames; 6887 } pf; 6888 struct fw_vi_stats_vf { 6889 __be64 tx_bcast_bytes; 6890 __be64 tx_bcast_frames; 6891 __be64 tx_mcast_bytes; 6892 __be64 tx_mcast_frames; 6893 __be64 tx_ucast_bytes; 6894 __be64 tx_ucast_frames; 6895 __be64 tx_drop_frames; 6896 __be64 tx_offload_bytes; 6897 __be64 tx_offload_frames; 6898 __be64 rx_bcast_bytes; 6899 __be64 rx_bcast_frames; 6900 __be64 rx_mcast_bytes; 6901 __be64 rx_mcast_frames; 6902 __be64 rx_ucast_bytes; 6903 __be64 rx_ucast_frames; 6904 __be64 rx_err_frames; 6905 } vf; 6906 } u; 6907}; 6908 6909#define S_FW_VI_STATS_CMD_VIID 0 6910#define M_FW_VI_STATS_CMD_VIID 0xfff 6911#define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6912#define G_FW_VI_STATS_CMD_VIID(x) \ 6913 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 6914 6915#define S_FW_VI_STATS_CMD_NSTATS 12 6916#define M_FW_VI_STATS_CMD_NSTATS 0x7 6917#define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6918#define G_FW_VI_STATS_CMD_NSTATS(x) \ 6919 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 6920 6921#define S_FW_VI_STATS_CMD_IX 0 6922#define M_FW_VI_STATS_CMD_IX 0x1f 6923#define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6924#define G_FW_VI_STATS_CMD_IX(x) \ 6925 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 6926 6927struct fw_acl_mac_cmd { 6928 __be32 op_to_vfn; 6929 __be32 en_to_len16; 6930 __u8 nmac; 6931 __u8 r3[7]; 6932 __be16 r4; 6933 __u8 macaddr0[6]; 6934 __be16 r5; 6935 __u8 macaddr1[6]; 6936 __be16 r6; 6937 __u8 macaddr2[6]; 6938 __be16 r7; 6939 __u8 macaddr3[6]; 6940}; 6941 6942#define S_FW_ACL_MAC_CMD_PFN 8 6943#define M_FW_ACL_MAC_CMD_PFN 0x7 6944#define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6945#define G_FW_ACL_MAC_CMD_PFN(x) \ 6946 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 6947 6948#define S_FW_ACL_MAC_CMD_VFN 0 6949#define M_FW_ACL_MAC_CMD_VFN 0xff 6950#define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6951#define G_FW_ACL_MAC_CMD_VFN(x) \ 6952 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 6953 6954#define S_FW_ACL_MAC_CMD_EN 31 6955#define M_FW_ACL_MAC_CMD_EN 0x1 6956#define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6957#define G_FW_ACL_MAC_CMD_EN(x) \ 6958 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6959#define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 6960 6961struct fw_acl_vlan_cmd { 6962 __be32 op_to_vfn; 6963 __be32 en_to_len16; 6964 __u8 nvlan; 6965 __u8 dropnovlan_fm; 6966 __u8 r3_lo[6]; 6967 __be16 vlanid[16]; 6968}; 6969 6970#define S_FW_ACL_VLAN_CMD_PFN 8 6971#define M_FW_ACL_VLAN_CMD_PFN 0x7 6972#define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6973#define G_FW_ACL_VLAN_CMD_PFN(x) \ 6974 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6975 6976#define S_FW_ACL_VLAN_CMD_VFN 0 6977#define M_FW_ACL_VLAN_CMD_VFN 0xff 6978#define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6979#define G_FW_ACL_VLAN_CMD_VFN(x) \ 6980 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 6981 6982#define S_FW_ACL_VLAN_CMD_EN 31 6983#define M_FW_ACL_VLAN_CMD_EN 0x1 6984#define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 6985#define G_FW_ACL_VLAN_CMD_EN(x) \ 6986 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 6987#define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 6988 6989#define S_FW_ACL_VLAN_CMD_TRANSPARENT 30 6990#define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1 6991#define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 6992 ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT) 6993#define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 6994 (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT) 6995#define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U) 6996 6997#define S_FW_ACL_VLAN_CMD_PMASK 16 6998#define M_FW_ACL_VLAN_CMD_PMASK 0xf 6999#define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK) 7000#define G_FW_ACL_VLAN_CMD_PMASK(x) \ 7001 (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK) 7002 7003#define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 7004#define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 7005#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 7006#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 7007 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 7008#define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 7009 7010#define S_FW_ACL_VLAN_CMD_FM 6 7011#define M_FW_ACL_VLAN_CMD_FM 0x1 7012#define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 7013#define G_FW_ACL_VLAN_CMD_FM(x) \ 7014 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 7015#define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 7016 7017/* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 7018enum fw_port_cap { 7019 FW_PORT_CAP_SPEED_100M = 0x0001, 7020 FW_PORT_CAP_SPEED_1G = 0x0002, 7021 FW_PORT_CAP_SPEED_25G = 0x0004, 7022 FW_PORT_CAP_SPEED_10G = 0x0008, 7023 FW_PORT_CAP_SPEED_40G = 0x0010, 7024 FW_PORT_CAP_SPEED_100G = 0x0020, 7025 FW_PORT_CAP_FC_RX = 0x0040, 7026 FW_PORT_CAP_FC_TX = 0x0080, 7027 FW_PORT_CAP_ANEG = 0x0100, 7028 FW_PORT_CAP_MDIAUTO = 0x0200, 7029 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 7030 FW_PORT_CAP_FEC_RS = 0x0800, 7031 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 7032 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 7033 FW_PORT_CAP_802_3_PAUSE = 0x4000, 7034 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 7035}; 7036 7037#define S_FW_PORT_CAP_SPEED 0 7038#define M_FW_PORT_CAP_SPEED 0x3f 7039#define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 7040#define G_FW_PORT_CAP_SPEED(x) \ 7041 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 7042 7043#define S_FW_PORT_CAP_FC 6 7044#define M_FW_PORT_CAP_FC 0x3 7045#define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 7046#define G_FW_PORT_CAP_FC(x) \ 7047 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 7048 7049#define S_FW_PORT_CAP_ANEG 8 7050#define M_FW_PORT_CAP_ANEG 0x1 7051#define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 7052#define G_FW_PORT_CAP_ANEG(x) \ 7053 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 7054 7055#define S_FW_PORT_CAP_FEC 11 7056#define M_FW_PORT_CAP_FEC 0x3 7057#define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 7058#define G_FW_PORT_CAP_FEC(x) \ 7059 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 7060 7061#define S_FW_PORT_CAP_FORCE_PAUSE 13 7062#define M_FW_PORT_CAP_FORCE_PAUSE 0x1 7063#define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE) 7064#define G_FW_PORT_CAP_FORCE_PAUSE(x) \ 7065 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE) 7066 7067#define S_FW_PORT_CAP_802_3 14 7068#define M_FW_PORT_CAP_802_3 0x3 7069#define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 7070#define G_FW_PORT_CAP_802_3(x) \ 7071 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 7072 7073enum fw_port_mdi { 7074 FW_PORT_CAP_MDI_UNCHANGED, 7075 FW_PORT_CAP_MDI_AUTO, 7076 FW_PORT_CAP_MDI_F_STRAIGHT, 7077 FW_PORT_CAP_MDI_F_CROSSOVER 7078}; 7079 7080#define S_FW_PORT_CAP_MDI 9 7081#define M_FW_PORT_CAP_MDI 3 7082#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 7083#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 7084 7085/* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 7086#define FW_PORT_CAP32_SPEED_100M 0x00000001UL 7087#define FW_PORT_CAP32_SPEED_1G 0x00000002UL 7088#define FW_PORT_CAP32_SPEED_10G 0x00000004UL 7089#define FW_PORT_CAP32_SPEED_25G 0x00000008UL 7090#define FW_PORT_CAP32_SPEED_40G 0x00000010UL 7091#define FW_PORT_CAP32_SPEED_50G 0x00000020UL 7092#define FW_PORT_CAP32_SPEED_100G 0x00000040UL 7093#define FW_PORT_CAP32_SPEED_200G 0x00000080UL 7094#define FW_PORT_CAP32_SPEED_400G 0x00000100UL 7095#define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 7096#define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 7097#define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 7098#define FW_PORT_CAP32_RESERVED1 0x0000f000UL 7099#define FW_PORT_CAP32_FC_RX 0x00010000UL 7100#define FW_PORT_CAP32_FC_TX 0x00020000UL 7101#define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 7102#define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 7103#define FW_PORT_CAP32_ANEG 0x00100000UL 7104#define FW_PORT_CAP32_MDIAUTO 0x00200000UL 7105#define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 7106#define FW_PORT_CAP32_FEC_RS 0x00800000UL 7107#define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 7108#define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 7109#define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 7110#define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 7111#define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 7112#define FW_PORT_CAP32_RESERVED2 0xe0000000UL 7113 7114#define S_FW_PORT_CAP32_SPEED 0 7115#define M_FW_PORT_CAP32_SPEED 0xfff 7116#define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 7117#define G_FW_PORT_CAP32_SPEED(x) \ 7118 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 7119 7120#define S_FW_PORT_CAP32_FC 16 7121#define M_FW_PORT_CAP32_FC 0x3 7122#define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 7123#define G_FW_PORT_CAP32_FC(x) \ 7124 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 7125 7126#define S_FW_PORT_CAP32_802_3 18 7127#define M_FW_PORT_CAP32_802_3 0x3 7128#define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 7129#define G_FW_PORT_CAP32_802_3(x) \ 7130 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 7131 7132#define S_FW_PORT_CAP32_ANEG 20 7133#define M_FW_PORT_CAP32_ANEG 0x1 7134#define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 7135#define G_FW_PORT_CAP32_ANEG(x) \ 7136 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 7137 7138#define S_FW_PORT_CAP32_FORCE_PAUSE 28 7139#define M_FW_PORT_CAP32_FORCE_PAUSE 0x1 7140#define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE) 7141#define G_FW_PORT_CAP32_FORCE_PAUSE(x) \ 7142 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE) 7143 7144enum fw_port_mdi32 { 7145 FW_PORT_CAP32_MDI_UNCHANGED, 7146 FW_PORT_CAP32_MDI_AUTO, 7147 FW_PORT_CAP32_MDI_F_STRAIGHT, 7148 FW_PORT_CAP32_MDI_F_CROSSOVER 7149}; 7150 7151#define S_FW_PORT_CAP32_MDI 21 7152#define M_FW_PORT_CAP32_MDI 3 7153#define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 7154#define G_FW_PORT_CAP32_MDI(x) \ 7155 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 7156 7157#define S_FW_PORT_CAP32_FEC 23 7158#define M_FW_PORT_CAP32_FEC 0x1f 7159#define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 7160#define G_FW_PORT_CAP32_FEC(x) \ 7161 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 7162 7163/* macros to isolate various 32-bit Port Capabilities sub-fields */ 7164#define CAP32_SPEED(__cap32) \ 7165 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 7166 7167#define CAP32_FEC(__cap32) \ 7168 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 7169 7170#define CAP32_FC(__cap32) \ 7171 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32) 7172 7173enum fw_port_action { 7174 FW_PORT_ACTION_L1_CFG = 0x0001, 7175 FW_PORT_ACTION_L2_CFG = 0x0002, 7176 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 7177 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 7178 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 7179 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 7180 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 7181 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 7182 FW_PORT_ACTION_L1_CFG32 = 0x0009, 7183 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 7184 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 7185 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 7186 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 7187 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 7188 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 7189 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 7190 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 7191 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 7192 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 7193 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 7194 FW_PORT_ACTION_PHY_RESET = 0x0040, 7195 FW_PORT_ACTION_PMA_RESET = 0x0041, 7196 FW_PORT_ACTION_PCS_RESET = 0x0042, 7197 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 7198 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 7199 FW_PORT_ACTION_AN_RESET = 0x0045, 7200}; 7201 7202enum fw_port_l2cfg_ctlbf { 7203 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 7204 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 7205 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 7206 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 7207 FW_PORT_L2_CTLBF_IVLAN = 0x10, 7208 FW_PORT_L2_CTLBF_TXIPG = 0x20, 7209 FW_PORT_L2_CTLBF_MTU = 0x40 7210}; 7211 7212enum fw_dcb_app_tlv_sf { 7213 FW_DCB_APP_SF_ETHERTYPE, 7214 FW_DCB_APP_SF_SOCKET_TCP, 7215 FW_DCB_APP_SF_SOCKET_UDP, 7216 FW_DCB_APP_SF_SOCKET_ALL, 7217}; 7218 7219enum fw_port_dcb_versions { 7220 FW_PORT_DCB_VER_UNKNOWN, 7221 FW_PORT_DCB_VER_CEE1D0, 7222 FW_PORT_DCB_VER_CEE1D01, 7223 FW_PORT_DCB_VER_IEEE, 7224 FW_PORT_DCB_VER_AUTO=7 7225}; 7226 7227enum fw_port_dcb_cfg { 7228 FW_PORT_DCB_CFG_PG = 0x01, 7229 FW_PORT_DCB_CFG_PFC = 0x02, 7230 FW_PORT_DCB_CFG_APPL = 0x04 7231}; 7232 7233enum fw_port_dcb_cfg_rc { 7234 FW_PORT_DCB_CFG_SUCCESS = 0x0, 7235 FW_PORT_DCB_CFG_ERROR = 0x1 7236}; 7237 7238enum fw_port_dcb_type { 7239 FW_PORT_DCB_TYPE_PGID = 0x00, 7240 FW_PORT_DCB_TYPE_PGRATE = 0x01, 7241 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 7242 FW_PORT_DCB_TYPE_PFC = 0x03, 7243 FW_PORT_DCB_TYPE_APP_ID = 0x04, 7244 FW_PORT_DCB_TYPE_CONTROL = 0x05, 7245}; 7246 7247enum fw_port_dcb_feature_state { 7248 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 7249 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 7250 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 7251 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7252}; 7253 7254enum fw_port_diag_ops { 7255 FW_PORT_DIAGS_TEMP = 0x00, 7256 FW_PORT_DIAGS_TX_POWER = 0x01, 7257 FW_PORT_DIAGS_RX_POWER = 0x02, 7258 FW_PORT_DIAGS_TX_DIS = 0x03, 7259}; 7260 7261struct fw_port_cmd { 7262 __be32 op_to_portid; 7263 __be32 action_to_len16; 7264 union fw_port { 7265 struct fw_port_l1cfg { 7266 __be32 rcap; 7267 __be32 r; 7268 } l1cfg; 7269 struct fw_port_l2cfg { 7270 __u8 ctlbf; 7271 __u8 ovlan3_to_ivlan0; 7272 __be16 ivlantype; 7273 __be16 txipg_force_pinfo; 7274 __be16 mtu; 7275 __be16 ovlan0mask; 7276 __be16 ovlan0type; 7277 __be16 ovlan1mask; 7278 __be16 ovlan1type; 7279 __be16 ovlan2mask; 7280 __be16 ovlan2type; 7281 __be16 ovlan3mask; 7282 __be16 ovlan3type; 7283 } l2cfg; 7284 struct fw_port_info { 7285 __be32 lstatus_to_modtype; 7286 __be16 pcap; 7287 __be16 acap; 7288 __be16 mtu; 7289 __u8 cbllen; 7290 __u8 auxlinfo; 7291 __u8 dcbxdis_pkd; 7292 __u8 r8_lo; 7293 __be16 lpacap; 7294 __be64 r9; 7295 } info; 7296 struct fw_port_diags { 7297 __u8 diagop; 7298 __u8 r[3]; 7299 __be32 diagval; 7300 } diags; 7301 union fw_port_dcb { 7302 struct fw_port_dcb_pgid { 7303 __u8 type; 7304 __u8 apply_pkd; 7305 __u8 r10_lo[2]; 7306 __be32 pgid; 7307 __be64 r11; 7308 } pgid; 7309 struct fw_port_dcb_pgrate { 7310 __u8 type; 7311 __u8 apply_pkd; 7312 __u8 r10_lo[5]; 7313 __u8 num_tcs_supported; 7314 __u8 pgrate[8]; 7315 __u8 tsa[8]; 7316 } pgrate; 7317 struct fw_port_dcb_priorate { 7318 __u8 type; 7319 __u8 apply_pkd; 7320 __u8 r10_lo[6]; 7321 __u8 strict_priorate[8]; 7322 } priorate; 7323 struct fw_port_dcb_pfc { 7324 __u8 type; 7325 __u8 pfcen; 7326 __u8 apply_pkd; 7327 __u8 r10_lo[4]; 7328 __u8 max_pfc_tcs; 7329 __be64 r11; 7330 } pfc; 7331 struct fw_port_app_priority { 7332 __u8 type; 7333 __u8 apply_pkd; 7334 __u8 r10_lo; 7335 __u8 idx; 7336 __u8 user_prio_map; 7337 __u8 sel_field; 7338 __be16 protocolid; 7339 __be64 r12; 7340 } app_priority; 7341 struct fw_port_dcb_control { 7342 __u8 type; 7343 __u8 all_syncd_pkd; 7344 __be16 dcb_version_to_app_state; 7345 __be32 r11; 7346 __be64 r12; 7347 } control; 7348 } dcb; 7349 struct fw_port_l1cfg32 { 7350 __be32 rcap32; 7351 __be32 r; 7352 } l1cfg32; 7353 struct fw_port_info32 { 7354 __be32 lstatus32_to_cbllen32; 7355 __be32 auxlinfo32_mtu32; 7356 __be32 linkattr32; 7357 __be32 pcaps32; 7358 __be32 acaps32; 7359 __be32 lpacaps32; 7360 } info32; 7361 } u; 7362}; 7363 7364#define S_FW_PORT_CMD_READ 22 7365#define M_FW_PORT_CMD_READ 0x1 7366#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 7367#define G_FW_PORT_CMD_READ(x) \ 7368 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 7369#define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 7370 7371#define S_FW_PORT_CMD_PORTID 0 7372#define M_FW_PORT_CMD_PORTID 0xf 7373#define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7374#define G_FW_PORT_CMD_PORTID(x) \ 7375 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7376 7377#define S_FW_PORT_CMD_ACTION 16 7378#define M_FW_PORT_CMD_ACTION 0xffff 7379#define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7380#define G_FW_PORT_CMD_ACTION(x) \ 7381 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7382 7383#define S_FW_PORT_CMD_OVLAN3 7 7384#define M_FW_PORT_CMD_OVLAN3 0x1 7385#define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7386#define G_FW_PORT_CMD_OVLAN3(x) \ 7387 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7388#define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7389 7390#define S_FW_PORT_CMD_OVLAN2 6 7391#define M_FW_PORT_CMD_OVLAN2 0x1 7392#define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7393#define G_FW_PORT_CMD_OVLAN2(x) \ 7394 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7395#define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7396 7397#define S_FW_PORT_CMD_OVLAN1 5 7398#define M_FW_PORT_CMD_OVLAN1 0x1 7399#define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7400#define G_FW_PORT_CMD_OVLAN1(x) \ 7401 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7402#define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7403 7404#define S_FW_PORT_CMD_OVLAN0 4 7405#define M_FW_PORT_CMD_OVLAN0 0x1 7406#define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7407#define G_FW_PORT_CMD_OVLAN0(x) \ 7408 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7409#define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7410 7411#define S_FW_PORT_CMD_IVLAN0 3 7412#define M_FW_PORT_CMD_IVLAN0 0x1 7413#define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7414#define G_FW_PORT_CMD_IVLAN0(x) \ 7415 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7416#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7417 7418#define S_FW_PORT_CMD_TXIPG 3 7419#define M_FW_PORT_CMD_TXIPG 0x1fff 7420#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7421#define G_FW_PORT_CMD_TXIPG(x) \ 7422 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7423 7424#define S_FW_PORT_CMD_FORCE_PINFO 0 7425#define M_FW_PORT_CMD_FORCE_PINFO 0x1 7426#define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7427#define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7428 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7429#define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7430 7431#define S_FW_PORT_CMD_LSTATUS 31 7432#define M_FW_PORT_CMD_LSTATUS 0x1 7433#define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7434#define G_FW_PORT_CMD_LSTATUS(x) \ 7435 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7436#define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7437 7438#define S_FW_PORT_CMD_LSPEED 24 7439#define M_FW_PORT_CMD_LSPEED 0x3f 7440#define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7441#define G_FW_PORT_CMD_LSPEED(x) \ 7442 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7443 7444#define S_FW_PORT_CMD_TXPAUSE 23 7445#define M_FW_PORT_CMD_TXPAUSE 0x1 7446#define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7447#define G_FW_PORT_CMD_TXPAUSE(x) \ 7448 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7449#define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7450 7451#define S_FW_PORT_CMD_RXPAUSE 22 7452#define M_FW_PORT_CMD_RXPAUSE 0x1 7453#define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7454#define G_FW_PORT_CMD_RXPAUSE(x) \ 7455 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7456#define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7457 7458#define S_FW_PORT_CMD_MDIOCAP 21 7459#define M_FW_PORT_CMD_MDIOCAP 0x1 7460#define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7461#define G_FW_PORT_CMD_MDIOCAP(x) \ 7462 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7463#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7464 7465#define S_FW_PORT_CMD_MDIOADDR 16 7466#define M_FW_PORT_CMD_MDIOADDR 0x1f 7467#define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7468#define G_FW_PORT_CMD_MDIOADDR(x) \ 7469 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7470 7471#define S_FW_PORT_CMD_LPTXPAUSE 15 7472#define M_FW_PORT_CMD_LPTXPAUSE 0x1 7473#define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7474#define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7475 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7476#define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7477 7478#define S_FW_PORT_CMD_LPRXPAUSE 14 7479#define M_FW_PORT_CMD_LPRXPAUSE 0x1 7480#define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7481#define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7482 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7483#define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7484 7485#define S_FW_PORT_CMD_PTYPE 8 7486#define M_FW_PORT_CMD_PTYPE 0x1f 7487#define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7488#define G_FW_PORT_CMD_PTYPE(x) \ 7489 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7490 7491#define S_FW_PORT_CMD_LINKDNRC 5 7492#define M_FW_PORT_CMD_LINKDNRC 0x7 7493#define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7494#define G_FW_PORT_CMD_LINKDNRC(x) \ 7495 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7496 7497#define S_FW_PORT_CMD_MODTYPE 0 7498#define M_FW_PORT_CMD_MODTYPE 0x1f 7499#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7500#define G_FW_PORT_CMD_MODTYPE(x) \ 7501 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7502 7503#define S_FW_PORT_AUXLINFO_KX4 2 7504#define M_FW_PORT_AUXLINFO_KX4 0x1 7505#define V_FW_PORT_AUXLINFO_KX4(x) \ 7506 ((x) << S_FW_PORT_AUXLINFO_KX4) 7507#define G_FW_PORT_AUXLINFO_KX4(x) \ 7508 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 7509#define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 7510 7511#define S_FW_PORT_AUXLINFO_KR 1 7512#define M_FW_PORT_AUXLINFO_KR 0x1 7513#define V_FW_PORT_AUXLINFO_KR(x) \ 7514 ((x) << S_FW_PORT_AUXLINFO_KR) 7515#define G_FW_PORT_AUXLINFO_KR(x) \ 7516 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 7517#define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 7518 7519#define S_FW_PORT_CMD_DCBXDIS 7 7520#define M_FW_PORT_CMD_DCBXDIS 0x1 7521#define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7522#define G_FW_PORT_CMD_DCBXDIS(x) \ 7523 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7524#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7525 7526#define S_FW_PORT_CMD_APPLY 7 7527#define M_FW_PORT_CMD_APPLY 0x1 7528#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7529#define G_FW_PORT_CMD_APPLY(x) \ 7530 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7531#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 7532 7533#define S_FW_PORT_CMD_ALL_SYNCD 7 7534#define M_FW_PORT_CMD_ALL_SYNCD 0x1 7535#define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7536#define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7537 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7538#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7539 7540#define S_FW_PORT_CMD_DCB_VERSION 12 7541#define M_FW_PORT_CMD_DCB_VERSION 0x7 7542#define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7543#define G_FW_PORT_CMD_DCB_VERSION(x) \ 7544 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7545 7546#define S_FW_PORT_CMD_PFC_STATE 8 7547#define M_FW_PORT_CMD_PFC_STATE 0xf 7548#define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7549#define G_FW_PORT_CMD_PFC_STATE(x) \ 7550 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7551 7552#define S_FW_PORT_CMD_ETS_STATE 4 7553#define M_FW_PORT_CMD_ETS_STATE 0xf 7554#define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7555#define G_FW_PORT_CMD_ETS_STATE(x) \ 7556 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7557 7558#define S_FW_PORT_CMD_APP_STATE 0 7559#define M_FW_PORT_CMD_APP_STATE 0xf 7560#define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7561#define G_FW_PORT_CMD_APP_STATE(x) \ 7562 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7563 7564#define S_FW_PORT_CMD_LSTATUS32 31 7565#define M_FW_PORT_CMD_LSTATUS32 0x1 7566#define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 7567#define G_FW_PORT_CMD_LSTATUS32(x) \ 7568 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 7569#define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 7570 7571#define S_FW_PORT_CMD_LINKDNRC32 28 7572#define M_FW_PORT_CMD_LINKDNRC32 0x7 7573#define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 7574#define G_FW_PORT_CMD_LINKDNRC32(x) \ 7575 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 7576 7577#define S_FW_PORT_CMD_DCBXDIS32 27 7578#define M_FW_PORT_CMD_DCBXDIS32 0x1 7579#define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 7580#define G_FW_PORT_CMD_DCBXDIS32(x) \ 7581 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 7582#define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 7583 7584#define S_FW_PORT_CMD_MDIOCAP32 26 7585#define M_FW_PORT_CMD_MDIOCAP32 0x1 7586#define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 7587#define G_FW_PORT_CMD_MDIOCAP32(x) \ 7588 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 7589#define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 7590 7591#define S_FW_PORT_CMD_MDIOADDR32 21 7592#define M_FW_PORT_CMD_MDIOADDR32 0x1f 7593#define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 7594#define G_FW_PORT_CMD_MDIOADDR32(x) \ 7595 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 7596 7597#define S_FW_PORT_CMD_PORTTYPE32 13 7598#define M_FW_PORT_CMD_PORTTYPE32 0xff 7599#define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 7600#define G_FW_PORT_CMD_PORTTYPE32(x) \ 7601 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 7602 7603#define S_FW_PORT_CMD_MODTYPE32 8 7604#define M_FW_PORT_CMD_MODTYPE32 0x1f 7605#define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 7606#define G_FW_PORT_CMD_MODTYPE32(x) \ 7607 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 7608 7609#define S_FW_PORT_CMD_CBLLEN32 0 7610#define M_FW_PORT_CMD_CBLLEN32 0xff 7611#define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 7612#define G_FW_PORT_CMD_CBLLEN32(x) \ 7613 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 7614 7615#define S_FW_PORT_CMD_AUXLINFO32 24 7616#define M_FW_PORT_CMD_AUXLINFO32 0xff 7617#define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 7618#define G_FW_PORT_CMD_AUXLINFO32(x) \ 7619 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 7620 7621#define S_FW_PORT_AUXLINFO32_KX4 2 7622#define M_FW_PORT_AUXLINFO32_KX4 0x1 7623#define V_FW_PORT_AUXLINFO32_KX4(x) \ 7624 ((x) << S_FW_PORT_AUXLINFO32_KX4) 7625#define G_FW_PORT_AUXLINFO32_KX4(x) \ 7626 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 7627#define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 7628 7629#define S_FW_PORT_AUXLINFO32_KR 1 7630#define M_FW_PORT_AUXLINFO32_KR 0x1 7631#define V_FW_PORT_AUXLINFO32_KR(x) \ 7632 ((x) << S_FW_PORT_AUXLINFO32_KR) 7633#define G_FW_PORT_AUXLINFO32_KR(x) \ 7634 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 7635#define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 7636 7637#define S_FW_PORT_CMD_MTU32 0 7638#define M_FW_PORT_CMD_MTU32 0xffff 7639#define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 7640#define G_FW_PORT_CMD_MTU32(x) \ 7641 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 7642 7643/* 7644 * These are configured into the VPD and hence tools that generate 7645 * VPD may use this enumeration. 7646 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7647 * 7648 * REMEMBER: 7649 * Update the Common Code t4_hw.c:t4_get_port_type_description() 7650 * with any new Firmware Port Technology Types! 7651 */ 7652enum fw_port_type { 7653 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 7654 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 7655 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7656 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7657 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 7658 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 7659 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 7660 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 7661 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 7662 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7663 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7664 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7665 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7666 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7667 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7668 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7669 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 7670 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 7671 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 7672 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7673 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 7674 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 7675 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ 7676 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 7677}; 7678 7679/* These are read from module's EEPROM and determined once the 7680 module is inserted. */ 7681enum fw_port_module_type { 7682 FW_PORT_MOD_TYPE_NA = 0x0, 7683 FW_PORT_MOD_TYPE_LR = 0x1, 7684 FW_PORT_MOD_TYPE_SR = 0x2, 7685 FW_PORT_MOD_TYPE_ER = 0x3, 7686 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 7687 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 7688 FW_PORT_MOD_TYPE_LRM = 0x6, 7689 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 7690 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 7691 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 7692 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 7693}; 7694 7695/* used by FW and tools may use this to generate VPD */ 7696enum fw_port_mod_sub_type { 7697 FW_PORT_MOD_SUB_TYPE_NA, 7698 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7699 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7700 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7701 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7702 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7703 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7704 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7705 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 7706 7707 /* 7708 * The following will never been in the VPD. They are TWINAX cable 7709 * lengths decoded from SFP+ module i2c PROMs. These should almost 7710 * certainly go somewhere else ... 7711 */ 7712 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7713 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7714 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7715 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 7716}; 7717 7718/* link down reason codes (3b) */ 7719enum fw_port_link_dn_rc { 7720 FW_PORT_LINK_DN_RC_NONE, 7721 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7722 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7723 FW_PORT_LINK_DN_RESERVED3, 7724 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7725 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7726 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7727 FW_PORT_LINK_DN_RESERVED7 7728}; 7729enum fw_port_stats_tx_index { 7730 FW_STAT_TX_PORT_BYTES_IX = 0, 7731 FW_STAT_TX_PORT_FRAMES_IX, 7732 FW_STAT_TX_PORT_BCAST_IX, 7733 FW_STAT_TX_PORT_MCAST_IX, 7734 FW_STAT_TX_PORT_UCAST_IX, 7735 FW_STAT_TX_PORT_ERROR_IX, 7736 FW_STAT_TX_PORT_64B_IX, 7737 FW_STAT_TX_PORT_65B_127B_IX, 7738 FW_STAT_TX_PORT_128B_255B_IX, 7739 FW_STAT_TX_PORT_256B_511B_IX, 7740 FW_STAT_TX_PORT_512B_1023B_IX, 7741 FW_STAT_TX_PORT_1024B_1518B_IX, 7742 FW_STAT_TX_PORT_1519B_MAX_IX, 7743 FW_STAT_TX_PORT_DROP_IX, 7744 FW_STAT_TX_PORT_PAUSE_IX, 7745 FW_STAT_TX_PORT_PPP0_IX, 7746 FW_STAT_TX_PORT_PPP1_IX, 7747 FW_STAT_TX_PORT_PPP2_IX, 7748 FW_STAT_TX_PORT_PPP3_IX, 7749 FW_STAT_TX_PORT_PPP4_IX, 7750 FW_STAT_TX_PORT_PPP5_IX, 7751 FW_STAT_TX_PORT_PPP6_IX, 7752 FW_STAT_TX_PORT_PPP7_IX, 7753 FW_NUM_PORT_TX_STATS 7754}; 7755 7756enum fw_port_stat_rx_index { 7757 FW_STAT_RX_PORT_BYTES_IX = 0, 7758 FW_STAT_RX_PORT_FRAMES_IX, 7759 FW_STAT_RX_PORT_BCAST_IX, 7760 FW_STAT_RX_PORT_MCAST_IX, 7761 FW_STAT_RX_PORT_UCAST_IX, 7762 FW_STAT_RX_PORT_MTU_ERROR_IX, 7763 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 7764 FW_STAT_RX_PORT_CRC_ERROR_IX, 7765 FW_STAT_RX_PORT_LEN_ERROR_IX, 7766 FW_STAT_RX_PORT_SYM_ERROR_IX, 7767 FW_STAT_RX_PORT_64B_IX, 7768 FW_STAT_RX_PORT_65B_127B_IX, 7769 FW_STAT_RX_PORT_128B_255B_IX, 7770 FW_STAT_RX_PORT_256B_511B_IX, 7771 FW_STAT_RX_PORT_512B_1023B_IX, 7772 FW_STAT_RX_PORT_1024B_1518B_IX, 7773 FW_STAT_RX_PORT_1519B_MAX_IX, 7774 FW_STAT_RX_PORT_PAUSE_IX, 7775 FW_STAT_RX_PORT_PPP0_IX, 7776 FW_STAT_RX_PORT_PPP1_IX, 7777 FW_STAT_RX_PORT_PPP2_IX, 7778 FW_STAT_RX_PORT_PPP3_IX, 7779 FW_STAT_RX_PORT_PPP4_IX, 7780 FW_STAT_RX_PORT_PPP5_IX, 7781 FW_STAT_RX_PORT_PPP6_IX, 7782 FW_STAT_RX_PORT_PPP7_IX, 7783 FW_STAT_RX_PORT_LESS_64B_IX, 7784 FW_STAT_RX_PORT_MAC_ERROR_IX, 7785 FW_NUM_PORT_RX_STATS 7786}; 7787/* port stats */ 7788#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7789 FW_NUM_PORT_RX_STATS) 7790 7791 7792struct fw_port_stats_cmd { 7793 __be32 op_to_portid; 7794 __be32 retval_len16; 7795 union fw_port_stats { 7796 struct fw_port_stats_ctl { 7797 __u8 nstats_bg_bm; 7798 __u8 tx_ix; 7799 __be16 r6; 7800 __be32 r7; 7801 __be64 stat0; 7802 __be64 stat1; 7803 __be64 stat2; 7804 __be64 stat3; 7805 __be64 stat4; 7806 __be64 stat5; 7807 } ctl; 7808 struct fw_port_stats_all { 7809 __be64 tx_bytes; 7810 __be64 tx_frames; 7811 __be64 tx_bcast; 7812 __be64 tx_mcast; 7813 __be64 tx_ucast; 7814 __be64 tx_error; 7815 __be64 tx_64b; 7816 __be64 tx_65b_127b; 7817 __be64 tx_128b_255b; 7818 __be64 tx_256b_511b; 7819 __be64 tx_512b_1023b; 7820 __be64 tx_1024b_1518b; 7821 __be64 tx_1519b_max; 7822 __be64 tx_drop; 7823 __be64 tx_pause; 7824 __be64 tx_ppp0; 7825 __be64 tx_ppp1; 7826 __be64 tx_ppp2; 7827 __be64 tx_ppp3; 7828 __be64 tx_ppp4; 7829 __be64 tx_ppp5; 7830 __be64 tx_ppp6; 7831 __be64 tx_ppp7; 7832 __be64 rx_bytes; 7833 __be64 rx_frames; 7834 __be64 rx_bcast; 7835 __be64 rx_mcast; 7836 __be64 rx_ucast; 7837 __be64 rx_mtu_error; 7838 __be64 rx_mtu_crc_error; 7839 __be64 rx_crc_error; 7840 __be64 rx_len_error; 7841 __be64 rx_sym_error; 7842 __be64 rx_64b; 7843 __be64 rx_65b_127b; 7844 __be64 rx_128b_255b; 7845 __be64 rx_256b_511b; 7846 __be64 rx_512b_1023b; 7847 __be64 rx_1024b_1518b; 7848 __be64 rx_1519b_max; 7849 __be64 rx_pause; 7850 __be64 rx_ppp0; 7851 __be64 rx_ppp1; 7852 __be64 rx_ppp2; 7853 __be64 rx_ppp3; 7854 __be64 rx_ppp4; 7855 __be64 rx_ppp5; 7856 __be64 rx_ppp6; 7857 __be64 rx_ppp7; 7858 __be64 rx_less_64b; 7859 __be64 rx_bg_drop; 7860 __be64 rx_bg_trunc; 7861 } all; 7862 } u; 7863}; 7864 7865#define S_FW_PORT_STATS_CMD_NSTATS 4 7866#define M_FW_PORT_STATS_CMD_NSTATS 0x7 7867#define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7868#define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7869 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 7870 7871#define S_FW_PORT_STATS_CMD_BG_BM 0 7872#define M_FW_PORT_STATS_CMD_BG_BM 0x3 7873#define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7874#define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7875 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 7876 7877#define S_FW_PORT_STATS_CMD_TX 7 7878#define M_FW_PORT_STATS_CMD_TX 0x1 7879#define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 7880#define G_FW_PORT_STATS_CMD_TX(x) \ 7881 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 7882#define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 7883 7884#define S_FW_PORT_STATS_CMD_IX 0 7885#define M_FW_PORT_STATS_CMD_IX 0x3f 7886#define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 7887#define G_FW_PORT_STATS_CMD_IX(x) \ 7888 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 7889 7890/* port loopback stats */ 7891#define FW_NUM_LB_STATS 14 7892enum fw_port_lb_stats_index { 7893 FW_STAT_LB_PORT_BYTES_IX, 7894 FW_STAT_LB_PORT_FRAMES_IX, 7895 FW_STAT_LB_PORT_BCAST_IX, 7896 FW_STAT_LB_PORT_MCAST_IX, 7897 FW_STAT_LB_PORT_UCAST_IX, 7898 FW_STAT_LB_PORT_ERROR_IX, 7899 FW_STAT_LB_PORT_64B_IX, 7900 FW_STAT_LB_PORT_65B_127B_IX, 7901 FW_STAT_LB_PORT_128B_255B_IX, 7902 FW_STAT_LB_PORT_256B_511B_IX, 7903 FW_STAT_LB_PORT_512B_1023B_IX, 7904 FW_STAT_LB_PORT_1024B_1518B_IX, 7905 FW_STAT_LB_PORT_1519B_MAX_IX, 7906 FW_STAT_LB_PORT_DROP_FRAMES_IX 7907}; 7908 7909struct fw_port_lb_stats_cmd { 7910 __be32 op_to_lbport; 7911 __be32 retval_len16; 7912 union fw_port_lb_stats { 7913 struct fw_port_lb_stats_ctl { 7914 __u8 nstats_bg_bm; 7915 __u8 ix_pkd; 7916 __be16 r6; 7917 __be32 r7; 7918 __be64 stat0; 7919 __be64 stat1; 7920 __be64 stat2; 7921 __be64 stat3; 7922 __be64 stat4; 7923 __be64 stat5; 7924 } ctl; 7925 struct fw_port_lb_stats_all { 7926 __be64 tx_bytes; 7927 __be64 tx_frames; 7928 __be64 tx_bcast; 7929 __be64 tx_mcast; 7930 __be64 tx_ucast; 7931 __be64 tx_error; 7932 __be64 tx_64b; 7933 __be64 tx_65b_127b; 7934 __be64 tx_128b_255b; 7935 __be64 tx_256b_511b; 7936 __be64 tx_512b_1023b; 7937 __be64 tx_1024b_1518b; 7938 __be64 tx_1519b_max; 7939 __be64 rx_lb_drop; 7940 __be64 rx_lb_trunc; 7941 } all; 7942 } u; 7943}; 7944 7945#define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7946#define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7947#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7948 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7949#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7950 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7951 7952#define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7953#define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7954#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7955 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7956#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7957 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7958 7959#define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7960#define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7961#define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7962#define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7963 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7964 7965#define S_FW_PORT_LB_STATS_CMD_IX 0 7966#define M_FW_PORT_LB_STATS_CMD_IX 0xf 7967#define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7968#define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7969 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 7970 7971/* Trace related defines */ 7972#define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7973#define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 7974 7975struct fw_port_trace_cmd { 7976 __be32 op_to_portid; 7977 __be32 retval_len16; 7978 __be16 traceen_to_pciech; 7979 __be16 qnum; 7980 __be32 r5; 7981}; 7982 7983#define S_FW_PORT_TRACE_CMD_PORTID 0 7984#define M_FW_PORT_TRACE_CMD_PORTID 0xf 7985#define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 7986#define G_FW_PORT_TRACE_CMD_PORTID(x) \ 7987 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 7988 7989#define S_FW_PORT_TRACE_CMD_TRACEEN 15 7990#define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 7991#define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 7992#define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 7993 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 7994#define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 7995 7996#define S_FW_PORT_TRACE_CMD_FLTMODE 14 7997#define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 7998#define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 7999#define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 8000 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 8001#define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 8002 8003#define S_FW_PORT_TRACE_CMD_DUPLEN 13 8004#define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 8005#define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 8006#define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 8007 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 8008#define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 8009 8010#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 8011#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 8012#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 8013 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 8014#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 8015 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 8016 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 8017 8018#define S_FW_PORT_TRACE_CMD_PCIECH 6 8019#define M_FW_PORT_TRACE_CMD_PCIECH 0x3 8020#define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 8021#define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 8022 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 8023 8024struct fw_port_trace_mmap_cmd { 8025 __be32 op_to_portid; 8026 __be32 retval_len16; 8027 __be32 fid_to_skipoffset; 8028 __be32 minpktsize_capturemax; 8029 __u8 map[224]; 8030}; 8031 8032#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 8033#define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 8034#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 8035 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 8036#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 8037 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 8038 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 8039 8040#define S_FW_PORT_TRACE_MMAP_CMD_FID 30 8041#define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 8042#define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 8043#define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 8044 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 8045 8046#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 8047#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 8048#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 8049 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 8050#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 8051 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 8052 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 8053#define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 8054 8055#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 8056#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 8057#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 8058 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 8059#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 8060 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 8061 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 8062#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 8063 8064#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 8065#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 8066#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8067 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8068#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8069 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 8070 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8071 8072#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 8073#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 8074#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8075 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8076#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8077 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 8078 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8079 8080#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 8081#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 8082#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8083 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8084#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8085 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 8086 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8087 8088#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 8089#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 8090#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8091 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8092#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8093 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 8094 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8095 8096enum fw_ptp_subop { 8097 8098 /* none */ 8099 FW_PTP_SC_INIT_TIMER = 0x00, 8100 FW_PTP_SC_TX_TYPE = 0x01, 8101 8102 /* init */ 8103 FW_PTP_SC_RXTIME_STAMP = 0x08, 8104 FW_PTP_SC_RDRX_TYPE = 0x09, 8105 8106 /* ts */ 8107 FW_PTP_SC_ADJ_FREQ = 0x10, 8108 FW_PTP_SC_ADJ_TIME = 0x11, 8109 FW_PTP_SC_ADJ_FTIME = 0x12, 8110 FW_PTP_SC_WALL_CLOCK = 0x13, 8111 FW_PTP_SC_GET_TIME = 0x14, 8112 FW_PTP_SC_SET_TIME = 0x15, 8113}; 8114 8115struct fw_ptp_cmd { 8116 __be32 op_to_portid; 8117 __be32 retval_len16; 8118 union fw_ptp { 8119 struct fw_ptp_sc { 8120 __u8 sc; 8121 __u8 r3[7]; 8122 } scmd; 8123 struct fw_ptp_init { 8124 __u8 sc; 8125 __u8 txchan; 8126 __be16 absid; 8127 __be16 mode; 8128 __be16 r3; 8129 } init; 8130 struct fw_ptp_ts { 8131 __u8 sc; 8132 __u8 sign; 8133 __be16 r3; 8134 __be32 ppb; 8135 __be64 tm; 8136 } ts; 8137 } u; 8138 __be64 r3; 8139}; 8140 8141#define S_FW_PTP_CMD_PORTID 0 8142#define M_FW_PTP_CMD_PORTID 0xf 8143#define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 8144#define G_FW_PTP_CMD_PORTID(x) \ 8145 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 8146 8147struct fw_rss_ind_tbl_cmd { 8148 __be32 op_to_viid; 8149 __be32 retval_len16; 8150 __be16 niqid; 8151 __be16 startidx; 8152 __be32 r3; 8153 __be32 iq0_to_iq2; 8154 __be32 iq3_to_iq5; 8155 __be32 iq6_to_iq8; 8156 __be32 iq9_to_iq11; 8157 __be32 iq12_to_iq14; 8158 __be32 iq15_to_iq17; 8159 __be32 iq18_to_iq20; 8160 __be32 iq21_to_iq23; 8161 __be32 iq24_to_iq26; 8162 __be32 iq27_to_iq29; 8163 __be32 iq30_iq31; 8164 __be32 r15_lo; 8165}; 8166 8167#define S_FW_RSS_IND_TBL_CMD_VIID 0 8168#define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 8169#define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 8170#define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 8171 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 8172 8173#define S_FW_RSS_IND_TBL_CMD_IQ0 20 8174#define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 8175#define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 8176#define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 8177 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 8178 8179#define S_FW_RSS_IND_TBL_CMD_IQ1 10 8180#define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 8181#define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 8182#define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 8183 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 8184 8185#define S_FW_RSS_IND_TBL_CMD_IQ2 0 8186#define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 8187#define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 8188#define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 8189 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 8190 8191#define S_FW_RSS_IND_TBL_CMD_IQ3 20 8192#define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 8193#define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 8194#define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 8195 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 8196 8197#define S_FW_RSS_IND_TBL_CMD_IQ4 10 8198#define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 8199#define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 8200#define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 8201 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 8202 8203#define S_FW_RSS_IND_TBL_CMD_IQ5 0 8204#define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 8205#define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 8206#define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 8207 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 8208 8209#define S_FW_RSS_IND_TBL_CMD_IQ6 20 8210#define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 8211#define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 8212#define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 8213 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 8214 8215#define S_FW_RSS_IND_TBL_CMD_IQ7 10 8216#define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 8217#define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 8218#define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 8219 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 8220 8221#define S_FW_RSS_IND_TBL_CMD_IQ8 0 8222#define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 8223#define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 8224#define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 8225 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 8226 8227#define S_FW_RSS_IND_TBL_CMD_IQ9 20 8228#define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 8229#define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 8230#define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 8231 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 8232 8233#define S_FW_RSS_IND_TBL_CMD_IQ10 10 8234#define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 8235#define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 8236#define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 8237 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 8238 8239#define S_FW_RSS_IND_TBL_CMD_IQ11 0 8240#define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 8241#define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 8242#define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 8243 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 8244 8245#define S_FW_RSS_IND_TBL_CMD_IQ12 20 8246#define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 8247#define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 8248#define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 8249 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 8250 8251#define S_FW_RSS_IND_TBL_CMD_IQ13 10 8252#define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 8253#define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 8254#define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 8255 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 8256 8257#define S_FW_RSS_IND_TBL_CMD_IQ14 0 8258#define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 8259#define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 8260#define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 8261 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 8262 8263#define S_FW_RSS_IND_TBL_CMD_IQ15 20 8264#define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 8265#define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 8266#define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 8267 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 8268 8269#define S_FW_RSS_IND_TBL_CMD_IQ16 10 8270#define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 8271#define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 8272#define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 8273 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 8274 8275#define S_FW_RSS_IND_TBL_CMD_IQ17 0 8276#define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 8277#define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 8278#define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 8279 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 8280 8281#define S_FW_RSS_IND_TBL_CMD_IQ18 20 8282#define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 8283#define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 8284#define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 8285 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 8286 8287#define S_FW_RSS_IND_TBL_CMD_IQ19 10 8288#define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 8289#define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 8290#define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 8291 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 8292 8293#define S_FW_RSS_IND_TBL_CMD_IQ20 0 8294#define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 8295#define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 8296#define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 8297 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 8298 8299#define S_FW_RSS_IND_TBL_CMD_IQ21 20 8300#define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 8301#define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 8302#define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 8303 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 8304 8305#define S_FW_RSS_IND_TBL_CMD_IQ22 10 8306#define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 8307#define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 8308#define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 8309 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 8310 8311#define S_FW_RSS_IND_TBL_CMD_IQ23 0 8312#define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 8313#define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 8314#define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 8315 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 8316 8317#define S_FW_RSS_IND_TBL_CMD_IQ24 20 8318#define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 8319#define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 8320#define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 8321 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 8322 8323#define S_FW_RSS_IND_TBL_CMD_IQ25 10 8324#define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 8325#define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 8326#define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 8327 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 8328 8329#define S_FW_RSS_IND_TBL_CMD_IQ26 0 8330#define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 8331#define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 8332#define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 8333 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 8334 8335#define S_FW_RSS_IND_TBL_CMD_IQ27 20 8336#define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 8337#define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 8338#define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 8339 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 8340 8341#define S_FW_RSS_IND_TBL_CMD_IQ28 10 8342#define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 8343#define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 8344#define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 8345 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 8346 8347#define S_FW_RSS_IND_TBL_CMD_IQ29 0 8348#define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 8349#define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 8350#define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 8351 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 8352 8353#define S_FW_RSS_IND_TBL_CMD_IQ30 20 8354#define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 8355#define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 8356#define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 8357 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 8358 8359#define S_FW_RSS_IND_TBL_CMD_IQ31 10 8360#define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 8361#define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 8362#define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 8363 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 8364 8365struct fw_rss_glb_config_cmd { 8366 __be32 op_to_write; 8367 __be32 retval_len16; 8368 union fw_rss_glb_config { 8369 struct fw_rss_glb_config_manual { 8370 __be32 mode_pkd; 8371 __be32 r3; 8372 __be64 r4; 8373 __be64 r5; 8374 } manual; 8375 struct fw_rss_glb_config_basicvirtual { 8376 __be32 mode_keymode; 8377 __be32 synmapen_to_hashtoeplitz; 8378 __be64 r8; 8379 __be64 r9; 8380 } basicvirtual; 8381 } u; 8382}; 8383 8384#define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 8385#define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 8386#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 8387#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 8388 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 8389 8390#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 8391#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 8392#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 8393 8394#define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 8395#define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 8396#define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8397 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8398#define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8399 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 8400 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8401 8402#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 8403#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 8404#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 8405#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 8406 8407#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 8408#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 8409#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8410 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8411#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8412 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 8413 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8414#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 8415 8416#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 8417#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 8418#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8419 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8420#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8421 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 8422 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8423#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 8424 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 8425 8426#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 8427#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 8428#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8429 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8430#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8431 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 8432 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8433#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 8434 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 8435 8436#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 8437#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 8438#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8439 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8440#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8441 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 8442 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8443#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 8444 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 8445 8446#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 8447#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 8448#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8449 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8450#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8451 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 8452 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8453#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 8454 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 8455 8456#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 8457#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 8458#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8459 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8460#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8461 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 8462 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8463#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 8464 8465#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 8466#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 8467#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8468 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8469#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8470 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 8471 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8472#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 8473 8474#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 8475#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 8476#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8477 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8478#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8479 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8480 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8481#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 8482 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 8483 8484#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8485#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8486#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8487 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8488#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8489 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8490 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8491#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 8492 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 8493 8494struct fw_rss_vi_config_cmd { 8495 __be32 op_to_viid; 8496 __be32 retval_len16; 8497 union fw_rss_vi_config { 8498 struct fw_rss_vi_config_manual { 8499 __be64 r3; 8500 __be64 r4; 8501 __be64 r5; 8502 } manual; 8503 struct fw_rss_vi_config_basicvirtual { 8504 __be32 r6; 8505 __be32 defaultq_to_udpen; 8506 __be32 secretkeyidx_pkd; 8507 __be32 secretkeyxor; 8508 __be64 r10; 8509 } basicvirtual; 8510 } u; 8511}; 8512 8513#define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8514#define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8515#define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8516#define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8517 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8518 8519#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8520#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8521#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8522 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8523#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8524 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8525 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8526 8527#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8528#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8529#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8530 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8531#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8532 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8533 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8534#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 8535 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 8536 8537#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8538#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8539#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8540 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8541#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8542 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8543 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8544#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 8545 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 8546 8547#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8548#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8549#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8550 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8551#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8552 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8553 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8554#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 8555 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 8556 8557#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8558#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8559#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8560 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8561#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8562 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8563 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8564#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 8565 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 8566 8567#define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8568#define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8569#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8570#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8571 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8572#define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8573 8574#define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 8575#define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 8576#define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8577 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8578#define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8579 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 8580 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8581 8582enum fw_sched_sc { 8583 FW_SCHED_SC_CONFIG = 0, 8584 FW_SCHED_SC_PARAMS = 1, 8585}; 8586 8587enum fw_sched_type { 8588 FW_SCHED_TYPE_PKTSCHED = 0, 8589 FW_SCHED_TYPE_STREAMSCHED = 1, 8590}; 8591 8592enum fw_sched_params_level { 8593 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 8594 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 8595 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 8596}; 8597 8598enum fw_sched_params_mode { 8599 FW_SCHED_PARAMS_MODE_CLASS = 0, 8600 FW_SCHED_PARAMS_MODE_FLOW = 1, 8601}; 8602 8603enum fw_sched_params_unit { 8604 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 8605 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 8606}; 8607 8608enum fw_sched_params_rate { 8609 FW_SCHED_PARAMS_RATE_REL = 0, 8610 FW_SCHED_PARAMS_RATE_ABS = 1, 8611}; 8612 8613struct fw_sched_cmd { 8614 __be32 op_to_write; 8615 __be32 retval_len16; 8616 union fw_sched { 8617 struct fw_sched_config { 8618 __u8 sc; 8619 __u8 type; 8620 __u8 minmaxen; 8621 __u8 r3[5]; 8622 __u8 nclasses[4]; 8623 __be32 r4; 8624 } config; 8625 struct fw_sched_params { 8626 __u8 sc; 8627 __u8 type; 8628 __u8 level; 8629 __u8 mode; 8630 __u8 unit; 8631 __u8 rate; 8632 __u8 ch; 8633 __u8 cl; 8634 __be32 min; 8635 __be32 max; 8636 __be16 weight; 8637 __be16 pktsize; 8638 __be16 burstsize; 8639 __be16 r4; 8640 } params; 8641 } u; 8642}; 8643 8644/* 8645 * length of the formatting string 8646 */ 8647#define FW_DEVLOG_FMT_LEN 192 8648 8649/* 8650 * maximum number of the formatting string parameters 8651 */ 8652#define FW_DEVLOG_FMT_PARAMS_NUM 8 8653 8654/* 8655 * priority levels 8656 */ 8657enum fw_devlog_level { 8658 FW_DEVLOG_LEVEL_EMERG = 0x0, 8659 FW_DEVLOG_LEVEL_CRIT = 0x1, 8660 FW_DEVLOG_LEVEL_ERR = 0x2, 8661 FW_DEVLOG_LEVEL_NOTICE = 0x3, 8662 FW_DEVLOG_LEVEL_INFO = 0x4, 8663 FW_DEVLOG_LEVEL_DEBUG = 0x5, 8664 FW_DEVLOG_LEVEL_MAX = 0x5, 8665}; 8666 8667/* 8668 * facilities that may send a log message 8669 */ 8670enum fw_devlog_facility { 8671 FW_DEVLOG_FACILITY_CORE = 0x00, 8672 FW_DEVLOG_FACILITY_CF = 0x01, 8673 FW_DEVLOG_FACILITY_SCHED = 0x02, 8674 FW_DEVLOG_FACILITY_TIMER = 0x04, 8675 FW_DEVLOG_FACILITY_RES = 0x06, 8676 FW_DEVLOG_FACILITY_HW = 0x08, 8677 FW_DEVLOG_FACILITY_FLR = 0x10, 8678 FW_DEVLOG_FACILITY_DMAQ = 0x12, 8679 FW_DEVLOG_FACILITY_PHY = 0x14, 8680 FW_DEVLOG_FACILITY_MAC = 0x16, 8681 FW_DEVLOG_FACILITY_PORT = 0x18, 8682 FW_DEVLOG_FACILITY_VI = 0x1A, 8683 FW_DEVLOG_FACILITY_FILTER = 0x1C, 8684 FW_DEVLOG_FACILITY_ACL = 0x1E, 8685 FW_DEVLOG_FACILITY_TM = 0x20, 8686 FW_DEVLOG_FACILITY_QFC = 0x22, 8687 FW_DEVLOG_FACILITY_DCB = 0x24, 8688 FW_DEVLOG_FACILITY_ETH = 0x26, 8689 FW_DEVLOG_FACILITY_OFLD = 0x28, 8690 FW_DEVLOG_FACILITY_RI = 0x2A, 8691 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 8692 FW_DEVLOG_FACILITY_FCOE = 0x2E, 8693 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 8694 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8695 FW_DEVLOG_FACILITY_CHNET = 0x34, 8696 FW_DEVLOG_FACILITY_COISCSI = 0x36, 8697 FW_DEVLOG_FACILITY_MAX = 0x38, 8698}; 8699 8700/* 8701 * log message format 8702 */ 8703struct fw_devlog_e { 8704 __be64 timestamp; 8705 __be32 seqno; 8706 __be16 reserved1; 8707 __u8 level; 8708 __u8 facility; 8709 __u8 fmt[FW_DEVLOG_FMT_LEN]; 8710 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 8711 __be32 reserved3[4]; 8712}; 8713 8714struct fw_devlog_cmd { 8715 __be32 op_to_write; 8716 __be32 retval_len16; 8717 __u8 level; 8718 __u8 r2[7]; 8719 __be32 memtype_devlog_memaddr16_devlog; 8720 __be32 memsize_devlog; 8721 __be32 r3[2]; 8722}; 8723 8724#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8725#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8726#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8727 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8728#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8729 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8730 8731#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8732#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8733#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8734 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8735#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8736 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8737 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8738 8739enum fw_watchdog_actions { 8740 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8741 FW_WATCHDOG_ACTION_FLR = 1, 8742 FW_WATCHDOG_ACTION_BYPASS = 2, 8743 FW_WATCHDOG_ACTION_TMPCHK = 3, 8744 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8745 8746 FW_WATCHDOG_ACTION_MAX = 5, 8747}; 8748 8749#define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 8750 8751struct fw_watchdog_cmd { 8752 __be32 op_to_vfn; 8753 __be32 retval_len16; 8754 __be32 timeout; 8755 __be32 action; 8756}; 8757 8758#define S_FW_WATCHDOG_CMD_PFN 8 8759#define M_FW_WATCHDOG_CMD_PFN 0x7 8760#define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8761#define G_FW_WATCHDOG_CMD_PFN(x) \ 8762 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8763 8764#define S_FW_WATCHDOG_CMD_VFN 0 8765#define M_FW_WATCHDOG_CMD_VFN 0xff 8766#define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8767#define G_FW_WATCHDOG_CMD_VFN(x) \ 8768 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8769 8770struct fw_clip_cmd { 8771 __be32 op_to_write; 8772 __be32 alloc_to_len16; 8773 __be64 ip_hi; 8774 __be64 ip_lo; 8775 __be32 r4[2]; 8776}; 8777 8778#define S_FW_CLIP_CMD_ALLOC 31 8779#define M_FW_CLIP_CMD_ALLOC 0x1 8780#define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8781#define G_FW_CLIP_CMD_ALLOC(x) \ 8782 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8783#define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 8784 8785#define S_FW_CLIP_CMD_FREE 30 8786#define M_FW_CLIP_CMD_FREE 0x1 8787#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8788#define G_FW_CLIP_CMD_FREE(x) \ 8789 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8790#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 8791 8792#define S_FW_CLIP_CMD_INDEX 16 8793#define M_FW_CLIP_CMD_INDEX 0x1fff 8794#define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX) 8795#define G_FW_CLIP_CMD_INDEX(x) \ 8796 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX) 8797 8798/****************************************************************************** 8799 * F O i S C S I C O M M A N D s 8800 **************************************/ 8801 8802#define FW_CHNET_IFACE_ADDR_MAX 3 8803 8804enum fw_chnet_iface_cmd_subop { 8805 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 8806 8807 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 8808 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 8809 8810 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 8811 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 8812 8813 FW_CHNET_IFACE_CMD_SUBOP_MAX, 8814}; 8815 8816struct fw_chnet_iface_cmd { 8817 __be32 op_to_portid; 8818 __be32 retval_len16; 8819 __u8 subop; 8820 __u8 r2[2]; 8821 __u8 flags; 8822 __be32 ifid_ifstate; 8823 __be16 mtu; 8824 __be16 vlanid; 8825 __be32 r3; 8826 __be16 r4; 8827 __u8 mac[6]; 8828}; 8829 8830#define S_FW_CHNET_IFACE_CMD_PORTID 0 8831#define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8832#define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8833#define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8834 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 8835 8836#define S_FW_CHNET_IFACE_CMD_RSS_IQID 16 8837#define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff 8838#define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 8839 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID) 8840#define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 8841 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID) 8842 8843#define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0 8844#define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1 8845#define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 8846 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F) 8847#define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 8848 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \ 8849 M_FW_CHNET_IFACE_CMD_RSS_IQID_F) 8850#define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U) 8851 8852#define S_FW_CHNET_IFACE_CMD_IFID 8 8853#define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8854#define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8855#define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8856 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 8857 8858#define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8859#define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8860#define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8861#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8862 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 8863 8864struct fw_fcoe_res_info_cmd { 8865 __be32 op_to_read; 8866 __be32 retval_len16; 8867 __be16 e_d_tov; 8868 __be16 r_a_tov_seq; 8869 __be16 r_a_tov_els; 8870 __be16 r_r_tov; 8871 __be32 max_xchgs; 8872 __be32 max_ssns; 8873 __be32 used_xchgs; 8874 __be32 used_ssns; 8875 __be32 max_fcfs; 8876 __be32 max_vnps; 8877 __be32 used_fcfs; 8878 __be32 used_vnps; 8879}; 8880 8881struct fw_fcoe_link_cmd { 8882 __be32 op_to_portid; 8883 __be32 retval_len16; 8884 __be32 sub_opcode_fcfi; 8885 __u8 r3; 8886 __u8 lstatus; 8887 __be16 flags; 8888 __u8 r4; 8889 __u8 set_vlan; 8890 __be16 vlan_id; 8891 __be32 vnpi_pkd; 8892 __be16 r6; 8893 __u8 phy_mac[6]; 8894 __u8 vnport_wwnn[8]; 8895 __u8 vnport_wwpn[8]; 8896}; 8897 8898#define S_FW_FCOE_LINK_CMD_PORTID 0 8899#define M_FW_FCOE_LINK_CMD_PORTID 0xf 8900#define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 8901#define G_FW_FCOE_LINK_CMD_PORTID(x) \ 8902 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 8903 8904#define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 8905#define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 8906#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8907 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 8908#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8909 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 8910 8911#define S_FW_FCOE_LINK_CMD_FCFI 0 8912#define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 8913#define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 8914#define G_FW_FCOE_LINK_CMD_FCFI(x) \ 8915 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 8916 8917#define S_FW_FCOE_LINK_CMD_VNPI 0 8918#define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 8919#define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 8920#define G_FW_FCOE_LINK_CMD_VNPI(x) \ 8921 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 8922 8923struct fw_fcoe_vnp_cmd { 8924 __be32 op_to_fcfi; 8925 __be32 alloc_to_len16; 8926 __be32 gen_wwn_to_vnpi; 8927 __be32 vf_id; 8928 __be16 iqid; 8929 __u8 vnport_mac[6]; 8930 __u8 vnport_wwnn[8]; 8931 __u8 vnport_wwpn[8]; 8932 __u8 cmn_srv_parms[16]; 8933 __u8 clsp_word_0_1[8]; 8934}; 8935 8936#define S_FW_FCOE_VNP_CMD_FCFI 0 8937#define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 8938#define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 8939#define G_FW_FCOE_VNP_CMD_FCFI(x) \ 8940 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 8941 8942#define S_FW_FCOE_VNP_CMD_ALLOC 31 8943#define M_FW_FCOE_VNP_CMD_ALLOC 0x1 8944#define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 8945#define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 8946 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 8947#define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 8948 8949#define S_FW_FCOE_VNP_CMD_FREE 30 8950#define M_FW_FCOE_VNP_CMD_FREE 0x1 8951#define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 8952#define G_FW_FCOE_VNP_CMD_FREE(x) \ 8953 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 8954#define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 8955 8956#define S_FW_FCOE_VNP_CMD_MODIFY 29 8957#define M_FW_FCOE_VNP_CMD_MODIFY 0x1 8958#define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 8959#define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 8960 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 8961#define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 8962 8963#define S_FW_FCOE_VNP_CMD_GEN_WWN 22 8964#define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 8965#define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 8966#define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 8967 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 8968#define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 8969 8970#define S_FW_FCOE_VNP_CMD_PERSIST 21 8971#define M_FW_FCOE_VNP_CMD_PERSIST 0x1 8972#define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 8973#define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 8974 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 8975#define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 8976 8977#define S_FW_FCOE_VNP_CMD_VFID_EN 20 8978#define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8979#define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 8980#define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 8981 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 8982#define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 8983 8984#define S_FW_FCOE_VNP_CMD_VNPI 0 8985#define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 8986#define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 8987#define G_FW_FCOE_VNP_CMD_VNPI(x) \ 8988 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 8989 8990struct fw_fcoe_sparams_cmd { 8991 __be32 op_to_portid; 8992 __be32 retval_len16; 8993 __u8 r3[7]; 8994 __u8 cos; 8995 __u8 lport_wwnn[8]; 8996 __u8 lport_wwpn[8]; 8997 __u8 cmn_srv_parms[16]; 8998 __u8 cls_srv_parms[16]; 8999}; 9000 9001#define S_FW_FCOE_SPARAMS_CMD_PORTID 0 9002#define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 9003#define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 9004#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 9005 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 9006 9007struct fw_fcoe_stats_cmd { 9008 __be32 op_to_flowid; 9009 __be32 free_to_len16; 9010 union fw_fcoe_stats { 9011 struct fw_fcoe_stats_ctl { 9012 __u8 nstats_port; 9013 __u8 port_valid_ix; 9014 __be16 r6; 9015 __be32 r7; 9016 __be64 stat0; 9017 __be64 stat1; 9018 __be64 stat2; 9019 __be64 stat3; 9020 __be64 stat4; 9021 __be64 stat5; 9022 } ctl; 9023 struct fw_fcoe_port_stats { 9024 __be64 tx_bcast_bytes; 9025 __be64 tx_bcast_frames; 9026 __be64 tx_mcast_bytes; 9027 __be64 tx_mcast_frames; 9028 __be64 tx_ucast_bytes; 9029 __be64 tx_ucast_frames; 9030 __be64 tx_drop_frames; 9031 __be64 tx_offload_bytes; 9032 __be64 tx_offload_frames; 9033 __be64 rx_bcast_bytes; 9034 __be64 rx_bcast_frames; 9035 __be64 rx_mcast_bytes; 9036 __be64 rx_mcast_frames; 9037 __be64 rx_ucast_bytes; 9038 __be64 rx_ucast_frames; 9039 __be64 rx_err_frames; 9040 } port_stats; 9041 struct fw_fcoe_fcf_stats { 9042 __be32 fip_tx_bytes; 9043 __be32 fip_tx_fr; 9044 __be64 fcf_ka; 9045 __be64 mcast_adv_rcvd; 9046 __be16 ucast_adv_rcvd; 9047 __be16 sol_sent; 9048 __be16 vlan_req; 9049 __be16 vlan_rpl; 9050 __be16 clr_vlink; 9051 __be16 link_down; 9052 __be16 link_up; 9053 __be16 logo; 9054 __be16 flogi_req; 9055 __be16 flogi_rpl; 9056 __be16 fdisc_req; 9057 __be16 fdisc_rpl; 9058 __be16 fka_prd_chg; 9059 __be16 fc_map_chg; 9060 __be16 vfid_chg; 9061 __u8 no_fka_req; 9062 __u8 no_vnp; 9063 } fcf_stats; 9064 struct fw_fcoe_pcb_stats { 9065 __be64 tx_bytes; 9066 __be64 tx_frames; 9067 __be64 rx_bytes; 9068 __be64 rx_frames; 9069 __be32 vnp_ka; 9070 __be32 unsol_els_rcvd; 9071 __be64 unsol_cmd_rcvd; 9072 __be16 implicit_logo; 9073 __be16 flogi_inv_sparm; 9074 __be16 fdisc_inv_sparm; 9075 __be16 flogi_rjt; 9076 __be16 fdisc_rjt; 9077 __be16 no_ssn; 9078 __be16 mac_flt_fail; 9079 __be16 inv_fr_rcvd; 9080 } pcb_stats; 9081 struct fw_fcoe_scb_stats { 9082 __be64 tx_bytes; 9083 __be64 tx_frames; 9084 __be64 rx_bytes; 9085 __be64 rx_frames; 9086 __be32 host_abrt_req; 9087 __be32 adap_auto_abrt; 9088 __be32 adap_abrt_rsp; 9089 __be32 host_ios_req; 9090 __be16 ssn_offl_ios; 9091 __be16 ssn_not_rdy_ios; 9092 __u8 rx_data_ddp_err; 9093 __u8 ddp_flt_set_err; 9094 __be16 rx_data_fr_err; 9095 __u8 bad_st_abrt_req; 9096 __u8 no_io_abrt_req; 9097 __u8 abort_tmo; 9098 __u8 abort_tmo_2; 9099 __be32 abort_req; 9100 __u8 no_ppod_res_tmo; 9101 __u8 bp_tmo; 9102 __u8 adap_auto_cls; 9103 __u8 no_io_cls_req; 9104 __be32 host_cls_req; 9105 __be64 unsol_cmd_rcvd; 9106 __be32 plogi_req_rcvd; 9107 __be32 prli_req_rcvd; 9108 __be16 logo_req_rcvd; 9109 __be16 prlo_req_rcvd; 9110 __be16 plogi_rjt_rcvd; 9111 __be16 prli_rjt_rcvd; 9112 __be32 adisc_req_rcvd; 9113 __be32 rscn_rcvd; 9114 __be32 rrq_req_rcvd; 9115 __be32 unsol_els_rcvd; 9116 __u8 adisc_rjt_rcvd; 9117 __u8 scr_rjt; 9118 __u8 ct_rjt; 9119 __u8 inval_bls_rcvd; 9120 __be32 ba_rjt_rcvd; 9121 } scb_stats; 9122 } u; 9123}; 9124 9125#define S_FW_FCOE_STATS_CMD_FLOWID 0 9126#define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 9127#define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 9128#define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 9129 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 9130 9131#define S_FW_FCOE_STATS_CMD_FREE 30 9132#define M_FW_FCOE_STATS_CMD_FREE 0x1 9133#define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 9134#define G_FW_FCOE_STATS_CMD_FREE(x) \ 9135 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 9136#define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 9137 9138#define S_FW_FCOE_STATS_CMD_NSTATS 4 9139#define M_FW_FCOE_STATS_CMD_NSTATS 0x7 9140#define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 9141#define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 9142 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 9143 9144#define S_FW_FCOE_STATS_CMD_PORT 0 9145#define M_FW_FCOE_STATS_CMD_PORT 0x3 9146#define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 9147#define G_FW_FCOE_STATS_CMD_PORT(x) \ 9148 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 9149 9150#define S_FW_FCOE_STATS_CMD_PORT_VALID 7 9151#define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 9152#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9153 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 9154#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9155 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 9156#define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 9157 9158#define S_FW_FCOE_STATS_CMD_IX 0 9159#define M_FW_FCOE_STATS_CMD_IX 0x3f 9160#define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 9161#define G_FW_FCOE_STATS_CMD_IX(x) \ 9162 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 9163 9164struct fw_fcoe_fcf_cmd { 9165 __be32 op_to_fcfi; 9166 __be32 retval_len16; 9167 __be16 priority_pkd; 9168 __u8 mac[6]; 9169 __u8 name_id[8]; 9170 __u8 fabric[8]; 9171 __be16 vf_id; 9172 __be16 max_fcoe_size; 9173 __u8 vlan_id; 9174 __u8 fc_map[3]; 9175 __be32 fka_adv; 9176 __be32 r6; 9177 __u8 r7_hi; 9178 __u8 fpma_to_portid; 9179 __u8 spma_mac[6]; 9180 __be64 r8; 9181}; 9182 9183#define S_FW_FCOE_FCF_CMD_FCFI 0 9184#define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 9185#define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 9186#define G_FW_FCOE_FCF_CMD_FCFI(x) \ 9187 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 9188 9189#define S_FW_FCOE_FCF_CMD_PRIORITY 0 9190#define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 9191#define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 9192#define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 9193 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 9194 9195#define S_FW_FCOE_FCF_CMD_FPMA 6 9196#define M_FW_FCOE_FCF_CMD_FPMA 0x1 9197#define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 9198#define G_FW_FCOE_FCF_CMD_FPMA(x) \ 9199 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 9200#define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 9201 9202#define S_FW_FCOE_FCF_CMD_SPMA 5 9203#define M_FW_FCOE_FCF_CMD_SPMA 0x1 9204#define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 9205#define G_FW_FCOE_FCF_CMD_SPMA(x) \ 9206 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 9207#define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 9208 9209#define S_FW_FCOE_FCF_CMD_LOGIN 4 9210#define M_FW_FCOE_FCF_CMD_LOGIN 0x1 9211#define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 9212#define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 9213 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 9214#define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 9215 9216#define S_FW_FCOE_FCF_CMD_PORTID 0 9217#define M_FW_FCOE_FCF_CMD_PORTID 0xf 9218#define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 9219#define G_FW_FCOE_FCF_CMD_PORTID(x) \ 9220 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 9221 9222/****************************************************************************** 9223 * E R R O R a n d D E B U G C O M M A N D s 9224 ******************************************************/ 9225 9226enum fw_error_type { 9227 FW_ERROR_TYPE_EXCEPTION = 0x0, 9228 FW_ERROR_TYPE_HWMODULE = 0x1, 9229 FW_ERROR_TYPE_WR = 0x2, 9230 FW_ERROR_TYPE_ACL = 0x3, 9231}; 9232 9233enum fw_dcb_ieee_locations { 9234 FW_IEEE_LOC_LOCAL, 9235 FW_IEEE_LOC_PEER, 9236 FW_IEEE_LOC_OPERATIONAL, 9237}; 9238 9239struct fw_dcb_ieee_cmd { 9240 __be32 op_to_location; 9241 __be32 changed_to_len16; 9242 union fw_dcbx_stats { 9243 struct fw_dcbx_pfc_stats_ieee { 9244 __be32 pfc_mbc_pkd; 9245 __be32 pfc_willing_to_pfc_en; 9246 } dcbx_pfc_stats; 9247 struct fw_dcbx_ets_stats_ieee { 9248 __be32 cbs_to_ets_max_tc; 9249 __be32 pg_table; 9250 __u8 pg_percent[8]; 9251 __u8 tsa[8]; 9252 } dcbx_ets_stats; 9253 struct fw_dcbx_app_stats_ieee { 9254 __be32 num_apps_pkd; 9255 __be32 r6; 9256 __be32 app[4]; 9257 } dcbx_app_stats; 9258 struct fw_dcbx_control { 9259 __be32 multi_peer_invalidated; 9260 __u8 version; 9261 __u8 r6[3]; 9262 } dcbx_control; 9263 } u; 9264}; 9265 9266#define S_FW_DCB_IEEE_CMD_PORT 8 9267#define M_FW_DCB_IEEE_CMD_PORT 0x7 9268#define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 9269#define G_FW_DCB_IEEE_CMD_PORT(x) \ 9270 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 9271 9272#define S_FW_DCB_IEEE_CMD_FEATURE 2 9273#define M_FW_DCB_IEEE_CMD_FEATURE 0x7 9274#define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 9275#define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 9276 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 9277 9278#define S_FW_DCB_IEEE_CMD_LOCATION 0 9279#define M_FW_DCB_IEEE_CMD_LOCATION 0x3 9280#define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 9281#define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 9282 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 9283 9284#define S_FW_DCB_IEEE_CMD_CHANGED 20 9285#define M_FW_DCB_IEEE_CMD_CHANGED 0x1 9286#define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 9287#define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 9288 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 9289#define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 9290 9291#define S_FW_DCB_IEEE_CMD_RECEIVED 19 9292#define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 9293#define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 9294#define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 9295 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 9296#define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 9297 9298#define S_FW_DCB_IEEE_CMD_APPLY 18 9299#define M_FW_DCB_IEEE_CMD_APPLY 0x1 9300#define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 9301#define G_FW_DCB_IEEE_CMD_APPLY(x) \ 9302 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 9303#define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 9304 9305#define S_FW_DCB_IEEE_CMD_DISABLED 17 9306#define M_FW_DCB_IEEE_CMD_DISABLED 0x1 9307#define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 9308#define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 9309 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 9310#define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 9311 9312#define S_FW_DCB_IEEE_CMD_MORE 16 9313#define M_FW_DCB_IEEE_CMD_MORE 0x1 9314#define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 9315#define G_FW_DCB_IEEE_CMD_MORE(x) \ 9316 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 9317#define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 9318 9319#define S_FW_DCB_IEEE_CMD_PFC_MBC 0 9320#define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 9321#define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 9322#define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 9323 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 9324#define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 9325 9326#define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 9327#define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 9328#define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9329 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 9330#define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9331 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 9332#define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 9333 9334#define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 9335#define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 9336#define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9337#define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 9338 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9339 9340#define S_FW_DCB_IEEE_CMD_PFC_EN 0 9341#define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 9342#define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 9343#define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 9344 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 9345 9346#define S_FW_DCB_IEEE_CMD_CBS 16 9347#define M_FW_DCB_IEEE_CMD_CBS 0x1 9348#define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 9349#define G_FW_DCB_IEEE_CMD_CBS(x) \ 9350 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 9351#define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 9352 9353#define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 9354#define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 9355#define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9356 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 9357#define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9358 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 9359#define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 9360 9361#define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 9362#define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 9363#define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9364#define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 9365 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9366 9367#define S_FW_DCB_IEEE_CMD_NUM_APPS 0 9368#define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 9369#define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 9370#define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 9371 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 9372 9373#define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 9374#define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 9375#define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 9376#define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 9377 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 9378#define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 9379 9380#define S_FW_DCB_IEEE_CMD_INVALIDATED 30 9381#define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 9382#define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9383 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 9384#define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9385 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 9386#define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 9387 9388/* Hand-written */ 9389#define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 9390#define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 9391#define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9392#define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 9393 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9394 9395#define S_FW_DCB_IEEE_CMD_APP_SELECT 3 9396#define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 9397#define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 9398#define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 9399 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 9400 9401#define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 9402#define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 9403#define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 9404#define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 9405 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 9406 9407 9408struct fw_error_cmd { 9409 __be32 op_to_type; 9410 __be32 len16_pkd; 9411 union fw_error { 9412 struct fw_error_exception { 9413 __be32 info[6]; 9414 } exception; 9415 struct fw_error_hwmodule { 9416 __be32 regaddr; 9417 __be32 regval; 9418 } hwmodule; 9419 struct fw_error_wr { 9420 __be16 cidx; 9421 __be16 pfn_vfn; 9422 __be32 eqid; 9423 __u8 wrhdr[16]; 9424 } wr; 9425 struct fw_error_acl { 9426 __be16 cidx; 9427 __be16 pfn_vfn; 9428 __be32 eqid; 9429 __be16 mv_pkd; 9430 __u8 val[6]; 9431 __be64 r4; 9432 } acl; 9433 } u; 9434}; 9435 9436#define S_FW_ERROR_CMD_FATAL 4 9437#define M_FW_ERROR_CMD_FATAL 0x1 9438#define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 9439#define G_FW_ERROR_CMD_FATAL(x) \ 9440 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 9441#define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 9442 9443#define S_FW_ERROR_CMD_TYPE 0 9444#define M_FW_ERROR_CMD_TYPE 0xf 9445#define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 9446#define G_FW_ERROR_CMD_TYPE(x) \ 9447 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 9448 9449#define S_FW_ERROR_CMD_PFN 8 9450#define M_FW_ERROR_CMD_PFN 0x7 9451#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9452#define G_FW_ERROR_CMD_PFN(x) \ 9453 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9454 9455#define S_FW_ERROR_CMD_VFN 0 9456#define M_FW_ERROR_CMD_VFN 0xff 9457#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9458#define G_FW_ERROR_CMD_VFN(x) \ 9459 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9460 9461#define S_FW_ERROR_CMD_PFN 8 9462#define M_FW_ERROR_CMD_PFN 0x7 9463#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9464#define G_FW_ERROR_CMD_PFN(x) \ 9465 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9466 9467#define S_FW_ERROR_CMD_VFN 0 9468#define M_FW_ERROR_CMD_VFN 0xff 9469#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9470#define G_FW_ERROR_CMD_VFN(x) \ 9471 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9472 9473#define S_FW_ERROR_CMD_MV 15 9474#define M_FW_ERROR_CMD_MV 0x1 9475#define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 9476#define G_FW_ERROR_CMD_MV(x) \ 9477 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 9478#define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 9479 9480struct fw_debug_cmd { 9481 __be32 op_type; 9482 __be32 len16_pkd; 9483 union fw_debug { 9484 struct fw_debug_assert { 9485 __be32 fcid; 9486 __be32 line; 9487 __be32 x; 9488 __be32 y; 9489 __u8 filename_0_7[8]; 9490 __u8 filename_8_15[8]; 9491 __be64 r3; 9492 } assert; 9493 struct fw_debug_prt { 9494 __be16 dprtstridx; 9495 __be16 r3[3]; 9496 __be32 dprtstrparam0; 9497 __be32 dprtstrparam1; 9498 __be32 dprtstrparam2; 9499 __be32 dprtstrparam3; 9500 } prt; 9501 } u; 9502}; 9503 9504#define S_FW_DEBUG_CMD_TYPE 0 9505#define M_FW_DEBUG_CMD_TYPE 0xff 9506#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 9507#define G_FW_DEBUG_CMD_TYPE(x) \ 9508 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 9509 9510enum fw_diag_cmd_type { 9511 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 9512}; 9513 9514enum fw_diag_cmd_ofldiag_op { 9515 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 9516 FW_DIAG_CMD_OFLDIAG_TEST_START, 9517 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 9518 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 9519}; 9520 9521enum fw_diag_cmd_ofldiag_status { 9522 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 9523 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 9524 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 9525 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 9526}; 9527 9528struct fw_diag_cmd { 9529 __be32 op_type; 9530 __be32 len16_pkd; 9531 union fw_diag_test { 9532 struct fw_diag_test_ofldiag { 9533 __u8 test_op; 9534 __u8 r3; 9535 __be16 test_status; 9536 __be32 duration; 9537 } ofldiag; 9538 } u; 9539}; 9540 9541#define S_FW_DIAG_CMD_TYPE 0 9542#define M_FW_DIAG_CMD_TYPE 0xff 9543#define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 9544#define G_FW_DIAG_CMD_TYPE(x) \ 9545 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 9546 9547struct fw_hma_cmd { 9548 __be32 op_pkd; 9549 __be32 retval_len16; 9550 __be32 mode_to_pcie_params; 9551 __be32 naddr_size; 9552 __be32 addr_size_pkd; 9553 __be32 r6; 9554 __be64 phy_address[5]; 9555}; 9556 9557#define S_FW_HMA_CMD_MODE 31 9558#define M_FW_HMA_CMD_MODE 0x1 9559#define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 9560#define G_FW_HMA_CMD_MODE(x) \ 9561 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 9562#define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 9563 9564#define S_FW_HMA_CMD_SOC 30 9565#define M_FW_HMA_CMD_SOC 0x1 9566#define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 9567#define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 9568#define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 9569 9570#define S_FW_HMA_CMD_EOC 29 9571#define M_FW_HMA_CMD_EOC 0x1 9572#define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 9573#define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 9574#define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 9575 9576#define S_FW_HMA_CMD_PCIE_PARAMS 0 9577#define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 9578#define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 9579#define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 9580 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 9581 9582#define S_FW_HMA_CMD_NADDR 12 9583#define M_FW_HMA_CMD_NADDR 0x3f 9584#define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 9585#define G_FW_HMA_CMD_NADDR(x) \ 9586 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 9587 9588#define S_FW_HMA_CMD_SIZE 0 9589#define M_FW_HMA_CMD_SIZE 0xfff 9590#define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 9591#define G_FW_HMA_CMD_SIZE(x) \ 9592 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 9593 9594#define S_FW_HMA_CMD_ADDR_SIZE 11 9595#define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 9596#define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 9597#define G_FW_HMA_CMD_ADDR_SIZE(x) \ 9598 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 9599 9600/****************************************************************************** 9601 * P C I E F W R E G I S T E R 9602 **************************************/ 9603 9604enum pcie_fw_eval { 9605 PCIE_FW_EVAL_CRASH = 0, 9606 PCIE_FW_EVAL_PREP = 1, 9607 PCIE_FW_EVAL_CONF = 2, 9608 PCIE_FW_EVAL_INIT = 3, 9609 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9610 PCIE_FW_EVAL_OVERHEAT = 5, 9611 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9612}; 9613 9614/** 9615 * Register definitions for the PCIE_FW register which the firmware uses 9616 * to retain status across RESETs. This register should be considered 9617 * as a READ-ONLY register for Host Software and only to be used to 9618 * track firmware initialization/error state, etc. 9619 */ 9620#define S_PCIE_FW_ERR 31 9621#define M_PCIE_FW_ERR 0x1 9622#define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9623#define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9624#define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9625 9626#define S_PCIE_FW_INIT 30 9627#define M_PCIE_FW_INIT 0x1 9628#define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9629#define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9630#define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9631 9632#define S_PCIE_FW_HALT 29 9633#define M_PCIE_FW_HALT 0x1 9634#define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9635#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9636#define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 9637 9638#define S_PCIE_FW_EVAL 24 9639#define M_PCIE_FW_EVAL 0x7 9640#define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9641#define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9642 9643#define S_PCIE_FW_STAGE 21 9644#define M_PCIE_FW_STAGE 0x7 9645#define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9646#define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9647 9648#define S_PCIE_FW_ASYNCNOT_VLD 20 9649#define M_PCIE_FW_ASYNCNOT_VLD 0x1 9650#define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9651 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9652#define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9653 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9654#define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9655 9656#define S_PCIE_FW_ASYNCNOTINT 19 9657#define M_PCIE_FW_ASYNCNOTINT 0x1 9658#define V_PCIE_FW_ASYNCNOTINT(x) \ 9659 ((x) << S_PCIE_FW_ASYNCNOTINT) 9660#define G_PCIE_FW_ASYNCNOTINT(x) \ 9661 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9662#define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9663 9664#define S_PCIE_FW_ASYNCNOT 16 9665#define M_PCIE_FW_ASYNCNOT 0x7 9666#define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9667#define G_PCIE_FW_ASYNCNOT(x) \ 9668 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9669 9670#define S_PCIE_FW_MASTER_VLD 15 9671#define M_PCIE_FW_MASTER_VLD 0x1 9672#define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9673#define G_PCIE_FW_MASTER_VLD(x) \ 9674 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9675#define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9676 9677#define S_PCIE_FW_MASTER 12 9678#define M_PCIE_FW_MASTER 0x7 9679#define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9680#define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9681 9682#define S_PCIE_FW_RESET_VLD 11 9683#define M_PCIE_FW_RESET_VLD 0x1 9684#define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9685#define G_PCIE_FW_RESET_VLD(x) \ 9686 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9687#define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9688 9689#define S_PCIE_FW_RESET 8 9690#define M_PCIE_FW_RESET 0x7 9691#define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9692#define G_PCIE_FW_RESET(x) \ 9693 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9694 9695#define S_PCIE_FW_REGISTERED 0 9696#define M_PCIE_FW_REGISTERED 0xff 9697#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9698#define G_PCIE_FW_REGISTERED(x) \ 9699 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9700 9701 9702/****************************************************************************** 9703 * P C I E F W P F 0 R E G I S T E R 9704 **********************************************/ 9705 9706/* 9707 * this register is available as 32-bit of persistent storage (accross 9708 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9709 * will not write it) 9710 */ 9711 9712 9713/****************************************************************************** 9714 * P C I E F W P F 7 R E G I S T E R 9715 **********************************************/ 9716 9717/* 9718 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9719 * access the "devlog" which needing to contact firmware. The encoding is 9720 * mostly the same as that returned by the DEVLOG command except for the size 9721 * which is encoded as the number of entries in multiples-1 of 128 here rather 9722 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9723 * and 15 means 2048. This of course in turn constrains the allowed values 9724 * for the devlog size ... 9725 */ 9726#define PCIE_FW_PF_DEVLOG 7 9727 9728#define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9729#define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9730#define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9731 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9732#define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9733 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9734 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9735 9736#define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9737#define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9738#define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9739#define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9740 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9741 9742#define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9743#define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9744#define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9745#define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9746 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9747 9748 9749/****************************************************************************** 9750 * B I N A R Y H E A D E R F O R M A T 9751 **********************************************/ 9752 9753/* 9754 * firmware binary header format 9755 */ 9756struct fw_hdr { 9757 __u8 ver; 9758 __u8 chip; /* terminator chip family */ 9759 __be16 len512; /* bin length in units of 512-bytes */ 9760 __be32 fw_ver; /* firmware version */ 9761 __be32 tp_microcode_ver; /* tcp processor microcode version */ 9762 __u8 intfver_nic; 9763 __u8 intfver_vnic; 9764 __u8 intfver_ofld; 9765 __u8 intfver_ri; 9766 __u8 intfver_iscsipdu; 9767 __u8 intfver_iscsi; 9768 __u8 intfver_fcoepdu; 9769 __u8 intfver_fcoe; 9770 __u32 reserved2; 9771 __u32 reserved3; 9772 __be32 magic; /* runtime or bootstrap fw */ 9773 __be32 flags; 9774 __be32 reserved6[23]; 9775}; 9776 9777enum fw_hdr_chip { 9778 FW_HDR_CHIP_T4, 9779 FW_HDR_CHIP_T5, 9780 FW_HDR_CHIP_T6 9781}; 9782 9783#define S_FW_HDR_FW_VER_MAJOR 24 9784#define M_FW_HDR_FW_VER_MAJOR 0xff 9785#define V_FW_HDR_FW_VER_MAJOR(x) \ 9786 ((x) << S_FW_HDR_FW_VER_MAJOR) 9787#define G_FW_HDR_FW_VER_MAJOR(x) \ 9788 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9789 9790#define S_FW_HDR_FW_VER_MINOR 16 9791#define M_FW_HDR_FW_VER_MINOR 0xff 9792#define V_FW_HDR_FW_VER_MINOR(x) \ 9793 ((x) << S_FW_HDR_FW_VER_MINOR) 9794#define G_FW_HDR_FW_VER_MINOR(x) \ 9795 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9796 9797#define S_FW_HDR_FW_VER_MICRO 8 9798#define M_FW_HDR_FW_VER_MICRO 0xff 9799#define V_FW_HDR_FW_VER_MICRO(x) \ 9800 ((x) << S_FW_HDR_FW_VER_MICRO) 9801#define G_FW_HDR_FW_VER_MICRO(x) \ 9802 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9803 9804#define S_FW_HDR_FW_VER_BUILD 0 9805#define M_FW_HDR_FW_VER_BUILD 0xff 9806#define V_FW_HDR_FW_VER_BUILD(x) \ 9807 ((x) << S_FW_HDR_FW_VER_BUILD) 9808#define G_FW_HDR_FW_VER_BUILD(x) \ 9809 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9810 9811enum { 9812 T4FW_VERSION_MAJOR = 0x01, 9813 T4FW_VERSION_MINOR = 0x17, 9814 T4FW_VERSION_MICRO = 0x00, 9815 T4FW_VERSION_BUILD = 0x00, 9816 9817 T5FW_VERSION_MAJOR = 0x01, 9818 T5FW_VERSION_MINOR = 0x17, 9819 T5FW_VERSION_MICRO = 0x00, 9820 T5FW_VERSION_BUILD = 0x00, 9821 9822 T6FW_VERSION_MAJOR = 0x01, 9823 T6FW_VERSION_MINOR = 0x17, 9824 T6FW_VERSION_MICRO = 0x00, 9825 T6FW_VERSION_BUILD = 0x00, 9826}; 9827 9828enum { 9829 /* T4 9830 */ 9831 T4FW_HDR_INTFVER_NIC = 0x00, 9832 T4FW_HDR_INTFVER_VNIC = 0x00, 9833 T4FW_HDR_INTFVER_OFLD = 0x00, 9834 T4FW_HDR_INTFVER_RI = 0x00, 9835 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 9836 T4FW_HDR_INTFVER_ISCSI = 0x00, 9837 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 9838 T4FW_HDR_INTFVER_FCOE = 0x00, 9839 9840 /* T5 9841 */ 9842 T5FW_HDR_INTFVER_NIC = 0x00, 9843 T5FW_HDR_INTFVER_VNIC = 0x00, 9844 T5FW_HDR_INTFVER_OFLD = 0x00, 9845 T5FW_HDR_INTFVER_RI = 0x00, 9846 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9847 T5FW_HDR_INTFVER_ISCSI = 0x00, 9848 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9849 T5FW_HDR_INTFVER_FCOE = 0x00, 9850 9851 /* T6 9852 */ 9853 T6FW_HDR_INTFVER_NIC = 0x00, 9854 T6FW_HDR_INTFVER_VNIC = 0x00, 9855 T6FW_HDR_INTFVER_OFLD = 0x00, 9856 T6FW_HDR_INTFVER_RI = 0x00, 9857 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9858 T6FW_HDR_INTFVER_ISCSI = 0x00, 9859 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9860 T6FW_HDR_INTFVER_FCOE = 0x00, 9861}; 9862 9863enum { 9864 FW_HDR_MAGIC_RUNTIME = 0x00000000, 9865 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9866}; 9867 9868enum fw_hdr_flags { 9869 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 9870}; 9871 9872/* 9873 * External PHY firmware binary header format 9874 */ 9875struct fw_ephy_hdr { 9876 __u8 ver; 9877 __u8 reserved; 9878 __be16 len512; /* bin length in units of 512-bytes */ 9879 __be32 magic; 9880 9881 __be16 vendor_id; 9882 __be16 device_id; 9883 __be32 version; 9884 9885 __be32 reserved1[4]; 9886}; 9887 9888enum { 9889 FW_EPHY_HDR_MAGIC = 0x65706879, 9890}; 9891 9892struct fw_ifconf_dhcp_info { 9893 __be32 addr; 9894 __be32 mask; 9895 __be16 vlanid; 9896 __be16 mtu; 9897 __be32 gw; 9898 __u8 op; 9899 __u8 len; 9900 __u8 data[270]; 9901}; 9902 9903#endif /* _T4FW_INTERFACE_H_ */ 9904