cxgb_common.h revision 180583
1167514Skmacy/************************************************************************** 2167514Skmacy 3177340SkmacyCopyright (c) 2007-2008, Chelsio Inc. 4167514SkmacyAll rights reserved. 5167514Skmacy 6167514SkmacyRedistribution and use in source and binary forms, with or without 7167514Skmacymodification, are permitted provided that the following conditions are met: 8167514Skmacy 9167514Skmacy 1. Redistributions of source code must retain the above copyright notice, 10167514Skmacy this list of conditions and the following disclaimer. 11167514Skmacy 12170076Skmacy 2. Neither the name of the Chelsio Corporation nor the names of its 13167514Skmacy contributors may be used to endorse or promote products derived from 14167514Skmacy this software without specific prior written permission. 15167514Skmacy 16167514SkmacyTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17167514SkmacyAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18167514SkmacyIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19167514SkmacyARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20167514SkmacyLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21167514SkmacyCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22167514SkmacySUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23167514SkmacyINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24167514SkmacyCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25167514SkmacyARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26167514SkmacyPOSSIBILITY OF SUCH DAMAGE. 27167514Skmacy 28167514Skmacy$FreeBSD: head/sys/dev/cxgb/common/cxgb_common.h 180583 2008-07-18 06:12:31Z kmacy $ 29167514Skmacy 30167514Skmacy***************************************************************************/ 31167514Skmacy#ifndef __CHELSIO_COMMON_H 32167514Skmacy#define __CHELSIO_COMMON_H 33167514Skmacy 34170076Skmacy#ifdef CONFIG_DEFINED 35170076Skmacy#include <cxgb_osdep.h> 36170076Skmacy#else 37167514Skmacy#include <dev/cxgb/cxgb_osdep.h> 38170076Skmacy#endif 39167514Skmacy 40167514Skmacyenum { 41170654Skmacy MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ 42167514Skmacy EEPROMSIZE = 8192, /* Serial EEPROM size */ 43172096Skmacy SERNUM_LEN = 16, /* Serial # length */ 44167514Skmacy RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 45167514Skmacy TCB_SIZE = 128, /* TCB size */ 46167514Skmacy NMTUS = 16, /* size of MTU table */ 47167514Skmacy NCCTRL_WIN = 32, /* # of congestion control windows */ 48167746Skmacy NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 49170654Skmacy PROTO_SRAM_LINES = 128, /* size of protocol sram */ 50180583Skmacy EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ 51167514Skmacy}; 52167514Skmacy 53170654Skmacy#define MAX_RX_COALESCING_LEN 12288U 54167514Skmacy 55167514Skmacyenum { 56167514Skmacy PAUSE_RX = 1 << 0, 57167514Skmacy PAUSE_TX = 1 << 1, 58167514Skmacy PAUSE_AUTONEG = 1 << 2 59167514Skmacy}; 60167514Skmacy 61167514Skmacyenum { 62170654Skmacy SUPPORTED_IRQ = 1 << 24 63167514Skmacy}; 64167514Skmacy 65167514Skmacyenum { /* adapter interrupt-maintained statistics */ 66167514Skmacy STAT_ULP_CH0_PBL_OOB, 67167514Skmacy STAT_ULP_CH1_PBL_OOB, 68167514Skmacy STAT_PCI_CORR_ECC, 69167514Skmacy 70167514Skmacy IRQ_NUM_STATS /* keep last */ 71167514Skmacy}; 72167514Skmacy 73167514Skmacyenum { 74170654Skmacy TP_VERSION_MAJOR = 1, 75171471Skmacy TP_VERSION_MINOR = 1, 76171471Skmacy TP_VERSION_MICRO = 0 77170654Skmacy}; 78170654Skmacy 79170654Skmacy#define S_TP_VERSION_MAJOR 16 80170654Skmacy#define M_TP_VERSION_MAJOR 0xFF 81170654Skmacy#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 82170654Skmacy#define G_TP_VERSION_MAJOR(x) \ 83170654Skmacy (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 84170654Skmacy 85170654Skmacy#define S_TP_VERSION_MINOR 8 86170654Skmacy#define M_TP_VERSION_MINOR 0xFF 87170654Skmacy#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 88170654Skmacy#define G_TP_VERSION_MINOR(x) \ 89170654Skmacy (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 90170654Skmacy 91170654Skmacy#define S_TP_VERSION_MICRO 0 92170654Skmacy#define M_TP_VERSION_MICRO 0xFF 93170654Skmacy#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 94170654Skmacy#define G_TP_VERSION_MICRO(x) \ 95170654Skmacy (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 96170654Skmacy 97170654Skmacyenum { 98176472Skmacy FW_VERSION_MAJOR = 5, 99176472Skmacy FW_VERSION_MINOR = 0, 100167746Skmacy FW_VERSION_MICRO = 0 101167746Skmacy}; 102167746Skmacy 103167746Skmacyenum { 104167514Skmacy SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 105167514Skmacy SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 106167514Skmacy SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 107167514Skmacy}; 108167514Skmacy 109167514Skmacyenum sge_context_type { /* SGE egress context types */ 110167514Skmacy SGE_CNTXT_RDMA = 0, 111167514Skmacy SGE_CNTXT_ETH = 2, 112167514Skmacy SGE_CNTXT_OFLD = 4, 113167514Skmacy SGE_CNTXT_CTRL = 5 114167514Skmacy}; 115167514Skmacy 116167514Skmacyenum { 117167514Skmacy AN_PKT_SIZE = 32, /* async notification packet size */ 118167514Skmacy IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 119167514Skmacy}; 120167514Skmacy 121167514Skmacystruct sg_ent { /* SGE scatter/gather entry */ 122180583Skmacy __be32 len[2]; 123180583Skmacy __be64 addr[2]; 124167514Skmacy}; 125167514Skmacy 126167514Skmacy#ifndef SGE_NUM_GENBITS 127167514Skmacy/* Must be 1 or 2 */ 128167514Skmacy# define SGE_NUM_GENBITS 2 129167514Skmacy#endif 130167514Skmacy 131167514Skmacy#define TX_DESC_FLITS 16U 132167514Skmacy#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 133167514Skmacy 134167514Skmacystruct cphy; 135167514Skmacy 136167514Skmacystruct mdio_ops { 137167514Skmacy int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 138167514Skmacy int reg_addr, unsigned int *val); 139167514Skmacy int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 140167514Skmacy int reg_addr, unsigned int val); 141167514Skmacy}; 142167514Skmacy 143167514Skmacystruct adapter_info { 144170654Skmacy unsigned char nports0; /* # of ports on channel 0 */ 145170654Skmacy unsigned char nports1; /* # of ports on channel 1 */ 146167514Skmacy unsigned char phy_base_addr; /* MDIO PHY base address */ 147170654Skmacy unsigned char mdien:1; 148170654Skmacy unsigned char mdiinv:1; 149167514Skmacy unsigned int gpio_out; /* GPIO output settings */ 150180583Skmacy unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */ 151167514Skmacy unsigned long caps; /* adapter capabilities */ 152167514Skmacy const struct mdio_ops *mdio_ops; /* MDIO operations */ 153167514Skmacy const char *desc; /* product description */ 154167514Skmacy}; 155167514Skmacy 156167514Skmacystruct port_type_info { 157176472Skmacy int (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr, 158176472Skmacy const struct mdio_ops *ops); 159167514Skmacy}; 160167514Skmacy 161167514Skmacystruct mc5_stats { 162167514Skmacy unsigned long parity_err; 163167514Skmacy unsigned long active_rgn_full; 164167514Skmacy unsigned long nfa_srch_err; 165167514Skmacy unsigned long unknown_cmd; 166167514Skmacy unsigned long reqq_parity_err; 167167514Skmacy unsigned long dispq_parity_err; 168167514Skmacy unsigned long del_act_empty; 169167514Skmacy}; 170167514Skmacy 171167514Skmacystruct mc7_stats { 172167514Skmacy unsigned long corr_err; 173167514Skmacy unsigned long uncorr_err; 174167514Skmacy unsigned long parity_err; 175167514Skmacy unsigned long addr_err; 176167514Skmacy}; 177167514Skmacy 178167514Skmacystruct mac_stats { 179167514Skmacy u64 tx_octets; /* total # of octets in good frames */ 180167514Skmacy u64 tx_octets_bad; /* total # of octets in error frames */ 181167514Skmacy u64 tx_frames; /* all good frames */ 182167514Skmacy u64 tx_mcast_frames; /* good multicast frames */ 183167514Skmacy u64 tx_bcast_frames; /* good broadcast frames */ 184167514Skmacy u64 tx_pause; /* # of transmitted pause frames */ 185167514Skmacy u64 tx_deferred; /* frames with deferred transmissions */ 186167514Skmacy u64 tx_late_collisions; /* # of late collisions */ 187167514Skmacy u64 tx_total_collisions; /* # of total collisions */ 188167514Skmacy u64 tx_excess_collisions; /* frame errors from excessive collissions */ 189167514Skmacy u64 tx_underrun; /* # of Tx FIFO underruns */ 190167514Skmacy u64 tx_len_errs; /* # of Tx length errors */ 191167514Skmacy u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 192167514Skmacy u64 tx_excess_deferral; /* # of frames with excessive deferral */ 193167514Skmacy u64 tx_fcs_errs; /* # of frames with bad FCS */ 194167514Skmacy 195167514Skmacy u64 tx_frames_64; /* # of Tx frames in a particular range */ 196167514Skmacy u64 tx_frames_65_127; 197167514Skmacy u64 tx_frames_128_255; 198167514Skmacy u64 tx_frames_256_511; 199167514Skmacy u64 tx_frames_512_1023; 200167514Skmacy u64 tx_frames_1024_1518; 201167514Skmacy u64 tx_frames_1519_max; 202167514Skmacy 203167514Skmacy u64 rx_octets; /* total # of octets in good frames */ 204167514Skmacy u64 rx_octets_bad; /* total # of octets in error frames */ 205167514Skmacy u64 rx_frames; /* all good frames */ 206167514Skmacy u64 rx_mcast_frames; /* good multicast frames */ 207167514Skmacy u64 rx_bcast_frames; /* good broadcast frames */ 208167514Skmacy u64 rx_pause; /* # of received pause frames */ 209167514Skmacy u64 rx_fcs_errs; /* # of received frames with bad FCS */ 210167514Skmacy u64 rx_align_errs; /* alignment errors */ 211167514Skmacy u64 rx_symbol_errs; /* symbol errors */ 212167514Skmacy u64 rx_data_errs; /* data errors */ 213167514Skmacy u64 rx_sequence_errs; /* sequence errors */ 214167514Skmacy u64 rx_runt; /* # of runt frames */ 215167514Skmacy u64 rx_jabber; /* # of jabber frames */ 216167514Skmacy u64 rx_short; /* # of short frames */ 217167514Skmacy u64 rx_too_long; /* # of oversized frames */ 218167514Skmacy u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 219167514Skmacy 220167514Skmacy u64 rx_frames_64; /* # of Rx frames in a particular range */ 221167514Skmacy u64 rx_frames_65_127; 222167514Skmacy u64 rx_frames_128_255; 223167514Skmacy u64 rx_frames_256_511; 224167514Skmacy u64 rx_frames_512_1023; 225167514Skmacy u64 rx_frames_1024_1518; 226167514Skmacy u64 rx_frames_1519_max; 227167514Skmacy 228167514Skmacy u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 229167514Skmacy 230167514Skmacy unsigned long tx_fifo_parity_err; 231167514Skmacy unsigned long rx_fifo_parity_err; 232167514Skmacy unsigned long tx_fifo_urun; 233167514Skmacy unsigned long rx_fifo_ovfl; 234167514Skmacy unsigned long serdes_signal_loss; 235167514Skmacy unsigned long xaui_pcs_ctc_err; 236167514Skmacy unsigned long xaui_pcs_align_change; 237167746Skmacy 238167746Skmacy unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 239167746Skmacy unsigned long num_resets; /* # times reset due to stuck TX */ 240167514Skmacy}; 241167514Skmacy 242167514Skmacystruct tp_mib_stats { 243167514Skmacy u32 ipInReceive_hi; 244167514Skmacy u32 ipInReceive_lo; 245167514Skmacy u32 ipInHdrErrors_hi; 246167514Skmacy u32 ipInHdrErrors_lo; 247167514Skmacy u32 ipInAddrErrors_hi; 248167514Skmacy u32 ipInAddrErrors_lo; 249167514Skmacy u32 ipInUnknownProtos_hi; 250167514Skmacy u32 ipInUnknownProtos_lo; 251167514Skmacy u32 ipInDiscards_hi; 252167514Skmacy u32 ipInDiscards_lo; 253167514Skmacy u32 ipInDelivers_hi; 254167514Skmacy u32 ipInDelivers_lo; 255167514Skmacy u32 ipOutRequests_hi; 256167514Skmacy u32 ipOutRequests_lo; 257167514Skmacy u32 ipOutDiscards_hi; 258167514Skmacy u32 ipOutDiscards_lo; 259167514Skmacy u32 ipOutNoRoutes_hi; 260167514Skmacy u32 ipOutNoRoutes_lo; 261167514Skmacy u32 ipReasmTimeout; 262167514Skmacy u32 ipReasmReqds; 263167514Skmacy u32 ipReasmOKs; 264167514Skmacy u32 ipReasmFails; 265167514Skmacy 266167514Skmacy u32 reserved[8]; 267167514Skmacy 268167514Skmacy u32 tcpActiveOpens; 269167514Skmacy u32 tcpPassiveOpens; 270167514Skmacy u32 tcpAttemptFails; 271167514Skmacy u32 tcpEstabResets; 272167514Skmacy u32 tcpOutRsts; 273167514Skmacy u32 tcpCurrEstab; 274167514Skmacy u32 tcpInSegs_hi; 275167514Skmacy u32 tcpInSegs_lo; 276167514Skmacy u32 tcpOutSegs_hi; 277167514Skmacy u32 tcpOutSegs_lo; 278167514Skmacy u32 tcpRetransSeg_hi; 279167514Skmacy u32 tcpRetransSeg_lo; 280167514Skmacy u32 tcpInErrs_hi; 281167514Skmacy u32 tcpInErrs_lo; 282167514Skmacy u32 tcpRtoMin; 283167514Skmacy u32 tcpRtoMax; 284167514Skmacy}; 285167514Skmacy 286167514Skmacystruct tp_params { 287167514Skmacy unsigned int nchan; /* # of channels */ 288167514Skmacy unsigned int pmrx_size; /* total PMRX capacity */ 289167514Skmacy unsigned int pmtx_size; /* total PMTX capacity */ 290167514Skmacy unsigned int cm_size; /* total CM capacity */ 291167514Skmacy unsigned int chan_rx_size; /* per channel Rx size */ 292167514Skmacy unsigned int chan_tx_size; /* per channel Tx size */ 293167514Skmacy unsigned int rx_pg_size; /* Rx page size */ 294167514Skmacy unsigned int tx_pg_size; /* Tx page size */ 295167514Skmacy unsigned int rx_num_pgs; /* # of Rx pages */ 296167514Skmacy unsigned int tx_num_pgs; /* # of Tx pages */ 297167514Skmacy unsigned int ntimer_qs; /* # of timer queues */ 298170654Skmacy unsigned int tre; /* log2 of core clocks per TP tick */ 299167746Skmacy unsigned int dack_re; /* DACK timer resolution */ 300167514Skmacy}; 301167514Skmacy 302167514Skmacystruct qset_params { /* SGE queue set parameters */ 303167514Skmacy unsigned int polling; /* polling/interrupt service for rspq */ 304170654Skmacy unsigned int lro; /* large receive offload */ 305180583Skmacy unsigned int coalesce_usecs; /* irq coalescing timer */ 306167514Skmacy unsigned int rspq_size; /* # of entries in response queue */ 307167514Skmacy unsigned int fl_size; /* # of entries in regular free list */ 308167514Skmacy unsigned int jumbo_size; /* # of entries in jumbo free list */ 309167514Skmacy unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 310167514Skmacy unsigned int cong_thres; /* FL congestion threshold */ 311167746Skmacy unsigned int vector; /* Interrupt (line or vector) number */ 312167514Skmacy}; 313167514Skmacy 314167514Skmacystruct sge_params { 315167514Skmacy unsigned int max_pkt_size; /* max offload pkt size */ 316167514Skmacy struct qset_params qset[SGE_QSETS]; 317167514Skmacy}; 318167514Skmacy 319167514Skmacystruct mc5_params { 320167514Skmacy unsigned int mode; /* selects MC5 width */ 321167514Skmacy unsigned int nservers; /* size of server region */ 322167514Skmacy unsigned int nfilters; /* size of filter region */ 323167514Skmacy unsigned int nroutes; /* size of routing region */ 324167514Skmacy}; 325167514Skmacy 326167514Skmacy/* Default MC5 region sizes */ 327167514Skmacyenum { 328167514Skmacy DEFAULT_NSERVERS = 512, 329167514Skmacy DEFAULT_NFILTERS = 128 330167514Skmacy}; 331167514Skmacy 332167514Skmacy/* MC5 modes, these must be non-0 */ 333167514Skmacyenum { 334167514Skmacy MC5_MODE_144_BIT = 1, 335167514Skmacy MC5_MODE_72_BIT = 2 336167514Skmacy}; 337167514Skmacy 338169978Skmacy/* MC5 min active region size */ 339169978Skmacyenum { MC5_MIN_TIDS = 16 }; 340169978Skmacy 341167514Skmacystruct vpd_params { 342167514Skmacy unsigned int cclk; 343167514Skmacy unsigned int mclk; 344167514Skmacy unsigned int uclk; 345167514Skmacy unsigned int mdc; 346167514Skmacy unsigned int mem_timing; 347172096Skmacy u8 sn[SERNUM_LEN + 1]; 348167514Skmacy u8 eth_base[6]; 349167514Skmacy u8 port_type[MAX_NPORTS]; 350167514Skmacy unsigned short xauicfg[2]; 351167514Skmacy}; 352167514Skmacy 353167514Skmacystruct pci_params { 354167514Skmacy unsigned int vpd_cap_addr; 355167514Skmacy unsigned int pcie_cap_addr; 356167514Skmacy unsigned short speed; 357167514Skmacy unsigned char width; 358167514Skmacy unsigned char variant; 359167514Skmacy}; 360167514Skmacy 361167514Skmacyenum { 362167514Skmacy PCI_VARIANT_PCI, 363167514Skmacy PCI_VARIANT_PCIX_MODE1_PARITY, 364167514Skmacy PCI_VARIANT_PCIX_MODE1_ECC, 365167514Skmacy PCI_VARIANT_PCIX_266_MODE2, 366167514Skmacy PCI_VARIANT_PCIE 367167514Skmacy}; 368167514Skmacy 369167514Skmacystruct adapter_params { 370167514Skmacy struct sge_params sge; 371167514Skmacy struct mc5_params mc5; 372167514Skmacy struct tp_params tp; 373167514Skmacy struct vpd_params vpd; 374167514Skmacy struct pci_params pci; 375167514Skmacy 376167514Skmacy const struct adapter_info *info; 377167514Skmacy 378167514Skmacy#ifdef CONFIG_CHELSIO_T3_CORE 379167514Skmacy unsigned short mtus[NMTUS]; 380167514Skmacy unsigned short a_wnd[NCCTRL_WIN]; 381167514Skmacy unsigned short b_wnd[NCCTRL_WIN]; 382167514Skmacy#endif 383167514Skmacy unsigned int nports; /* # of ethernet ports */ 384170654Skmacy unsigned int chan_map; /* bitmap of in-use Tx channels */ 385167514Skmacy unsigned int stats_update_period; /* MAC stats accumulation period */ 386167514Skmacy unsigned int linkpoll_period; /* link poll period in 0.1s */ 387167514Skmacy unsigned int rev; /* chip revision */ 388169978Skmacy unsigned int offload; 389167514Skmacy}; 390167514Skmacy 391167746Skmacyenum { /* chip revisions */ 392167746Skmacy T3_REV_A = 0, 393167746Skmacy T3_REV_B = 2, 394167746Skmacy T3_REV_B2 = 3, 395171471Skmacy T3_REV_C = 4, 396167746Skmacy}; 397167746Skmacy 398167514Skmacystruct trace_params { 399167514Skmacy u32 sip; 400167514Skmacy u32 sip_mask; 401167514Skmacy u32 dip; 402167514Skmacy u32 dip_mask; 403167514Skmacy u16 sport; 404167514Skmacy u16 sport_mask; 405167514Skmacy u16 dport; 406167514Skmacy u16 dport_mask; 407167514Skmacy u32 vlan:12; 408167514Skmacy u32 vlan_mask:12; 409167514Skmacy u32 intf:4; 410167514Skmacy u32 intf_mask:4; 411167514Skmacy u8 proto; 412167514Skmacy u8 proto_mask; 413167514Skmacy}; 414167514Skmacy 415167514Skmacystruct link_config { 416167514Skmacy unsigned int supported; /* link capabilities */ 417167514Skmacy unsigned int advertising; /* advertised capabilities */ 418167514Skmacy unsigned short requested_speed; /* speed user has requested */ 419167514Skmacy unsigned short speed; /* actual link speed */ 420167514Skmacy unsigned char requested_duplex; /* duplex user has requested */ 421167514Skmacy unsigned char duplex; /* actual link duplex */ 422167514Skmacy unsigned char requested_fc; /* flow control user has requested */ 423167514Skmacy unsigned char fc; /* actual link flow control */ 424167514Skmacy unsigned char autoneg; /* autonegotiating? */ 425167514Skmacy unsigned int link_ok; /* link up? */ 426167514Skmacy}; 427167514Skmacy 428167514Skmacy#define SPEED_INVALID 0xffff 429167514Skmacy#define DUPLEX_INVALID 0xff 430167514Skmacy 431167514Skmacystruct mc5 { 432167514Skmacy adapter_t *adapter; 433167514Skmacy unsigned int tcam_size; 434167514Skmacy unsigned char part_type; 435167514Skmacy unsigned char parity_enabled; 436167514Skmacy unsigned char mode; 437167514Skmacy struct mc5_stats stats; 438167514Skmacy}; 439167514Skmacy 440167514Skmacystatic inline unsigned int t3_mc5_size(const struct mc5 *p) 441167514Skmacy{ 442167514Skmacy return p->tcam_size; 443167514Skmacy} 444167514Skmacy 445167514Skmacystruct mc7 { 446167514Skmacy adapter_t *adapter; /* backpointer to adapter */ 447167514Skmacy unsigned int size; /* memory size in bytes */ 448167514Skmacy unsigned int width; /* MC7 interface width */ 449167514Skmacy unsigned int offset; /* register address offset for MC7 instance */ 450167514Skmacy const char *name; /* name of MC7 instance */ 451167514Skmacy struct mc7_stats stats; /* MC7 statistics */ 452167514Skmacy}; 453167514Skmacy 454167514Skmacystatic inline unsigned int t3_mc7_size(const struct mc7 *p) 455167514Skmacy{ 456167514Skmacy return p->size; 457167514Skmacy} 458167514Skmacy 459167514Skmacystruct cmac { 460167514Skmacy adapter_t *adapter; 461167514Skmacy unsigned int offset; 462170654Skmacy unsigned char nucast; /* # of address filters for unicast MACs */ 463170654Skmacy unsigned char multiport; /* multiple ports connected to this MAC */ 464170654Skmacy unsigned char ext_port; /* external MAC port */ 465170654Skmacy unsigned char promisc_map; /* which external ports are promiscuous */ 466169978Skmacy unsigned int tx_tcnt; 467169978Skmacy unsigned int tx_xcnt; 468169978Skmacy u64 tx_mcnt; 469169978Skmacy unsigned int rx_xcnt; 470171471Skmacy unsigned int rx_ocnt; 471169978Skmacy u64 rx_mcnt; 472167746Skmacy unsigned int toggle_cnt; 473167746Skmacy unsigned int txen; 474172096Skmacy u64 rx_pause; 475167514Skmacy struct mac_stats stats; 476167514Skmacy}; 477167514Skmacy 478167514Skmacyenum { 479167514Skmacy MAC_DIRECTION_RX = 1, 480167514Skmacy MAC_DIRECTION_TX = 2, 481167514Skmacy MAC_RXFIFO_SIZE = 32768 482167514Skmacy}; 483167514Skmacy 484180583Skmacy/* IEEE 802.3 specified MDIO devices */ 485167514Skmacyenum { 486167514Skmacy MDIO_DEV_PMA_PMD = 1, 487167514Skmacy MDIO_DEV_WIS = 2, 488167514Skmacy MDIO_DEV_PCS = 3, 489180583Skmacy MDIO_DEV_XGXS = 4, 490180583Skmacy MDIO_DEV_ANEG = 7, 491180583Skmacy MDIO_DEV_VEND1 = 30, 492180583Skmacy MDIO_DEV_VEND2 = 31 493167514Skmacy}; 494167514Skmacy 495180583Skmacy/* LASI control and status registers */ 496180583Skmacyenum { 497180583Skmacy RX_ALARM_CTRL = 0x9000, 498180583Skmacy TX_ALARM_CTRL = 0x9001, 499180583Skmacy LASI_CTRL = 0x9002, 500180583Skmacy RX_ALARM_STAT = 0x9003, 501180583Skmacy TX_ALARM_STAT = 0x9004, 502180583Skmacy LASI_STAT = 0x9005 503180583Skmacy}; 504180583Skmacy 505167514Skmacy/* PHY loopback direction */ 506167514Skmacyenum { 507167514Skmacy PHY_LOOPBACK_TX = 1, 508167514Skmacy PHY_LOOPBACK_RX = 2 509167514Skmacy}; 510167514Skmacy 511167514Skmacy/* PHY interrupt types */ 512167514Skmacyenum { 513167514Skmacy cphy_cause_link_change = 1, 514167514Skmacy cphy_cause_fifo_error = 2 515167514Skmacy}; 516167514Skmacy 517167514Skmacy/* PHY operations */ 518167514Skmacystruct cphy_ops { 519167514Skmacy int (*reset)(struct cphy *phy, int wait); 520167514Skmacy 521167514Skmacy int (*intr_enable)(struct cphy *phy); 522167514Skmacy int (*intr_disable)(struct cphy *phy); 523167514Skmacy int (*intr_clear)(struct cphy *phy); 524167514Skmacy int (*intr_handler)(struct cphy *phy); 525167514Skmacy 526167514Skmacy int (*autoneg_enable)(struct cphy *phy); 527167514Skmacy int (*autoneg_restart)(struct cphy *phy); 528167514Skmacy 529167514Skmacy int (*advertise)(struct cphy *phy, unsigned int advertise_map); 530167514Skmacy int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 531167514Skmacy int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 532167514Skmacy int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 533167514Skmacy int *duplex, int *fc); 534167514Skmacy int (*power_down)(struct cphy *phy, int enable); 535167514Skmacy}; 536167514Skmacy 537167514Skmacy/* A PHY instance */ 538167514Skmacystruct cphy { 539167514Skmacy int addr; /* PHY address */ 540176472Skmacy unsigned int caps; /* PHY capabilities */ 541167514Skmacy adapter_t *adapter; /* associated adapter */ 542176472Skmacy const char *desc; /* PHY description */ 543167514Skmacy unsigned long fifo_errors; /* FIFO over/under-flows */ 544167514Skmacy const struct cphy_ops *ops; /* PHY operations */ 545167514Skmacy int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 546167514Skmacy int reg_addr, unsigned int *val); 547167514Skmacy int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 548167514Skmacy int reg_addr, unsigned int val); 549167514Skmacy}; 550167514Skmacy 551167514Skmacy/* Convenience MDIO read/write wrappers */ 552167514Skmacystatic inline int mdio_read(struct cphy *phy, int mmd, int reg, 553167514Skmacy unsigned int *valp) 554167514Skmacy{ 555167514Skmacy return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 556167514Skmacy} 557167514Skmacy 558167514Skmacystatic inline int mdio_write(struct cphy *phy, int mmd, int reg, 559167514Skmacy unsigned int val) 560167514Skmacy{ 561167514Skmacy return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 562167514Skmacy} 563167514Skmacy 564167514Skmacy/* Convenience initializer */ 565167514Skmacystatic inline void cphy_init(struct cphy *phy, adapter_t *adapter, 566167514Skmacy int phy_addr, struct cphy_ops *phy_ops, 567180583Skmacy const struct mdio_ops *mdio_ops, unsigned int caps, 568180583Skmacy const char *desc) 569167514Skmacy{ 570167514Skmacy phy->adapter = adapter; 571167514Skmacy phy->addr = phy_addr; 572176472Skmacy phy->caps = caps; 573176472Skmacy phy->desc = desc; 574167514Skmacy phy->ops = phy_ops; 575167514Skmacy if (mdio_ops) { 576167514Skmacy phy->mdio_read = mdio_ops->read; 577167514Skmacy phy->mdio_write = mdio_ops->write; 578167514Skmacy } 579167514Skmacy} 580167514Skmacy 581167514Skmacy/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 582167514Skmacy#define MAC_STATS_ACCUM_SECS 180 583167514Skmacy 584171471Skmacy/* The external MAC needs accumulation every 30 seconds */ 585171471Skmacy#define VSC_STATS_ACCUM_SECS 30 586171471Skmacy 587167514Skmacy#define XGM_REG(reg_addr, idx) \ 588167514Skmacy ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 589167514Skmacy 590167514Skmacystruct addr_val_pair { 591167514Skmacy unsigned int reg_addr; 592167514Skmacy unsigned int val; 593167514Skmacy}; 594167514Skmacy 595170076Skmacy#ifdef CONFIG_DEFINED 596170076Skmacy#include <cxgb_adapter.h> 597170076Skmacy#else 598167514Skmacy#include <dev/cxgb/cxgb_adapter.h> 599170076Skmacy#endif 600167514Skmacy 601167514Skmacy#ifndef PCI_VENDOR_ID_CHELSIO 602167514Skmacy# define PCI_VENDOR_ID_CHELSIO 0x1425 603167514Skmacy#endif 604167514Skmacy 605167514Skmacy#define for_each_port(adapter, iter) \ 606167514Skmacy for (iter = 0; iter < (adapter)->params.nports; ++iter) 607167514Skmacy 608167514Skmacy#define adapter_info(adap) ((adap)->params.info) 609167514Skmacy 610167514Skmacystatic inline int uses_xaui(const adapter_t *adap) 611167514Skmacy{ 612167514Skmacy return adapter_info(adap)->caps & SUPPORTED_AUI; 613167514Skmacy} 614167514Skmacy 615167514Skmacystatic inline int is_10G(const adapter_t *adap) 616167514Skmacy{ 617167514Skmacy return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 618167514Skmacy} 619167514Skmacy 620167514Skmacystatic inline int is_offload(const adapter_t *adap) 621167514Skmacy{ 622167514Skmacy#ifdef CONFIG_CHELSIO_T3_CORE 623169978Skmacy return adap->params.offload; 624167514Skmacy#else 625167514Skmacy return 0; 626167514Skmacy#endif 627167514Skmacy} 628167514Skmacy 629167514Skmacystatic inline unsigned int core_ticks_per_usec(const adapter_t *adap) 630167514Skmacy{ 631167514Skmacy return adap->params.vpd.cclk / 1000; 632167514Skmacy} 633167514Skmacy 634167746Skmacystatic inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 635167746Skmacy unsigned int ticks) 636167746Skmacy{ 637167746Skmacy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 638167746Skmacy} 639167746Skmacy 640167514Skmacystatic inline unsigned int is_pcie(const adapter_t *adap) 641167514Skmacy{ 642167514Skmacy return adap->params.pci.variant == PCI_VARIANT_PCIE; 643167514Skmacy} 644167514Skmacy 645167514Skmacyvoid t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 646167514Skmacyvoid t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 647167514Skmacy unsigned int offset); 648167514Skmacyint t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 649167514Skmacy int attempts, int delay, u32 *valp); 650167514Skmacy 651167514Skmacystatic inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 652167514Skmacy int polarity, int attempts, int delay) 653167514Skmacy{ 654167514Skmacy return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 655167514Skmacy delay, NULL); 656167514Skmacy} 657167514Skmacy 658167514Skmacyint t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 659167514Skmacy unsigned int set); 660167514Skmacyint t3_phy_reset(struct cphy *phy, int mmd, int wait); 661167514Skmacyint t3_phy_advertise(struct cphy *phy, unsigned int advert); 662180583Skmacyint t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 663167514Skmacyint t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 664180583Skmacyint t3_phy_lasi_intr_enable(struct cphy *phy); 665180583Skmacyint t3_phy_lasi_intr_disable(struct cphy *phy); 666180583Skmacyint t3_phy_lasi_intr_clear(struct cphy *phy); 667180583Skmacyint t3_phy_lasi_intr_handler(struct cphy *phy); 668167514Skmacy 669167514Skmacyvoid t3_intr_enable(adapter_t *adapter); 670167514Skmacyvoid t3_intr_disable(adapter_t *adapter); 671167514Skmacyvoid t3_intr_clear(adapter_t *adapter); 672167514Skmacyvoid t3_port_intr_enable(adapter_t *adapter, int idx); 673167514Skmacyvoid t3_port_intr_disable(adapter_t *adapter, int idx); 674167514Skmacyvoid t3_port_intr_clear(adapter_t *adapter, int idx); 675167514Skmacyint t3_slow_intr_handler(adapter_t *adapter); 676167514Skmacyint t3_phy_intr_handler(adapter_t *adapter); 677167514Skmacy 678167514Skmacyvoid t3_link_changed(adapter_t *adapter, int port_id); 679167514Skmacyint t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 680167514Skmacyconst struct adapter_info *t3_get_adapter_info(unsigned int board_id); 681167514Skmacyint t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 682167514Skmacyint t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 683167514Skmacyint t3_seeprom_wp(adapter_t *adapter, int enable); 684167514Skmacyint t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 685167514Skmacy u32 *data, int byte_oriented); 686171471Skmacyint t3_get_tp_version(adapter_t *adapter, u32 *vers); 687176472Skmacyint t3_check_tpsram_version(adapter_t *adapter, int *must_load); 688171471Skmacyint t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); 689180583Skmacyint t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 690167514Skmacyint t3_get_fw_version(adapter_t *adapter, u32 *vers); 691176472Skmacyint t3_check_fw_version(adapter_t *adapter, int *must_load); 692180583Skmacyint t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); 693167514Skmacyint t3_init_hw(adapter_t *adapter, u32 fw_params); 694167514Skmacyvoid mac_prep(struct cmac *mac, adapter_t *adapter, int index); 695167514Skmacyvoid early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 696167514Skmacyint t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 697167514Skmacyvoid t3_led_ready(adapter_t *adapter); 698167514Skmacyvoid t3_fatal_err(adapter_t *adapter); 699167514Skmacyvoid t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 700180583Skmacyvoid t3_enable_filters(adapter_t *adap); 701177340Skmacyvoid t3_tp_set_offload_mode(adapter_t *adap, int enable); 702167514Skmacyvoid t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 703167514Skmacy const u16 *rspq); 704167514Skmacyint t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 705171471Skmacyint t3_set_proto_sram(adapter_t *adap, const u8 *data); 706167514Skmacyint t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 707167514Skmacyvoid t3_port_failover(adapter_t *adapter, int port); 708167514Skmacyvoid t3_failover_done(adapter_t *adapter, int port); 709167514Skmacyvoid t3_failover_clear(adapter_t *adapter); 710167514Skmacyint t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 711167514Skmacy unsigned int *valp); 712167514Skmacyint t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 713167514Skmacy u64 *buf); 714167514Skmacy 715167514Skmacyint t3_mac_reset(struct cmac *mac); 716167514Skmacyvoid t3b_pcs_reset(struct cmac *mac); 717167514Skmacyint t3_mac_enable(struct cmac *mac, int which); 718167514Skmacyint t3_mac_disable(struct cmac *mac, int which); 719167514Skmacyint t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 720167514Skmacyint t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 721167514Skmacyint t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 722170654Skmacyint t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); 723167514Skmacyconst struct mac_stats *t3_mac_update_stats(struct cmac *mac); 724167514Skmacyint t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 725167514Skmacy int fc); 726167746Skmacyint t3b2_mac_watchdog_task(struct cmac *mac); 727167514Skmacy 728167514Skmacyvoid t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 729167514Skmacyint t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 730167514Skmacy unsigned int nroutes); 731167514Skmacyvoid t3_mc5_intr_handler(struct mc5 *mc5); 732167514Skmacyint t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 733167514Skmacy u32 *buf); 734167514Skmacy 735180583Skmacy#ifdef CONFIG_CHELSIO_T3_CORE 736167514Skmacyint t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 737167514Skmacyvoid t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 738167514Skmacyvoid t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 739167514Skmacyvoid t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 740167514Skmacy unsigned short alpha[NCCTRL_WIN], 741167514Skmacy unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 742167514Skmacyvoid t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 743167514Skmacyvoid t3_get_cong_cntl_tab(adapter_t *adap, 744167514Skmacy unsigned short incr[NMTUS][NCCTRL_WIN]); 745167514Skmacyvoid t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 746167514Skmacy int filter_index, int invert, int enable); 747167514Skmacyint t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 748167746Skmacyint t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 749167746Skmacyvoid t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 750167746Skmacy unsigned int *ipg); 751167746Skmacyvoid t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 752167746Skmacyvoid t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 753167746Skmacy unsigned int start, unsigned int n); 754167514Skmacy#endif 755167514Skmacy 756167514Skmacyvoid t3_sge_prep(adapter_t *adap, struct sge_params *p); 757167514Skmacyvoid t3_sge_init(adapter_t *adap, struct sge_params *p); 758167514Skmacyint t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 759167514Skmacy enum sge_context_type type, int respq, u64 base_addr, 760167514Skmacy unsigned int size, unsigned int token, int gen, 761167514Skmacy unsigned int cidx); 762167514Skmacyint t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 763167514Skmacy u64 base_addr, unsigned int size, unsigned int esize, 764167514Skmacy unsigned int cong_thres, int gen, unsigned int cidx); 765167514Skmacyint t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 766167514Skmacy u64 base_addr, unsigned int size, 767167514Skmacy unsigned int fl_thres, int gen, unsigned int cidx); 768167514Skmacyint t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 769167514Skmacy unsigned int size, int rspq, int ovfl_mode, 770167514Skmacy unsigned int credits, unsigned int credit_thres); 771167514Skmacyint t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 772167514Skmacyint t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 773167514Skmacyint t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 774167514Skmacyint t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 775167514Skmacyint t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 776167514Skmacyint t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 777167514Skmacyint t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 778167514Skmacyint t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 779167514Skmacyint t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 780167514Skmacy unsigned int credits); 781167514Skmacy 782170654Skmacyint t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); 783170654Skmacyint t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); 784170654Skmacyint t3_vsc7323_init(adapter_t *adap, int nports); 785170654Skmacyint t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); 786171471Skmacyint t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); 787170654Skmacyint t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); 788170654Skmacyint t3_vsc7323_enable(adapter_t *adap, int port, int which); 789170654Skmacyint t3_vsc7323_disable(adapter_t *adap, int port, int which); 790170654Skmacyconst struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); 791170654Skmacy 792176472Skmacyint t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 793180583Skmacy const struct mdio_ops *mdio_ops); 794176472Skmacyint t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 795180583Skmacy const struct mdio_ops *mdio_ops); 796176472Skmacyint t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 797180583Skmacy const struct mdio_ops *mdio_ops); 798176472Skmacyint t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 799180583Skmacy const struct mdio_ops *mdio_ops); 800180583Skmacyint t3_ael2005_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 801180583Skmacy const struct mdio_ops *mdio_ops); 802176472Skmacyint t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 803180583Skmacy const struct mdio_ops *mdio_ops); 804180583Skmacyint t3_tn1010_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 805180583Skmacy const struct mdio_ops *mdio_ops); 806176472Skmacyint t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 807180583Skmacy const struct mdio_ops *mdio_ops); 808167514Skmacy#endif /* __CHELSIO_COMMON_H */ 809