cxgb_common.h revision 180583
1/************************************************************************** 2 3Copyright (c) 2007-2008, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28$FreeBSD: head/sys/dev/cxgb/common/cxgb_common.h 180583 2008-07-18 06:12:31Z kmacy $ 29 30***************************************************************************/ 31#ifndef __CHELSIO_COMMON_H 32#define __CHELSIO_COMMON_H 33 34#ifdef CONFIG_DEFINED 35#include <cxgb_osdep.h> 36#else 37#include <dev/cxgb/cxgb_osdep.h> 38#endif 39 40enum { 41 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ 42 EEPROMSIZE = 8192, /* Serial EEPROM size */ 43 SERNUM_LEN = 16, /* Serial # length */ 44 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 45 TCB_SIZE = 128, /* TCB size */ 46 NMTUS = 16, /* size of MTU table */ 47 NCCTRL_WIN = 32, /* # of congestion control windows */ 48 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 49 PROTO_SRAM_LINES = 128, /* size of protocol sram */ 50 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ 51}; 52 53#define MAX_RX_COALESCING_LEN 12288U 54 55enum { 56 PAUSE_RX = 1 << 0, 57 PAUSE_TX = 1 << 1, 58 PAUSE_AUTONEG = 1 << 2 59}; 60 61enum { 62 SUPPORTED_IRQ = 1 << 24 63}; 64 65enum { /* adapter interrupt-maintained statistics */ 66 STAT_ULP_CH0_PBL_OOB, 67 STAT_ULP_CH1_PBL_OOB, 68 STAT_PCI_CORR_ECC, 69 70 IRQ_NUM_STATS /* keep last */ 71}; 72 73enum { 74 TP_VERSION_MAJOR = 1, 75 TP_VERSION_MINOR = 1, 76 TP_VERSION_MICRO = 0 77}; 78 79#define S_TP_VERSION_MAJOR 16 80#define M_TP_VERSION_MAJOR 0xFF 81#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 82#define G_TP_VERSION_MAJOR(x) \ 83 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 84 85#define S_TP_VERSION_MINOR 8 86#define M_TP_VERSION_MINOR 0xFF 87#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 88#define G_TP_VERSION_MINOR(x) \ 89 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 90 91#define S_TP_VERSION_MICRO 0 92#define M_TP_VERSION_MICRO 0xFF 93#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 94#define G_TP_VERSION_MICRO(x) \ 95 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 96 97enum { 98 FW_VERSION_MAJOR = 5, 99 FW_VERSION_MINOR = 0, 100 FW_VERSION_MICRO = 0 101}; 102 103enum { 104 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 105 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 106 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 107}; 108 109enum sge_context_type { /* SGE egress context types */ 110 SGE_CNTXT_RDMA = 0, 111 SGE_CNTXT_ETH = 2, 112 SGE_CNTXT_OFLD = 4, 113 SGE_CNTXT_CTRL = 5 114}; 115 116enum { 117 AN_PKT_SIZE = 32, /* async notification packet size */ 118 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 119}; 120 121struct sg_ent { /* SGE scatter/gather entry */ 122 __be32 len[2]; 123 __be64 addr[2]; 124}; 125 126#ifndef SGE_NUM_GENBITS 127/* Must be 1 or 2 */ 128# define SGE_NUM_GENBITS 2 129#endif 130 131#define TX_DESC_FLITS 16U 132#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 133 134struct cphy; 135 136struct mdio_ops { 137 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 138 int reg_addr, unsigned int *val); 139 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 140 int reg_addr, unsigned int val); 141}; 142 143struct adapter_info { 144 unsigned char nports0; /* # of ports on channel 0 */ 145 unsigned char nports1; /* # of ports on channel 1 */ 146 unsigned char phy_base_addr; /* MDIO PHY base address */ 147 unsigned char mdien:1; 148 unsigned char mdiinv:1; 149 unsigned int gpio_out; /* GPIO output settings */ 150 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */ 151 unsigned long caps; /* adapter capabilities */ 152 const struct mdio_ops *mdio_ops; /* MDIO operations */ 153 const char *desc; /* product description */ 154}; 155 156struct port_type_info { 157 int (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr, 158 const struct mdio_ops *ops); 159}; 160 161struct mc5_stats { 162 unsigned long parity_err; 163 unsigned long active_rgn_full; 164 unsigned long nfa_srch_err; 165 unsigned long unknown_cmd; 166 unsigned long reqq_parity_err; 167 unsigned long dispq_parity_err; 168 unsigned long del_act_empty; 169}; 170 171struct mc7_stats { 172 unsigned long corr_err; 173 unsigned long uncorr_err; 174 unsigned long parity_err; 175 unsigned long addr_err; 176}; 177 178struct mac_stats { 179 u64 tx_octets; /* total # of octets in good frames */ 180 u64 tx_octets_bad; /* total # of octets in error frames */ 181 u64 tx_frames; /* all good frames */ 182 u64 tx_mcast_frames; /* good multicast frames */ 183 u64 tx_bcast_frames; /* good broadcast frames */ 184 u64 tx_pause; /* # of transmitted pause frames */ 185 u64 tx_deferred; /* frames with deferred transmissions */ 186 u64 tx_late_collisions; /* # of late collisions */ 187 u64 tx_total_collisions; /* # of total collisions */ 188 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 189 u64 tx_underrun; /* # of Tx FIFO underruns */ 190 u64 tx_len_errs; /* # of Tx length errors */ 191 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 192 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 193 u64 tx_fcs_errs; /* # of frames with bad FCS */ 194 195 u64 tx_frames_64; /* # of Tx frames in a particular range */ 196 u64 tx_frames_65_127; 197 u64 tx_frames_128_255; 198 u64 tx_frames_256_511; 199 u64 tx_frames_512_1023; 200 u64 tx_frames_1024_1518; 201 u64 tx_frames_1519_max; 202 203 u64 rx_octets; /* total # of octets in good frames */ 204 u64 rx_octets_bad; /* total # of octets in error frames */ 205 u64 rx_frames; /* all good frames */ 206 u64 rx_mcast_frames; /* good multicast frames */ 207 u64 rx_bcast_frames; /* good broadcast frames */ 208 u64 rx_pause; /* # of received pause frames */ 209 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 210 u64 rx_align_errs; /* alignment errors */ 211 u64 rx_symbol_errs; /* symbol errors */ 212 u64 rx_data_errs; /* data errors */ 213 u64 rx_sequence_errs; /* sequence errors */ 214 u64 rx_runt; /* # of runt frames */ 215 u64 rx_jabber; /* # of jabber frames */ 216 u64 rx_short; /* # of short frames */ 217 u64 rx_too_long; /* # of oversized frames */ 218 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 219 220 u64 rx_frames_64; /* # of Rx frames in a particular range */ 221 u64 rx_frames_65_127; 222 u64 rx_frames_128_255; 223 u64 rx_frames_256_511; 224 u64 rx_frames_512_1023; 225 u64 rx_frames_1024_1518; 226 u64 rx_frames_1519_max; 227 228 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 229 230 unsigned long tx_fifo_parity_err; 231 unsigned long rx_fifo_parity_err; 232 unsigned long tx_fifo_urun; 233 unsigned long rx_fifo_ovfl; 234 unsigned long serdes_signal_loss; 235 unsigned long xaui_pcs_ctc_err; 236 unsigned long xaui_pcs_align_change; 237 238 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 239 unsigned long num_resets; /* # times reset due to stuck TX */ 240}; 241 242struct tp_mib_stats { 243 u32 ipInReceive_hi; 244 u32 ipInReceive_lo; 245 u32 ipInHdrErrors_hi; 246 u32 ipInHdrErrors_lo; 247 u32 ipInAddrErrors_hi; 248 u32 ipInAddrErrors_lo; 249 u32 ipInUnknownProtos_hi; 250 u32 ipInUnknownProtos_lo; 251 u32 ipInDiscards_hi; 252 u32 ipInDiscards_lo; 253 u32 ipInDelivers_hi; 254 u32 ipInDelivers_lo; 255 u32 ipOutRequests_hi; 256 u32 ipOutRequests_lo; 257 u32 ipOutDiscards_hi; 258 u32 ipOutDiscards_lo; 259 u32 ipOutNoRoutes_hi; 260 u32 ipOutNoRoutes_lo; 261 u32 ipReasmTimeout; 262 u32 ipReasmReqds; 263 u32 ipReasmOKs; 264 u32 ipReasmFails; 265 266 u32 reserved[8]; 267 268 u32 tcpActiveOpens; 269 u32 tcpPassiveOpens; 270 u32 tcpAttemptFails; 271 u32 tcpEstabResets; 272 u32 tcpOutRsts; 273 u32 tcpCurrEstab; 274 u32 tcpInSegs_hi; 275 u32 tcpInSegs_lo; 276 u32 tcpOutSegs_hi; 277 u32 tcpOutSegs_lo; 278 u32 tcpRetransSeg_hi; 279 u32 tcpRetransSeg_lo; 280 u32 tcpInErrs_hi; 281 u32 tcpInErrs_lo; 282 u32 tcpRtoMin; 283 u32 tcpRtoMax; 284}; 285 286struct tp_params { 287 unsigned int nchan; /* # of channels */ 288 unsigned int pmrx_size; /* total PMRX capacity */ 289 unsigned int pmtx_size; /* total PMTX capacity */ 290 unsigned int cm_size; /* total CM capacity */ 291 unsigned int chan_rx_size; /* per channel Rx size */ 292 unsigned int chan_tx_size; /* per channel Tx size */ 293 unsigned int rx_pg_size; /* Rx page size */ 294 unsigned int tx_pg_size; /* Tx page size */ 295 unsigned int rx_num_pgs; /* # of Rx pages */ 296 unsigned int tx_num_pgs; /* # of Tx pages */ 297 unsigned int ntimer_qs; /* # of timer queues */ 298 unsigned int tre; /* log2 of core clocks per TP tick */ 299 unsigned int dack_re; /* DACK timer resolution */ 300}; 301 302struct qset_params { /* SGE queue set parameters */ 303 unsigned int polling; /* polling/interrupt service for rspq */ 304 unsigned int lro; /* large receive offload */ 305 unsigned int coalesce_usecs; /* irq coalescing timer */ 306 unsigned int rspq_size; /* # of entries in response queue */ 307 unsigned int fl_size; /* # of entries in regular free list */ 308 unsigned int jumbo_size; /* # of entries in jumbo free list */ 309 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 310 unsigned int cong_thres; /* FL congestion threshold */ 311 unsigned int vector; /* Interrupt (line or vector) number */ 312}; 313 314struct sge_params { 315 unsigned int max_pkt_size; /* max offload pkt size */ 316 struct qset_params qset[SGE_QSETS]; 317}; 318 319struct mc5_params { 320 unsigned int mode; /* selects MC5 width */ 321 unsigned int nservers; /* size of server region */ 322 unsigned int nfilters; /* size of filter region */ 323 unsigned int nroutes; /* size of routing region */ 324}; 325 326/* Default MC5 region sizes */ 327enum { 328 DEFAULT_NSERVERS = 512, 329 DEFAULT_NFILTERS = 128 330}; 331 332/* MC5 modes, these must be non-0 */ 333enum { 334 MC5_MODE_144_BIT = 1, 335 MC5_MODE_72_BIT = 2 336}; 337 338/* MC5 min active region size */ 339enum { MC5_MIN_TIDS = 16 }; 340 341struct vpd_params { 342 unsigned int cclk; 343 unsigned int mclk; 344 unsigned int uclk; 345 unsigned int mdc; 346 unsigned int mem_timing; 347 u8 sn[SERNUM_LEN + 1]; 348 u8 eth_base[6]; 349 u8 port_type[MAX_NPORTS]; 350 unsigned short xauicfg[2]; 351}; 352 353struct pci_params { 354 unsigned int vpd_cap_addr; 355 unsigned int pcie_cap_addr; 356 unsigned short speed; 357 unsigned char width; 358 unsigned char variant; 359}; 360 361enum { 362 PCI_VARIANT_PCI, 363 PCI_VARIANT_PCIX_MODE1_PARITY, 364 PCI_VARIANT_PCIX_MODE1_ECC, 365 PCI_VARIANT_PCIX_266_MODE2, 366 PCI_VARIANT_PCIE 367}; 368 369struct adapter_params { 370 struct sge_params sge; 371 struct mc5_params mc5; 372 struct tp_params tp; 373 struct vpd_params vpd; 374 struct pci_params pci; 375 376 const struct adapter_info *info; 377 378#ifdef CONFIG_CHELSIO_T3_CORE 379 unsigned short mtus[NMTUS]; 380 unsigned short a_wnd[NCCTRL_WIN]; 381 unsigned short b_wnd[NCCTRL_WIN]; 382#endif 383 unsigned int nports; /* # of ethernet ports */ 384 unsigned int chan_map; /* bitmap of in-use Tx channels */ 385 unsigned int stats_update_period; /* MAC stats accumulation period */ 386 unsigned int linkpoll_period; /* link poll period in 0.1s */ 387 unsigned int rev; /* chip revision */ 388 unsigned int offload; 389}; 390 391enum { /* chip revisions */ 392 T3_REV_A = 0, 393 T3_REV_B = 2, 394 T3_REV_B2 = 3, 395 T3_REV_C = 4, 396}; 397 398struct trace_params { 399 u32 sip; 400 u32 sip_mask; 401 u32 dip; 402 u32 dip_mask; 403 u16 sport; 404 u16 sport_mask; 405 u16 dport; 406 u16 dport_mask; 407 u32 vlan:12; 408 u32 vlan_mask:12; 409 u32 intf:4; 410 u32 intf_mask:4; 411 u8 proto; 412 u8 proto_mask; 413}; 414 415struct link_config { 416 unsigned int supported; /* link capabilities */ 417 unsigned int advertising; /* advertised capabilities */ 418 unsigned short requested_speed; /* speed user has requested */ 419 unsigned short speed; /* actual link speed */ 420 unsigned char requested_duplex; /* duplex user has requested */ 421 unsigned char duplex; /* actual link duplex */ 422 unsigned char requested_fc; /* flow control user has requested */ 423 unsigned char fc; /* actual link flow control */ 424 unsigned char autoneg; /* autonegotiating? */ 425 unsigned int link_ok; /* link up? */ 426}; 427 428#define SPEED_INVALID 0xffff 429#define DUPLEX_INVALID 0xff 430 431struct mc5 { 432 adapter_t *adapter; 433 unsigned int tcam_size; 434 unsigned char part_type; 435 unsigned char parity_enabled; 436 unsigned char mode; 437 struct mc5_stats stats; 438}; 439 440static inline unsigned int t3_mc5_size(const struct mc5 *p) 441{ 442 return p->tcam_size; 443} 444 445struct mc7 { 446 adapter_t *adapter; /* backpointer to adapter */ 447 unsigned int size; /* memory size in bytes */ 448 unsigned int width; /* MC7 interface width */ 449 unsigned int offset; /* register address offset for MC7 instance */ 450 const char *name; /* name of MC7 instance */ 451 struct mc7_stats stats; /* MC7 statistics */ 452}; 453 454static inline unsigned int t3_mc7_size(const struct mc7 *p) 455{ 456 return p->size; 457} 458 459struct cmac { 460 adapter_t *adapter; 461 unsigned int offset; 462 unsigned char nucast; /* # of address filters for unicast MACs */ 463 unsigned char multiport; /* multiple ports connected to this MAC */ 464 unsigned char ext_port; /* external MAC port */ 465 unsigned char promisc_map; /* which external ports are promiscuous */ 466 unsigned int tx_tcnt; 467 unsigned int tx_xcnt; 468 u64 tx_mcnt; 469 unsigned int rx_xcnt; 470 unsigned int rx_ocnt; 471 u64 rx_mcnt; 472 unsigned int toggle_cnt; 473 unsigned int txen; 474 u64 rx_pause; 475 struct mac_stats stats; 476}; 477 478enum { 479 MAC_DIRECTION_RX = 1, 480 MAC_DIRECTION_TX = 2, 481 MAC_RXFIFO_SIZE = 32768 482}; 483 484/* IEEE 802.3 specified MDIO devices */ 485enum { 486 MDIO_DEV_PMA_PMD = 1, 487 MDIO_DEV_WIS = 2, 488 MDIO_DEV_PCS = 3, 489 MDIO_DEV_XGXS = 4, 490 MDIO_DEV_ANEG = 7, 491 MDIO_DEV_VEND1 = 30, 492 MDIO_DEV_VEND2 = 31 493}; 494 495/* LASI control and status registers */ 496enum { 497 RX_ALARM_CTRL = 0x9000, 498 TX_ALARM_CTRL = 0x9001, 499 LASI_CTRL = 0x9002, 500 RX_ALARM_STAT = 0x9003, 501 TX_ALARM_STAT = 0x9004, 502 LASI_STAT = 0x9005 503}; 504 505/* PHY loopback direction */ 506enum { 507 PHY_LOOPBACK_TX = 1, 508 PHY_LOOPBACK_RX = 2 509}; 510 511/* PHY interrupt types */ 512enum { 513 cphy_cause_link_change = 1, 514 cphy_cause_fifo_error = 2 515}; 516 517/* PHY operations */ 518struct cphy_ops { 519 int (*reset)(struct cphy *phy, int wait); 520 521 int (*intr_enable)(struct cphy *phy); 522 int (*intr_disable)(struct cphy *phy); 523 int (*intr_clear)(struct cphy *phy); 524 int (*intr_handler)(struct cphy *phy); 525 526 int (*autoneg_enable)(struct cphy *phy); 527 int (*autoneg_restart)(struct cphy *phy); 528 529 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 530 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 531 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 532 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 533 int *duplex, int *fc); 534 int (*power_down)(struct cphy *phy, int enable); 535}; 536 537/* A PHY instance */ 538struct cphy { 539 int addr; /* PHY address */ 540 unsigned int caps; /* PHY capabilities */ 541 adapter_t *adapter; /* associated adapter */ 542 const char *desc; /* PHY description */ 543 unsigned long fifo_errors; /* FIFO over/under-flows */ 544 const struct cphy_ops *ops; /* PHY operations */ 545 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 546 int reg_addr, unsigned int *val); 547 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 548 int reg_addr, unsigned int val); 549}; 550 551/* Convenience MDIO read/write wrappers */ 552static inline int mdio_read(struct cphy *phy, int mmd, int reg, 553 unsigned int *valp) 554{ 555 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 556} 557 558static inline int mdio_write(struct cphy *phy, int mmd, int reg, 559 unsigned int val) 560{ 561 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 562} 563 564/* Convenience initializer */ 565static inline void cphy_init(struct cphy *phy, adapter_t *adapter, 566 int phy_addr, struct cphy_ops *phy_ops, 567 const struct mdio_ops *mdio_ops, unsigned int caps, 568 const char *desc) 569{ 570 phy->adapter = adapter; 571 phy->addr = phy_addr; 572 phy->caps = caps; 573 phy->desc = desc; 574 phy->ops = phy_ops; 575 if (mdio_ops) { 576 phy->mdio_read = mdio_ops->read; 577 phy->mdio_write = mdio_ops->write; 578 } 579} 580 581/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 582#define MAC_STATS_ACCUM_SECS 180 583 584/* The external MAC needs accumulation every 30 seconds */ 585#define VSC_STATS_ACCUM_SECS 30 586 587#define XGM_REG(reg_addr, idx) \ 588 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 589 590struct addr_val_pair { 591 unsigned int reg_addr; 592 unsigned int val; 593}; 594 595#ifdef CONFIG_DEFINED 596#include <cxgb_adapter.h> 597#else 598#include <dev/cxgb/cxgb_adapter.h> 599#endif 600 601#ifndef PCI_VENDOR_ID_CHELSIO 602# define PCI_VENDOR_ID_CHELSIO 0x1425 603#endif 604 605#define for_each_port(adapter, iter) \ 606 for (iter = 0; iter < (adapter)->params.nports; ++iter) 607 608#define adapter_info(adap) ((adap)->params.info) 609 610static inline int uses_xaui(const adapter_t *adap) 611{ 612 return adapter_info(adap)->caps & SUPPORTED_AUI; 613} 614 615static inline int is_10G(const adapter_t *adap) 616{ 617 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 618} 619 620static inline int is_offload(const adapter_t *adap) 621{ 622#ifdef CONFIG_CHELSIO_T3_CORE 623 return adap->params.offload; 624#else 625 return 0; 626#endif 627} 628 629static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 630{ 631 return adap->params.vpd.cclk / 1000; 632} 633 634static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 635 unsigned int ticks) 636{ 637 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 638} 639 640static inline unsigned int is_pcie(const adapter_t *adap) 641{ 642 return adap->params.pci.variant == PCI_VARIANT_PCIE; 643} 644 645void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 646void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 647 unsigned int offset); 648int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 649 int attempts, int delay, u32 *valp); 650 651static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 652 int polarity, int attempts, int delay) 653{ 654 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 655 delay, NULL); 656} 657 658int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 659 unsigned int set); 660int t3_phy_reset(struct cphy *phy, int mmd, int wait); 661int t3_phy_advertise(struct cphy *phy, unsigned int advert); 662int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 663int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 664int t3_phy_lasi_intr_enable(struct cphy *phy); 665int t3_phy_lasi_intr_disable(struct cphy *phy); 666int t3_phy_lasi_intr_clear(struct cphy *phy); 667int t3_phy_lasi_intr_handler(struct cphy *phy); 668 669void t3_intr_enable(adapter_t *adapter); 670void t3_intr_disable(adapter_t *adapter); 671void t3_intr_clear(adapter_t *adapter); 672void t3_port_intr_enable(adapter_t *adapter, int idx); 673void t3_port_intr_disable(adapter_t *adapter, int idx); 674void t3_port_intr_clear(adapter_t *adapter, int idx); 675int t3_slow_intr_handler(adapter_t *adapter); 676int t3_phy_intr_handler(adapter_t *adapter); 677 678void t3_link_changed(adapter_t *adapter, int port_id); 679int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 680const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 681int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 682int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 683int t3_seeprom_wp(adapter_t *adapter, int enable); 684int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 685 u32 *data, int byte_oriented); 686int t3_get_tp_version(adapter_t *adapter, u32 *vers); 687int t3_check_tpsram_version(adapter_t *adapter, int *must_load); 688int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); 689int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 690int t3_get_fw_version(adapter_t *adapter, u32 *vers); 691int t3_check_fw_version(adapter_t *adapter, int *must_load); 692int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); 693int t3_init_hw(adapter_t *adapter, u32 fw_params); 694void mac_prep(struct cmac *mac, adapter_t *adapter, int index); 695void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 696int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 697void t3_led_ready(adapter_t *adapter); 698void t3_fatal_err(adapter_t *adapter); 699void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 700void t3_enable_filters(adapter_t *adap); 701void t3_tp_set_offload_mode(adapter_t *adap, int enable); 702void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 703 const u16 *rspq); 704int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 705int t3_set_proto_sram(adapter_t *adap, const u8 *data); 706int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 707void t3_port_failover(adapter_t *adapter, int port); 708void t3_failover_done(adapter_t *adapter, int port); 709void t3_failover_clear(adapter_t *adapter); 710int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 711 unsigned int *valp); 712int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 713 u64 *buf); 714 715int t3_mac_reset(struct cmac *mac); 716void t3b_pcs_reset(struct cmac *mac); 717int t3_mac_enable(struct cmac *mac, int which); 718int t3_mac_disable(struct cmac *mac, int which); 719int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 720int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 721int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 722int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); 723const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 724int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 725 int fc); 726int t3b2_mac_watchdog_task(struct cmac *mac); 727 728void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 729int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 730 unsigned int nroutes); 731void t3_mc5_intr_handler(struct mc5 *mc5); 732int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 733 u32 *buf); 734 735#ifdef CONFIG_CHELSIO_T3_CORE 736int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 737void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 738void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 739void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 740 unsigned short alpha[NCCTRL_WIN], 741 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 742void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 743void t3_get_cong_cntl_tab(adapter_t *adap, 744 unsigned short incr[NMTUS][NCCTRL_WIN]); 745void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 746 int filter_index, int invert, int enable); 747int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 748int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 749void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 750 unsigned int *ipg); 751void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 752void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 753 unsigned int start, unsigned int n); 754#endif 755 756void t3_sge_prep(adapter_t *adap, struct sge_params *p); 757void t3_sge_init(adapter_t *adap, struct sge_params *p); 758int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 759 enum sge_context_type type, int respq, u64 base_addr, 760 unsigned int size, unsigned int token, int gen, 761 unsigned int cidx); 762int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 763 u64 base_addr, unsigned int size, unsigned int esize, 764 unsigned int cong_thres, int gen, unsigned int cidx); 765int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 766 u64 base_addr, unsigned int size, 767 unsigned int fl_thres, int gen, unsigned int cidx); 768int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 769 unsigned int size, int rspq, int ovfl_mode, 770 unsigned int credits, unsigned int credit_thres); 771int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 772int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 773int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 774int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 775int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 776int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 777int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 778int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 779int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 780 unsigned int credits); 781 782int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); 783int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); 784int t3_vsc7323_init(adapter_t *adap, int nports); 785int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); 786int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); 787int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); 788int t3_vsc7323_enable(adapter_t *adap, int port, int which); 789int t3_vsc7323_disable(adapter_t *adap, int port, int which); 790const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); 791 792int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 793 const struct mdio_ops *mdio_ops); 794int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 795 const struct mdio_ops *mdio_ops); 796int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 797 const struct mdio_ops *mdio_ops); 798int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 799 const struct mdio_ops *mdio_ops); 800int t3_ael2005_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 801 const struct mdio_ops *mdio_ops); 802int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 803 const struct mdio_ops *mdio_ops); 804int t3_tn1010_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 805 const struct mdio_ops *mdio_ops); 806int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 807 const struct mdio_ops *mdio_ops); 808#endif /* __CHELSIO_COMMON_H */ 809