1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2005-2006 Atheros Communications, Inc. 4 * All rights reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $FreeBSD$ 19 */ 20 21#ifndef __AH_REGDOMAIN_DOMAINS_H__ 22#define __AH_REGDOMAIN_DOMAINS_H__ 23 24/* 25 * BMLEN defines the size of the bitmask used to hold frequency 26 * band specifications. Note this must agree with the BM macro 27 * definition that's used to setup initializers. See also further 28 * comments below. 29 */ 30/* BMLEN is now defined in ah_regdomain.h */ 31#define W0(_a) \ 32 (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0)) 33#define W1(_a) \ 34 (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0)) 35#define BM1(_fa) { W0(_fa), W1(_fa) } 36#define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) } 37#define BM3(_fa, _fb, _fc) \ 38 { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) } 39#define BM4(_fa, _fb, _fc, _fd) \ 40 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \ 41 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) } 42#define BM5(_fa, _fb, _fc, _fd, _fe) \ 43 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \ 44 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) } 45#define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \ 46 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \ 47 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) } 48#define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \ 49 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 50 W0(_fg),\ 51 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 52 W1(_fg) } 53#define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ 54 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 55 W0(_fg) | W0(_fh) , \ 56 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 57 W1(_fg) | W1(_fh) } 58#define BM9(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi) \ 59 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 60 W0(_fg) | W0(_fh) | W0(_fi) , \ 61 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 62 W1(_fg) | W1(_fh) | W1(_fi) } 63 64static REG_DOMAIN regDomains[] = { 65 66 {.regDmnEnum = DEBUG_REG_DMN, 67 .conformanceTestLimit = FCC, 68 .dfsMask = DFS_FCC3, 69 .chan11a = BM4(F1_4950_4980, 70 F1_5120_5240, 71 F1_5260_5700, 72 F1_5745_5825), 73 .chan11a_half = BM4(F1_4945_4985, 74 F2_5120_5240, 75 F2_5260_5700, 76 F7_5745_5825), 77 .chan11a_quarter = BM4(F1_4942_4987, 78 F3_5120_5240, 79 F3_5260_5700, 80 F8_5745_5825), 81 .chan11a_turbo = BM8(T1_5130_5210, 82 T1_5250_5330, 83 T1_5370_5490, 84 T1_5530_5650, 85 T1_5150_5190, 86 T1_5230_5310, 87 T1_5350_5470, 88 T1_5510_5670), 89 .chan11a_dyn_turbo = BM4(T1_5200_5240, 90 T1_5280_5280, 91 T1_5540_5660, 92 T1_5765_5805), 93 .chan11b = BM4(F1_2312_2372, 94 F1_2412_2472, 95 F1_2484_2484, 96 F1_2512_2732), 97 .chan11g = BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732), 98 .chan11g_turbo = BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732), 99 .chan11g_half = BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732), 100 .chan11g_quarter = BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732), 101 }, 102 103 {.regDmnEnum = APL1, 104 .conformanceTestLimit = FCC, 105 .chan11a = BM1(F4_5745_5825), 106 }, 107 108 {.regDmnEnum = APL2, 109 .conformanceTestLimit = FCC, 110 .chan11a = BM1(F1_5745_5805), 111 }, 112 113 {.regDmnEnum = APL3, 114 .conformanceTestLimit = FCC, 115 .chan11a = BM2(F1_5280_5320, F2_5745_5805), 116 }, 117 118 {.regDmnEnum = APL4, 119 .conformanceTestLimit = FCC, 120 .chan11a = BM2(F4_5180_5240, F3_5745_5825), 121 }, 122 123 {.regDmnEnum = APL5, 124 .conformanceTestLimit = FCC, 125 .chan11a = BM1(F2_5745_5825), 126 }, 127 128 {.regDmnEnum = APL6, 129 .conformanceTestLimit = ETSI, 130 .dfsMask = DFS_ETSI, 131 .pscan = PSCAN_FCC_T | PSCAN_FCC, 132 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825), 133 .chan11a_turbo = BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800), 134 }, 135 136 {.regDmnEnum = APL8, 137 .conformanceTestLimit = ETSI, 138 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 139 .chan11a = BM2(F6_5260_5320, F4_5745_5825), 140 }, 141 142 {.regDmnEnum = APL9, 143 .conformanceTestLimit = ETSI, 144 .dfsMask = DFS_ETSI, 145 .pscan = PSCAN_ETSI, 146 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 147 .chan11a = BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805), 148 }, 149 150 {.regDmnEnum = ETSI1, 151 .conformanceTestLimit = ETSI, 152 .dfsMask = DFS_ETSI, 153 .pscan = PSCAN_ETSI, 154 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 155 .chan11a = BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700), 156 }, 157 158 {.regDmnEnum = ETSI2, 159 .conformanceTestLimit = ETSI, 160 .dfsMask = DFS_ETSI, 161 .pscan = PSCAN_ETSI, 162 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 163 .chan11a = BM1(F3_5180_5240), 164 }, 165 166 {.regDmnEnum = ETSI3, 167 .conformanceTestLimit = ETSI, 168 .dfsMask = DFS_ETSI, 169 .pscan = PSCAN_ETSI, 170 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 171 .chan11a = BM2(W2_5180_5240, F2_5260_5320), 172 }, 173 174 {.regDmnEnum = ETSI4, 175 .conformanceTestLimit = ETSI, 176 .dfsMask = DFS_ETSI, 177 .pscan = PSCAN_ETSI, 178 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 179 .chan11a = BM2(F3_5180_5240, F1_5260_5320), 180 }, 181 182 {.regDmnEnum = ETSI5, 183 .conformanceTestLimit = ETSI, 184 .dfsMask = DFS_ETSI, 185 .pscan = PSCAN_ETSI, 186 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 187 .chan11a = BM1(F1_5180_5240), 188 }, 189 190 {.regDmnEnum = ETSI6, 191 .conformanceTestLimit = ETSI, 192 .dfsMask = DFS_ETSI, 193 .pscan = PSCAN_ETSI, 194 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 195 .chan11a = BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700), 196 }, 197 198 {.regDmnEnum = FCC1, 199 .conformanceTestLimit = FCC, 200 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 201 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 202 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 203 }, 204 205 {.regDmnEnum = FCC2, 206 .conformanceTestLimit = FCC, 207 .chan11a = BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825), 208 .chan11a_dyn_turbo = BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805), 209 }, 210 211 {.regDmnEnum = FCC3, 212 .conformanceTestLimit = FCC, 213 .dfsMask = DFS_FCC3, 214 .pscan = PSCAN_FCC | PSCAN_FCC_T, 215 .chan11a = BM4(F2_5180_5240, 216 F3_5260_5320, 217 F1_5500_5700, 218 F5_5745_5825), 219 .chan11a_turbo = BM4(T1_5210_5210, 220 T1_5250_5250, 221 T1_5290_5290, 222 T2_5760_5800), 223 .chan11a_dyn_turbo = BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660), 224 }, 225 226 {.regDmnEnum = FCC4, 227 .conformanceTestLimit = FCC, 228 .dfsMask = DFS_FCC3, 229 .pscan = PSCAN_FCC | PSCAN_FCC_T, 230 .chan11a = BM1(F1_4950_4980), 231 .chan11a_half = BM1(F1_4945_4985), 232 .chan11a_quarter = BM1(F1_4942_4987), 233 }, 234 235 /* FCC1 w/ 1/2 and 1/4 width channels */ 236 {.regDmnEnum = FCC5, 237 .conformanceTestLimit = FCC, 238 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 239 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 240 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 241 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 242 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 243 }, 244 245 {.regDmnEnum = MKK1, 246 .conformanceTestLimit = MKK, 247 .pscan = PSCAN_MKK1, 248 .flags = DISALLOW_ADHOC_11A_TURB, 249 .chan11a = BM1(F1_5170_5230), 250 }, 251 252 {.regDmnEnum = MKK2, 253 .conformanceTestLimit = MKK, 254 .pscan = PSCAN_MKK2, 255 .flags = DISALLOW_ADHOC_11A_TURB, 256 .chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230), 257 .chan11a_half = BM4(F1_4915_4925, 258 F1_4935_4945, 259 F1_5035_5040, 260 F1_5055_5055), 261 }, 262 263 /* UNI-1 even */ 264 {.regDmnEnum = MKK3, 265 .conformanceTestLimit = MKK, 266 .pscan = PSCAN_MKK3, 267 .flags = DISALLOW_ADHOC_11A_TURB, 268 .chan11a = BM1(F4_5180_5240), 269 }, 270 271 /* UNI-1 even + UNI-2 */ 272 {.regDmnEnum = MKK4, 273 .conformanceTestLimit = MKK, 274 .dfsMask = DFS_MKK4, 275 .pscan = PSCAN_MKK3, 276 .flags = DISALLOW_ADHOC_11A_TURB, 277 .chan11a = BM2(F4_5180_5240, F2_5260_5320), 278 }, 279 280 /* UNI-1 even + UNI-2 + mid-band */ 281 {.regDmnEnum = MKK5, 282 .conformanceTestLimit = MKK, 283 .dfsMask = DFS_MKK4, 284 .pscan = PSCAN_MKK3, 285 .flags = DISALLOW_ADHOC_11A_TURB, 286 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700), 287 }, 288 289 /* UNI-1 odd + even */ 290 {.regDmnEnum = MKK6, 291 .conformanceTestLimit = MKK, 292 .pscan = PSCAN_MKK1, 293 .flags = DISALLOW_ADHOC_11A_TURB, 294 .chan11a = BM2(F2_5170_5230, F4_5180_5240), 295 }, 296 297 /* UNI-1 odd + UNI-1 even + UNI-2 */ 298 {.regDmnEnum = MKK7, 299 .conformanceTestLimit = MKK, 300 .dfsMask = DFS_MKK4, 301 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 302 .flags = DISALLOW_ADHOC_11A_TURB, 303 .chan11a = BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320), 304 }, 305 306 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ 307 {.regDmnEnum = MKK8, 308 .conformanceTestLimit = MKK, 309 .dfsMask = DFS_MKK4, 310 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 311 .flags = DISALLOW_ADHOC_11A_TURB, 312 .chan11a = BM4(F1_5170_5230, 313 F4_5180_5240, 314 F2_5260_5320, 315 F4_5500_5700), 316 }, 317 318 /* UNI-1 even + 4.9 GHZ */ 319 {.regDmnEnum = MKK9, 320 .conformanceTestLimit = MKK, 321 .pscan = PSCAN_MKK3, 322 .flags = DISALLOW_ADHOC_11A_TURB, 323 .chan11a = BM7(F1_4915_4925, 324 F1_4935_4945, 325 F1_4920_4980, 326 F1_5035_5040, 327 F1_5055_5055, 328 F1_5040_5080, 329 F4_5180_5240), 330 }, 331 332 /* UNI-1 even + UNI-2 + 4.9 GHZ */ 333 {.regDmnEnum = MKK10, 334 .conformanceTestLimit = MKK, 335 .dfsMask = DFS_MKK4, 336 .pscan = PSCAN_MKK3, 337 .flags = DISALLOW_ADHOC_11A_TURB, 338 .chan11a = BM8(F1_4915_4925, 339 F1_4935_4945, 340 F1_4920_4980, 341 F1_5035_5040, 342 F1_5055_5055, 343 F1_5040_5080, 344 F4_5180_5240, 345 F2_5260_5320), 346 }, 347 348 /* Defined here to use when 2G channels are authorised for country K2 */ 349 {.regDmnEnum = APLD, 350 .conformanceTestLimit = NO_CTL, 351 .chan11b = BM2(F2_2312_2372,F2_2412_2472), 352 .chan11g = BM2(G2_2312_2372,G2_2412_2472), 353 }, 354 355 {.regDmnEnum = ETSIA, 356 .conformanceTestLimit = NO_CTL, 357 .pscan = PSCAN_ETSIA, 358 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 359 .chan11b = BM1(F1_2457_2472), 360 .chan11g = BM1(G1_2457_2472), 361 .chan11g_turbo = BM1(T2_2437_2437) 362 }, 363 364 {.regDmnEnum = ETSIB, 365 .conformanceTestLimit = ETSI, 366 .pscan = PSCAN_ETSIB, 367 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 368 .chan11b = BM1(F1_2432_2442), 369 .chan11g = BM1(G1_2432_2442), 370 .chan11g_turbo = BM1(T2_2437_2437) 371 }, 372 373 {.regDmnEnum = ETSIC, 374 .conformanceTestLimit = ETSI, 375 .pscan = PSCAN_ETSIC, 376 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 377 .chan11b = BM1(F3_2412_2472), 378 .chan11g = BM1(G3_2412_2472), 379 .chan11g_turbo = BM1(T2_2437_2437) 380 }, 381 382 {.regDmnEnum = FCCA, 383 .conformanceTestLimit = FCC, 384 .chan11b = BM1(F1_2412_2462), 385 .chan11g = BM1(G1_2412_2462), 386 .chan11g_turbo = BM1(T2_2437_2437), 387 }, 388 389 /* FCCA w/ 1/2 and 1/4 width channels */ 390 {.regDmnEnum = FCCB, 391 .conformanceTestLimit = FCC, 392 .chan11b = BM1(F1_2412_2462), 393 .chan11g = BM1(G1_2412_2462), 394 .chan11g_turbo = BM1(T2_2437_2437), 395 .chan11g_half = BM1(G3_2412_2462), 396 .chan11g_quarter = BM1(G4_2412_2462), 397 }, 398 399 {.regDmnEnum = MKKA, 400 .conformanceTestLimit = MKK, 401 .pscan = PSCAN_MKKA | PSCAN_MKKA_G 402 | PSCAN_MKKA1 | PSCAN_MKKA1_G 403 | PSCAN_MKKA2 | PSCAN_MKKA2_G, 404 .flags = DISALLOW_ADHOC_11A_TURB, 405 .chan11b = BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484), 406 .chan11g = BM2(G2_2412_2462, G1_2467_2472), 407 .chan11g_turbo = BM1(T2_2437_2437) 408 }, 409 410 {.regDmnEnum = MKKC, 411 .conformanceTestLimit = MKK, 412 .chan11b = BM1(F2_2412_2472), 413 .chan11g = BM1(G2_2412_2472), 414 .chan11g_turbo = BM1(T2_2437_2437) 415 }, 416 417 {.regDmnEnum = WORLD, 418 .conformanceTestLimit = ETSI, 419 .chan11b = BM1(F2_2412_2472), 420 .chan11g = BM1(G2_2412_2472), 421 .chan11g_turbo = BM1(T2_2437_2437) 422 }, 423 424 {.regDmnEnum = WOR0_WORLD, 425 .conformanceTestLimit = NO_CTL, 426 .dfsMask = DFS_FCC3 | DFS_ETSI, 427 .pscan = PSCAN_WWR, 428 .flags = ADHOC_PER_11D, 429 .chan11a = BM5(W1_5260_5320, 430 W1_5180_5240, 431 W1_5170_5230, 432 W1_5745_5825, 433 W1_5500_5700), 434 .chan11a_turbo = BM3(WT1_5210_5250, 435 WT1_5290_5290, 436 WT1_5760_5800), 437 .chan11b = BM8(W1_2412_2412, 438 W1_2437_2442, 439 W1_2462_2462, 440 W1_2472_2472, 441 W1_2417_2432, 442 W1_2447_2457, 443 W1_2467_2467, 444 W1_2484_2484), 445 .chan11g = BM7(WG1_2412_2412, 446 WG1_2437_2442, 447 WG1_2462_2462, 448 WG1_2472_2472, 449 WG1_2417_2432, 450 WG1_2447_2457, 451 WG1_2467_2467), 452 .chan11g_turbo = BM1(T3_2437_2437) 453 }, 454 455 {.regDmnEnum = WOR01_WORLD, 456 .conformanceTestLimit = NO_CTL, 457 .dfsMask = DFS_FCC3 | DFS_ETSI, 458 .pscan = PSCAN_WWR, 459 .flags = ADHOC_PER_11D, 460 .chan11a = BM5(W1_5260_5320, 461 W1_5180_5240, 462 W1_5170_5230, 463 W1_5745_5825, 464 W1_5500_5700), 465 .chan11a_turbo = BM3(WT1_5210_5250, 466 WT1_5290_5290, 467 WT1_5760_5800), 468 .chan11b = BM5(W1_2412_2412, 469 W1_2437_2442, 470 W1_2462_2462, 471 W1_2417_2432, 472 W1_2447_2457), 473 .chan11g = BM5(WG1_2412_2412, 474 WG1_2437_2442, 475 WG1_2462_2462, 476 WG1_2417_2432, 477 WG1_2447_2457), 478 .chan11g_turbo = BM1(T3_2437_2437)}, 479 480 {.regDmnEnum = WOR02_WORLD, 481 .conformanceTestLimit = NO_CTL, 482 .dfsMask = DFS_FCC3 | DFS_ETSI, 483 .pscan = PSCAN_WWR, 484 .flags = ADHOC_PER_11D, 485 .chan11a = BM5(W1_5260_5320, 486 W1_5180_5240, 487 W1_5170_5230, 488 W1_5745_5825, 489 W1_5500_5700), 490 .chan11a_turbo = BM3(WT1_5210_5250, 491 WT1_5290_5290, 492 WT1_5760_5800), 493 .chan11b = BM7(W1_2412_2412, 494 W1_2437_2442, 495 W1_2462_2462, 496 W1_2472_2472, 497 W1_2417_2432, 498 W1_2447_2457, 499 W1_2467_2467), 500 .chan11g = BM7(WG1_2412_2412, 501 WG1_2437_2442, 502 WG1_2462_2462, 503 WG1_2472_2472, 504 WG1_2417_2432, 505 WG1_2447_2457, 506 WG1_2467_2467), 507 .chan11g_turbo = BM1(T3_2437_2437)}, 508 509 {.regDmnEnum = EU1_WORLD, 510 .conformanceTestLimit = NO_CTL, 511 .dfsMask = DFS_FCC3 | DFS_ETSI, 512 .pscan = PSCAN_WWR, 513 .flags = ADHOC_PER_11D, 514 .chan11a = BM5(W1_5260_5320, 515 W1_5180_5240, 516 W1_5170_5230, 517 W1_5745_5825, 518 W1_5500_5700), 519 .chan11a_turbo = BM3(WT1_5210_5250, 520 WT1_5290_5290, 521 WT1_5760_5800), 522 .chan11b = BM7(W1_2412_2412, 523 W1_2437_2442, 524 W1_2462_2462, 525 W2_2472_2472, 526 W1_2417_2432, 527 W1_2447_2457, 528 W2_2467_2467), 529 .chan11g = BM7(WG1_2412_2412, 530 WG1_2437_2442, 531 WG1_2462_2462, 532 WG2_2472_2472, 533 WG1_2417_2432, 534 WG1_2447_2457, 535 WG2_2467_2467), 536 .chan11g_turbo = BM1(T3_2437_2437)}, 537 538 {.regDmnEnum = WOR1_WORLD, 539 .conformanceTestLimit = NO_CTL, 540 .dfsMask = DFS_FCC3 | DFS_ETSI, 541 .pscan = PSCAN_WWR, 542 .flags = DISALLOW_ADHOC_11A, 543 .chan11a = BM5(W1_5260_5320, 544 W1_5180_5240, 545 W1_5170_5230, 546 W1_5745_5825, 547 W1_5500_5700), 548 .chan11b = BM8(W1_2412_2412, 549 W1_2437_2442, 550 W1_2462_2462, 551 W1_2472_2472, 552 W1_2417_2432, 553 W1_2447_2457, 554 W1_2467_2467, 555 W1_2484_2484), 556 .chan11g = BM7(WG1_2412_2412, 557 WG1_2437_2442, 558 WG1_2462_2462, 559 WG1_2472_2472, 560 WG1_2417_2432, 561 WG1_2447_2457, 562 WG1_2467_2467), 563 .chan11g_turbo = BM1(T3_2437_2437) 564 }, 565 566 {.regDmnEnum = WOR2_WORLD, 567 .conformanceTestLimit = NO_CTL, 568 .dfsMask = DFS_FCC3 | DFS_ETSI, 569 .pscan = PSCAN_WWR, 570 .flags = DISALLOW_ADHOC_11A, 571 .chan11a = BM5(W1_5260_5320, 572 W1_5180_5240, 573 W1_5170_5230, 574 W1_5745_5825, 575 W1_5500_5700), 576 .chan11a_turbo = BM3(WT1_5210_5250, 577 WT1_5290_5290, 578 WT1_5760_5800), 579 .chan11b = BM8(W1_2412_2412, 580 W1_2437_2442, 581 W1_2462_2462, 582 W1_2472_2472, 583 W1_2417_2432, 584 W1_2447_2457, 585 W1_2467_2467, 586 W1_2484_2484), 587 .chan11g = BM7(WG1_2412_2412, 588 WG1_2437_2442, 589 WG1_2462_2462, 590 WG1_2472_2472, 591 WG1_2417_2432, 592 WG1_2447_2457, 593 WG1_2467_2467), 594 .chan11g_turbo = BM1(T3_2437_2437)}, 595 596 {.regDmnEnum = WOR3_WORLD, 597 .conformanceTestLimit = NO_CTL, 598 .dfsMask = DFS_FCC3 | DFS_ETSI, 599 .pscan = PSCAN_WWR, 600 .flags = ADHOC_PER_11D, 601 .chan11a = BM4(W1_5260_5320, 602 W1_5180_5240, 603 W1_5170_5230, 604 W1_5745_5825), 605 .chan11a_turbo = BM3(WT1_5210_5250, 606 WT1_5290_5290, 607 WT1_5760_5800), 608 .chan11b = BM7(W1_2412_2412, 609 W1_2437_2442, 610 W1_2462_2462, 611 W1_2472_2472, 612 W1_2417_2432, 613 W1_2447_2457, 614 W1_2467_2467), 615 .chan11g = BM7(WG1_2412_2412, 616 WG1_2437_2442, 617 WG1_2462_2462, 618 WG1_2472_2472, 619 WG1_2417_2432, 620 WG1_2447_2457, 621 WG1_2467_2467), 622 .chan11g_turbo = BM1(T3_2437_2437)}, 623 624 {.regDmnEnum = WOR4_WORLD, 625 .conformanceTestLimit = NO_CTL, 626 .dfsMask = DFS_FCC3 | DFS_ETSI, 627 .pscan = PSCAN_WWR, 628 .flags = DISALLOW_ADHOC_11A, 629 .chan11a = BM4(W2_5260_5320, 630 W2_5180_5240, 631 F2_5745_5805, 632 W2_5825_5825), 633 .chan11a_turbo = BM3(WT1_5210_5250, 634 WT1_5290_5290, 635 WT1_5760_5800), 636 .chan11b = BM5(W1_2412_2412, 637 W1_2437_2442, 638 W1_2462_2462, 639 W1_2417_2432, 640 W1_2447_2457), 641 .chan11g = BM5(WG1_2412_2412, 642 WG1_2437_2442, 643 WG1_2462_2462, 644 WG1_2417_2432, 645 WG1_2447_2457), 646 .chan11g_turbo = BM1(T3_2437_2437)}, 647 648 {.regDmnEnum = WOR5_ETSIC, 649 .conformanceTestLimit = NO_CTL, 650 .dfsMask = DFS_FCC3 | DFS_ETSI, 651 .pscan = PSCAN_WWR, 652 .flags = DISALLOW_ADHOC_11A, 653 .chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825), 654 .chan11b = BM7(W1_2412_2412, 655 W1_2437_2442, 656 W1_2462_2462, 657 W2_2472_2472, 658 W1_2417_2432, 659 W1_2447_2457, 660 W2_2467_2467), 661 .chan11g = BM7(WG1_2412_2412, 662 WG1_2437_2442, 663 WG1_2462_2462, 664 WG2_2472_2472, 665 WG1_2417_2432, 666 WG1_2447_2457, 667 WG2_2467_2467), 668 .chan11g_turbo = BM1(T3_2437_2437)}, 669 670 {.regDmnEnum = WOR9_WORLD, 671 .conformanceTestLimit = NO_CTL, 672 .dfsMask = DFS_FCC3 | DFS_ETSI, 673 .pscan = PSCAN_WWR, 674 .flags = DISALLOW_ADHOC_11A, 675 .chan11a = BM4(W1_5260_5320, 676 W1_5180_5240, 677 W1_5745_5825, 678 W1_5500_5700), 679 .chan11a_turbo = BM3(WT1_5210_5250, 680 WT1_5290_5290, 681 WT1_5760_5800), 682 .chan11b = BM5(W1_2412_2412, 683 W1_2437_2442, 684 W1_2462_2462, 685 W1_2417_2432, 686 W1_2447_2457), 687 .chan11g = BM5(WG1_2412_2412, 688 WG1_2437_2442, 689 WG1_2462_2462, 690 WG1_2417_2432, 691 WG1_2447_2457), 692 .chan11g_turbo = BM1(T3_2437_2437)}, 693 694 {.regDmnEnum = WORA_WORLD, 695 .conformanceTestLimit = NO_CTL, 696 .dfsMask = DFS_FCC3 | DFS_ETSI, 697 .pscan = PSCAN_WWR, 698 .flags = DISALLOW_ADHOC_11A, 699 .chan11a = BM4(W1_5260_5320, 700 W1_5180_5240, 701 W1_5745_5825, 702 W1_5500_5700), 703 .chan11b = BM7(W1_2412_2412, 704 W1_2437_2442, 705 W1_2462_2462, 706 W1_2472_2472, 707 W1_2417_2432, 708 W1_2447_2457, 709 W1_2467_2467), 710 .chan11g = BM7(WG1_2412_2412, 711 WG1_2437_2442, 712 WG1_2462_2462, 713 WG1_2472_2472, 714 WG1_2417_2432, 715 WG1_2447_2457, 716 WG1_2467_2467), 717 .chan11g_turbo = BM1(T3_2437_2437)}, 718 719 {.regDmnEnum = WORB_WORLD, 720 .conformanceTestLimit = NO_CTL, 721 .dfsMask = DFS_FCC3 | DFS_ETSI, 722 .pscan = PSCAN_WWR, 723 .flags = DISALLOW_ADHOC_11A, 724 .chan11a = BM4(W1_5260_5320, 725 W1_5180_5240, 726 W1_5745_5825, 727 W1_5500_5700), 728 .chan11b = BM7(W1_2412_2412, 729 W1_2437_2442, 730 W1_2462_2462, 731 W1_2472_2472, 732 W1_2417_2432, 733 W1_2447_2457, 734 W1_2467_2467), 735 .chan11g = BM7(WG1_2412_2412, 736 WG1_2437_2442, 737 WG1_2462_2462, 738 WG1_2472_2472, 739 WG1_2417_2432, 740 WG1_2447_2457, 741 WG1_2467_2467), 742 .chan11g_turbo = BM1(T3_2437_2437)}, 743 744 {.regDmnEnum = WORC_WORLD, 745 .conformanceTestLimit = NO_CTL, 746 .dfsMask = DFS_FCC3 | DFS_ETSI, 747 .pscan = PSCAN_WWR, 748 .flags = ADHOC_PER_11D, 749 .chan11a = BM4(W1_5260_5320, 750 W1_5180_5240, 751 W1_5745_5825, 752 W1_5500_5700), 753 .chan11b = BM7(W1_2412_2412, 754 W1_2437_2442, 755 W1_2462_2462, 756 W1_2472_2472, 757 W1_2417_2432, 758 W1_2447_2457, 759 W1_2467_2467), 760 .chan11g = BM7(WG1_2412_2412, 761 WG1_2437_2442, 762 WG1_2462_2462, 763 WG1_2472_2472, 764 WG1_2417_2432, 765 WG1_2447_2457, 766 WG1_2467_2467), 767 .chan11g_turbo = BM1(T3_2437_2437)}, 768 769 {.regDmnEnum = NULL1, 770 .conformanceTestLimit = NO_CTL, 771 } 772}; 773 774#endif 775