1/*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/ata/ata-all.h> 50#include <dev/ata/ata-pci.h> 51#include <ata_if.h> 52 53/* local prototypes */ 54static int ata_highpoint_chipinit(device_t dev); 55static int ata_highpoint_ch_attach(device_t dev); 56static int ata_highpoint_setmode(device_t dev, int target, int mode); 57static int ata_highpoint_check_80pin(device_t dev, int mode); 58 59/* misc defines */ 60#define HPT_366 0 61#define HPT_370 1 62#define HPT_372 2 63#define HPT_374 3 64#define HPT_OLD 1 65 66 67/* 68 * HighPoint chipset support functions 69 */ 70static int 71ata_highpoint_probe(device_t dev) 72{ 73 struct ata_pci_controller *ctlr = device_get_softc(dev); 74 const struct ata_chip_id *idx; 75 static const struct ata_chip_id ids[] = 76 {{ ATA_HPT374, 0x07, HPT_374, 0, ATA_UDMA6, "HPT374" }, 77 { ATA_HPT372, 0x02, HPT_372, 0, ATA_UDMA6, "HPT372N" }, 78 { ATA_HPT372, 0x01, HPT_372, 0, ATA_UDMA6, "HPT372" }, 79 { ATA_HPT371, 0x01, HPT_372, 0, ATA_UDMA6, "HPT371" }, 80 { ATA_HPT366, 0x05, HPT_372, 0, ATA_UDMA6, "HPT372" }, 81 { ATA_HPT366, 0x03, HPT_370, 0, ATA_UDMA5, "HPT370" }, 82 { ATA_HPT366, 0x02, HPT_366, 0, ATA_UDMA4, "HPT368" }, 83 { ATA_HPT366, 0x00, HPT_366, HPT_OLD, ATA_UDMA4, "HPT366" }, 84 { ATA_HPT302, 0x01, HPT_372, 0, ATA_UDMA6, "HPT302" }, 85 { 0, 0, 0, 0, 0, 0}}; 86 char buffer[64]; 87 88 if (pci_get_vendor(dev) != ATA_HIGHPOINT_ID) 89 return ENXIO; 90 91 if (!(idx = ata_match_chip(dev, ids))) 92 return ENXIO; 93 94 strcpy(buffer, "HighPoint "); 95 strcat(buffer, idx->text); 96 if (idx->cfg1 == HPT_374) { 97 if (pci_get_function(dev) == 0) 98 strcat(buffer, " (channel 0+1)"); 99 if (pci_get_function(dev) == 1) 100 strcat(buffer, " (channel 2+3)"); 101 } 102 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 103 device_set_desc_copy(dev, buffer); 104 ctlr->chip = idx; 105 ctlr->chipinit = ata_highpoint_chipinit; 106 return (BUS_PROBE_LOW_PRIORITY); 107} 108 109static int 110ata_highpoint_chipinit(device_t dev) 111{ 112 struct ata_pci_controller *ctlr = device_get_softc(dev); 113 114 if (ata_setup_interrupt(dev, ata_generic_intr)) 115 return ENXIO; 116 117 if (ctlr->chip->cfg2 == HPT_OLD) { 118 /* disable interrupt prediction */ 119 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 120 } 121 else { 122 /* disable interrupt prediction */ 123 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 124 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 125 126 /* enable interrupts */ 127 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 128 129 /* set clocks etc */ 130 if (ctlr->chip->cfg1 < HPT_372) 131 pci_write_config(dev, 0x5b, 0x22, 1); 132 else 133 pci_write_config(dev, 0x5b, 134 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 135 } 136 ctlr->ch_attach = ata_highpoint_ch_attach; 137 ctlr->ch_detach = ata_pci_ch_detach; 138 ctlr->setmode = ata_highpoint_setmode; 139 return 0; 140} 141 142static int 143ata_highpoint_ch_attach(device_t dev) 144{ 145 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 146 struct ata_channel *ch = device_get_softc(dev); 147 148 /* setup the usual register normal pci style */ 149 if (ata_pci_ch_attach(dev)) 150 return (ENXIO); 151 ch->flags |= ATA_ALWAYS_DMASTAT; 152 ch->flags |= ATA_CHECKS_CABLE; 153 if (ctlr->chip->cfg1 == HPT_366) 154 ch->flags |= ATA_NO_ATAPI_DMA; 155 return (0); 156} 157 158static int 159ata_highpoint_setmode(device_t dev, int target, int mode) 160{ 161 device_t parent = device_get_parent(dev); 162 struct ata_pci_controller *ctlr = device_get_softc(parent); 163 struct ata_channel *ch = device_get_softc(dev); 164 int devno = (ch->unit << 1) + target; 165 static const uint32_t timings33[][4] = { 166 /* HPT366 HPT370 HPT372 HPT374 mode */ 167 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 168 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 169 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 170 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 171 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 172 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 173 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 174 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 175 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 176 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 177 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 178 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 179 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 180 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 181 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 182 }; 183 184 mode = min(mode, ctlr->chip->max_dma); 185 mode = ata_highpoint_check_80pin(dev, mode); 186 /* 187 * most if not all HPT chips cant really handle that the device is 188 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 189 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 190 */ 191 mode = min(mode, ATA_UDMA5); 192 pci_write_config(parent, 0x40 + (devno << 2), 193 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 194 return (mode); 195} 196 197static int 198ata_highpoint_check_80pin(device_t dev, int mode) 199{ 200 device_t parent = device_get_parent(dev); 201 struct ata_pci_controller *ctlr = device_get_softc(parent); 202 struct ata_channel *ch = device_get_softc(dev); 203 u_int8_t reg, val, res; 204 205 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) { 206 reg = ch->unit ? 0x57 : 0x53; 207 val = pci_read_config(parent, reg, 1); 208 pci_write_config(parent, reg, val | 0x80, 1); 209 } 210 else { 211 reg = 0x5b; 212 val = pci_read_config(parent, reg, 1); 213 pci_write_config(parent, reg, val & 0xfe, 1); 214 } 215 res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 216 pci_write_config(parent, reg, val, 1); 217 218 if (ata_dma_check_80pin && mode > ATA_UDMA2 && res) { 219 ata_print_cable(dev, "controller"); 220 mode = ATA_UDMA2; 221 } 222 return mode; 223} 224 225ATA_DECLARE_DRIVER(ata_highpoint); 226