1/*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/ata/ata-all.h> 50#include <dev/ata/ata-pci.h> 51#include <ata_if.h> 52 53/* local prototypes */ 54static int ata_ati_chipinit(device_t dev); 55static int ata_ati_dumb_ch_attach(device_t dev); 56static int ata_ati_ixp700_ch_attach(device_t dev); 57static int ata_ati_setmode(device_t dev, int target, int mode); 58 59/* misc defines */ 60#define SII_MEMIO 1 /* must match ata_siliconimage.c's definition */ 61#define SII_BUG 0x04 /* must match ata_siliconimage.c's definition */ 62 63#define ATI_SATA SII_MEMIO 64#define ATI_PATA 0x02 65#define ATI_AHCI 0x04 66 67/* 68 * ATI chipset support functions 69 */ 70static int 71ata_ati_probe(device_t dev) 72{ 73 struct ata_pci_controller *ctlr = device_get_softc(dev); 74 static const struct ata_chip_id ids[] = 75 {{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" }, 76 { ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" }, 77 { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP300" }, 78 { ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" }, 79 { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 80 { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 81 { ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" }, 82 { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" }, 83 { ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" }, 84 { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 85 { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 86 { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 87 { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 88 { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 89 { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 90 { ATA_AMD_HUDSON2, 0x00, ATI_PATA, 0, ATA_UDMA6, "Hudson-2" }, 91 { ATA_AMD_HUDSON2_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 92 { ATA_AMD_HUDSON2_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 93 { ATA_AMD_HUDSON2_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 94 { ATA_AMD_HUDSON2_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 95 { ATA_AMD_HUDSON2_S5, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 96 { 0, 0, 0, 0, 0, 0}}; 97 98 if (pci_get_vendor(dev) != ATA_AMD_ID && pci_get_vendor(dev) != ATA_ATI_ID) 99 return ENXIO; 100 101 if (!(ctlr->chip = ata_match_chip(dev, ids))) 102 return ENXIO; 103 104 switch (ctlr->chip->cfg1) { 105 case ATI_PATA: 106 ctlr->chipinit = ata_ati_chipinit; 107 break; 108 case ATI_SATA: 109 /* 110 * the ATI SATA controller is actually a SiI 3112 controller 111 */ 112 ctlr->chipinit = ata_sii_chipinit; 113 break; 114 case ATI_AHCI: 115 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) 116 return (ENXIO); 117 ctlr->chipinit = ata_ati_chipinit; 118 break; 119 } 120 121 ata_set_desc(dev); 122 return (BUS_PROBE_LOW_PRIORITY); 123} 124 125static int 126ata_ati_chipinit(device_t dev) 127{ 128 struct ata_pci_controller *ctlr = device_get_softc(dev); 129 device_t smbdev; 130 uint8_t satacfg; 131 132 if (ata_setup_interrupt(dev, ata_generic_intr)) 133 return ENXIO; 134 135 if (ctlr->chip->cfg1 == ATI_AHCI) { 136 ctlr->ch_attach = ata_ati_dumb_ch_attach; 137 ctlr->setmode = ata_sata_setmode; 138 return (0); 139 } 140 switch (ctlr->chip->chipid) { 141 case ATA_ATI_IXP600: 142 /* IXP600 only has 1 PATA channel */ 143 ctlr->channels = 1; 144 break; 145 case ATA_ATI_IXP700: 146 /* 147 * When "combined mode" is enabled, an additional PATA channel is 148 * emulated with two SATA ports and appears on this device. 149 * This mode can only be detected via SMB controller. 150 */ 151 smbdev = pci_find_device(ATA_ATI_ID, 0x4385); 152 if (smbdev != NULL) { 153 satacfg = pci_read_config(smbdev, 0xad, 1); 154 if (bootverbose) 155 device_printf(dev, "SATA controller %s (%s%s channel)\n", 156 (satacfg & 0x01) == 0 ? "disabled" : "enabled", 157 (satacfg & 0x08) == 0 ? "" : "combined mode, ", 158 (satacfg & 0x10) == 0 ? "primary" : "secondary"); 159 ctlr->chipset_data = (void *)(uintptr_t)satacfg; 160 /* 161 * If SATA controller is enabled but combined mode is disabled, 162 * we have only one PATA channel. Ignore a non-existent channel. 163 */ 164 if ((satacfg & 0x09) == 0x01) 165 ctlr->ichannels &= ~(1 << ((satacfg & 0x10) >> 4)); 166 else { 167 ctlr->ch_attach = ata_ati_ixp700_ch_attach; 168 } 169 } 170 break; 171 } 172 173 ctlr->setmode = ata_ati_setmode; 174 return 0; 175} 176 177static int 178ata_ati_dumb_ch_attach(device_t dev) 179{ 180 struct ata_channel *ch = device_get_softc(dev); 181 182 if (ata_pci_ch_attach(dev)) 183 return ENXIO; 184 ch->flags |= ATA_SATA; 185 return (0); 186} 187 188static int 189ata_ati_ixp700_ch_attach(device_t dev) 190{ 191 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 192 struct ata_channel *ch = device_get_softc(dev); 193 uint8_t satacfg = (uint8_t)(uintptr_t)ctlr->chipset_data; 194 195 /* Setup the usual register normal pci style. */ 196 if (ata_pci_ch_attach(dev)) 197 return ENXIO; 198 199 /* One of channels is PATA, another is SATA. */ 200 if (ch->unit == ((satacfg & 0x10) >> 4)) 201 ch->flags |= ATA_SATA; 202 return (0); 203} 204 205static int 206ata_ati_setmode(device_t dev, int target, int mode) 207{ 208 device_t parent = device_get_parent(dev); 209 struct ata_pci_controller *ctlr = device_get_softc(parent); 210 struct ata_channel *ch = device_get_softc(dev); 211 int devno = (ch->unit << 1) + target; 212 int offset = (devno ^ 0x01) << 3; 213 int piomode; 214 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 215 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 216 217 mode = min(mode, ctlr->chip->max_dma); 218 if (mode >= ATA_UDMA0) { 219 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 220 pci_write_config(parent, 0x56, 221 (pci_read_config(parent, 0x56, 2) & 222 ~(0xf << (devno << 2))) | 223 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 224 pci_write_config(parent, 0x54, 225 pci_read_config(parent, 0x54, 1) | 226 (0x01 << devno), 1); 227 pci_write_config(parent, 0x44, 228 (pci_read_config(parent, 0x44, 4) & 229 ~(0xff << offset)) | 230 (dmatimings[2] << offset), 4); 231 piomode = ATA_PIO4; 232 } else if (mode >= ATA_WDMA0) { 233 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 234 pci_write_config(parent, 0x54, 235 pci_read_config(parent, 0x54, 1) & 236 ~(0x01 << devno), 1); 237 pci_write_config(parent, 0x44, 238 (pci_read_config(parent, 0x44, 4) & 239 ~(0xff << offset)) | 240 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 241 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 242 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 243 } else { 244 /* Disable UDMA, set requested PIO. */ 245 pci_write_config(parent, 0x54, 246 pci_read_config(parent, 0x54, 1) & 247 ~(0x01 << devno), 1); 248 piomode = mode; 249 } 250 /* Set PIO mode and timings, calculated above. */ 251 pci_write_config(parent, 0x4a, 252 (pci_read_config(parent, 0x4a, 2) & 253 ~(0xf << (devno << 2))) | 254 ((piomode - ATA_PIO0) << (devno<<2)),2); 255 pci_write_config(parent, 0x40, 256 (pci_read_config(parent, 0x40, 4) & 257 ~(0xff << offset)) | 258 (piotimings[ata_mode2idx(piomode)] << offset), 4); 259 return (mode); 260} 261 262ATA_DECLARE_DRIVER(ata_ati); 263MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1); 264