if_ale.c revision 233688
1184870Syongari/*- 2184870Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3184870Syongari * All rights reserved. 4184870Syongari * 5184870Syongari * Redistribution and use in source and binary forms, with or without 6184870Syongari * modification, are permitted provided that the following conditions 7184870Syongari * are met: 8184870Syongari * 1. Redistributions of source code must retain the above copyright 9184870Syongari * notice unmodified, this list of conditions, and the following 10184870Syongari * disclaimer. 11184870Syongari * 2. Redistributions in binary form must reproduce the above copyright 12184870Syongari * notice, this list of conditions and the following disclaimer in the 13184870Syongari * documentation and/or other materials provided with the distribution. 14184870Syongari * 15184870Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16184870Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17184870Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18184870Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19184870Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20184870Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21184870Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22184870Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23184870Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24184870Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25184870Syongari * SUCH DAMAGE. 26184870Syongari */ 27184870Syongari 28184870Syongari/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29184870Syongari 30184870Syongari#include <sys/cdefs.h> 31184870Syongari__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 233688 2012-03-30 04:46:39Z yongari $"); 32184870Syongari 33184870Syongari#include <sys/param.h> 34184870Syongari#include <sys/systm.h> 35184870Syongari#include <sys/bus.h> 36184870Syongari#include <sys/endian.h> 37184870Syongari#include <sys/kernel.h> 38184870Syongari#include <sys/malloc.h> 39184870Syongari#include <sys/mbuf.h> 40184870Syongari#include <sys/module.h> 41184870Syongari#include <sys/rman.h> 42184870Syongari#include <sys/queue.h> 43184870Syongari#include <sys/socket.h> 44184870Syongari#include <sys/sockio.h> 45184870Syongari#include <sys/sysctl.h> 46184870Syongari#include <sys/taskqueue.h> 47184870Syongari 48184870Syongari#include <net/bpf.h> 49184870Syongari#include <net/if.h> 50184870Syongari#include <net/if_arp.h> 51184870Syongari#include <net/ethernet.h> 52184870Syongari#include <net/if_dl.h> 53184870Syongari#include <net/if_llc.h> 54184870Syongari#include <net/if_media.h> 55184870Syongari#include <net/if_types.h> 56184870Syongari#include <net/if_vlan_var.h> 57184870Syongari 58184870Syongari#include <netinet/in.h> 59184870Syongari#include <netinet/in_systm.h> 60184870Syongari#include <netinet/ip.h> 61184870Syongari#include <netinet/tcp.h> 62184870Syongari 63184870Syongari#include <dev/mii/mii.h> 64184870Syongari#include <dev/mii/miivar.h> 65184870Syongari 66184870Syongari#include <dev/pci/pcireg.h> 67184870Syongari#include <dev/pci/pcivar.h> 68184870Syongari 69184870Syongari#include <machine/bus.h> 70184870Syongari#include <machine/in_cksum.h> 71184870Syongari 72184870Syongari#include <dev/ale/if_alereg.h> 73184870Syongari#include <dev/ale/if_alevar.h> 74184870Syongari 75184870Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 76184870Syongari#include "miibus_if.h" 77184870Syongari 78184870Syongari/* For more information about Tx checksum offload issues see ale_encap(). */ 79184870Syongari#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 80184870Syongari 81184870SyongariMODULE_DEPEND(ale, pci, 1, 1, 1); 82184870SyongariMODULE_DEPEND(ale, ether, 1, 1, 1); 83184870SyongariMODULE_DEPEND(ale, miibus, 1, 1, 1); 84184870Syongari 85184870Syongari/* Tunables. */ 86184870Syongaristatic int msi_disable = 0; 87184870Syongaristatic int msix_disable = 0; 88184870SyongariTUNABLE_INT("hw.ale.msi_disable", &msi_disable); 89184870SyongariTUNABLE_INT("hw.ale.msix_disable", &msix_disable); 90184870Syongari 91184870Syongari/* 92184870Syongari * Devices supported by this driver. 93184870Syongari */ 94184870Syongaristatic struct ale_dev { 95184870Syongari uint16_t ale_vendorid; 96184870Syongari uint16_t ale_deviceid; 97184870Syongari const char *ale_name; 98184870Syongari} ale_devs[] = { 99184870Syongari { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 100184870Syongari "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 101184870Syongari}; 102184870Syongari 103184870Syongaristatic int ale_attach(device_t); 104184870Syongaristatic int ale_check_boundary(struct ale_softc *); 105184870Syongaristatic int ale_detach(device_t); 106184870Syongaristatic int ale_dma_alloc(struct ale_softc *); 107184870Syongaristatic void ale_dma_free(struct ale_softc *); 108184870Syongaristatic void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109184870Syongaristatic int ale_encap(struct ale_softc *, struct mbuf **); 110184870Syongaristatic void ale_get_macaddr(struct ale_softc *); 111184870Syongaristatic void ale_init(void *); 112184870Syongaristatic void ale_init_locked(struct ale_softc *); 113184870Syongaristatic void ale_init_rx_pages(struct ale_softc *); 114184870Syongaristatic void ale_init_tx_ring(struct ale_softc *); 115184870Syongaristatic void ale_int_task(void *, int); 116184870Syongaristatic int ale_intr(void *); 117184870Syongaristatic int ale_ioctl(struct ifnet *, u_long, caddr_t); 118184870Syongaristatic void ale_mac_config(struct ale_softc *); 119184870Syongaristatic int ale_miibus_readreg(device_t, int, int); 120184870Syongaristatic void ale_miibus_statchg(device_t); 121184870Syongaristatic int ale_miibus_writereg(device_t, int, int, int); 122184870Syongaristatic int ale_mediachange(struct ifnet *); 123184870Syongaristatic void ale_mediastatus(struct ifnet *, struct ifmediareq *); 124184870Syongaristatic void ale_phy_reset(struct ale_softc *); 125184870Syongaristatic int ale_probe(device_t); 126184870Syongaristatic void ale_reset(struct ale_softc *); 127184870Syongaristatic int ale_resume(device_t); 128184870Syongaristatic void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 129184870Syongari uint32_t, uint32_t *); 130184870Syongaristatic void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 131184870Syongaristatic int ale_rxeof(struct ale_softc *sc, int); 132184870Syongaristatic void ale_rxfilter(struct ale_softc *); 133184870Syongaristatic void ale_rxvlan(struct ale_softc *); 134184870Syongaristatic void ale_setlinkspeed(struct ale_softc *); 135184870Syongaristatic void ale_setwol(struct ale_softc *); 136184870Syongaristatic int ale_shutdown(device_t); 137184870Syongaristatic void ale_start(struct ifnet *); 138216925Sjhbstatic void ale_start_locked(struct ifnet *); 139184870Syongaristatic void ale_stats_clear(struct ale_softc *); 140184870Syongaristatic void ale_stats_update(struct ale_softc *); 141184870Syongaristatic void ale_stop(struct ale_softc *); 142184870Syongaristatic void ale_stop_mac(struct ale_softc *); 143184870Syongaristatic int ale_suspend(device_t); 144184870Syongaristatic void ale_sysctl_node(struct ale_softc *); 145184870Syongaristatic void ale_tick(void *); 146184870Syongaristatic void ale_txeof(struct ale_softc *); 147184870Syongaristatic void ale_watchdog(struct ale_softc *); 148184870Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 149184870Syongaristatic int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 150184870Syongaristatic int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 151184870Syongari 152184870Syongaristatic device_method_t ale_methods[] = { 153184870Syongari /* Device interface. */ 154184870Syongari DEVMETHOD(device_probe, ale_probe), 155184870Syongari DEVMETHOD(device_attach, ale_attach), 156184870Syongari DEVMETHOD(device_detach, ale_detach), 157184870Syongari DEVMETHOD(device_shutdown, ale_shutdown), 158184870Syongari DEVMETHOD(device_suspend, ale_suspend), 159184870Syongari DEVMETHOD(device_resume, ale_resume), 160184870Syongari 161184870Syongari /* MII interface. */ 162184870Syongari DEVMETHOD(miibus_readreg, ale_miibus_readreg), 163184870Syongari DEVMETHOD(miibus_writereg, ale_miibus_writereg), 164184870Syongari DEVMETHOD(miibus_statchg, ale_miibus_statchg), 165184870Syongari 166184870Syongari { NULL, NULL } 167184870Syongari}; 168184870Syongari 169184870Syongaristatic driver_t ale_driver = { 170184870Syongari "ale", 171184870Syongari ale_methods, 172184870Syongari sizeof(struct ale_softc) 173184870Syongari}; 174184870Syongari 175184870Syongaristatic devclass_t ale_devclass; 176184870Syongari 177184870SyongariDRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0); 178184870SyongariDRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 179184870Syongari 180184870Syongaristatic struct resource_spec ale_res_spec_mem[] = { 181184870Syongari { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 182184870Syongari { -1, 0, 0 } 183184870Syongari}; 184184870Syongari 185184870Syongaristatic struct resource_spec ale_irq_spec_legacy[] = { 186184870Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 187184870Syongari { -1, 0, 0 } 188184870Syongari}; 189184870Syongari 190184870Syongaristatic struct resource_spec ale_irq_spec_msi[] = { 191184870Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 192184870Syongari { -1, 0, 0 } 193184870Syongari}; 194184870Syongari 195184870Syongaristatic struct resource_spec ale_irq_spec_msix[] = { 196184870Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 197184870Syongari { -1, 0, 0 } 198184870Syongari}; 199184870Syongari 200184870Syongaristatic int 201184870Syongariale_miibus_readreg(device_t dev, int phy, int reg) 202184870Syongari{ 203184870Syongari struct ale_softc *sc; 204184870Syongari uint32_t v; 205184870Syongari int i; 206184870Syongari 207184870Syongari sc = device_get_softc(dev); 208184870Syongari 209184870Syongari CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 210184870Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 211184870Syongari for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 212184870Syongari DELAY(5); 213184870Syongari v = CSR_READ_4(sc, ALE_MDIO); 214184870Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 215184870Syongari break; 216184870Syongari } 217184870Syongari 218184870Syongari if (i == 0) { 219184870Syongari device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 220184870Syongari return (0); 221184870Syongari } 222184870Syongari 223184870Syongari return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 224184870Syongari} 225184870Syongari 226184870Syongaristatic int 227184870Syongariale_miibus_writereg(device_t dev, int phy, int reg, int val) 228184870Syongari{ 229184870Syongari struct ale_softc *sc; 230184870Syongari uint32_t v; 231184870Syongari int i; 232184870Syongari 233184870Syongari sc = device_get_softc(dev); 234184870Syongari 235184870Syongari CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 236184870Syongari (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 237184870Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 238184870Syongari for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 239184870Syongari DELAY(5); 240184870Syongari v = CSR_READ_4(sc, ALE_MDIO); 241184870Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 242184870Syongari break; 243184870Syongari } 244184870Syongari 245184870Syongari if (i == 0) 246184870Syongari device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 247184870Syongari 248184870Syongari return (0); 249184870Syongari} 250184870Syongari 251184870Syongaristatic void 252184870Syongariale_miibus_statchg(device_t dev) 253184870Syongari{ 254184870Syongari struct ale_softc *sc; 255233688Syongari struct mii_data *mii; 256233688Syongari struct ifnet *ifp; 257233688Syongari uint32_t reg; 258184870Syongari 259184870Syongari sc = device_get_softc(dev); 260233688Syongari mii = device_get_softc(sc->ale_miibus); 261233688Syongari ifp = sc->ale_ifp; 262233688Syongari if (mii == NULL || ifp == NULL || 263233688Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 264233688Syongari return; 265184870Syongari 266233688Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 267233688Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 268233688Syongari (IFM_ACTIVE | IFM_AVALID)) { 269233688Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 270233688Syongari case IFM_10_T: 271233688Syongari case IFM_100_TX: 272233688Syongari sc->ale_flags |= ALE_FLAG_LINK; 273233688Syongari break; 274233688Syongari case IFM_1000_T: 275233688Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 276233688Syongari sc->ale_flags |= ALE_FLAG_LINK; 277233688Syongari break; 278233688Syongari default: 279233688Syongari break; 280233688Syongari } 281233688Syongari } 282233688Syongari 283233688Syongari /* Stop Rx/Tx MACs. */ 284233688Syongari ale_stop_mac(sc); 285233688Syongari 286233688Syongari /* Program MACs with resolved speed/duplex/flow-control. */ 287233688Syongari if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 288233688Syongari ale_mac_config(sc); 289233688Syongari /* Reenable Tx/Rx MACs. */ 290233688Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 291233688Syongari reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 292233688Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 293233688Syongari } 294184870Syongari} 295184870Syongari 296184870Syongaristatic void 297184870Syongariale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 298184870Syongari{ 299184870Syongari struct ale_softc *sc; 300184870Syongari struct mii_data *mii; 301184870Syongari 302184870Syongari sc = ifp->if_softc; 303184870Syongari ALE_LOCK(sc); 304184870Syongari mii = device_get_softc(sc->ale_miibus); 305184870Syongari 306184870Syongari mii_pollstat(mii); 307184870Syongari ifmr->ifm_status = mii->mii_media_status; 308184870Syongari ifmr->ifm_active = mii->mii_media_active; 309226478Syongari ALE_UNLOCK(sc); 310184870Syongari} 311184870Syongari 312184870Syongaristatic int 313184870Syongariale_mediachange(struct ifnet *ifp) 314184870Syongari{ 315184870Syongari struct ale_softc *sc; 316184870Syongari struct mii_data *mii; 317184870Syongari struct mii_softc *miisc; 318184870Syongari int error; 319184870Syongari 320184870Syongari sc = ifp->if_softc; 321184870Syongari ALE_LOCK(sc); 322184870Syongari mii = device_get_softc(sc->ale_miibus); 323221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 324221407Smarius PHY_RESET(miisc); 325184870Syongari error = mii_mediachg(mii); 326184870Syongari ALE_UNLOCK(sc); 327184870Syongari 328184870Syongari return (error); 329184870Syongari} 330184870Syongari 331184870Syongaristatic int 332184870Syongariale_probe(device_t dev) 333184870Syongari{ 334184870Syongari struct ale_dev *sp; 335184870Syongari int i; 336184870Syongari uint16_t vendor, devid; 337184870Syongari 338184870Syongari vendor = pci_get_vendor(dev); 339184870Syongari devid = pci_get_device(dev); 340184870Syongari sp = ale_devs; 341184870Syongari for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 342184870Syongari if (vendor == sp->ale_vendorid && 343184870Syongari devid == sp->ale_deviceid) { 344184870Syongari device_set_desc(dev, sp->ale_name); 345184870Syongari return (BUS_PROBE_DEFAULT); 346184870Syongari } 347184870Syongari sp++; 348184870Syongari } 349184870Syongari 350184870Syongari return (ENXIO); 351184870Syongari} 352184870Syongari 353184870Syongaristatic void 354184870Syongariale_get_macaddr(struct ale_softc *sc) 355184870Syongari{ 356184870Syongari uint32_t ea[2], reg; 357184870Syongari int i, vpdc; 358184870Syongari 359184870Syongari reg = CSR_READ_4(sc, ALE_SPI_CTRL); 360184870Syongari if ((reg & SPI_VPD_ENB) != 0) { 361184870Syongari reg &= ~SPI_VPD_ENB; 362184870Syongari CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 363184870Syongari } 364184870Syongari 365219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 366184870Syongari /* 367184870Syongari * PCI VPD capability found, let TWSI reload EEPROM. 368184870Syongari * This will set ethernet address of controller. 369184870Syongari */ 370184870Syongari CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 371184870Syongari TWSI_CTRL_SW_LD_START); 372184870Syongari for (i = 100; i > 0; i--) { 373184870Syongari DELAY(1000); 374184870Syongari reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 375184870Syongari if ((reg & TWSI_CTRL_SW_LD_START) == 0) 376184870Syongari break; 377184870Syongari } 378184870Syongari if (i == 0) 379184870Syongari device_printf(sc->ale_dev, 380184870Syongari "reloading EEPROM timeout!\n"); 381184870Syongari } else { 382184870Syongari if (bootverbose) 383184870Syongari device_printf(sc->ale_dev, 384184870Syongari "PCI VPD capability not found!\n"); 385184870Syongari } 386184870Syongari 387184870Syongari ea[0] = CSR_READ_4(sc, ALE_PAR0); 388184870Syongari ea[1] = CSR_READ_4(sc, ALE_PAR1); 389184870Syongari sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 390184870Syongari sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 391184870Syongari sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 392184870Syongari sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 393184870Syongari sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 394184870Syongari sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 395184870Syongari} 396184870Syongari 397184870Syongaristatic void 398184870Syongariale_phy_reset(struct ale_softc *sc) 399184870Syongari{ 400184870Syongari 401184870Syongari /* Reset magic from Linux. */ 402184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 403184870Syongari GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 404184870Syongari GPHY_CTRL_PHY_PLL_ON); 405184870Syongari DELAY(1000); 406184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 407184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 408184870Syongari GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 409184870Syongari DELAY(1000); 410185576Syongari 411185576Syongari#define ATPHY_DBG_ADDR 0x1D 412185576Syongari#define ATPHY_DBG_DATA 0x1E 413185576Syongari 414185576Syongari /* Enable hibernation mode. */ 415185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 416185576Syongari ATPHY_DBG_ADDR, 0x0B); 417185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 418185576Syongari ATPHY_DBG_DATA, 0xBC00); 419185576Syongari /* Set Class A/B for all modes. */ 420185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 421185576Syongari ATPHY_DBG_ADDR, 0x00); 422185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423185576Syongari ATPHY_DBG_DATA, 0x02EF); 424185576Syongari /* Enable 10BT power saving. */ 425185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 426185576Syongari ATPHY_DBG_ADDR, 0x12); 427185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 428185576Syongari ATPHY_DBG_DATA, 0x4C04); 429185576Syongari /* Adjust 1000T power. */ 430185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 431185576Syongari ATPHY_DBG_ADDR, 0x04); 432185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 433185576Syongari ATPHY_DBG_ADDR, 0x8BBB); 434185576Syongari /* 10BT center tap voltage. */ 435185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 436185576Syongari ATPHY_DBG_ADDR, 0x05); 437185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 438185576Syongari ATPHY_DBG_ADDR, 0x2C46); 439185576Syongari 440185576Syongari#undef ATPHY_DBG_ADDR 441185576Syongari#undef ATPHY_DBG_DATA 442185576Syongari DELAY(1000); 443184870Syongari} 444184870Syongari 445184870Syongaristatic int 446184870Syongariale_attach(device_t dev) 447184870Syongari{ 448184870Syongari struct ale_softc *sc; 449184870Syongari struct ifnet *ifp; 450184870Syongari uint16_t burst; 451184870Syongari int error, i, msic, msixc, pmc; 452184870Syongari uint32_t rxf_len, txf_len; 453184870Syongari 454184870Syongari error = 0; 455184870Syongari sc = device_get_softc(dev); 456184870Syongari sc->ale_dev = dev; 457184870Syongari 458184870Syongari mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 459184870Syongari MTX_DEF); 460184870Syongari callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 461184870Syongari TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 462184870Syongari 463184870Syongari /* Map the device. */ 464184870Syongari pci_enable_busmaster(dev); 465184870Syongari sc->ale_res_spec = ale_res_spec_mem; 466184870Syongari sc->ale_irq_spec = ale_irq_spec_legacy; 467184870Syongari error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 468184870Syongari if (error != 0) { 469184870Syongari device_printf(dev, "cannot allocate memory resources.\n"); 470184870Syongari goto fail; 471184870Syongari } 472184870Syongari 473184870Syongari /* Set PHY address. */ 474184870Syongari sc->ale_phyaddr = ALE_PHY_ADDR; 475184870Syongari 476184870Syongari /* Reset PHY. */ 477184870Syongari ale_phy_reset(sc); 478184870Syongari 479184870Syongari /* Reset the ethernet controller. */ 480184870Syongari ale_reset(sc); 481184870Syongari 482184870Syongari /* Get PCI and chip id/revision. */ 483184870Syongari sc->ale_rev = pci_get_revid(dev); 484184870Syongari if (sc->ale_rev >= 0xF0) { 485184870Syongari /* L2E Rev. B. AR8114 */ 486184870Syongari sc->ale_flags |= ALE_FLAG_FASTETHER; 487184870Syongari } else { 488184870Syongari if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 489184870Syongari /* L1E AR8121 */ 490184870Syongari sc->ale_flags |= ALE_FLAG_JUMBO; 491184870Syongari } else { 492184870Syongari /* L2E Rev. A. AR8113 */ 493184870Syongari sc->ale_flags |= ALE_FLAG_FASTETHER; 494184870Syongari } 495184870Syongari } 496184870Syongari /* 497184870Syongari * All known controllers seems to require 4 bytes alignment 498184870Syongari * of Tx buffers to make Tx checksum offload with custom 499184870Syongari * checksum generation method work. 500184870Syongari */ 501184870Syongari sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 502184870Syongari /* 503184870Syongari * All known controllers seems to have issues on Rx checksum 504184870Syongari * offload for fragmented IP datagrams. 505184870Syongari */ 506184870Syongari sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 507184870Syongari /* 508184870Syongari * Don't use Tx CMB. It is known to cause RRS update failure 509184870Syongari * under certain circumstances. Typical phenomenon of the 510184870Syongari * issue would be unexpected sequence number encountered in 511184870Syongari * Rx handler. 512184870Syongari */ 513184870Syongari sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 514184870Syongari sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 515184870Syongari MASTER_CHIP_REV_SHIFT; 516184870Syongari if (bootverbose) { 517184870Syongari device_printf(dev, "PCI device revision : 0x%04x\n", 518184870Syongari sc->ale_rev); 519184870Syongari device_printf(dev, "Chip id/revision : 0x%04x\n", 520184870Syongari sc->ale_chip_rev); 521184870Syongari } 522184870Syongari txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 523184870Syongari rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 524184870Syongari /* 525184870Syongari * Uninitialized hardware returns an invalid chip id/revision 526184870Syongari * as well as 0xFFFFFFFF for Tx/Rx fifo length. 527184870Syongari */ 528184870Syongari if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 529184870Syongari rxf_len == 0xFFFFFFF) { 530184870Syongari device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 531184870Syongari "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 532184870Syongari txf_len, rxf_len); 533184870Syongari error = ENXIO; 534184870Syongari goto fail; 535184870Syongari } 536184870Syongari device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 537184870Syongari 538184870Syongari /* Allocate IRQ resources. */ 539184870Syongari msixc = pci_msix_count(dev); 540184870Syongari msic = pci_msi_count(dev); 541184870Syongari if (bootverbose) { 542184870Syongari device_printf(dev, "MSIX count : %d\n", msixc); 543184870Syongari device_printf(dev, "MSI count : %d\n", msic); 544184870Syongari } 545184870Syongari 546184870Syongari /* Prefer MSIX over MSI. */ 547184870Syongari if (msix_disable == 0 || msi_disable == 0) { 548184870Syongari if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 549184870Syongari pci_alloc_msix(dev, &msixc) == 0) { 550184870Syongari if (msic == ALE_MSIX_MESSAGES) { 551184870Syongari device_printf(dev, "Using %d MSIX messages.\n", 552184870Syongari msixc); 553184870Syongari sc->ale_flags |= ALE_FLAG_MSIX; 554184870Syongari sc->ale_irq_spec = ale_irq_spec_msix; 555184870Syongari } else 556184870Syongari pci_release_msi(dev); 557184870Syongari } 558184870Syongari if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 559184870Syongari msic == ALE_MSI_MESSAGES && 560184870Syongari pci_alloc_msi(dev, &msic) == 0) { 561184870Syongari if (msic == ALE_MSI_MESSAGES) { 562184870Syongari device_printf(dev, "Using %d MSI messages.\n", 563184870Syongari msic); 564184870Syongari sc->ale_flags |= ALE_FLAG_MSI; 565184870Syongari sc->ale_irq_spec = ale_irq_spec_msi; 566184870Syongari } else 567184870Syongari pci_release_msi(dev); 568184870Syongari } 569184870Syongari } 570184870Syongari 571184870Syongari error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 572184870Syongari if (error != 0) { 573184870Syongari device_printf(dev, "cannot allocate IRQ resources.\n"); 574184870Syongari goto fail; 575184870Syongari } 576184870Syongari 577184870Syongari /* Get DMA parameters from PCIe device control register. */ 578219902Sjhb if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 579184870Syongari sc->ale_flags |= ALE_FLAG_PCIE; 580184870Syongari burst = pci_read_config(dev, i + 0x08, 2); 581184870Syongari /* Max read request size. */ 582184870Syongari sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 583184870Syongari DMA_CFG_RD_BURST_SHIFT; 584184870Syongari /* Max payload size. */ 585184870Syongari sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 586184870Syongari DMA_CFG_WR_BURST_SHIFT; 587184870Syongari if (bootverbose) { 588184870Syongari device_printf(dev, "Read request size : %d bytes.\n", 589184870Syongari 128 << ((burst >> 12) & 0x07)); 590184870Syongari device_printf(dev, "TLP payload size : %d bytes.\n", 591184870Syongari 128 << ((burst >> 5) & 0x07)); 592184870Syongari } 593184870Syongari } else { 594184870Syongari sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 595184870Syongari sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 596184870Syongari } 597184870Syongari 598184870Syongari /* Create device sysctl node. */ 599184870Syongari ale_sysctl_node(sc); 600184870Syongari 601184870Syongari if ((error = ale_dma_alloc(sc) != 0)) 602184870Syongari goto fail; 603184870Syongari 604184870Syongari /* Load station address. */ 605184870Syongari ale_get_macaddr(sc); 606184870Syongari 607184870Syongari ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 608184870Syongari if (ifp == NULL) { 609184870Syongari device_printf(dev, "cannot allocate ifnet structure.\n"); 610184870Syongari error = ENXIO; 611184870Syongari goto fail; 612184870Syongari } 613184870Syongari 614184870Syongari ifp->if_softc = sc; 615184870Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 616184870Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 617184870Syongari ifp->if_ioctl = ale_ioctl; 618184870Syongari ifp->if_start = ale_start; 619184870Syongari ifp->if_init = ale_init; 620184870Syongari ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 621184870Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 622184870Syongari IFQ_SET_READY(&ifp->if_snd); 623184870Syongari ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 624184870Syongari ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 625219902Sjhb if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 626184870Syongari sc->ale_flags |= ALE_FLAG_PMCAP; 627184870Syongari ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 628184870Syongari } 629184870Syongari ifp->if_capenable = ifp->if_capabilities; 630184870Syongari 631184870Syongari /* Set up MII bus. */ 632213893Smarius error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 633213893Smarius ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 634213893Smarius 0); 635213893Smarius if (error != 0) { 636213893Smarius device_printf(dev, "attaching PHYs failed\n"); 637184870Syongari goto fail; 638184870Syongari } 639184870Syongari 640184870Syongari ether_ifattach(ifp, sc->ale_eaddr); 641184870Syongari 642184870Syongari /* VLAN capability setup. */ 643204378Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 644204378Syongari IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 645184870Syongari ifp->if_capenable = ifp->if_capabilities; 646195153Syongari /* 647195153Syongari * Even though controllers supported by ale(3) have Rx checksum 648195153Syongari * offload bug the workaround for fragmented frames seemed to 649195153Syongari * work so far. However it seems Rx checksum offload does not 650195153Syongari * work under certain conditions. So disable Rx checksum offload 651195153Syongari * until I find more clue about it but allow users to override it. 652195153Syongari */ 653195153Syongari ifp->if_capenable &= ~IFCAP_RXCSUM; 654184870Syongari 655184870Syongari /* Tell the upper layer(s) we support long frames. */ 656184870Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 657184870Syongari 658184870Syongari /* Create local taskq. */ 659184870Syongari sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 660184870Syongari taskqueue_thread_enqueue, &sc->ale_tq); 661184870Syongari if (sc->ale_tq == NULL) { 662184870Syongari device_printf(dev, "could not create taskqueue.\n"); 663184870Syongari ether_ifdetach(ifp); 664184870Syongari error = ENXIO; 665184870Syongari goto fail; 666184870Syongari } 667184870Syongari taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 668184870Syongari device_get_nameunit(sc->ale_dev)); 669184870Syongari 670184870Syongari if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 671184870Syongari msic = ALE_MSIX_MESSAGES; 672184870Syongari else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 673184870Syongari msic = ALE_MSI_MESSAGES; 674184870Syongari else 675184870Syongari msic = 1; 676184870Syongari for (i = 0; i < msic; i++) { 677184870Syongari error = bus_setup_intr(dev, sc->ale_irq[i], 678184870Syongari INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 679184870Syongari &sc->ale_intrhand[i]); 680184870Syongari if (error != 0) 681184870Syongari break; 682184870Syongari } 683184870Syongari if (error != 0) { 684184870Syongari device_printf(dev, "could not set up interrupt handler.\n"); 685184870Syongari taskqueue_free(sc->ale_tq); 686184870Syongari sc->ale_tq = NULL; 687184870Syongari ether_ifdetach(ifp); 688184870Syongari goto fail; 689184870Syongari } 690184870Syongari 691184870Syongarifail: 692184870Syongari if (error != 0) 693184870Syongari ale_detach(dev); 694184870Syongari 695184870Syongari return (error); 696184870Syongari} 697184870Syongari 698184870Syongaristatic int 699184870Syongariale_detach(device_t dev) 700184870Syongari{ 701184870Syongari struct ale_softc *sc; 702184870Syongari struct ifnet *ifp; 703184870Syongari int i, msic; 704184870Syongari 705184870Syongari sc = device_get_softc(dev); 706184870Syongari 707184870Syongari ifp = sc->ale_ifp; 708184870Syongari if (device_is_attached(dev)) { 709217542Sjhb ether_ifdetach(ifp); 710184870Syongari ALE_LOCK(sc); 711184870Syongari ale_stop(sc); 712184870Syongari ALE_UNLOCK(sc); 713184870Syongari callout_drain(&sc->ale_tick_ch); 714184870Syongari taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 715184870Syongari } 716184870Syongari 717184870Syongari if (sc->ale_tq != NULL) { 718184870Syongari taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 719184870Syongari taskqueue_free(sc->ale_tq); 720184870Syongari sc->ale_tq = NULL; 721184870Syongari } 722184870Syongari 723184870Syongari if (sc->ale_miibus != NULL) { 724184870Syongari device_delete_child(dev, sc->ale_miibus); 725184870Syongari sc->ale_miibus = NULL; 726184870Syongari } 727184870Syongari bus_generic_detach(dev); 728184870Syongari ale_dma_free(sc); 729184870Syongari 730184870Syongari if (ifp != NULL) { 731184870Syongari if_free(ifp); 732184870Syongari sc->ale_ifp = NULL; 733184870Syongari } 734184870Syongari 735184870Syongari if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 736184870Syongari msic = ALE_MSIX_MESSAGES; 737184870Syongari else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 738184870Syongari msic = ALE_MSI_MESSAGES; 739184870Syongari else 740184870Syongari msic = 1; 741184870Syongari for (i = 0; i < msic; i++) { 742184870Syongari if (sc->ale_intrhand[i] != NULL) { 743184870Syongari bus_teardown_intr(dev, sc->ale_irq[i], 744184870Syongari sc->ale_intrhand[i]); 745184870Syongari sc->ale_intrhand[i] = NULL; 746184870Syongari } 747184870Syongari } 748184870Syongari 749184870Syongari bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 750184870Syongari if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 751184870Syongari pci_release_msi(dev); 752184870Syongari bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 753184870Syongari mtx_destroy(&sc->ale_mtx); 754184870Syongari 755184870Syongari return (0); 756184870Syongari} 757184870Syongari 758184870Syongari#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 759184870Syongari SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 760184870Syongari 761217323Smdf#if __FreeBSD_version >= 900030 762184870Syongari#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 763217323Smdf SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 764217323Smdf#elif __FreeBSD_version > 800000 765217323Smdf#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 766184870Syongari SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 767184870Syongari#else 768184870Syongari#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 769184870Syongari SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 770184870Syongari#endif 771184870Syongari 772184870Syongaristatic void 773184870Syongariale_sysctl_node(struct ale_softc *sc) 774184870Syongari{ 775184870Syongari struct sysctl_ctx_list *ctx; 776184870Syongari struct sysctl_oid_list *child, *parent; 777184870Syongari struct sysctl_oid *tree; 778184870Syongari struct ale_hw_stats *stats; 779184870Syongari int error; 780184870Syongari 781184870Syongari stats = &sc->ale_stats; 782184870Syongari ctx = device_get_sysctl_ctx(sc->ale_dev); 783184870Syongari child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 784184870Syongari 785184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 786184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 787184870Syongari sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 788184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 789184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 790184870Syongari sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 791184870Syongari /* Pull in device tunables. */ 792184870Syongari sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 793184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 794184870Syongari device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 795184870Syongari if (error == 0) { 796184870Syongari if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 797184870Syongari sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 798184870Syongari device_printf(sc->ale_dev, "int_rx_mod value out of " 799184870Syongari "range; using default: %d\n", 800184870Syongari ALE_IM_RX_TIMER_DEFAULT); 801184870Syongari sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 802184870Syongari } 803184870Syongari } 804184870Syongari sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 805184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 806184870Syongari device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 807184870Syongari if (error == 0) { 808184870Syongari if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 809184870Syongari sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 810184870Syongari device_printf(sc->ale_dev, "int_tx_mod value out of " 811184870Syongari "range; using default: %d\n", 812184870Syongari ALE_IM_TX_TIMER_DEFAULT); 813184870Syongari sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 814184870Syongari } 815184870Syongari } 816184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 817184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 818184870Syongari sysctl_hw_ale_proc_limit, "I", 819184870Syongari "max number of Rx events to process"); 820184870Syongari /* Pull in device tunables. */ 821184870Syongari sc->ale_process_limit = ALE_PROC_DEFAULT; 822184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 823184870Syongari device_get_unit(sc->ale_dev), "process_limit", 824184870Syongari &sc->ale_process_limit); 825184870Syongari if (error == 0) { 826184870Syongari if (sc->ale_process_limit < ALE_PROC_MIN || 827184870Syongari sc->ale_process_limit > ALE_PROC_MAX) { 828184870Syongari device_printf(sc->ale_dev, 829184870Syongari "process_limit value out of range; " 830184870Syongari "using default: %d\n", ALE_PROC_DEFAULT); 831184870Syongari sc->ale_process_limit = ALE_PROC_DEFAULT; 832184870Syongari } 833184870Syongari } 834184870Syongari 835184870Syongari /* Misc statistics. */ 836184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 837184870Syongari &stats->reset_brk_seq, 838184870Syongari "Controller resets due to broken Rx sequnce number"); 839184870Syongari 840184870Syongari tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 841184870Syongari NULL, "ATE statistics"); 842184870Syongari parent = SYSCTL_CHILDREN(tree); 843184870Syongari 844184870Syongari /* Rx statistics. */ 845184870Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 846184870Syongari NULL, "Rx MAC statistics"); 847184870Syongari child = SYSCTL_CHILDREN(tree); 848184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 849184870Syongari &stats->rx_frames, "Good frames"); 850184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 851184870Syongari &stats->rx_bcast_frames, "Good broadcast frames"); 852184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 853184870Syongari &stats->rx_mcast_frames, "Good multicast frames"); 854184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 855184870Syongari &stats->rx_pause_frames, "Pause control frames"); 856184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 857184870Syongari &stats->rx_control_frames, "Control frames"); 858184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 859184870Syongari &stats->rx_crcerrs, "CRC errors"); 860184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 861184870Syongari &stats->rx_lenerrs, "Frames with length mismatched"); 862184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 863184870Syongari &stats->rx_bytes, "Good octets"); 864184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 865184870Syongari &stats->rx_bcast_bytes, "Good broadcast octets"); 866184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 867184870Syongari &stats->rx_mcast_bytes, "Good multicast octets"); 868184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 869184870Syongari &stats->rx_runts, "Too short frames"); 870184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 871184870Syongari &stats->rx_fragments, "Fragmented frames"); 872184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 873184870Syongari &stats->rx_pkts_64, "64 bytes frames"); 874184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 875184870Syongari &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 876184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 877184870Syongari &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 878184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 879184870Syongari &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 880184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 881184870Syongari &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 882184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 883184870Syongari &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 884184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 885184870Syongari &stats->rx_pkts_1519_max, "1519 to max frames"); 886184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 887184870Syongari &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 888184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 889184870Syongari &stats->rx_fifo_oflows, "FIFO overflows"); 890184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 891184870Syongari &stats->rx_rrs_errs, "Return status write-back errors"); 892184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 893184870Syongari &stats->rx_alignerrs, "Alignment errors"); 894184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 895184870Syongari &stats->rx_pkts_filtered, 896184870Syongari "Frames dropped due to address filtering"); 897184870Syongari 898184870Syongari /* Tx statistics. */ 899184870Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 900184870Syongari NULL, "Tx MAC statistics"); 901184870Syongari child = SYSCTL_CHILDREN(tree); 902184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 903184870Syongari &stats->tx_frames, "Good frames"); 904184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 905184870Syongari &stats->tx_bcast_frames, "Good broadcast frames"); 906184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 907184870Syongari &stats->tx_mcast_frames, "Good multicast frames"); 908184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 909184870Syongari &stats->tx_pause_frames, "Pause control frames"); 910184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 911184870Syongari &stats->tx_control_frames, "Control frames"); 912184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 913184870Syongari &stats->tx_excess_defer, "Frames with excessive derferrals"); 914184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 915184870Syongari &stats->tx_excess_defer, "Frames with derferrals"); 916184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 917184870Syongari &stats->tx_bytes, "Good octets"); 918184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 919184870Syongari &stats->tx_bcast_bytes, "Good broadcast octets"); 920184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 921184870Syongari &stats->tx_mcast_bytes, "Good multicast octets"); 922184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 923184870Syongari &stats->tx_pkts_64, "64 bytes frames"); 924184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 925184870Syongari &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 926184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 927184870Syongari &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 928184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 929184870Syongari &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 930184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 931184870Syongari &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 932184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 933184870Syongari &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 934184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 935184870Syongari &stats->tx_pkts_1519_max, "1519 to max frames"); 936184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 937184870Syongari &stats->tx_single_colls, "Single collisions"); 938184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 939184870Syongari &stats->tx_multi_colls, "Multiple collisions"); 940184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 941184870Syongari &stats->tx_late_colls, "Late collisions"); 942184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 943184870Syongari &stats->tx_excess_colls, "Excessive collisions"); 944184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 945184870Syongari &stats->tx_abort, "Aborted frames due to Excessive collisions"); 946184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 947184870Syongari &stats->tx_underrun, "FIFO underruns"); 948184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 949184870Syongari &stats->tx_desc_underrun, "Descriptor write-back errors"); 950184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 951184870Syongari &stats->tx_lenerrs, "Frames with length mismatched"); 952184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 953184870Syongari &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 954184870Syongari} 955184870Syongari 956184870Syongari#undef ALE_SYSCTL_STAT_ADD32 957184870Syongari#undef ALE_SYSCTL_STAT_ADD64 958184870Syongari 959184870Syongaristruct ale_dmamap_arg { 960184870Syongari bus_addr_t ale_busaddr; 961184870Syongari}; 962184870Syongari 963184870Syongaristatic void 964184870Syongariale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 965184870Syongari{ 966184870Syongari struct ale_dmamap_arg *ctx; 967184870Syongari 968184870Syongari if (error != 0) 969184870Syongari return; 970184870Syongari 971184870Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 972184870Syongari 973184870Syongari ctx = (struct ale_dmamap_arg *)arg; 974184870Syongari ctx->ale_busaddr = segs[0].ds_addr; 975184870Syongari} 976184870Syongari 977184870Syongari/* 978184870Syongari * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 979184870Syongari * which specifies high address region of DMA blocks. Therefore these 980184870Syongari * blocks should have the same high address of given 4GB address 981184870Syongari * space(i.e. crossing 4GB boundary is not allowed). 982184870Syongari */ 983184870Syongaristatic int 984184870Syongariale_check_boundary(struct ale_softc *sc) 985184870Syongari{ 986184870Syongari bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 987184870Syongari bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 988184870Syongari 989184870Syongari rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 990184870Syongari sc->ale_pagesize; 991184870Syongari rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 992184870Syongari sc->ale_pagesize; 993184870Syongari tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 994184870Syongari tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 995184870Syongari rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 996184870Syongari rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 997184870Syongari 998184870Syongari if ((ALE_ADDR_HI(tx_ring_end) != 999184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 1000184870Syongari (ALE_ADDR_HI(rx_page_end[0]) != 1001184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 1002184870Syongari (ALE_ADDR_HI(rx_page_end[1]) != 1003184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1004184870Syongari (ALE_ADDR_HI(tx_cmb_end) != 1005184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1006184870Syongari (ALE_ADDR_HI(rx_cmb_end[0]) != 1007184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1008184870Syongari (ALE_ADDR_HI(rx_cmb_end[1]) != 1009184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1010184870Syongari return (EFBIG); 1011184870Syongari 1012184870Syongari if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1013184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1014184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1015184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1016184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1017184870Syongari return (EFBIG); 1018184870Syongari 1019184870Syongari return (0); 1020184870Syongari} 1021184870Syongari 1022184870Syongaristatic int 1023184870Syongariale_dma_alloc(struct ale_softc *sc) 1024184870Syongari{ 1025184870Syongari struct ale_txdesc *txd; 1026184870Syongari bus_addr_t lowaddr; 1027184870Syongari struct ale_dmamap_arg ctx; 1028184870Syongari int error, guard_size, i; 1029184870Syongari 1030184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1031184870Syongari guard_size = ALE_JUMBO_FRAMELEN; 1032184870Syongari else 1033184870Syongari guard_size = ALE_MAX_FRAMELEN; 1034184870Syongari sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1035184870Syongari ALE_RX_PAGE_ALIGN); 1036184870Syongari lowaddr = BUS_SPACE_MAXADDR; 1037184870Syongariagain: 1038184870Syongari /* Create parent DMA tag. */ 1039184870Syongari error = bus_dma_tag_create( 1040184870Syongari bus_get_dma_tag(sc->ale_dev), /* parent */ 1041184870Syongari 1, 0, /* alignment, boundary */ 1042184870Syongari lowaddr, /* lowaddr */ 1043184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1044184870Syongari NULL, NULL, /* filter, filterarg */ 1045184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1046184870Syongari 0, /* nsegments */ 1047184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1048184870Syongari 0, /* flags */ 1049184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1050184870Syongari &sc->ale_cdata.ale_parent_tag); 1051184870Syongari if (error != 0) { 1052184870Syongari device_printf(sc->ale_dev, 1053184870Syongari "could not create parent DMA tag.\n"); 1054184870Syongari goto fail; 1055184870Syongari } 1056184870Syongari 1057184870Syongari /* Create DMA tag for Tx descriptor ring. */ 1058184870Syongari error = bus_dma_tag_create( 1059184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1060184870Syongari ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1061184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1062184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1063184870Syongari NULL, NULL, /* filter, filterarg */ 1064184870Syongari ALE_TX_RING_SZ, /* maxsize */ 1065184870Syongari 1, /* nsegments */ 1066184870Syongari ALE_TX_RING_SZ, /* maxsegsize */ 1067184870Syongari 0, /* flags */ 1068184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1069184870Syongari &sc->ale_cdata.ale_tx_ring_tag); 1070184870Syongari if (error != 0) { 1071184870Syongari device_printf(sc->ale_dev, 1072184870Syongari "could not create Tx ring DMA tag.\n"); 1073184870Syongari goto fail; 1074184870Syongari } 1075184870Syongari 1076184870Syongari /* Create DMA tag for Rx pages. */ 1077184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1078184870Syongari error = bus_dma_tag_create( 1079184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1080184870Syongari ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1081184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1082184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1083184870Syongari NULL, NULL, /* filter, filterarg */ 1084184870Syongari sc->ale_pagesize, /* maxsize */ 1085184870Syongari 1, /* nsegments */ 1086184870Syongari sc->ale_pagesize, /* maxsegsize */ 1087184870Syongari 0, /* flags */ 1088184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1089184870Syongari &sc->ale_cdata.ale_rx_page[i].page_tag); 1090184870Syongari if (error != 0) { 1091184870Syongari device_printf(sc->ale_dev, 1092184870Syongari "could not create Rx page %d DMA tag.\n", i); 1093184870Syongari goto fail; 1094184870Syongari } 1095184870Syongari } 1096184870Syongari 1097184870Syongari /* Create DMA tag for Tx coalescing message block. */ 1098184870Syongari error = bus_dma_tag_create( 1099184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1100184870Syongari ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1101184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1102184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1103184870Syongari NULL, NULL, /* filter, filterarg */ 1104184870Syongari ALE_TX_CMB_SZ, /* maxsize */ 1105184870Syongari 1, /* nsegments */ 1106184870Syongari ALE_TX_CMB_SZ, /* maxsegsize */ 1107184870Syongari 0, /* flags */ 1108184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1109184870Syongari &sc->ale_cdata.ale_tx_cmb_tag); 1110184870Syongari if (error != 0) { 1111184870Syongari device_printf(sc->ale_dev, 1112184870Syongari "could not create Tx CMB DMA tag.\n"); 1113184870Syongari goto fail; 1114184870Syongari } 1115184870Syongari 1116184870Syongari /* Create DMA tag for Rx coalescing message block. */ 1117184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1118184870Syongari error = bus_dma_tag_create( 1119184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1120184870Syongari ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1121184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1122184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1123184870Syongari NULL, NULL, /* filter, filterarg */ 1124184870Syongari ALE_RX_CMB_SZ, /* maxsize */ 1125184870Syongari 1, /* nsegments */ 1126184870Syongari ALE_RX_CMB_SZ, /* maxsegsize */ 1127184870Syongari 0, /* flags */ 1128184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1129184870Syongari &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1130184870Syongari if (error != 0) { 1131184870Syongari device_printf(sc->ale_dev, 1132184870Syongari "could not create Rx page %d CMB DMA tag.\n", i); 1133184870Syongari goto fail; 1134184870Syongari } 1135184870Syongari } 1136184870Syongari 1137184870Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1138184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1139184870Syongari (void **)&sc->ale_cdata.ale_tx_ring, 1140184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1141184870Syongari &sc->ale_cdata.ale_tx_ring_map); 1142184870Syongari if (error != 0) { 1143184870Syongari device_printf(sc->ale_dev, 1144184870Syongari "could not allocate DMA'able memory for Tx ring.\n"); 1145184870Syongari goto fail; 1146184870Syongari } 1147184870Syongari ctx.ale_busaddr = 0; 1148184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1149184870Syongari sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1150184870Syongari ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1151184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1152184870Syongari device_printf(sc->ale_dev, 1153184870Syongari "could not load DMA'able memory for Tx ring.\n"); 1154184870Syongari goto fail; 1155184870Syongari } 1156184870Syongari sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1157184870Syongari 1158184870Syongari /* Rx pages. */ 1159184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1160184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1161184870Syongari (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1162184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1163184870Syongari &sc->ale_cdata.ale_rx_page[i].page_map); 1164184870Syongari if (error != 0) { 1165184870Syongari device_printf(sc->ale_dev, 1166184870Syongari "could not allocate DMA'able memory for " 1167184870Syongari "Rx page %d.\n", i); 1168184870Syongari goto fail; 1169184870Syongari } 1170184870Syongari ctx.ale_busaddr = 0; 1171184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1172184870Syongari sc->ale_cdata.ale_rx_page[i].page_map, 1173184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr, 1174184870Syongari sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1175184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1176184870Syongari device_printf(sc->ale_dev, 1177184870Syongari "could not load DMA'able memory for " 1178184870Syongari "Rx page %d.\n", i); 1179184870Syongari goto fail; 1180184870Syongari } 1181184870Syongari sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1182184870Syongari } 1183184870Syongari 1184184870Syongari /* Tx CMB. */ 1185184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1186184870Syongari (void **)&sc->ale_cdata.ale_tx_cmb, 1187184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1188184870Syongari &sc->ale_cdata.ale_tx_cmb_map); 1189184870Syongari if (error != 0) { 1190184870Syongari device_printf(sc->ale_dev, 1191184870Syongari "could not allocate DMA'able memory for Tx CMB.\n"); 1192184870Syongari goto fail; 1193184870Syongari } 1194184870Syongari ctx.ale_busaddr = 0; 1195184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1196184870Syongari sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1197184870Syongari ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1198184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1199184870Syongari device_printf(sc->ale_dev, 1200184870Syongari "could not load DMA'able memory for Tx CMB.\n"); 1201184870Syongari goto fail; 1202184870Syongari } 1203184870Syongari sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1204184870Syongari 1205184870Syongari /* Rx CMB. */ 1206184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1207184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1208184870Syongari (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1209184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1210184870Syongari &sc->ale_cdata.ale_rx_page[i].cmb_map); 1211184870Syongari if (error != 0) { 1212184870Syongari device_printf(sc->ale_dev, "could not allocate " 1213184870Syongari "DMA'able memory for Rx page %d CMB.\n", i); 1214184870Syongari goto fail; 1215184870Syongari } 1216184870Syongari ctx.ale_busaddr = 0; 1217184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1218184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map, 1219184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr, 1220184870Syongari ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1221184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1222184870Syongari device_printf(sc->ale_dev, "could not load DMA'able " 1223184870Syongari "memory for Rx page %d CMB.\n", i); 1224184870Syongari goto fail; 1225184870Syongari } 1226184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1227184870Syongari } 1228184870Syongari 1229184870Syongari /* 1230184870Syongari * Tx descriptors/RXF0/CMB DMA blocks share the same 1231184870Syongari * high address region of 64bit DMA address space. 1232184870Syongari */ 1233184870Syongari if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1234184870Syongari (error = ale_check_boundary(sc)) != 0) { 1235184870Syongari device_printf(sc->ale_dev, "4GB boundary crossed, " 1236184870Syongari "switching to 32bit DMA addressing mode.\n"); 1237184870Syongari ale_dma_free(sc); 1238184870Syongari /* 1239184870Syongari * Limit max allowable DMA address space to 32bit 1240184870Syongari * and try again. 1241184870Syongari */ 1242184870Syongari lowaddr = BUS_SPACE_MAXADDR_32BIT; 1243184870Syongari goto again; 1244184870Syongari } 1245184870Syongari 1246184870Syongari /* 1247184870Syongari * Create Tx buffer parent tag. 1248184870Syongari * AR81xx allows 64bit DMA addressing of Tx buffers so it 1249184870Syongari * needs separate parent DMA tag as parent DMA address space 1250184870Syongari * could be restricted to be within 32bit address space by 1251184870Syongari * 4GB boundary crossing. 1252184870Syongari */ 1253184870Syongari error = bus_dma_tag_create( 1254184870Syongari bus_get_dma_tag(sc->ale_dev), /* parent */ 1255184870Syongari 1, 0, /* alignment, boundary */ 1256184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1257184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1258184870Syongari NULL, NULL, /* filter, filterarg */ 1259184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1260184870Syongari 0, /* nsegments */ 1261184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1262184870Syongari 0, /* flags */ 1263184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1264184870Syongari &sc->ale_cdata.ale_buffer_tag); 1265184870Syongari if (error != 0) { 1266184870Syongari device_printf(sc->ale_dev, 1267184870Syongari "could not create parent buffer DMA tag.\n"); 1268184870Syongari goto fail; 1269184870Syongari } 1270184870Syongari 1271184870Syongari /* Create DMA tag for Tx buffers. */ 1272184870Syongari error = bus_dma_tag_create( 1273184870Syongari sc->ale_cdata.ale_buffer_tag, /* parent */ 1274184870Syongari 1, 0, /* alignment, boundary */ 1275184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1276184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1277184870Syongari NULL, NULL, /* filter, filterarg */ 1278184870Syongari ALE_TSO_MAXSIZE, /* maxsize */ 1279184870Syongari ALE_MAXTXSEGS, /* nsegments */ 1280184870Syongari ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1281184870Syongari 0, /* flags */ 1282184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1283184870Syongari &sc->ale_cdata.ale_tx_tag); 1284184870Syongari if (error != 0) { 1285184870Syongari device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1286184870Syongari goto fail; 1287184870Syongari } 1288184870Syongari 1289184870Syongari /* Create DMA maps for Tx buffers. */ 1290184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 1291184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 1292184870Syongari txd->tx_m = NULL; 1293184870Syongari txd->tx_dmamap = NULL; 1294184870Syongari error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1295184870Syongari &txd->tx_dmamap); 1296184870Syongari if (error != 0) { 1297184870Syongari device_printf(sc->ale_dev, 1298184870Syongari "could not create Tx dmamap.\n"); 1299184870Syongari goto fail; 1300184870Syongari } 1301184870Syongari } 1302184870Syongari 1303184870Syongarifail: 1304184870Syongari return (error); 1305184870Syongari} 1306184870Syongari 1307184870Syongaristatic void 1308184870Syongariale_dma_free(struct ale_softc *sc) 1309184870Syongari{ 1310184870Syongari struct ale_txdesc *txd; 1311184870Syongari int i; 1312184870Syongari 1313184870Syongari /* Tx buffers. */ 1314184870Syongari if (sc->ale_cdata.ale_tx_tag != NULL) { 1315184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 1316184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 1317184870Syongari if (txd->tx_dmamap != NULL) { 1318184870Syongari bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1319184870Syongari txd->tx_dmamap); 1320184870Syongari txd->tx_dmamap = NULL; 1321184870Syongari } 1322184870Syongari } 1323184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1324184870Syongari sc->ale_cdata.ale_tx_tag = NULL; 1325184870Syongari } 1326184870Syongari /* Tx descriptor ring. */ 1327184870Syongari if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1328184870Syongari if (sc->ale_cdata.ale_tx_ring_map != NULL) 1329184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1330184870Syongari sc->ale_cdata.ale_tx_ring_map); 1331184870Syongari if (sc->ale_cdata.ale_tx_ring_map != NULL && 1332184870Syongari sc->ale_cdata.ale_tx_ring != NULL) 1333184870Syongari bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1334184870Syongari sc->ale_cdata.ale_tx_ring, 1335184870Syongari sc->ale_cdata.ale_tx_ring_map); 1336184870Syongari sc->ale_cdata.ale_tx_ring = NULL; 1337184870Syongari sc->ale_cdata.ale_tx_ring_map = NULL; 1338184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1339184870Syongari sc->ale_cdata.ale_tx_ring_tag = NULL; 1340184870Syongari } 1341184870Syongari /* Rx page block. */ 1342184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1343184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1344184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1345184870Syongari bus_dmamap_unload( 1346184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag, 1347184870Syongari sc->ale_cdata.ale_rx_page[i].page_map); 1348184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1349184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1350184870Syongari bus_dmamem_free( 1351184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag, 1352184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr, 1353184870Syongari sc->ale_cdata.ale_rx_page[i].page_map); 1354184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1355184870Syongari sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1356184870Syongari bus_dma_tag_destroy( 1357184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag); 1358184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1359184870Syongari } 1360184870Syongari } 1361184870Syongari /* Rx CMB. */ 1362184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1363184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1364184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1365184870Syongari bus_dmamap_unload( 1366184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag, 1367184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map); 1368184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1369184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1370184870Syongari bus_dmamem_free( 1371184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag, 1372184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr, 1373184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map); 1374184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1375184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1376184870Syongari bus_dma_tag_destroy( 1377184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag); 1378184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1379184870Syongari } 1380184870Syongari } 1381184870Syongari /* Tx CMB. */ 1382184870Syongari if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1383184870Syongari if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1384184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1385184870Syongari sc->ale_cdata.ale_tx_cmb_map); 1386184870Syongari if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1387184870Syongari sc->ale_cdata.ale_tx_cmb != NULL) 1388184870Syongari bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1389184870Syongari sc->ale_cdata.ale_tx_cmb, 1390184870Syongari sc->ale_cdata.ale_tx_cmb_map); 1391184870Syongari sc->ale_cdata.ale_tx_cmb = NULL; 1392184870Syongari sc->ale_cdata.ale_tx_cmb_map = NULL; 1393184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1394184870Syongari sc->ale_cdata.ale_tx_cmb_tag = NULL; 1395184870Syongari } 1396184870Syongari if (sc->ale_cdata.ale_buffer_tag != NULL) { 1397184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1398184870Syongari sc->ale_cdata.ale_buffer_tag = NULL; 1399184870Syongari } 1400184870Syongari if (sc->ale_cdata.ale_parent_tag != NULL) { 1401184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1402184870Syongari sc->ale_cdata.ale_parent_tag = NULL; 1403184870Syongari } 1404184870Syongari} 1405184870Syongari 1406184870Syongaristatic int 1407184870Syongariale_shutdown(device_t dev) 1408184870Syongari{ 1409184870Syongari 1410184870Syongari return (ale_suspend(dev)); 1411184870Syongari} 1412184870Syongari 1413184870Syongari/* 1414184870Syongari * Note, this driver resets the link speed to 10/100Mbps by 1415184870Syongari * restarting auto-negotiation in suspend/shutdown phase but we 1416184870Syongari * don't know whether that auto-negotiation would succeed or not 1417184870Syongari * as driver has no control after powering off/suspend operation. 1418184870Syongari * If the renegotiation fail WOL may not work. Running at 1Gbps 1419184870Syongari * will draw more power than 375mA at 3.3V which is specified in 1420184870Syongari * PCI specification and that would result in complete 1421184870Syongari * shutdowning power to ethernet controller. 1422184870Syongari * 1423184870Syongari * TODO 1424184870Syongari * Save current negotiated media speed/duplex/flow-control to 1425184870Syongari * softc and restore the same link again after resuming. PHY 1426184870Syongari * handling such as power down/resetting to 100Mbps may be better 1427184870Syongari * handled in suspend method in phy driver. 1428184870Syongari */ 1429184870Syongaristatic void 1430184870Syongariale_setlinkspeed(struct ale_softc *sc) 1431184870Syongari{ 1432184870Syongari struct mii_data *mii; 1433184870Syongari int aneg, i; 1434184870Syongari 1435184870Syongari mii = device_get_softc(sc->ale_miibus); 1436184870Syongari mii_pollstat(mii); 1437184870Syongari aneg = 0; 1438184870Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1439184870Syongari (IFM_ACTIVE | IFM_AVALID)) { 1440184870Syongari switch IFM_SUBTYPE(mii->mii_media_active) { 1441184870Syongari case IFM_10_T: 1442184870Syongari case IFM_100_TX: 1443184870Syongari return; 1444184870Syongari case IFM_1000_T: 1445184870Syongari aneg++; 1446184870Syongari break; 1447184870Syongari default: 1448184870Syongari break; 1449184870Syongari } 1450184870Syongari } 1451184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1452184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1453184870Syongari MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1454184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1455184870Syongari MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1456184870Syongari DELAY(1000); 1457184870Syongari if (aneg != 0) { 1458184870Syongari /* 1459184870Syongari * Poll link state until ale(4) get a 10/100Mbps link. 1460184870Syongari */ 1461184870Syongari for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1462184870Syongari mii_pollstat(mii); 1463184870Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1464184870Syongari == (IFM_ACTIVE | IFM_AVALID)) { 1465184870Syongari switch (IFM_SUBTYPE( 1466184870Syongari mii->mii_media_active)) { 1467184870Syongari case IFM_10_T: 1468184870Syongari case IFM_100_TX: 1469184870Syongari ale_mac_config(sc); 1470184870Syongari return; 1471184870Syongari default: 1472184870Syongari break; 1473184870Syongari } 1474184870Syongari } 1475184870Syongari ALE_UNLOCK(sc); 1476184870Syongari pause("alelnk", hz); 1477184870Syongari ALE_LOCK(sc); 1478184870Syongari } 1479184870Syongari if (i == MII_ANEGTICKS_GIGE) 1480184870Syongari device_printf(sc->ale_dev, 1481184870Syongari "establishing a link failed, WOL may not work!"); 1482184870Syongari } 1483184870Syongari /* 1484184870Syongari * No link, force MAC to have 100Mbps, full-duplex link. 1485184870Syongari * This is the last resort and may/may not work. 1486184870Syongari */ 1487184870Syongari mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1488184870Syongari mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1489184870Syongari ale_mac_config(sc); 1490184870Syongari} 1491184870Syongari 1492184870Syongaristatic void 1493184870Syongariale_setwol(struct ale_softc *sc) 1494184870Syongari{ 1495184870Syongari struct ifnet *ifp; 1496184870Syongari uint32_t reg, pmcs; 1497184870Syongari uint16_t pmstat; 1498184870Syongari int pmc; 1499184870Syongari 1500184870Syongari ALE_LOCK_ASSERT(sc); 1501184870Syongari 1502219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1503184870Syongari /* Disable WOL. */ 1504184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1505184870Syongari reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1506184870Syongari reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1507184870Syongari CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1508184870Syongari /* Force PHY power down. */ 1509184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1510184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1511184870Syongari GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1512184870Syongari GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1513184870Syongari GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1514184870Syongari return; 1515184870Syongari } 1516184870Syongari 1517184870Syongari ifp = sc->ale_ifp; 1518184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1519184870Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1520184870Syongari ale_setlinkspeed(sc); 1521184870Syongari } 1522184870Syongari 1523184870Syongari pmcs = 0; 1524184870Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1525184870Syongari pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1526184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1527184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 1528184870Syongari reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1529184870Syongari MAC_CFG_BCAST); 1530184870Syongari if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1531184870Syongari reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1532184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1533184870Syongari reg |= MAC_CFG_RX_ENB; 1534184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1535184870Syongari 1536184870Syongari if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1537184870Syongari /* WOL disabled, PHY power down. */ 1538184870Syongari reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1539184870Syongari reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1540184870Syongari CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1541184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1542184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1543184870Syongari GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1544184870Syongari GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1545184870Syongari GPHY_CTRL_PWDOWN_HW); 1546184870Syongari } 1547184870Syongari /* Request PME. */ 1548184870Syongari pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1549184870Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1550184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1551184870Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1552184870Syongari pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1553184870Syongari} 1554184870Syongari 1555184870Syongaristatic int 1556184870Syongariale_suspend(device_t dev) 1557184870Syongari{ 1558184870Syongari struct ale_softc *sc; 1559184870Syongari 1560184870Syongari sc = device_get_softc(dev); 1561184870Syongari 1562184870Syongari ALE_LOCK(sc); 1563184870Syongari ale_stop(sc); 1564184870Syongari ale_setwol(sc); 1565184870Syongari ALE_UNLOCK(sc); 1566184870Syongari 1567184870Syongari return (0); 1568184870Syongari} 1569184870Syongari 1570184870Syongaristatic int 1571184870Syongariale_resume(device_t dev) 1572184870Syongari{ 1573184870Syongari struct ale_softc *sc; 1574184870Syongari struct ifnet *ifp; 1575184870Syongari int pmc; 1576189379Syongari uint16_t pmstat; 1577184870Syongari 1578184870Syongari sc = device_get_softc(dev); 1579184870Syongari 1580184870Syongari ALE_LOCK(sc); 1581219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1582184870Syongari /* Disable PME and clear PME status. */ 1583184870Syongari pmstat = pci_read_config(sc->ale_dev, 1584184870Syongari pmc + PCIR_POWER_STATUS, 2); 1585184870Syongari if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1586184870Syongari pmstat &= ~PCIM_PSTAT_PMEENABLE; 1587184870Syongari pci_write_config(sc->ale_dev, 1588184870Syongari pmc + PCIR_POWER_STATUS, pmstat, 2); 1589184870Syongari } 1590184870Syongari } 1591184870Syongari /* Reset PHY. */ 1592184870Syongari ale_phy_reset(sc); 1593184870Syongari ifp = sc->ale_ifp; 1594184870Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1595184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1596184870Syongari ale_init_locked(sc); 1597184870Syongari } 1598184870Syongari ALE_UNLOCK(sc); 1599184870Syongari 1600184870Syongari return (0); 1601184870Syongari} 1602184870Syongari 1603184870Syongaristatic int 1604184870Syongariale_encap(struct ale_softc *sc, struct mbuf **m_head) 1605184870Syongari{ 1606184870Syongari struct ale_txdesc *txd, *txd_last; 1607184870Syongari struct tx_desc *desc; 1608184870Syongari struct mbuf *m; 1609184870Syongari struct ip *ip; 1610184870Syongari struct tcphdr *tcp; 1611184870Syongari bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1612184870Syongari bus_dmamap_t map; 1613207251Syongari uint32_t cflags, hdrlen, ip_off, poff, vtag; 1614184870Syongari int error, i, nsegs, prod, si; 1615184870Syongari 1616184870Syongari ALE_LOCK_ASSERT(sc); 1617184870Syongari 1618184870Syongari M_ASSERTPKTHDR((*m_head)); 1619184870Syongari 1620184870Syongari m = *m_head; 1621184870Syongari ip = NULL; 1622184870Syongari tcp = NULL; 1623184870Syongari cflags = vtag = 0; 1624184870Syongari ip_off = poff = 0; 1625184870Syongari if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1626184870Syongari /* 1627184870Syongari * AR81xx requires offset of TCP/UDP payload in its Tx 1628184870Syongari * descriptor to perform hardware Tx checksum offload. 1629184870Syongari * Additionally, TSO requires IP/TCP header size and 1630184870Syongari * modification of IP/TCP header in order to make TSO 1631184870Syongari * engine work. This kind of operation takes many CPU 1632184870Syongari * cycles on FreeBSD so fast host CPU is required to 1633184870Syongari * get smooth TSO performance. 1634184870Syongari */ 1635184870Syongari struct ether_header *eh; 1636184870Syongari 1637184870Syongari if (M_WRITABLE(m) == 0) { 1638184870Syongari /* Get a writable copy. */ 1639184870Syongari m = m_dup(*m_head, M_DONTWAIT); 1640184870Syongari /* Release original mbufs. */ 1641184870Syongari m_freem(*m_head); 1642184870Syongari if (m == NULL) { 1643184870Syongari *m_head = NULL; 1644184870Syongari return (ENOBUFS); 1645184870Syongari } 1646184870Syongari *m_head = m; 1647184870Syongari } 1648184870Syongari 1649184870Syongari /* 1650184870Syongari * Buggy-controller requires 4 byte aligned Tx buffer 1651184870Syongari * to make custom checksum offload work. 1652184870Syongari */ 1653184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1654184870Syongari (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1655184870Syongari (mtod(m, intptr_t) & 3) != 0) { 1656184870Syongari m = m_defrag(*m_head, M_DONTWAIT); 1657184870Syongari if (m == NULL) { 1658184870Syongari *m_head = NULL; 1659184870Syongari return (ENOBUFS); 1660184870Syongari } 1661184870Syongari *m_head = m; 1662184870Syongari } 1663184870Syongari 1664184870Syongari ip_off = sizeof(struct ether_header); 1665184870Syongari m = m_pullup(m, ip_off); 1666184870Syongari if (m == NULL) { 1667184870Syongari *m_head = NULL; 1668184870Syongari return (ENOBUFS); 1669184870Syongari } 1670184870Syongari eh = mtod(m, struct ether_header *); 1671184870Syongari /* 1672184870Syongari * Check if hardware VLAN insertion is off. 1673184870Syongari * Additional check for LLC/SNAP frame? 1674184870Syongari */ 1675184870Syongari if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1676184870Syongari ip_off = sizeof(struct ether_vlan_header); 1677184870Syongari m = m_pullup(m, ip_off); 1678184870Syongari if (m == NULL) { 1679184870Syongari *m_head = NULL; 1680184870Syongari return (ENOBUFS); 1681184870Syongari } 1682184870Syongari } 1683184870Syongari m = m_pullup(m, ip_off + sizeof(struct ip)); 1684184870Syongari if (m == NULL) { 1685184870Syongari *m_head = NULL; 1686184870Syongari return (ENOBUFS); 1687184870Syongari } 1688184870Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1689184870Syongari poff = ip_off + (ip->ip_hl << 2); 1690184870Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1691184870Syongari /* 1692184870Syongari * XXX 1693184870Syongari * AR81xx requires the first descriptor should 1694184870Syongari * not include any TCP playload for TSO case. 1695184870Syongari * (i.e. ethernet header + IP + TCP header only) 1696184870Syongari * m_pullup(9) above will ensure this too. 1697184870Syongari * However it's not correct if the first mbuf 1698184870Syongari * of the chain does not use cluster. 1699184870Syongari */ 1700184870Syongari m = m_pullup(m, poff + sizeof(struct tcphdr)); 1701184870Syongari if (m == NULL) { 1702184870Syongari *m_head = NULL; 1703184870Syongari return (ENOBUFS); 1704184870Syongari } 1705213844Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1706184870Syongari tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1707207251Syongari m = m_pullup(m, poff + (tcp->th_off << 2)); 1708207251Syongari if (m == NULL) { 1709207251Syongari *m_head = NULL; 1710207251Syongari return (ENOBUFS); 1711207251Syongari } 1712184870Syongari /* 1713184870Syongari * AR81xx requires IP/TCP header size and offset as 1714184870Syongari * well as TCP pseudo checksum which complicates 1715184870Syongari * TSO configuration. I guess this comes from the 1716184870Syongari * adherence to Microsoft NDIS Large Send 1717184870Syongari * specification which requires insertion of 1718184870Syongari * pseudo checksum by upper stack. The pseudo 1719184870Syongari * checksum that NDIS refers to doesn't include 1720184870Syongari * TCP payload length so ale(4) should recompute 1721184870Syongari * the pseudo checksum here. Hopefully this wouldn't 1722184870Syongari * be much burden on modern CPUs. 1723184870Syongari * Reset IP checksum and recompute TCP pseudo 1724184870Syongari * checksum as NDIS specification said. 1725184870Syongari */ 1726184870Syongari ip->ip_sum = 0; 1727184870Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1728184870Syongari ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1729184870Syongari } 1730184870Syongari *m_head = m; 1731184870Syongari } 1732184870Syongari 1733184870Syongari si = prod = sc->ale_cdata.ale_tx_prod; 1734184870Syongari txd = &sc->ale_cdata.ale_txdesc[prod]; 1735184870Syongari txd_last = txd; 1736184870Syongari map = txd->tx_dmamap; 1737184870Syongari 1738184870Syongari error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1739184870Syongari *m_head, txsegs, &nsegs, 0); 1740184870Syongari if (error == EFBIG) { 1741184870Syongari m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); 1742184870Syongari if (m == NULL) { 1743184870Syongari m_freem(*m_head); 1744184870Syongari *m_head = NULL; 1745184870Syongari return (ENOMEM); 1746184870Syongari } 1747184870Syongari *m_head = m; 1748184870Syongari error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1749184870Syongari *m_head, txsegs, &nsegs, 0); 1750184870Syongari if (error != 0) { 1751184870Syongari m_freem(*m_head); 1752184870Syongari *m_head = NULL; 1753184870Syongari return (error); 1754184870Syongari } 1755184870Syongari } else if (error != 0) 1756184870Syongari return (error); 1757184870Syongari if (nsegs == 0) { 1758184870Syongari m_freem(*m_head); 1759184870Syongari *m_head = NULL; 1760184870Syongari return (EIO); 1761184870Syongari } 1762184870Syongari 1763184870Syongari /* Check descriptor overrun. */ 1764207251Syongari if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1765184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1766184870Syongari return (ENOBUFS); 1767184870Syongari } 1768184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1769184870Syongari 1770184870Syongari m = *m_head; 1771206876Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1772206876Syongari /* Request TSO and set MSS. */ 1773206876Syongari cflags |= ALE_TD_TSO; 1774206876Syongari cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1775206876Syongari /* Set IP/TCP header size. */ 1776206876Syongari cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1777206876Syongari cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1778206876Syongari } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1779184870Syongari /* 1780184870Syongari * AR81xx supports Tx custom checksum offload feature 1781184870Syongari * that offloads single 16bit checksum computation. 1782184870Syongari * So you can choose one among IP, TCP and UDP. 1783184870Syongari * Normally driver sets checksum start/insertion 1784184870Syongari * position from the information of TCP/UDP frame as 1785184870Syongari * TCP/UDP checksum takes more time than that of IP. 1786184870Syongari * However it seems that custom checksum offload 1787184870Syongari * requires 4 bytes aligned Tx buffers due to hardware 1788184870Syongari * bug. 1789184870Syongari * AR81xx also supports explicit Tx checksum computation 1790184870Syongari * if it is told that the size of IP header and TCP 1791184870Syongari * header(for UDP, the header size does not matter 1792184870Syongari * because it's fixed length). However with this scheme 1793184870Syongari * TSO does not work so you have to choose one either 1794184870Syongari * TSO or explicit Tx checksum offload. I chosen TSO 1795184870Syongari * plus custom checksum offload with work-around which 1796184870Syongari * will cover most common usage for this consumer 1797184870Syongari * ethernet controller. The work-around takes a lot of 1798184870Syongari * CPU cycles if Tx buffer is not aligned on 4 bytes 1799184870Syongari * boundary, though. 1800184870Syongari */ 1801184870Syongari cflags |= ALE_TD_CXSUM; 1802184870Syongari /* Set checksum start offset. */ 1803184870Syongari cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1804184870Syongari /* Set checksum insertion position of TCP/UDP. */ 1805184870Syongari cflags |= ((poff + m->m_pkthdr.csum_data) << 1806184870Syongari ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1807184870Syongari } 1808184870Syongari 1809184870Syongari /* Configure VLAN hardware tag insertion. */ 1810184870Syongari if ((m->m_flags & M_VLANTAG) != 0) { 1811184870Syongari vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1812184870Syongari vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1813184870Syongari cflags |= ALE_TD_INSERT_VLAN_TAG; 1814184870Syongari } 1815184870Syongari 1816207251Syongari i = 0; 1817207251Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1818207251Syongari /* 1819207251Syongari * Make sure the first fragment contains 1820207251Syongari * only ethernet and IP/TCP header with options. 1821207251Syongari */ 1822207251Syongari hdrlen = poff + (tcp->th_off << 2); 1823184870Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1824184870Syongari desc->addr = htole64(txsegs[i].ds_addr); 1825207251Syongari desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1826207251Syongari desc->flags = htole32(cflags); 1827207251Syongari sc->ale_cdata.ale_tx_cnt++; 1828207251Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1829207251Syongari if (m->m_len - hdrlen > 0) { 1830207251Syongari /* Handle remaining payload of the first fragment. */ 1831207251Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1832207251Syongari desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1833207251Syongari desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1834207251Syongari vtag); 1835207251Syongari desc->flags = htole32(cflags); 1836207251Syongari sc->ale_cdata.ale_tx_cnt++; 1837207251Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1838207251Syongari } 1839207251Syongari i = 1; 1840207251Syongari } 1841207251Syongari for (; i < nsegs; i++) { 1842207251Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1843207251Syongari desc->addr = htole64(txsegs[i].ds_addr); 1844184870Syongari desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1845184870Syongari desc->flags = htole32(cflags); 1846184870Syongari sc->ale_cdata.ale_tx_cnt++; 1847184870Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1848184870Syongari } 1849184870Syongari /* Update producer index. */ 1850184870Syongari sc->ale_cdata.ale_tx_prod = prod; 1851184870Syongari /* Set TSO header on the first descriptor. */ 1852184870Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1853184870Syongari desc = &sc->ale_cdata.ale_tx_ring[si]; 1854184870Syongari desc->flags |= htole32(ALE_TD_TSO_HDR); 1855184870Syongari } 1856184870Syongari 1857184870Syongari /* Finally set EOP on the last descriptor. */ 1858184870Syongari prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1859184870Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1860184870Syongari desc->flags |= htole32(ALE_TD_EOP); 1861184870Syongari 1862184870Syongari /* Swap dmamap of the first and the last. */ 1863184870Syongari txd = &sc->ale_cdata.ale_txdesc[prod]; 1864184870Syongari map = txd_last->tx_dmamap; 1865184870Syongari txd_last->tx_dmamap = txd->tx_dmamap; 1866184870Syongari txd->tx_dmamap = map; 1867184870Syongari txd->tx_m = m; 1868184870Syongari 1869184870Syongari /* Sync descriptors. */ 1870184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1871184870Syongari sc->ale_cdata.ale_tx_ring_map, 1872184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1873184870Syongari 1874184870Syongari return (0); 1875184870Syongari} 1876184870Syongari 1877184870Syongaristatic void 1878216925Sjhbale_start(struct ifnet *ifp) 1879184870Syongari{ 1880216925Sjhb struct ale_softc *sc; 1881184870Syongari 1882216925Sjhb sc = ifp->if_softc; 1883216925Sjhb ALE_LOCK(sc); 1884216925Sjhb ale_start_locked(ifp); 1885216925Sjhb ALE_UNLOCK(sc); 1886184870Syongari} 1887184870Syongari 1888184870Syongaristatic void 1889216925Sjhbale_start_locked(struct ifnet *ifp) 1890184870Syongari{ 1891184870Syongari struct ale_softc *sc; 1892184870Syongari struct mbuf *m_head; 1893184870Syongari int enq; 1894184870Syongari 1895184870Syongari sc = ifp->if_softc; 1896184870Syongari 1897216925Sjhb ALE_LOCK_ASSERT(sc); 1898184870Syongari 1899184870Syongari /* Reclaim transmitted frames. */ 1900184870Syongari if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1901184870Syongari ale_txeof(sc); 1902184870Syongari 1903184870Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1904216925Sjhb IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1905184870Syongari return; 1906184870Syongari 1907184870Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1908184870Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1909184870Syongari if (m_head == NULL) 1910184870Syongari break; 1911184870Syongari /* 1912184870Syongari * Pack the data into the transmit ring. If we 1913184870Syongari * don't have room, set the OACTIVE flag and wait 1914184870Syongari * for the NIC to drain the ring. 1915184870Syongari */ 1916184870Syongari if (ale_encap(sc, &m_head)) { 1917184870Syongari if (m_head == NULL) 1918184870Syongari break; 1919184870Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1920184870Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1921184870Syongari break; 1922184870Syongari } 1923184870Syongari 1924184870Syongari enq++; 1925184870Syongari /* 1926184870Syongari * If there's a BPF listener, bounce a copy of this frame 1927184870Syongari * to him. 1928184870Syongari */ 1929184870Syongari ETHER_BPF_MTAP(ifp, m_head); 1930184870Syongari } 1931184870Syongari 1932184870Syongari if (enq > 0) { 1933184870Syongari /* Kick. */ 1934184870Syongari CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1935184870Syongari sc->ale_cdata.ale_tx_prod); 1936184870Syongari /* Set a timeout in case the chip goes out to lunch. */ 1937184870Syongari sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1938184870Syongari } 1939184870Syongari} 1940184870Syongari 1941184870Syongaristatic void 1942184870Syongariale_watchdog(struct ale_softc *sc) 1943184870Syongari{ 1944184870Syongari struct ifnet *ifp; 1945184870Syongari 1946184870Syongari ALE_LOCK_ASSERT(sc); 1947184870Syongari 1948184870Syongari if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1949184870Syongari return; 1950184870Syongari 1951184870Syongari ifp = sc->ale_ifp; 1952184870Syongari if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1953184870Syongari if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1954184870Syongari ifp->if_oerrors++; 1955184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1956184870Syongari ale_init_locked(sc); 1957184870Syongari return; 1958184870Syongari } 1959184870Syongari if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1960184870Syongari ifp->if_oerrors++; 1961184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1962184870Syongari ale_init_locked(sc); 1963184870Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1964216925Sjhb ale_start_locked(ifp); 1965184870Syongari} 1966184870Syongari 1967184870Syongaristatic int 1968184870Syongariale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1969184870Syongari{ 1970184870Syongari struct ale_softc *sc; 1971184870Syongari struct ifreq *ifr; 1972184870Syongari struct mii_data *mii; 1973184870Syongari int error, mask; 1974184870Syongari 1975184870Syongari sc = ifp->if_softc; 1976184870Syongari ifr = (struct ifreq *)data; 1977184870Syongari error = 0; 1978184870Syongari switch (cmd) { 1979184870Syongari case SIOCSIFMTU: 1980184870Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1981184870Syongari ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1982184870Syongari ifr->ifr_mtu > ETHERMTU)) 1983184870Syongari error = EINVAL; 1984184870Syongari else if (ifp->if_mtu != ifr->ifr_mtu) { 1985184870Syongari ALE_LOCK(sc); 1986184870Syongari ifp->if_mtu = ifr->ifr_mtu; 1987184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1988184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1989184870Syongari ale_init_locked(sc); 1990184870Syongari } 1991184870Syongari ALE_UNLOCK(sc); 1992184870Syongari } 1993184870Syongari break; 1994184870Syongari case SIOCSIFFLAGS: 1995184870Syongari ALE_LOCK(sc); 1996184870Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1997184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1998184870Syongari if (((ifp->if_flags ^ sc->ale_if_flags) 1999184870Syongari & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2000184870Syongari ale_rxfilter(sc); 2001184870Syongari } else { 2002217542Sjhb ale_init_locked(sc); 2003184870Syongari } 2004184870Syongari } else { 2005184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2006184870Syongari ale_stop(sc); 2007184870Syongari } 2008184870Syongari sc->ale_if_flags = ifp->if_flags; 2009184870Syongari ALE_UNLOCK(sc); 2010184870Syongari break; 2011184870Syongari case SIOCADDMULTI: 2012184870Syongari case SIOCDELMULTI: 2013184870Syongari ALE_LOCK(sc); 2014184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2015184870Syongari ale_rxfilter(sc); 2016184870Syongari ALE_UNLOCK(sc); 2017184870Syongari break; 2018184870Syongari case SIOCSIFMEDIA: 2019184870Syongari case SIOCGIFMEDIA: 2020184870Syongari mii = device_get_softc(sc->ale_miibus); 2021184870Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2022184870Syongari break; 2023184870Syongari case SIOCSIFCAP: 2024184870Syongari ALE_LOCK(sc); 2025184870Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2026184870Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2027184870Syongari (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2028184870Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2029184870Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2030184870Syongari ifp->if_hwassist |= ALE_CSUM_FEATURES; 2031184870Syongari else 2032184870Syongari ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2033184870Syongari } 2034184870Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2035184870Syongari (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2036184870Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2037184870Syongari if ((mask & IFCAP_TSO4) != 0 && 2038184870Syongari (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2039184870Syongari ifp->if_capenable ^= IFCAP_TSO4; 2040184870Syongari if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2041184870Syongari ifp->if_hwassist |= CSUM_TSO; 2042184870Syongari else 2043184870Syongari ifp->if_hwassist &= ~CSUM_TSO; 2044184870Syongari } 2045184870Syongari 2046184870Syongari if ((mask & IFCAP_WOL_MCAST) != 0 && 2047184870Syongari (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2048184870Syongari ifp->if_capenable ^= IFCAP_WOL_MCAST; 2049184870Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2050184870Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2051184870Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2052184870Syongari if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2053184870Syongari (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2054184870Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2055184870Syongari if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2056184870Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2057184870Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2058204378Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2059204378Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2060204378Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2061204378Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2062204378Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2063204378Syongari ale_rxvlan(sc); 2064204378Syongari } 2065184870Syongari ALE_UNLOCK(sc); 2066184870Syongari VLAN_CAPABILITIES(ifp); 2067184870Syongari break; 2068184870Syongari default: 2069184870Syongari error = ether_ioctl(ifp, cmd, data); 2070184870Syongari break; 2071184870Syongari } 2072184870Syongari 2073184870Syongari return (error); 2074184870Syongari} 2075184870Syongari 2076184870Syongaristatic void 2077184870Syongariale_mac_config(struct ale_softc *sc) 2078184870Syongari{ 2079184870Syongari struct mii_data *mii; 2080184870Syongari uint32_t reg; 2081184870Syongari 2082184870Syongari ALE_LOCK_ASSERT(sc); 2083184870Syongari 2084184870Syongari mii = device_get_softc(sc->ale_miibus); 2085184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 2086184870Syongari reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2087184870Syongari MAC_CFG_SPEED_MASK); 2088184870Syongari /* Reprogram MAC with resolved speed/duplex. */ 2089184870Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 2090184870Syongari case IFM_10_T: 2091184870Syongari case IFM_100_TX: 2092184870Syongari reg |= MAC_CFG_SPEED_10_100; 2093184870Syongari break; 2094184870Syongari case IFM_1000_T: 2095184870Syongari reg |= MAC_CFG_SPEED_1000; 2096184870Syongari break; 2097184870Syongari } 2098184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2099184870Syongari reg |= MAC_CFG_FULL_DUPLEX; 2100184870Syongari#ifdef notyet 2101184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2102184870Syongari reg |= MAC_CFG_TX_FC; 2103184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2104184870Syongari reg |= MAC_CFG_RX_FC; 2105184870Syongari#endif 2106184870Syongari } 2107184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2108184870Syongari} 2109184870Syongari 2110184870Syongaristatic void 2111184870Syongariale_stats_clear(struct ale_softc *sc) 2112184870Syongari{ 2113184870Syongari struct smb sb; 2114184870Syongari uint32_t *reg; 2115184870Syongari int i; 2116184870Syongari 2117184870Syongari for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2118184870Syongari CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2119184870Syongari i += sizeof(uint32_t); 2120184870Syongari } 2121184870Syongari /* Read Tx statistics. */ 2122184870Syongari for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2123184870Syongari CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2124184870Syongari i += sizeof(uint32_t); 2125184870Syongari } 2126184870Syongari} 2127184870Syongari 2128184870Syongaristatic void 2129184870Syongariale_stats_update(struct ale_softc *sc) 2130184870Syongari{ 2131184870Syongari struct ale_hw_stats *stat; 2132184870Syongari struct smb sb, *smb; 2133184870Syongari struct ifnet *ifp; 2134184870Syongari uint32_t *reg; 2135184870Syongari int i; 2136184870Syongari 2137184870Syongari ALE_LOCK_ASSERT(sc); 2138184870Syongari 2139184870Syongari ifp = sc->ale_ifp; 2140184870Syongari stat = &sc->ale_stats; 2141184870Syongari smb = &sb; 2142184870Syongari 2143184870Syongari /* Read Rx statistics. */ 2144184870Syongari for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2145184870Syongari *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2146184870Syongari i += sizeof(uint32_t); 2147184870Syongari } 2148184870Syongari /* Read Tx statistics. */ 2149184870Syongari for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2150184870Syongari *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2151184870Syongari i += sizeof(uint32_t); 2152184870Syongari } 2153184870Syongari 2154184870Syongari /* Rx stats. */ 2155184870Syongari stat->rx_frames += smb->rx_frames; 2156184870Syongari stat->rx_bcast_frames += smb->rx_bcast_frames; 2157184870Syongari stat->rx_mcast_frames += smb->rx_mcast_frames; 2158184870Syongari stat->rx_pause_frames += smb->rx_pause_frames; 2159184870Syongari stat->rx_control_frames += smb->rx_control_frames; 2160184870Syongari stat->rx_crcerrs += smb->rx_crcerrs; 2161184870Syongari stat->rx_lenerrs += smb->rx_lenerrs; 2162184870Syongari stat->rx_bytes += smb->rx_bytes; 2163184870Syongari stat->rx_runts += smb->rx_runts; 2164184870Syongari stat->rx_fragments += smb->rx_fragments; 2165184870Syongari stat->rx_pkts_64 += smb->rx_pkts_64; 2166184870Syongari stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2167184870Syongari stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2168184870Syongari stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2169184870Syongari stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2170184870Syongari stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2171184870Syongari stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2172184870Syongari stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2173184870Syongari stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2174184870Syongari stat->rx_rrs_errs += smb->rx_rrs_errs; 2175184870Syongari stat->rx_alignerrs += smb->rx_alignerrs; 2176184870Syongari stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2177184870Syongari stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2178184870Syongari stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2179184870Syongari 2180184870Syongari /* Tx stats. */ 2181184870Syongari stat->tx_frames += smb->tx_frames; 2182184870Syongari stat->tx_bcast_frames += smb->tx_bcast_frames; 2183184870Syongari stat->tx_mcast_frames += smb->tx_mcast_frames; 2184184870Syongari stat->tx_pause_frames += smb->tx_pause_frames; 2185184870Syongari stat->tx_excess_defer += smb->tx_excess_defer; 2186184870Syongari stat->tx_control_frames += smb->tx_control_frames; 2187184870Syongari stat->tx_deferred += smb->tx_deferred; 2188184870Syongari stat->tx_bytes += smb->tx_bytes; 2189184870Syongari stat->tx_pkts_64 += smb->tx_pkts_64; 2190184870Syongari stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2191184870Syongari stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2192184870Syongari stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2193184870Syongari stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2194184870Syongari stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2195184870Syongari stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2196184870Syongari stat->tx_single_colls += smb->tx_single_colls; 2197184870Syongari stat->tx_multi_colls += smb->tx_multi_colls; 2198184870Syongari stat->tx_late_colls += smb->tx_late_colls; 2199184870Syongari stat->tx_excess_colls += smb->tx_excess_colls; 2200184870Syongari stat->tx_abort += smb->tx_abort; 2201184870Syongari stat->tx_underrun += smb->tx_underrun; 2202184870Syongari stat->tx_desc_underrun += smb->tx_desc_underrun; 2203184870Syongari stat->tx_lenerrs += smb->tx_lenerrs; 2204184870Syongari stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2205184870Syongari stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2206184870Syongari stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2207184870Syongari 2208184870Syongari /* Update counters in ifnet. */ 2209184870Syongari ifp->if_opackets += smb->tx_frames; 2210184870Syongari 2211184870Syongari ifp->if_collisions += smb->tx_single_colls + 2212184870Syongari smb->tx_multi_colls * 2 + smb->tx_late_colls + 2213184870Syongari smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2214184870Syongari 2215184870Syongari /* 2216184870Syongari * XXX 2217184870Syongari * tx_pkts_truncated counter looks suspicious. It constantly 2218184870Syongari * increments with no sign of Tx errors. This may indicate 2219184870Syongari * the counter name is not correct one so I've removed the 2220184870Syongari * counter in output errors. 2221184870Syongari */ 2222184870Syongari ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2223184870Syongari smb->tx_underrun; 2224184870Syongari 2225184870Syongari ifp->if_ipackets += smb->rx_frames; 2226184870Syongari 2227184870Syongari ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2228184870Syongari smb->rx_runts + smb->rx_pkts_truncated + 2229184870Syongari smb->rx_fifo_oflows + smb->rx_rrs_errs + 2230184870Syongari smb->rx_alignerrs; 2231184870Syongari} 2232184870Syongari 2233184870Syongaristatic int 2234184870Syongariale_intr(void *arg) 2235184870Syongari{ 2236184870Syongari struct ale_softc *sc; 2237184870Syongari uint32_t status; 2238184870Syongari 2239184870Syongari sc = (struct ale_softc *)arg; 2240184870Syongari 2241184870Syongari status = CSR_READ_4(sc, ALE_INTR_STATUS); 2242184870Syongari if ((status & ALE_INTRS) == 0) 2243184870Syongari return (FILTER_STRAY); 2244184870Syongari /* Disable interrupts. */ 2245184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2246184870Syongari taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2247184870Syongari 2248184870Syongari return (FILTER_HANDLED); 2249184870Syongari} 2250184870Syongari 2251184870Syongaristatic void 2252184870Syongariale_int_task(void *arg, int pending) 2253184870Syongari{ 2254184870Syongari struct ale_softc *sc; 2255184870Syongari struct ifnet *ifp; 2256184870Syongari uint32_t status; 2257184870Syongari int more; 2258184870Syongari 2259184870Syongari sc = (struct ale_softc *)arg; 2260184870Syongari 2261184870Syongari status = CSR_READ_4(sc, ALE_INTR_STATUS); 2262217542Sjhb ALE_LOCK(sc); 2263216438Syongari if (sc->ale_morework != 0) 2264184870Syongari status |= INTR_RX_PKT; 2265184870Syongari if ((status & ALE_INTRS) == 0) 2266184870Syongari goto done; 2267184870Syongari 2268184870Syongari /* Acknowledge interrupts but still disable interrupts. */ 2269184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2270184870Syongari 2271184870Syongari ifp = sc->ale_ifp; 2272184870Syongari more = 0; 2273184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2274184870Syongari more = ale_rxeof(sc, sc->ale_process_limit); 2275184870Syongari if (more == EAGAIN) 2276216438Syongari sc->ale_morework = 1; 2277184870Syongari else if (more == EIO) { 2278184870Syongari sc->ale_stats.reset_brk_seq++; 2279184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2280184870Syongari ale_init_locked(sc); 2281184870Syongari ALE_UNLOCK(sc); 2282184870Syongari return; 2283184870Syongari } 2284184870Syongari 2285184870Syongari if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2286184870Syongari if ((status & INTR_DMA_RD_TO_RST) != 0) 2287184870Syongari device_printf(sc->ale_dev, 2288184870Syongari "DMA read error! -- resetting\n"); 2289184870Syongari if ((status & INTR_DMA_WR_TO_RST) != 0) 2290184870Syongari device_printf(sc->ale_dev, 2291184870Syongari "DMA write error! -- resetting\n"); 2292184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2293184870Syongari ale_init_locked(sc); 2294184870Syongari ALE_UNLOCK(sc); 2295184870Syongari return; 2296184870Syongari } 2297184870Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2298216925Sjhb ale_start_locked(ifp); 2299184870Syongari } 2300184870Syongari 2301184870Syongari if (more == EAGAIN || 2302184870Syongari (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2303217542Sjhb ALE_UNLOCK(sc); 2304184870Syongari taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2305184870Syongari return; 2306184870Syongari } 2307184870Syongari 2308184870Syongaridone: 2309217542Sjhb ALE_UNLOCK(sc); 2310217542Sjhb 2311184870Syongari /* Re-enable interrupts. */ 2312184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2313184870Syongari} 2314184870Syongari 2315184870Syongaristatic void 2316184870Syongariale_txeof(struct ale_softc *sc) 2317184870Syongari{ 2318184870Syongari struct ifnet *ifp; 2319184870Syongari struct ale_txdesc *txd; 2320184870Syongari uint32_t cons, prod; 2321184870Syongari int prog; 2322184870Syongari 2323184870Syongari ALE_LOCK_ASSERT(sc); 2324184870Syongari 2325184870Syongari ifp = sc->ale_ifp; 2326184870Syongari 2327184870Syongari if (sc->ale_cdata.ale_tx_cnt == 0) 2328184870Syongari return; 2329184870Syongari 2330184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2331184870Syongari sc->ale_cdata.ale_tx_ring_map, 2332184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2333184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2334184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2335184870Syongari sc->ale_cdata.ale_tx_cmb_map, 2336184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2337184870Syongari prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2338184870Syongari } else 2339184870Syongari prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2340184870Syongari cons = sc->ale_cdata.ale_tx_cons; 2341184870Syongari /* 2342184870Syongari * Go through our Tx list and free mbufs for those 2343184870Syongari * frames which have been transmitted. 2344184870Syongari */ 2345184870Syongari for (prog = 0; cons != prod; prog++, 2346184870Syongari ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2347184870Syongari if (sc->ale_cdata.ale_tx_cnt <= 0) 2348184870Syongari break; 2349184870Syongari prog++; 2350184870Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2351184870Syongari sc->ale_cdata.ale_tx_cnt--; 2352184870Syongari txd = &sc->ale_cdata.ale_txdesc[cons]; 2353184870Syongari if (txd->tx_m != NULL) { 2354184870Syongari /* Reclaim transmitted mbufs. */ 2355184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2356184870Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2357184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2358184870Syongari txd->tx_dmamap); 2359184870Syongari m_freem(txd->tx_m); 2360184870Syongari txd->tx_m = NULL; 2361184870Syongari } 2362184870Syongari } 2363184870Syongari 2364184870Syongari if (prog > 0) { 2365184870Syongari sc->ale_cdata.ale_tx_cons = cons; 2366184870Syongari /* 2367184870Syongari * Unarm watchdog timer only when there is no pending 2368184870Syongari * Tx descriptors in queue. 2369184870Syongari */ 2370184870Syongari if (sc->ale_cdata.ale_tx_cnt == 0) 2371184870Syongari sc->ale_watchdog_timer = 0; 2372184870Syongari } 2373184870Syongari} 2374184870Syongari 2375184870Syongaristatic void 2376184870Syongariale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2377184870Syongari uint32_t length, uint32_t *prod) 2378184870Syongari{ 2379184870Syongari struct ale_rx_page *rx_page; 2380184870Syongari 2381184870Syongari rx_page = *page; 2382184870Syongari /* Update consumer position. */ 2383184870Syongari rx_page->cons += roundup(length + sizeof(struct rx_rs), 2384184870Syongari ALE_RX_PAGE_ALIGN); 2385184870Syongari if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2386184870Syongari /* 2387184870Syongari * End of Rx page reached, let hardware reuse 2388184870Syongari * this page. 2389184870Syongari */ 2390184870Syongari rx_page->cons = 0; 2391184870Syongari *rx_page->cmb_addr = 0; 2392184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2393184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2394184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2395184870Syongari RXF_VALID); 2396184870Syongari /* Switch to alternate Rx page. */ 2397184870Syongari sc->ale_cdata.ale_rx_curp ^= 1; 2398184870Syongari rx_page = *page = 2399184870Syongari &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2400184870Syongari /* Page flipped, sync CMB and Rx page. */ 2401184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2402184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2403184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2404184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2405184870Syongari /* Sync completed, cache updated producer index. */ 2406184870Syongari *prod = *rx_page->cmb_addr; 2407184870Syongari } 2408184870Syongari} 2409184870Syongari 2410184870Syongari 2411184870Syongari/* 2412184870Syongari * It seems that AR81xx controller can compute partial checksum. 2413184870Syongari * The partial checksum value can be used to accelerate checksum 2414184870Syongari * computation for fragmented TCP/UDP packets. Upper network stack 2415184870Syongari * already takes advantage of the partial checksum value in IP 2416184870Syongari * reassembly stage. But I'm not sure the correctness of the 2417184870Syongari * partial hardware checksum assistance due to lack of data sheet. 2418184870Syongari * In addition, the Rx feature of controller that requires copying 2419184870Syongari * for every frames effectively nullifies one of most nice offload 2420184870Syongari * capability of controller. 2421184870Syongari */ 2422184870Syongaristatic void 2423184870Syongariale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2424184870Syongari{ 2425184870Syongari struct ifnet *ifp; 2426184870Syongari struct ip *ip; 2427184870Syongari char *p; 2428184870Syongari 2429184870Syongari ifp = sc->ale_ifp; 2430184870Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2431184870Syongari if ((status & ALE_RD_IPCSUM_NOK) == 0) 2432184870Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2433184870Syongari 2434184870Syongari if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2435184870Syongari if (((status & ALE_RD_IPV4_FRAG) == 0) && 2436184870Syongari ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2437184870Syongari ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2438184870Syongari m->m_pkthdr.csum_flags |= 2439184870Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2440184870Syongari m->m_pkthdr.csum_data = 0xffff; 2441184870Syongari } 2442184870Syongari } else { 2443184870Syongari if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2444184870Syongari (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2445184870Syongari p = mtod(m, char *); 2446184870Syongari p += ETHER_HDR_LEN; 2447184870Syongari if ((status & ALE_RD_802_3) != 0) 2448184870Syongari p += LLC_SNAPFRAMELEN; 2449184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2450184870Syongari (status & ALE_RD_VLAN) != 0) 2451184870Syongari p += ETHER_VLAN_ENCAP_LEN; 2452184870Syongari ip = (struct ip *)p; 2453184870Syongari if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2454184870Syongari return; 2455184870Syongari m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2456184870Syongari CSUM_PSEUDO_HDR; 2457184870Syongari m->m_pkthdr.csum_data = 0xffff; 2458184870Syongari } 2459184870Syongari } 2460184870Syongari /* 2461184870Syongari * Don't mark bad checksum for TCP/UDP frames 2462184870Syongari * as fragmented frames may always have set 2463184870Syongari * bad checksummed bit of frame status. 2464184870Syongari */ 2465184870Syongari} 2466184870Syongari 2467184870Syongari/* Process received frames. */ 2468184870Syongaristatic int 2469184870Syongariale_rxeof(struct ale_softc *sc, int count) 2470184870Syongari{ 2471184870Syongari struct ale_rx_page *rx_page; 2472184870Syongari struct rx_rs *rs; 2473184870Syongari struct ifnet *ifp; 2474184870Syongari struct mbuf *m; 2475184870Syongari uint32_t length, prod, seqno, status, vtags; 2476184870Syongari int prog; 2477184870Syongari 2478184870Syongari ifp = sc->ale_ifp; 2479184870Syongari rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2480184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2481184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2482184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2483184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2484184870Syongari /* 2485184870Syongari * Don't directly access producer index as hardware may 2486184870Syongari * update it while Rx handler is in progress. It would 2487184870Syongari * be even better if there is a way to let hardware 2488184870Syongari * know how far driver processed its received frames. 2489184870Syongari * Alternatively, hardware could provide a way to disable 2490184870Syongari * CMB updates until driver acknowledges the end of CMB 2491184870Syongari * access. 2492184870Syongari */ 2493184870Syongari prod = *rx_page->cmb_addr; 2494184870Syongari for (prog = 0; prog < count; prog++) { 2495184870Syongari if (rx_page->cons >= prod) 2496184870Syongari break; 2497184870Syongari rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2498184870Syongari seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2499184870Syongari if (sc->ale_cdata.ale_rx_seqno != seqno) { 2500184870Syongari /* 2501184870Syongari * Normally I believe this should not happen unless 2502184870Syongari * severe driver bug or corrupted memory. However 2503184870Syongari * it seems to happen under certain conditions which 2504184870Syongari * is triggered by abrupt Rx events such as initiation 2505184870Syongari * of bulk transfer of remote host. It's not easy to 2506184870Syongari * reproduce this and I doubt it could be related 2507184870Syongari * with FIFO overflow of hardware or activity of Tx 2508184870Syongari * CMB updates. I also remember similar behaviour 2509184870Syongari * seen on RealTek 8139 which uses resembling Rx 2510184870Syongari * scheme. 2511184870Syongari */ 2512184870Syongari if (bootverbose) 2513184870Syongari device_printf(sc->ale_dev, 2514184870Syongari "garbled seq: %u, expected: %u -- " 2515184870Syongari "resetting!\n", seqno, 2516184870Syongari sc->ale_cdata.ale_rx_seqno); 2517184870Syongari return (EIO); 2518184870Syongari } 2519184870Syongari /* Frame received. */ 2520184870Syongari sc->ale_cdata.ale_rx_seqno++; 2521184870Syongari length = ALE_RX_BYTES(le32toh(rs->length)); 2522184870Syongari status = le32toh(rs->flags); 2523184870Syongari if ((status & ALE_RD_ERROR) != 0) { 2524184870Syongari /* 2525184870Syongari * We want to pass the following frames to upper 2526184870Syongari * layer regardless of error status of Rx return 2527184870Syongari * status. 2528184870Syongari * 2529184870Syongari * o IP/TCP/UDP checksum is bad. 2530184870Syongari * o frame length and protocol specific length 2531184870Syongari * does not match. 2532184870Syongari */ 2533184870Syongari if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2534184870Syongari ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2535184870Syongari ALE_RD_TRUNC)) != 0) { 2536184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2537184870Syongari continue; 2538184870Syongari } 2539184870Syongari } 2540184870Syongari /* 2541184870Syongari * m_devget(9) is major bottle-neck of ale(4)(It comes 2542184870Syongari * from hardware limitation). For jumbo frames we could 2543184870Syongari * get a slightly better performance if driver use 2544184870Syongari * m_getjcl(9) with proper buffer size argument. However 2545184870Syongari * that would make code more complicated and I don't 2546184870Syongari * think users would expect good Rx performance numbers 2547184870Syongari * on these low-end consumer ethernet controller. 2548184870Syongari */ 2549184870Syongari m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2550184870Syongari ETHER_ALIGN, ifp, NULL); 2551184870Syongari if (m == NULL) { 2552184870Syongari ifp->if_iqdrops++; 2553184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2554184870Syongari continue; 2555184870Syongari } 2556184870Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2557184870Syongari (status & ALE_RD_IPV4) != 0) 2558184870Syongari ale_rxcsum(sc, m, status); 2559184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2560184870Syongari (status & ALE_RD_VLAN) != 0) { 2561184870Syongari vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2562184870Syongari m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2563184870Syongari m->m_flags |= M_VLANTAG; 2564184870Syongari } 2565184870Syongari 2566184870Syongari /* Pass it to upper layer. */ 2567217542Sjhb ALE_UNLOCK(sc); 2568184870Syongari (*ifp->if_input)(ifp, m); 2569217542Sjhb ALE_LOCK(sc); 2570184870Syongari 2571184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2572184870Syongari } 2573184870Syongari 2574184870Syongari return (count > 0 ? 0 : EAGAIN); 2575184870Syongari} 2576184870Syongari 2577184870Syongaristatic void 2578184870Syongariale_tick(void *arg) 2579184870Syongari{ 2580184870Syongari struct ale_softc *sc; 2581184870Syongari struct mii_data *mii; 2582184870Syongari 2583184870Syongari sc = (struct ale_softc *)arg; 2584184870Syongari 2585184870Syongari ALE_LOCK_ASSERT(sc); 2586184870Syongari 2587184870Syongari mii = device_get_softc(sc->ale_miibus); 2588184870Syongari mii_tick(mii); 2589184870Syongari ale_stats_update(sc); 2590184870Syongari /* 2591184870Syongari * Reclaim Tx buffers that have been transferred. It's not 2592184870Syongari * needed here but it would release allocated mbuf chains 2593184870Syongari * faster and limit the maximum delay to a hz. 2594184870Syongari */ 2595184870Syongari ale_txeof(sc); 2596184870Syongari ale_watchdog(sc); 2597184870Syongari callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2598184870Syongari} 2599184870Syongari 2600184870Syongaristatic void 2601184870Syongariale_reset(struct ale_softc *sc) 2602184870Syongari{ 2603184870Syongari uint32_t reg; 2604184870Syongari int i; 2605184870Syongari 2606184870Syongari /* Initialize PCIe module. From Linux. */ 2607184870Syongari CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2608184870Syongari 2609184870Syongari CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2610184870Syongari for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2611184870Syongari DELAY(10); 2612184870Syongari if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2613184870Syongari break; 2614184870Syongari } 2615184870Syongari if (i == 0) 2616184870Syongari device_printf(sc->ale_dev, "master reset timeout!\n"); 2617184870Syongari 2618184870Syongari for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2619184870Syongari if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2620184870Syongari break; 2621184870Syongari DELAY(10); 2622184870Syongari } 2623184870Syongari 2624184870Syongari if (i == 0) 2625184870Syongari device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2626184870Syongari} 2627184870Syongari 2628184870Syongaristatic void 2629184870Syongariale_init(void *xsc) 2630184870Syongari{ 2631184870Syongari struct ale_softc *sc; 2632184870Syongari 2633184870Syongari sc = (struct ale_softc *)xsc; 2634184870Syongari ALE_LOCK(sc); 2635184870Syongari ale_init_locked(sc); 2636184870Syongari ALE_UNLOCK(sc); 2637184870Syongari} 2638184870Syongari 2639184870Syongaristatic void 2640184870Syongariale_init_locked(struct ale_softc *sc) 2641184870Syongari{ 2642184870Syongari struct ifnet *ifp; 2643184870Syongari struct mii_data *mii; 2644184870Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 2645184870Syongari bus_addr_t paddr; 2646184870Syongari uint32_t reg, rxf_hi, rxf_lo; 2647184870Syongari 2648184870Syongari ALE_LOCK_ASSERT(sc); 2649184870Syongari 2650184870Syongari ifp = sc->ale_ifp; 2651184870Syongari mii = device_get_softc(sc->ale_miibus); 2652184870Syongari 2653184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2654184870Syongari return; 2655184870Syongari /* 2656184870Syongari * Cancel any pending I/O. 2657184870Syongari */ 2658184870Syongari ale_stop(sc); 2659184870Syongari /* 2660184870Syongari * Reset the chip to a known state. 2661184870Syongari */ 2662184870Syongari ale_reset(sc); 2663184870Syongari /* Initialize Tx descriptors, DMA memory blocks. */ 2664184870Syongari ale_init_rx_pages(sc); 2665184870Syongari ale_init_tx_ring(sc); 2666184870Syongari 2667184870Syongari /* Reprogram the station address. */ 2668184870Syongari bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2669184870Syongari CSR_WRITE_4(sc, ALE_PAR0, 2670184870Syongari eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2671184870Syongari CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2672184870Syongari /* 2673184870Syongari * Clear WOL status and disable all WOL feature as WOL 2674184870Syongari * would interfere Rx operation under normal environments. 2675184870Syongari */ 2676184870Syongari CSR_READ_4(sc, ALE_WOL_CFG); 2677184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2678184870Syongari /* 2679184870Syongari * Set Tx descriptor/RXF0/CMB base addresses. They share 2680184870Syongari * the same high address part of DMAable region. 2681184870Syongari */ 2682184870Syongari paddr = sc->ale_cdata.ale_tx_ring_paddr; 2683184870Syongari CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2684184870Syongari CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2685184870Syongari CSR_WRITE_4(sc, ALE_TPD_CNT, 2686184870Syongari (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2687184870Syongari /* Set Rx page base address, note we use single queue. */ 2688184870Syongari paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2689184870Syongari CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2690184870Syongari paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2691184870Syongari CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2692184870Syongari /* Set Tx/Rx CMB addresses. */ 2693184870Syongari paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2694184870Syongari CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2695184870Syongari paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2696184870Syongari CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2697184870Syongari paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2698184870Syongari CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2699184870Syongari /* Mark RXF0 is valid. */ 2700184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2701184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2702184870Syongari /* 2703184870Syongari * No need to initialize RFX1/RXF2/RXF3. We don't use 2704184870Syongari * multi-queue yet. 2705184870Syongari */ 2706184870Syongari 2707184870Syongari /* Set Rx page size, excluding guard frame size. */ 2708184870Syongari CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2709184870Syongari /* Tell hardware that we're ready to load DMA blocks. */ 2710184870Syongari CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2711184870Syongari 2712184870Syongari /* Set Rx/Tx interrupt trigger threshold. */ 2713184870Syongari CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2714184870Syongari (4 << INT_TRIG_TX_THRESH_SHIFT)); 2715184870Syongari /* 2716184870Syongari * XXX 2717184870Syongari * Set interrupt trigger timer, its purpose and relation 2718184870Syongari * with interrupt moderation mechanism is not clear yet. 2719184870Syongari */ 2720184870Syongari CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2721184870Syongari ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2722184870Syongari (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2723184870Syongari 2724184870Syongari /* Configure interrupt moderation timer. */ 2725184870Syongari reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2726184870Syongari reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2727184870Syongari CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2728184870Syongari reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2729184870Syongari reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2730184870Syongari reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2731184870Syongari if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2732184870Syongari reg |= MASTER_IM_RX_TIMER_ENB; 2733184870Syongari if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2734184870Syongari reg |= MASTER_IM_TX_TIMER_ENB; 2735184870Syongari CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2736184870Syongari CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2737184870Syongari 2738184870Syongari /* Set Maximum frame size of controller. */ 2739184870Syongari if (ifp->if_mtu < ETHERMTU) 2740184870Syongari sc->ale_max_frame_size = ETHERMTU; 2741184870Syongari else 2742184870Syongari sc->ale_max_frame_size = ifp->if_mtu; 2743184870Syongari sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2744184870Syongari ETHER_CRC_LEN; 2745184870Syongari CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2746184870Syongari /* Configure IPG/IFG parameters. */ 2747184870Syongari CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2748184870Syongari ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2749184870Syongari ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2750184870Syongari ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2751184870Syongari ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2752184870Syongari /* Set parameters for half-duplex media. */ 2753184870Syongari CSR_WRITE_4(sc, ALE_HDPX_CFG, 2754184870Syongari ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2755184870Syongari HDPX_CFG_LCOL_MASK) | 2756184870Syongari ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2757184870Syongari HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2758184870Syongari ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2759184870Syongari HDPX_CFG_ABEBT_MASK) | 2760184870Syongari ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2761184870Syongari HDPX_CFG_JAMIPG_MASK)); 2762184870Syongari 2763184870Syongari /* Configure Tx jumbo frame parameters. */ 2764184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2765184870Syongari if (ifp->if_mtu < ETHERMTU) 2766184870Syongari reg = sc->ale_max_frame_size; 2767184870Syongari else if (ifp->if_mtu < 6 * 1024) 2768184870Syongari reg = (sc->ale_max_frame_size * 2) / 3; 2769184870Syongari else 2770184870Syongari reg = sc->ale_max_frame_size / 2; 2771184870Syongari CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2772184870Syongari roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2773184870Syongari TX_JUMBO_THRESH_UNIT_SHIFT); 2774184870Syongari } 2775184870Syongari /* Configure TxQ. */ 2776185577Syongari reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2777185577Syongari << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2778184870Syongari reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2779184870Syongari TXQ_CFG_TPD_BURST_MASK; 2780184870Syongari CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2781184870Syongari 2782184870Syongari /* Configure Rx jumbo frame & flow control parameters. */ 2783184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2784184870Syongari reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2785184870Syongari CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2786184870Syongari (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2787184870Syongari RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2788184870Syongari ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2789184870Syongari RX_JUMBO_LKAH_MASK)); 2790184870Syongari reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2791184870Syongari rxf_hi = (reg * 7) / 10; 2792184870Syongari rxf_lo = (reg * 3)/ 10; 2793184870Syongari CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2794184870Syongari ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2795184870Syongari RX_FIFO_PAUSE_THRESH_LO_MASK) | 2796184870Syongari ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2797184870Syongari RX_FIFO_PAUSE_THRESH_HI_MASK)); 2798184870Syongari } 2799184870Syongari 2800184870Syongari /* Disable RSS. */ 2801184870Syongari CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2802184870Syongari CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2803184870Syongari 2804184870Syongari /* Configure RxQ. */ 2805184870Syongari CSR_WRITE_4(sc, ALE_RXQ_CFG, 2806184870Syongari RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2807184870Syongari 2808184870Syongari /* Configure DMA parameters. */ 2809184870Syongari reg = 0; 2810184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2811184870Syongari reg |= DMA_CFG_TXCMB_ENB; 2812184870Syongari CSR_WRITE_4(sc, ALE_DMA_CFG, 2813184870Syongari DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2814184870Syongari sc->ale_dma_rd_burst | reg | 2815184870Syongari sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2816184870Syongari ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2817184870Syongari DMA_CFG_RD_DELAY_CNT_MASK) | 2818184870Syongari ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2819184870Syongari DMA_CFG_WR_DELAY_CNT_MASK)); 2820184870Syongari 2821184870Syongari /* 2822184870Syongari * Hardware can be configured to issue SMB interrupt based 2823184870Syongari * on programmed interval. Since there is a callout that is 2824184870Syongari * invoked for every hz in driver we use that instead of 2825184870Syongari * relying on periodic SMB interrupt. 2826184870Syongari */ 2827184870Syongari CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2828184870Syongari /* Clear MAC statistics. */ 2829184870Syongari ale_stats_clear(sc); 2830184870Syongari 2831184870Syongari /* 2832184870Syongari * Configure Tx/Rx MACs. 2833184870Syongari * - Auto-padding for short frames. 2834184870Syongari * - Enable CRC generation. 2835184870Syongari * Actual reconfiguration of MAC for resolved speed/duplex 2836184870Syongari * is followed after detection of link establishment. 2837184870Syongari * AR81xx always does checksum computation regardless of 2838184870Syongari * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2839184870Syongari * cause Rx handling issue for fragmented IP datagrams due 2840184870Syongari * to silicon bug. 2841184870Syongari */ 2842184870Syongari reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2843184870Syongari ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2844184870Syongari MAC_CFG_PREAMBLE_MASK); 2845184870Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2846184870Syongari reg |= MAC_CFG_SPEED_10_100; 2847184870Syongari else 2848184870Syongari reg |= MAC_CFG_SPEED_1000; 2849184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2850184870Syongari 2851184870Syongari /* Set up the receive filter. */ 2852184870Syongari ale_rxfilter(sc); 2853184870Syongari ale_rxvlan(sc); 2854184870Syongari 2855184870Syongari /* Acknowledge all pending interrupts and clear it. */ 2856184870Syongari CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2857184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2858184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2859184870Syongari 2860233688Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2861233688Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2862233688Syongari 2863184870Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 2864184870Syongari /* Switch to the current media. */ 2865184870Syongari mii_mediachg(mii); 2866184870Syongari 2867184870Syongari callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2868184870Syongari} 2869184870Syongari 2870184870Syongaristatic void 2871184870Syongariale_stop(struct ale_softc *sc) 2872184870Syongari{ 2873184870Syongari struct ifnet *ifp; 2874184870Syongari struct ale_txdesc *txd; 2875184870Syongari uint32_t reg; 2876184870Syongari int i; 2877184870Syongari 2878184870Syongari ALE_LOCK_ASSERT(sc); 2879184870Syongari /* 2880184870Syongari * Mark the interface down and cancel the watchdog timer. 2881184870Syongari */ 2882184870Syongari ifp = sc->ale_ifp; 2883184870Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2884184870Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 2885184870Syongari callout_stop(&sc->ale_tick_ch); 2886184870Syongari sc->ale_watchdog_timer = 0; 2887184870Syongari ale_stats_update(sc); 2888184870Syongari /* Disable interrupts. */ 2889184870Syongari CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2890184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2891184870Syongari /* Disable queue processing and DMA. */ 2892184870Syongari reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2893184870Syongari reg &= ~TXQ_CFG_ENB; 2894184870Syongari CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2895184870Syongari reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2896184870Syongari reg &= ~RXQ_CFG_ENB; 2897184870Syongari CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2898184870Syongari reg = CSR_READ_4(sc, ALE_DMA_CFG); 2899184870Syongari reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2900184870Syongari CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2901184870Syongari DELAY(1000); 2902184870Syongari /* Stop Rx/Tx MACs. */ 2903184870Syongari ale_stop_mac(sc); 2904184870Syongari /* Disable interrupts which might be touched in taskq handler. */ 2905184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2906184870Syongari 2907184870Syongari /* 2908184870Syongari * Free TX mbufs still in the queues. 2909184870Syongari */ 2910184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 2911184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 2912184870Syongari if (txd->tx_m != NULL) { 2913184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2914184870Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2915184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2916184870Syongari txd->tx_dmamap); 2917184870Syongari m_freem(txd->tx_m); 2918184870Syongari txd->tx_m = NULL; 2919184870Syongari } 2920184870Syongari } 2921184870Syongari} 2922184870Syongari 2923184870Syongaristatic void 2924184870Syongariale_stop_mac(struct ale_softc *sc) 2925184870Syongari{ 2926184870Syongari uint32_t reg; 2927184870Syongari int i; 2928184870Syongari 2929184870Syongari ALE_LOCK_ASSERT(sc); 2930184870Syongari 2931184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 2932184870Syongari if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2933184870Syongari reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2934184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2935184870Syongari } 2936184870Syongari 2937184870Syongari for (i = ALE_TIMEOUT; i > 0; i--) { 2938184870Syongari reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2939184870Syongari if (reg == 0) 2940184870Syongari break; 2941184870Syongari DELAY(10); 2942184870Syongari } 2943184870Syongari if (i == 0) 2944184870Syongari device_printf(sc->ale_dev, 2945184870Syongari "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2946184870Syongari} 2947184870Syongari 2948184870Syongaristatic void 2949184870Syongariale_init_tx_ring(struct ale_softc *sc) 2950184870Syongari{ 2951184870Syongari struct ale_txdesc *txd; 2952184870Syongari int i; 2953184870Syongari 2954184870Syongari ALE_LOCK_ASSERT(sc); 2955184870Syongari 2956184870Syongari sc->ale_cdata.ale_tx_prod = 0; 2957184870Syongari sc->ale_cdata.ale_tx_cons = 0; 2958184870Syongari sc->ale_cdata.ale_tx_cnt = 0; 2959184870Syongari 2960184870Syongari bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2961184870Syongari bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2962184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 2963184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 2964184870Syongari txd->tx_m = NULL; 2965184870Syongari } 2966184870Syongari *sc->ale_cdata.ale_tx_cmb = 0; 2967184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2968184870Syongari sc->ale_cdata.ale_tx_cmb_map, 2969184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2970184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2971184870Syongari sc->ale_cdata.ale_tx_ring_map, 2972184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2973184870Syongari} 2974184870Syongari 2975184870Syongaristatic void 2976184870Syongariale_init_rx_pages(struct ale_softc *sc) 2977184870Syongari{ 2978184870Syongari struct ale_rx_page *rx_page; 2979184870Syongari int i; 2980184870Syongari 2981184870Syongari ALE_LOCK_ASSERT(sc); 2982184870Syongari 2983216438Syongari sc->ale_morework = 0; 2984184870Syongari sc->ale_cdata.ale_rx_seqno = 0; 2985184870Syongari sc->ale_cdata.ale_rx_curp = 0; 2986184870Syongari 2987184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 2988184870Syongari rx_page = &sc->ale_cdata.ale_rx_page[i]; 2989184870Syongari bzero(rx_page->page_addr, sc->ale_pagesize); 2990184870Syongari bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2991184870Syongari rx_page->cons = 0; 2992184870Syongari *rx_page->cmb_addr = 0; 2993184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2994184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2995184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2996184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2997184870Syongari } 2998184870Syongari} 2999184870Syongari 3000184870Syongaristatic void 3001184870Syongariale_rxvlan(struct ale_softc *sc) 3002184870Syongari{ 3003184870Syongari struct ifnet *ifp; 3004184870Syongari uint32_t reg; 3005184870Syongari 3006184870Syongari ALE_LOCK_ASSERT(sc); 3007184870Syongari 3008184870Syongari ifp = sc->ale_ifp; 3009184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 3010184870Syongari reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3011184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3012184870Syongari reg |= MAC_CFG_VLAN_TAG_STRIP; 3013184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3014184870Syongari} 3015184870Syongari 3016184870Syongaristatic void 3017184870Syongariale_rxfilter(struct ale_softc *sc) 3018184870Syongari{ 3019184870Syongari struct ifnet *ifp; 3020184870Syongari struct ifmultiaddr *ifma; 3021184870Syongari uint32_t crc; 3022184870Syongari uint32_t mchash[2]; 3023184870Syongari uint32_t rxcfg; 3024184870Syongari 3025184870Syongari ALE_LOCK_ASSERT(sc); 3026184870Syongari 3027184870Syongari ifp = sc->ale_ifp; 3028184870Syongari 3029184870Syongari rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3030184870Syongari rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3031184870Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 3032184870Syongari rxcfg |= MAC_CFG_BCAST; 3033184870Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3034184870Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 3035184870Syongari rxcfg |= MAC_CFG_PROMISC; 3036184870Syongari if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3037184870Syongari rxcfg |= MAC_CFG_ALLMULTI; 3038184870Syongari CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3039184870Syongari CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3040184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3041184870Syongari return; 3042184870Syongari } 3043184870Syongari 3044184870Syongari /* Program new filter. */ 3045184870Syongari bzero(mchash, sizeof(mchash)); 3046184870Syongari 3047195049Srwatson if_maddr_rlock(ifp); 3048184870Syongari TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3049184870Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 3050184870Syongari continue; 3051197627Syongari crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3052184870Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 3053184870Syongari mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3054184870Syongari } 3055195049Srwatson if_maddr_runlock(ifp); 3056184870Syongari 3057184870Syongari CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3058184870Syongari CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3059184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3060184870Syongari} 3061184870Syongari 3062184870Syongaristatic int 3063184870Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3064184870Syongari{ 3065184870Syongari int error, value; 3066184870Syongari 3067184870Syongari if (arg1 == NULL) 3068184870Syongari return (EINVAL); 3069184870Syongari value = *(int *)arg1; 3070184870Syongari error = sysctl_handle_int(oidp, &value, 0, req); 3071184870Syongari if (error || req->newptr == NULL) 3072184870Syongari return (error); 3073184870Syongari if (value < low || value > high) 3074184870Syongari return (EINVAL); 3075184870Syongari *(int *)arg1 = value; 3076184870Syongari 3077184870Syongari return (0); 3078184870Syongari} 3079184870Syongari 3080184870Syongaristatic int 3081184870Syongarisysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3082184870Syongari{ 3083184870Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3084184870Syongari ALE_PROC_MIN, ALE_PROC_MAX)); 3085184870Syongari} 3086184870Syongari 3087184870Syongaristatic int 3088184870Syongarisysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3089184870Syongari{ 3090184870Syongari 3091184870Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3092184870Syongari ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3093184870Syongari} 3094