if_ale.c revision 221407
1184870Syongari/*- 2184870Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3184870Syongari * All rights reserved. 4184870Syongari * 5184870Syongari * Redistribution and use in source and binary forms, with or without 6184870Syongari * modification, are permitted provided that the following conditions 7184870Syongari * are met: 8184870Syongari * 1. Redistributions of source code must retain the above copyright 9184870Syongari * notice unmodified, this list of conditions, and the following 10184870Syongari * disclaimer. 11184870Syongari * 2. Redistributions in binary form must reproduce the above copyright 12184870Syongari * notice, this list of conditions and the following disclaimer in the 13184870Syongari * documentation and/or other materials provided with the distribution. 14184870Syongari * 15184870Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16184870Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17184870Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18184870Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19184870Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20184870Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21184870Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22184870Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23184870Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24184870Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25184870Syongari * SUCH DAMAGE. 26184870Syongari */ 27184870Syongari 28184870Syongari/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29184870Syongari 30184870Syongari#include <sys/cdefs.h> 31184870Syongari__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 221407 2011-05-03 19:51:29Z marius $"); 32184870Syongari 33184870Syongari#include <sys/param.h> 34184870Syongari#include <sys/systm.h> 35184870Syongari#include <sys/bus.h> 36184870Syongari#include <sys/endian.h> 37184870Syongari#include <sys/kernel.h> 38184870Syongari#include <sys/malloc.h> 39184870Syongari#include <sys/mbuf.h> 40184870Syongari#include <sys/module.h> 41184870Syongari#include <sys/rman.h> 42184870Syongari#include <sys/queue.h> 43184870Syongari#include <sys/socket.h> 44184870Syongari#include <sys/sockio.h> 45184870Syongari#include <sys/sysctl.h> 46184870Syongari#include <sys/taskqueue.h> 47184870Syongari 48184870Syongari#include <net/bpf.h> 49184870Syongari#include <net/if.h> 50184870Syongari#include <net/if_arp.h> 51184870Syongari#include <net/ethernet.h> 52184870Syongari#include <net/if_dl.h> 53184870Syongari#include <net/if_llc.h> 54184870Syongari#include <net/if_media.h> 55184870Syongari#include <net/if_types.h> 56184870Syongari#include <net/if_vlan_var.h> 57184870Syongari 58184870Syongari#include <netinet/in.h> 59184870Syongari#include <netinet/in_systm.h> 60184870Syongari#include <netinet/ip.h> 61184870Syongari#include <netinet/tcp.h> 62184870Syongari 63184870Syongari#include <dev/mii/mii.h> 64184870Syongari#include <dev/mii/miivar.h> 65184870Syongari 66184870Syongari#include <dev/pci/pcireg.h> 67184870Syongari#include <dev/pci/pcivar.h> 68184870Syongari 69184870Syongari#include <machine/bus.h> 70184870Syongari#include <machine/in_cksum.h> 71184870Syongari 72184870Syongari#include <dev/ale/if_alereg.h> 73184870Syongari#include <dev/ale/if_alevar.h> 74184870Syongari 75184870Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 76184870Syongari#include "miibus_if.h" 77184870Syongari 78184870Syongari/* For more information about Tx checksum offload issues see ale_encap(). */ 79184870Syongari#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 80184870Syongari 81184870SyongariMODULE_DEPEND(ale, pci, 1, 1, 1); 82184870SyongariMODULE_DEPEND(ale, ether, 1, 1, 1); 83184870SyongariMODULE_DEPEND(ale, miibus, 1, 1, 1); 84184870Syongari 85184870Syongari/* Tunables. */ 86184870Syongaristatic int msi_disable = 0; 87184870Syongaristatic int msix_disable = 0; 88184870SyongariTUNABLE_INT("hw.ale.msi_disable", &msi_disable); 89184870SyongariTUNABLE_INT("hw.ale.msix_disable", &msix_disable); 90184870Syongari 91184870Syongari/* 92184870Syongari * Devices supported by this driver. 93184870Syongari */ 94184870Syongaristatic struct ale_dev { 95184870Syongari uint16_t ale_vendorid; 96184870Syongari uint16_t ale_deviceid; 97184870Syongari const char *ale_name; 98184870Syongari} ale_devs[] = { 99184870Syongari { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 100184870Syongari "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 101184870Syongari}; 102184870Syongari 103184870Syongaristatic int ale_attach(device_t); 104184870Syongaristatic int ale_check_boundary(struct ale_softc *); 105184870Syongaristatic int ale_detach(device_t); 106184870Syongaristatic int ale_dma_alloc(struct ale_softc *); 107184870Syongaristatic void ale_dma_free(struct ale_softc *); 108184870Syongaristatic void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109184870Syongaristatic int ale_encap(struct ale_softc *, struct mbuf **); 110184870Syongaristatic void ale_get_macaddr(struct ale_softc *); 111184870Syongaristatic void ale_init(void *); 112184870Syongaristatic void ale_init_locked(struct ale_softc *); 113184870Syongaristatic void ale_init_rx_pages(struct ale_softc *); 114184870Syongaristatic void ale_init_tx_ring(struct ale_softc *); 115184870Syongaristatic void ale_int_task(void *, int); 116184870Syongaristatic int ale_intr(void *); 117184870Syongaristatic int ale_ioctl(struct ifnet *, u_long, caddr_t); 118184870Syongaristatic void ale_link_task(void *, int); 119184870Syongaristatic void ale_mac_config(struct ale_softc *); 120184870Syongaristatic int ale_miibus_readreg(device_t, int, int); 121184870Syongaristatic void ale_miibus_statchg(device_t); 122184870Syongaristatic int ale_miibus_writereg(device_t, int, int, int); 123184870Syongaristatic int ale_mediachange(struct ifnet *); 124184870Syongaristatic void ale_mediastatus(struct ifnet *, struct ifmediareq *); 125184870Syongaristatic void ale_phy_reset(struct ale_softc *); 126184870Syongaristatic int ale_probe(device_t); 127184870Syongaristatic void ale_reset(struct ale_softc *); 128184870Syongaristatic int ale_resume(device_t); 129184870Syongaristatic void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 130184870Syongari uint32_t, uint32_t *); 131184870Syongaristatic void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 132184870Syongaristatic int ale_rxeof(struct ale_softc *sc, int); 133184870Syongaristatic void ale_rxfilter(struct ale_softc *); 134184870Syongaristatic void ale_rxvlan(struct ale_softc *); 135184870Syongaristatic void ale_setlinkspeed(struct ale_softc *); 136184870Syongaristatic void ale_setwol(struct ale_softc *); 137184870Syongaristatic int ale_shutdown(device_t); 138184870Syongaristatic void ale_start(struct ifnet *); 139216925Sjhbstatic void ale_start_locked(struct ifnet *); 140184870Syongaristatic void ale_stats_clear(struct ale_softc *); 141184870Syongaristatic void ale_stats_update(struct ale_softc *); 142184870Syongaristatic void ale_stop(struct ale_softc *); 143184870Syongaristatic void ale_stop_mac(struct ale_softc *); 144184870Syongaristatic int ale_suspend(device_t); 145184870Syongaristatic void ale_sysctl_node(struct ale_softc *); 146184870Syongaristatic void ale_tick(void *); 147184870Syongaristatic void ale_txeof(struct ale_softc *); 148184870Syongaristatic void ale_watchdog(struct ale_softc *); 149184870Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150184870Syongaristatic int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 151184870Syongaristatic int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 152184870Syongari 153184870Syongaristatic device_method_t ale_methods[] = { 154184870Syongari /* Device interface. */ 155184870Syongari DEVMETHOD(device_probe, ale_probe), 156184870Syongari DEVMETHOD(device_attach, ale_attach), 157184870Syongari DEVMETHOD(device_detach, ale_detach), 158184870Syongari DEVMETHOD(device_shutdown, ale_shutdown), 159184870Syongari DEVMETHOD(device_suspend, ale_suspend), 160184870Syongari DEVMETHOD(device_resume, ale_resume), 161184870Syongari 162184870Syongari /* MII interface. */ 163184870Syongari DEVMETHOD(miibus_readreg, ale_miibus_readreg), 164184870Syongari DEVMETHOD(miibus_writereg, ale_miibus_writereg), 165184870Syongari DEVMETHOD(miibus_statchg, ale_miibus_statchg), 166184870Syongari 167184870Syongari { NULL, NULL } 168184870Syongari}; 169184870Syongari 170184870Syongaristatic driver_t ale_driver = { 171184870Syongari "ale", 172184870Syongari ale_methods, 173184870Syongari sizeof(struct ale_softc) 174184870Syongari}; 175184870Syongari 176184870Syongaristatic devclass_t ale_devclass; 177184870Syongari 178184870SyongariDRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0); 179184870SyongariDRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 180184870Syongari 181184870Syongaristatic struct resource_spec ale_res_spec_mem[] = { 182184870Syongari { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 183184870Syongari { -1, 0, 0 } 184184870Syongari}; 185184870Syongari 186184870Syongaristatic struct resource_spec ale_irq_spec_legacy[] = { 187184870Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 188184870Syongari { -1, 0, 0 } 189184870Syongari}; 190184870Syongari 191184870Syongaristatic struct resource_spec ale_irq_spec_msi[] = { 192184870Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 193184870Syongari { -1, 0, 0 } 194184870Syongari}; 195184870Syongari 196184870Syongaristatic struct resource_spec ale_irq_spec_msix[] = { 197184870Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 198184870Syongari { -1, 0, 0 } 199184870Syongari}; 200184870Syongari 201184870Syongaristatic int 202184870Syongariale_miibus_readreg(device_t dev, int phy, int reg) 203184870Syongari{ 204184870Syongari struct ale_softc *sc; 205184870Syongari uint32_t v; 206184870Syongari int i; 207184870Syongari 208184870Syongari sc = device_get_softc(dev); 209184870Syongari 210184870Syongari CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 211184870Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 212184870Syongari for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 213184870Syongari DELAY(5); 214184870Syongari v = CSR_READ_4(sc, ALE_MDIO); 215184870Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 216184870Syongari break; 217184870Syongari } 218184870Syongari 219184870Syongari if (i == 0) { 220184870Syongari device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 221184870Syongari return (0); 222184870Syongari } 223184870Syongari 224184870Syongari return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 225184870Syongari} 226184870Syongari 227184870Syongaristatic int 228184870Syongariale_miibus_writereg(device_t dev, int phy, int reg, int val) 229184870Syongari{ 230184870Syongari struct ale_softc *sc; 231184870Syongari uint32_t v; 232184870Syongari int i; 233184870Syongari 234184870Syongari sc = device_get_softc(dev); 235184870Syongari 236184870Syongari CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 237184870Syongari (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 238184870Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 239184870Syongari for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 240184870Syongari DELAY(5); 241184870Syongari v = CSR_READ_4(sc, ALE_MDIO); 242184870Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 243184870Syongari break; 244184870Syongari } 245184870Syongari 246184870Syongari if (i == 0) 247184870Syongari device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 248184870Syongari 249184870Syongari return (0); 250184870Syongari} 251184870Syongari 252184870Syongaristatic void 253184870Syongariale_miibus_statchg(device_t dev) 254184870Syongari{ 255184870Syongari struct ale_softc *sc; 256184870Syongari 257184870Syongari sc = device_get_softc(dev); 258184870Syongari 259184870Syongari taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task); 260184870Syongari} 261184870Syongari 262184870Syongaristatic void 263184870Syongariale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 264184870Syongari{ 265184870Syongari struct ale_softc *sc; 266184870Syongari struct mii_data *mii; 267184870Syongari 268184870Syongari sc = ifp->if_softc; 269184870Syongari ALE_LOCK(sc); 270184870Syongari mii = device_get_softc(sc->ale_miibus); 271184870Syongari 272184870Syongari mii_pollstat(mii); 273184870Syongari ALE_UNLOCK(sc); 274184870Syongari ifmr->ifm_status = mii->mii_media_status; 275184870Syongari ifmr->ifm_active = mii->mii_media_active; 276184870Syongari} 277184870Syongari 278184870Syongaristatic int 279184870Syongariale_mediachange(struct ifnet *ifp) 280184870Syongari{ 281184870Syongari struct ale_softc *sc; 282184870Syongari struct mii_data *mii; 283184870Syongari struct mii_softc *miisc; 284184870Syongari int error; 285184870Syongari 286184870Syongari sc = ifp->if_softc; 287184870Syongari ALE_LOCK(sc); 288184870Syongari mii = device_get_softc(sc->ale_miibus); 289221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 290221407Smarius PHY_RESET(miisc); 291184870Syongari error = mii_mediachg(mii); 292184870Syongari ALE_UNLOCK(sc); 293184870Syongari 294184870Syongari return (error); 295184870Syongari} 296184870Syongari 297184870Syongaristatic int 298184870Syongariale_probe(device_t dev) 299184870Syongari{ 300184870Syongari struct ale_dev *sp; 301184870Syongari int i; 302184870Syongari uint16_t vendor, devid; 303184870Syongari 304184870Syongari vendor = pci_get_vendor(dev); 305184870Syongari devid = pci_get_device(dev); 306184870Syongari sp = ale_devs; 307184870Syongari for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 308184870Syongari if (vendor == sp->ale_vendorid && 309184870Syongari devid == sp->ale_deviceid) { 310184870Syongari device_set_desc(dev, sp->ale_name); 311184870Syongari return (BUS_PROBE_DEFAULT); 312184870Syongari } 313184870Syongari sp++; 314184870Syongari } 315184870Syongari 316184870Syongari return (ENXIO); 317184870Syongari} 318184870Syongari 319184870Syongaristatic void 320184870Syongariale_get_macaddr(struct ale_softc *sc) 321184870Syongari{ 322184870Syongari uint32_t ea[2], reg; 323184870Syongari int i, vpdc; 324184870Syongari 325184870Syongari reg = CSR_READ_4(sc, ALE_SPI_CTRL); 326184870Syongari if ((reg & SPI_VPD_ENB) != 0) { 327184870Syongari reg &= ~SPI_VPD_ENB; 328184870Syongari CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 329184870Syongari } 330184870Syongari 331219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 332184870Syongari /* 333184870Syongari * PCI VPD capability found, let TWSI reload EEPROM. 334184870Syongari * This will set ethernet address of controller. 335184870Syongari */ 336184870Syongari CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 337184870Syongari TWSI_CTRL_SW_LD_START); 338184870Syongari for (i = 100; i > 0; i--) { 339184870Syongari DELAY(1000); 340184870Syongari reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 341184870Syongari if ((reg & TWSI_CTRL_SW_LD_START) == 0) 342184870Syongari break; 343184870Syongari } 344184870Syongari if (i == 0) 345184870Syongari device_printf(sc->ale_dev, 346184870Syongari "reloading EEPROM timeout!\n"); 347184870Syongari } else { 348184870Syongari if (bootverbose) 349184870Syongari device_printf(sc->ale_dev, 350184870Syongari "PCI VPD capability not found!\n"); 351184870Syongari } 352184870Syongari 353184870Syongari ea[0] = CSR_READ_4(sc, ALE_PAR0); 354184870Syongari ea[1] = CSR_READ_4(sc, ALE_PAR1); 355184870Syongari sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 356184870Syongari sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 357184870Syongari sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 358184870Syongari sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 359184870Syongari sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 360184870Syongari sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 361184870Syongari} 362184870Syongari 363184870Syongaristatic void 364184870Syongariale_phy_reset(struct ale_softc *sc) 365184870Syongari{ 366184870Syongari 367184870Syongari /* Reset magic from Linux. */ 368184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 369184870Syongari GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 370184870Syongari GPHY_CTRL_PHY_PLL_ON); 371184870Syongari DELAY(1000); 372184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 373184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 374184870Syongari GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 375184870Syongari DELAY(1000); 376185576Syongari 377185576Syongari#define ATPHY_DBG_ADDR 0x1D 378185576Syongari#define ATPHY_DBG_DATA 0x1E 379185576Syongari 380185576Syongari /* Enable hibernation mode. */ 381185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 382185576Syongari ATPHY_DBG_ADDR, 0x0B); 383185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 384185576Syongari ATPHY_DBG_DATA, 0xBC00); 385185576Syongari /* Set Class A/B for all modes. */ 386185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 387185576Syongari ATPHY_DBG_ADDR, 0x00); 388185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 389185576Syongari ATPHY_DBG_DATA, 0x02EF); 390185576Syongari /* Enable 10BT power saving. */ 391185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 392185576Syongari ATPHY_DBG_ADDR, 0x12); 393185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 394185576Syongari ATPHY_DBG_DATA, 0x4C04); 395185576Syongari /* Adjust 1000T power. */ 396185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 397185576Syongari ATPHY_DBG_ADDR, 0x04); 398185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 399185576Syongari ATPHY_DBG_ADDR, 0x8BBB); 400185576Syongari /* 10BT center tap voltage. */ 401185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 402185576Syongari ATPHY_DBG_ADDR, 0x05); 403185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 404185576Syongari ATPHY_DBG_ADDR, 0x2C46); 405185576Syongari 406185576Syongari#undef ATPHY_DBG_ADDR 407185576Syongari#undef ATPHY_DBG_DATA 408185576Syongari DELAY(1000); 409184870Syongari} 410184870Syongari 411184870Syongaristatic int 412184870Syongariale_attach(device_t dev) 413184870Syongari{ 414184870Syongari struct ale_softc *sc; 415184870Syongari struct ifnet *ifp; 416184870Syongari uint16_t burst; 417184870Syongari int error, i, msic, msixc, pmc; 418184870Syongari uint32_t rxf_len, txf_len; 419184870Syongari 420184870Syongari error = 0; 421184870Syongari sc = device_get_softc(dev); 422184870Syongari sc->ale_dev = dev; 423184870Syongari 424184870Syongari mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 425184870Syongari MTX_DEF); 426184870Syongari callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 427184870Syongari TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 428184870Syongari TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc); 429184870Syongari 430184870Syongari /* Map the device. */ 431184870Syongari pci_enable_busmaster(dev); 432184870Syongari sc->ale_res_spec = ale_res_spec_mem; 433184870Syongari sc->ale_irq_spec = ale_irq_spec_legacy; 434184870Syongari error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 435184870Syongari if (error != 0) { 436184870Syongari device_printf(dev, "cannot allocate memory resources.\n"); 437184870Syongari goto fail; 438184870Syongari } 439184870Syongari 440184870Syongari /* Set PHY address. */ 441184870Syongari sc->ale_phyaddr = ALE_PHY_ADDR; 442184870Syongari 443184870Syongari /* Reset PHY. */ 444184870Syongari ale_phy_reset(sc); 445184870Syongari 446184870Syongari /* Reset the ethernet controller. */ 447184870Syongari ale_reset(sc); 448184870Syongari 449184870Syongari /* Get PCI and chip id/revision. */ 450184870Syongari sc->ale_rev = pci_get_revid(dev); 451184870Syongari if (sc->ale_rev >= 0xF0) { 452184870Syongari /* L2E Rev. B. AR8114 */ 453184870Syongari sc->ale_flags |= ALE_FLAG_FASTETHER; 454184870Syongari } else { 455184870Syongari if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 456184870Syongari /* L1E AR8121 */ 457184870Syongari sc->ale_flags |= ALE_FLAG_JUMBO; 458184870Syongari } else { 459184870Syongari /* L2E Rev. A. AR8113 */ 460184870Syongari sc->ale_flags |= ALE_FLAG_FASTETHER; 461184870Syongari } 462184870Syongari } 463184870Syongari /* 464184870Syongari * All known controllers seems to require 4 bytes alignment 465184870Syongari * of Tx buffers to make Tx checksum offload with custom 466184870Syongari * checksum generation method work. 467184870Syongari */ 468184870Syongari sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 469184870Syongari /* 470184870Syongari * All known controllers seems to have issues on Rx checksum 471184870Syongari * offload for fragmented IP datagrams. 472184870Syongari */ 473184870Syongari sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 474184870Syongari /* 475184870Syongari * Don't use Tx CMB. It is known to cause RRS update failure 476184870Syongari * under certain circumstances. Typical phenomenon of the 477184870Syongari * issue would be unexpected sequence number encountered in 478184870Syongari * Rx handler. 479184870Syongari */ 480184870Syongari sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 481184870Syongari sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 482184870Syongari MASTER_CHIP_REV_SHIFT; 483184870Syongari if (bootverbose) { 484184870Syongari device_printf(dev, "PCI device revision : 0x%04x\n", 485184870Syongari sc->ale_rev); 486184870Syongari device_printf(dev, "Chip id/revision : 0x%04x\n", 487184870Syongari sc->ale_chip_rev); 488184870Syongari } 489184870Syongari txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 490184870Syongari rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 491184870Syongari /* 492184870Syongari * Uninitialized hardware returns an invalid chip id/revision 493184870Syongari * as well as 0xFFFFFFFF for Tx/Rx fifo length. 494184870Syongari */ 495184870Syongari if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 496184870Syongari rxf_len == 0xFFFFFFF) { 497184870Syongari device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 498184870Syongari "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 499184870Syongari txf_len, rxf_len); 500184870Syongari error = ENXIO; 501184870Syongari goto fail; 502184870Syongari } 503184870Syongari device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 504184870Syongari 505184870Syongari /* Allocate IRQ resources. */ 506184870Syongari msixc = pci_msix_count(dev); 507184870Syongari msic = pci_msi_count(dev); 508184870Syongari if (bootverbose) { 509184870Syongari device_printf(dev, "MSIX count : %d\n", msixc); 510184870Syongari device_printf(dev, "MSI count : %d\n", msic); 511184870Syongari } 512184870Syongari 513184870Syongari /* Prefer MSIX over MSI. */ 514184870Syongari if (msix_disable == 0 || msi_disable == 0) { 515184870Syongari if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 516184870Syongari pci_alloc_msix(dev, &msixc) == 0) { 517184870Syongari if (msic == ALE_MSIX_MESSAGES) { 518184870Syongari device_printf(dev, "Using %d MSIX messages.\n", 519184870Syongari msixc); 520184870Syongari sc->ale_flags |= ALE_FLAG_MSIX; 521184870Syongari sc->ale_irq_spec = ale_irq_spec_msix; 522184870Syongari } else 523184870Syongari pci_release_msi(dev); 524184870Syongari } 525184870Syongari if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 526184870Syongari msic == ALE_MSI_MESSAGES && 527184870Syongari pci_alloc_msi(dev, &msic) == 0) { 528184870Syongari if (msic == ALE_MSI_MESSAGES) { 529184870Syongari device_printf(dev, "Using %d MSI messages.\n", 530184870Syongari msic); 531184870Syongari sc->ale_flags |= ALE_FLAG_MSI; 532184870Syongari sc->ale_irq_spec = ale_irq_spec_msi; 533184870Syongari } else 534184870Syongari pci_release_msi(dev); 535184870Syongari } 536184870Syongari } 537184870Syongari 538184870Syongari error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 539184870Syongari if (error != 0) { 540184870Syongari device_printf(dev, "cannot allocate IRQ resources.\n"); 541184870Syongari goto fail; 542184870Syongari } 543184870Syongari 544184870Syongari /* Get DMA parameters from PCIe device control register. */ 545219902Sjhb if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 546184870Syongari sc->ale_flags |= ALE_FLAG_PCIE; 547184870Syongari burst = pci_read_config(dev, i + 0x08, 2); 548184870Syongari /* Max read request size. */ 549184870Syongari sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 550184870Syongari DMA_CFG_RD_BURST_SHIFT; 551184870Syongari /* Max payload size. */ 552184870Syongari sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 553184870Syongari DMA_CFG_WR_BURST_SHIFT; 554184870Syongari if (bootverbose) { 555184870Syongari device_printf(dev, "Read request size : %d bytes.\n", 556184870Syongari 128 << ((burst >> 12) & 0x07)); 557184870Syongari device_printf(dev, "TLP payload size : %d bytes.\n", 558184870Syongari 128 << ((burst >> 5) & 0x07)); 559184870Syongari } 560184870Syongari } else { 561184870Syongari sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 562184870Syongari sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 563184870Syongari } 564184870Syongari 565184870Syongari /* Create device sysctl node. */ 566184870Syongari ale_sysctl_node(sc); 567184870Syongari 568184870Syongari if ((error = ale_dma_alloc(sc) != 0)) 569184870Syongari goto fail; 570184870Syongari 571184870Syongari /* Load station address. */ 572184870Syongari ale_get_macaddr(sc); 573184870Syongari 574184870Syongari ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 575184870Syongari if (ifp == NULL) { 576184870Syongari device_printf(dev, "cannot allocate ifnet structure.\n"); 577184870Syongari error = ENXIO; 578184870Syongari goto fail; 579184870Syongari } 580184870Syongari 581184870Syongari ifp->if_softc = sc; 582184870Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 583184870Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 584184870Syongari ifp->if_ioctl = ale_ioctl; 585184870Syongari ifp->if_start = ale_start; 586184870Syongari ifp->if_init = ale_init; 587184870Syongari ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 588184870Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 589184870Syongari IFQ_SET_READY(&ifp->if_snd); 590184870Syongari ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 591184870Syongari ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 592219902Sjhb if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 593184870Syongari sc->ale_flags |= ALE_FLAG_PMCAP; 594184870Syongari ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 595184870Syongari } 596184870Syongari ifp->if_capenable = ifp->if_capabilities; 597184870Syongari 598184870Syongari /* Set up MII bus. */ 599213893Smarius error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 600213893Smarius ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 601213893Smarius 0); 602213893Smarius if (error != 0) { 603213893Smarius device_printf(dev, "attaching PHYs failed\n"); 604184870Syongari goto fail; 605184870Syongari } 606184870Syongari 607184870Syongari ether_ifattach(ifp, sc->ale_eaddr); 608184870Syongari 609184870Syongari /* VLAN capability setup. */ 610204378Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 611204378Syongari IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 612184870Syongari ifp->if_capenable = ifp->if_capabilities; 613195153Syongari /* 614195153Syongari * Even though controllers supported by ale(3) have Rx checksum 615195153Syongari * offload bug the workaround for fragmented frames seemed to 616195153Syongari * work so far. However it seems Rx checksum offload does not 617195153Syongari * work under certain conditions. So disable Rx checksum offload 618195153Syongari * until I find more clue about it but allow users to override it. 619195153Syongari */ 620195153Syongari ifp->if_capenable &= ~IFCAP_RXCSUM; 621184870Syongari 622184870Syongari /* Tell the upper layer(s) we support long frames. */ 623184870Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 624184870Syongari 625184870Syongari /* Create local taskq. */ 626184870Syongari sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 627184870Syongari taskqueue_thread_enqueue, &sc->ale_tq); 628184870Syongari if (sc->ale_tq == NULL) { 629184870Syongari device_printf(dev, "could not create taskqueue.\n"); 630184870Syongari ether_ifdetach(ifp); 631184870Syongari error = ENXIO; 632184870Syongari goto fail; 633184870Syongari } 634184870Syongari taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 635184870Syongari device_get_nameunit(sc->ale_dev)); 636184870Syongari 637184870Syongari if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 638184870Syongari msic = ALE_MSIX_MESSAGES; 639184870Syongari else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 640184870Syongari msic = ALE_MSI_MESSAGES; 641184870Syongari else 642184870Syongari msic = 1; 643184870Syongari for (i = 0; i < msic; i++) { 644184870Syongari error = bus_setup_intr(dev, sc->ale_irq[i], 645184870Syongari INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 646184870Syongari &sc->ale_intrhand[i]); 647184870Syongari if (error != 0) 648184870Syongari break; 649184870Syongari } 650184870Syongari if (error != 0) { 651184870Syongari device_printf(dev, "could not set up interrupt handler.\n"); 652184870Syongari taskqueue_free(sc->ale_tq); 653184870Syongari sc->ale_tq = NULL; 654184870Syongari ether_ifdetach(ifp); 655184870Syongari goto fail; 656184870Syongari } 657184870Syongari 658184870Syongarifail: 659184870Syongari if (error != 0) 660184870Syongari ale_detach(dev); 661184870Syongari 662184870Syongari return (error); 663184870Syongari} 664184870Syongari 665184870Syongaristatic int 666184870Syongariale_detach(device_t dev) 667184870Syongari{ 668184870Syongari struct ale_softc *sc; 669184870Syongari struct ifnet *ifp; 670184870Syongari int i, msic; 671184870Syongari 672184870Syongari sc = device_get_softc(dev); 673184870Syongari 674184870Syongari ifp = sc->ale_ifp; 675184870Syongari if (device_is_attached(dev)) { 676217542Sjhb ether_ifdetach(ifp); 677184870Syongari ALE_LOCK(sc); 678184870Syongari ale_stop(sc); 679184870Syongari ALE_UNLOCK(sc); 680184870Syongari callout_drain(&sc->ale_tick_ch); 681184870Syongari taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 682184870Syongari taskqueue_drain(taskqueue_swi, &sc->ale_link_task); 683184870Syongari } 684184870Syongari 685184870Syongari if (sc->ale_tq != NULL) { 686184870Syongari taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 687184870Syongari taskqueue_free(sc->ale_tq); 688184870Syongari sc->ale_tq = NULL; 689184870Syongari } 690184870Syongari 691184870Syongari if (sc->ale_miibus != NULL) { 692184870Syongari device_delete_child(dev, sc->ale_miibus); 693184870Syongari sc->ale_miibus = NULL; 694184870Syongari } 695184870Syongari bus_generic_detach(dev); 696184870Syongari ale_dma_free(sc); 697184870Syongari 698184870Syongari if (ifp != NULL) { 699184870Syongari if_free(ifp); 700184870Syongari sc->ale_ifp = NULL; 701184870Syongari } 702184870Syongari 703184870Syongari if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 704184870Syongari msic = ALE_MSIX_MESSAGES; 705184870Syongari else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 706184870Syongari msic = ALE_MSI_MESSAGES; 707184870Syongari else 708184870Syongari msic = 1; 709184870Syongari for (i = 0; i < msic; i++) { 710184870Syongari if (sc->ale_intrhand[i] != NULL) { 711184870Syongari bus_teardown_intr(dev, sc->ale_irq[i], 712184870Syongari sc->ale_intrhand[i]); 713184870Syongari sc->ale_intrhand[i] = NULL; 714184870Syongari } 715184870Syongari } 716184870Syongari 717184870Syongari bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 718184870Syongari if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 719184870Syongari pci_release_msi(dev); 720184870Syongari bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 721184870Syongari mtx_destroy(&sc->ale_mtx); 722184870Syongari 723184870Syongari return (0); 724184870Syongari} 725184870Syongari 726184870Syongari#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 727184870Syongari SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 728184870Syongari 729217323Smdf#if __FreeBSD_version >= 900030 730184870Syongari#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 731217323Smdf SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 732217323Smdf#elif __FreeBSD_version > 800000 733217323Smdf#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 734184870Syongari SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 735184870Syongari#else 736184870Syongari#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 737184870Syongari SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 738184870Syongari#endif 739184870Syongari 740184870Syongaristatic void 741184870Syongariale_sysctl_node(struct ale_softc *sc) 742184870Syongari{ 743184870Syongari struct sysctl_ctx_list *ctx; 744184870Syongari struct sysctl_oid_list *child, *parent; 745184870Syongari struct sysctl_oid *tree; 746184870Syongari struct ale_hw_stats *stats; 747184870Syongari int error; 748184870Syongari 749184870Syongari stats = &sc->ale_stats; 750184870Syongari ctx = device_get_sysctl_ctx(sc->ale_dev); 751184870Syongari child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 752184870Syongari 753184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 754184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 755184870Syongari sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 756184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 757184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 758184870Syongari sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 759184870Syongari /* Pull in device tunables. */ 760184870Syongari sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 761184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 762184870Syongari device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 763184870Syongari if (error == 0) { 764184870Syongari if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 765184870Syongari sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 766184870Syongari device_printf(sc->ale_dev, "int_rx_mod value out of " 767184870Syongari "range; using default: %d\n", 768184870Syongari ALE_IM_RX_TIMER_DEFAULT); 769184870Syongari sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 770184870Syongari } 771184870Syongari } 772184870Syongari sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 773184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 774184870Syongari device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 775184870Syongari if (error == 0) { 776184870Syongari if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 777184870Syongari sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 778184870Syongari device_printf(sc->ale_dev, "int_tx_mod value out of " 779184870Syongari "range; using default: %d\n", 780184870Syongari ALE_IM_TX_TIMER_DEFAULT); 781184870Syongari sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 782184870Syongari } 783184870Syongari } 784184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 785184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 786184870Syongari sysctl_hw_ale_proc_limit, "I", 787184870Syongari "max number of Rx events to process"); 788184870Syongari /* Pull in device tunables. */ 789184870Syongari sc->ale_process_limit = ALE_PROC_DEFAULT; 790184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 791184870Syongari device_get_unit(sc->ale_dev), "process_limit", 792184870Syongari &sc->ale_process_limit); 793184870Syongari if (error == 0) { 794184870Syongari if (sc->ale_process_limit < ALE_PROC_MIN || 795184870Syongari sc->ale_process_limit > ALE_PROC_MAX) { 796184870Syongari device_printf(sc->ale_dev, 797184870Syongari "process_limit value out of range; " 798184870Syongari "using default: %d\n", ALE_PROC_DEFAULT); 799184870Syongari sc->ale_process_limit = ALE_PROC_DEFAULT; 800184870Syongari } 801184870Syongari } 802184870Syongari 803184870Syongari /* Misc statistics. */ 804184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 805184870Syongari &stats->reset_brk_seq, 806184870Syongari "Controller resets due to broken Rx sequnce number"); 807184870Syongari 808184870Syongari tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 809184870Syongari NULL, "ATE statistics"); 810184870Syongari parent = SYSCTL_CHILDREN(tree); 811184870Syongari 812184870Syongari /* Rx statistics. */ 813184870Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 814184870Syongari NULL, "Rx MAC statistics"); 815184870Syongari child = SYSCTL_CHILDREN(tree); 816184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 817184870Syongari &stats->rx_frames, "Good frames"); 818184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 819184870Syongari &stats->rx_bcast_frames, "Good broadcast frames"); 820184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 821184870Syongari &stats->rx_mcast_frames, "Good multicast frames"); 822184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 823184870Syongari &stats->rx_pause_frames, "Pause control frames"); 824184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 825184870Syongari &stats->rx_control_frames, "Control frames"); 826184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 827184870Syongari &stats->rx_crcerrs, "CRC errors"); 828184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 829184870Syongari &stats->rx_lenerrs, "Frames with length mismatched"); 830184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 831184870Syongari &stats->rx_bytes, "Good octets"); 832184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 833184870Syongari &stats->rx_bcast_bytes, "Good broadcast octets"); 834184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 835184870Syongari &stats->rx_mcast_bytes, "Good multicast octets"); 836184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 837184870Syongari &stats->rx_runts, "Too short frames"); 838184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 839184870Syongari &stats->rx_fragments, "Fragmented frames"); 840184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 841184870Syongari &stats->rx_pkts_64, "64 bytes frames"); 842184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 843184870Syongari &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 844184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 845184870Syongari &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 846184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 847184870Syongari &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 848184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 849184870Syongari &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 850184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 851184870Syongari &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 852184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 853184870Syongari &stats->rx_pkts_1519_max, "1519 to max frames"); 854184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 855184870Syongari &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 856184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 857184870Syongari &stats->rx_fifo_oflows, "FIFO overflows"); 858184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 859184870Syongari &stats->rx_rrs_errs, "Return status write-back errors"); 860184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 861184870Syongari &stats->rx_alignerrs, "Alignment errors"); 862184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 863184870Syongari &stats->rx_pkts_filtered, 864184870Syongari "Frames dropped due to address filtering"); 865184870Syongari 866184870Syongari /* Tx statistics. */ 867184870Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 868184870Syongari NULL, "Tx MAC statistics"); 869184870Syongari child = SYSCTL_CHILDREN(tree); 870184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 871184870Syongari &stats->tx_frames, "Good frames"); 872184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 873184870Syongari &stats->tx_bcast_frames, "Good broadcast frames"); 874184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 875184870Syongari &stats->tx_mcast_frames, "Good multicast frames"); 876184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 877184870Syongari &stats->tx_pause_frames, "Pause control frames"); 878184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 879184870Syongari &stats->tx_control_frames, "Control frames"); 880184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 881184870Syongari &stats->tx_excess_defer, "Frames with excessive derferrals"); 882184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 883184870Syongari &stats->tx_excess_defer, "Frames with derferrals"); 884184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 885184870Syongari &stats->tx_bytes, "Good octets"); 886184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 887184870Syongari &stats->tx_bcast_bytes, "Good broadcast octets"); 888184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 889184870Syongari &stats->tx_mcast_bytes, "Good multicast octets"); 890184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 891184870Syongari &stats->tx_pkts_64, "64 bytes frames"); 892184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 893184870Syongari &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 894184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 895184870Syongari &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 896184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 897184870Syongari &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 898184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 899184870Syongari &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 900184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 901184870Syongari &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 902184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 903184870Syongari &stats->tx_pkts_1519_max, "1519 to max frames"); 904184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 905184870Syongari &stats->tx_single_colls, "Single collisions"); 906184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 907184870Syongari &stats->tx_multi_colls, "Multiple collisions"); 908184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 909184870Syongari &stats->tx_late_colls, "Late collisions"); 910184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 911184870Syongari &stats->tx_excess_colls, "Excessive collisions"); 912184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 913184870Syongari &stats->tx_abort, "Aborted frames due to Excessive collisions"); 914184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 915184870Syongari &stats->tx_underrun, "FIFO underruns"); 916184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 917184870Syongari &stats->tx_desc_underrun, "Descriptor write-back errors"); 918184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 919184870Syongari &stats->tx_lenerrs, "Frames with length mismatched"); 920184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 921184870Syongari &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 922184870Syongari} 923184870Syongari 924184870Syongari#undef ALE_SYSCTL_STAT_ADD32 925184870Syongari#undef ALE_SYSCTL_STAT_ADD64 926184870Syongari 927184870Syongaristruct ale_dmamap_arg { 928184870Syongari bus_addr_t ale_busaddr; 929184870Syongari}; 930184870Syongari 931184870Syongaristatic void 932184870Syongariale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 933184870Syongari{ 934184870Syongari struct ale_dmamap_arg *ctx; 935184870Syongari 936184870Syongari if (error != 0) 937184870Syongari return; 938184870Syongari 939184870Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 940184870Syongari 941184870Syongari ctx = (struct ale_dmamap_arg *)arg; 942184870Syongari ctx->ale_busaddr = segs[0].ds_addr; 943184870Syongari} 944184870Syongari 945184870Syongari/* 946184870Syongari * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 947184870Syongari * which specifies high address region of DMA blocks. Therefore these 948184870Syongari * blocks should have the same high address of given 4GB address 949184870Syongari * space(i.e. crossing 4GB boundary is not allowed). 950184870Syongari */ 951184870Syongaristatic int 952184870Syongariale_check_boundary(struct ale_softc *sc) 953184870Syongari{ 954184870Syongari bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 955184870Syongari bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 956184870Syongari 957184870Syongari rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 958184870Syongari sc->ale_pagesize; 959184870Syongari rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 960184870Syongari sc->ale_pagesize; 961184870Syongari tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 962184870Syongari tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 963184870Syongari rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 964184870Syongari rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 965184870Syongari 966184870Syongari if ((ALE_ADDR_HI(tx_ring_end) != 967184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 968184870Syongari (ALE_ADDR_HI(rx_page_end[0]) != 969184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 970184870Syongari (ALE_ADDR_HI(rx_page_end[1]) != 971184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 972184870Syongari (ALE_ADDR_HI(tx_cmb_end) != 973184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 974184870Syongari (ALE_ADDR_HI(rx_cmb_end[0]) != 975184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 976184870Syongari (ALE_ADDR_HI(rx_cmb_end[1]) != 977184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 978184870Syongari return (EFBIG); 979184870Syongari 980184870Syongari if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 981184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 982184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 983184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 984184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 985184870Syongari return (EFBIG); 986184870Syongari 987184870Syongari return (0); 988184870Syongari} 989184870Syongari 990184870Syongaristatic int 991184870Syongariale_dma_alloc(struct ale_softc *sc) 992184870Syongari{ 993184870Syongari struct ale_txdesc *txd; 994184870Syongari bus_addr_t lowaddr; 995184870Syongari struct ale_dmamap_arg ctx; 996184870Syongari int error, guard_size, i; 997184870Syongari 998184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 999184870Syongari guard_size = ALE_JUMBO_FRAMELEN; 1000184870Syongari else 1001184870Syongari guard_size = ALE_MAX_FRAMELEN; 1002184870Syongari sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1003184870Syongari ALE_RX_PAGE_ALIGN); 1004184870Syongari lowaddr = BUS_SPACE_MAXADDR; 1005184870Syongariagain: 1006184870Syongari /* Create parent DMA tag. */ 1007184870Syongari error = bus_dma_tag_create( 1008184870Syongari bus_get_dma_tag(sc->ale_dev), /* parent */ 1009184870Syongari 1, 0, /* alignment, boundary */ 1010184870Syongari lowaddr, /* lowaddr */ 1011184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1012184870Syongari NULL, NULL, /* filter, filterarg */ 1013184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1014184870Syongari 0, /* nsegments */ 1015184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1016184870Syongari 0, /* flags */ 1017184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1018184870Syongari &sc->ale_cdata.ale_parent_tag); 1019184870Syongari if (error != 0) { 1020184870Syongari device_printf(sc->ale_dev, 1021184870Syongari "could not create parent DMA tag.\n"); 1022184870Syongari goto fail; 1023184870Syongari } 1024184870Syongari 1025184870Syongari /* Create DMA tag for Tx descriptor ring. */ 1026184870Syongari error = bus_dma_tag_create( 1027184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1028184870Syongari ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1029184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1030184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1031184870Syongari NULL, NULL, /* filter, filterarg */ 1032184870Syongari ALE_TX_RING_SZ, /* maxsize */ 1033184870Syongari 1, /* nsegments */ 1034184870Syongari ALE_TX_RING_SZ, /* maxsegsize */ 1035184870Syongari 0, /* flags */ 1036184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1037184870Syongari &sc->ale_cdata.ale_tx_ring_tag); 1038184870Syongari if (error != 0) { 1039184870Syongari device_printf(sc->ale_dev, 1040184870Syongari "could not create Tx ring DMA tag.\n"); 1041184870Syongari goto fail; 1042184870Syongari } 1043184870Syongari 1044184870Syongari /* Create DMA tag for Rx pages. */ 1045184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1046184870Syongari error = bus_dma_tag_create( 1047184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1048184870Syongari ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1049184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1050184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1051184870Syongari NULL, NULL, /* filter, filterarg */ 1052184870Syongari sc->ale_pagesize, /* maxsize */ 1053184870Syongari 1, /* nsegments */ 1054184870Syongari sc->ale_pagesize, /* maxsegsize */ 1055184870Syongari 0, /* flags */ 1056184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1057184870Syongari &sc->ale_cdata.ale_rx_page[i].page_tag); 1058184870Syongari if (error != 0) { 1059184870Syongari device_printf(sc->ale_dev, 1060184870Syongari "could not create Rx page %d DMA tag.\n", i); 1061184870Syongari goto fail; 1062184870Syongari } 1063184870Syongari } 1064184870Syongari 1065184870Syongari /* Create DMA tag for Tx coalescing message block. */ 1066184870Syongari error = bus_dma_tag_create( 1067184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1068184870Syongari ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1069184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1070184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1071184870Syongari NULL, NULL, /* filter, filterarg */ 1072184870Syongari ALE_TX_CMB_SZ, /* maxsize */ 1073184870Syongari 1, /* nsegments */ 1074184870Syongari ALE_TX_CMB_SZ, /* maxsegsize */ 1075184870Syongari 0, /* flags */ 1076184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1077184870Syongari &sc->ale_cdata.ale_tx_cmb_tag); 1078184870Syongari if (error != 0) { 1079184870Syongari device_printf(sc->ale_dev, 1080184870Syongari "could not create Tx CMB DMA tag.\n"); 1081184870Syongari goto fail; 1082184870Syongari } 1083184870Syongari 1084184870Syongari /* Create DMA tag for Rx coalescing message block. */ 1085184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1086184870Syongari error = bus_dma_tag_create( 1087184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1088184870Syongari ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1089184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1090184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1091184870Syongari NULL, NULL, /* filter, filterarg */ 1092184870Syongari ALE_RX_CMB_SZ, /* maxsize */ 1093184870Syongari 1, /* nsegments */ 1094184870Syongari ALE_RX_CMB_SZ, /* maxsegsize */ 1095184870Syongari 0, /* flags */ 1096184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1097184870Syongari &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1098184870Syongari if (error != 0) { 1099184870Syongari device_printf(sc->ale_dev, 1100184870Syongari "could not create Rx page %d CMB DMA tag.\n", i); 1101184870Syongari goto fail; 1102184870Syongari } 1103184870Syongari } 1104184870Syongari 1105184870Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1106184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1107184870Syongari (void **)&sc->ale_cdata.ale_tx_ring, 1108184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1109184870Syongari &sc->ale_cdata.ale_tx_ring_map); 1110184870Syongari if (error != 0) { 1111184870Syongari device_printf(sc->ale_dev, 1112184870Syongari "could not allocate DMA'able memory for Tx ring.\n"); 1113184870Syongari goto fail; 1114184870Syongari } 1115184870Syongari ctx.ale_busaddr = 0; 1116184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1117184870Syongari sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1118184870Syongari ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1119184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1120184870Syongari device_printf(sc->ale_dev, 1121184870Syongari "could not load DMA'able memory for Tx ring.\n"); 1122184870Syongari goto fail; 1123184870Syongari } 1124184870Syongari sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1125184870Syongari 1126184870Syongari /* Rx pages. */ 1127184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1128184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1129184870Syongari (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1130184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1131184870Syongari &sc->ale_cdata.ale_rx_page[i].page_map); 1132184870Syongari if (error != 0) { 1133184870Syongari device_printf(sc->ale_dev, 1134184870Syongari "could not allocate DMA'able memory for " 1135184870Syongari "Rx page %d.\n", i); 1136184870Syongari goto fail; 1137184870Syongari } 1138184870Syongari ctx.ale_busaddr = 0; 1139184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1140184870Syongari sc->ale_cdata.ale_rx_page[i].page_map, 1141184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr, 1142184870Syongari sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1143184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1144184870Syongari device_printf(sc->ale_dev, 1145184870Syongari "could not load DMA'able memory for " 1146184870Syongari "Rx page %d.\n", i); 1147184870Syongari goto fail; 1148184870Syongari } 1149184870Syongari sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1150184870Syongari } 1151184870Syongari 1152184870Syongari /* Tx CMB. */ 1153184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1154184870Syongari (void **)&sc->ale_cdata.ale_tx_cmb, 1155184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1156184870Syongari &sc->ale_cdata.ale_tx_cmb_map); 1157184870Syongari if (error != 0) { 1158184870Syongari device_printf(sc->ale_dev, 1159184870Syongari "could not allocate DMA'able memory for Tx CMB.\n"); 1160184870Syongari goto fail; 1161184870Syongari } 1162184870Syongari ctx.ale_busaddr = 0; 1163184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1164184870Syongari sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1165184870Syongari ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1166184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1167184870Syongari device_printf(sc->ale_dev, 1168184870Syongari "could not load DMA'able memory for Tx CMB.\n"); 1169184870Syongari goto fail; 1170184870Syongari } 1171184870Syongari sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1172184870Syongari 1173184870Syongari /* Rx CMB. */ 1174184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1175184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1176184870Syongari (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1177184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1178184870Syongari &sc->ale_cdata.ale_rx_page[i].cmb_map); 1179184870Syongari if (error != 0) { 1180184870Syongari device_printf(sc->ale_dev, "could not allocate " 1181184870Syongari "DMA'able memory for Rx page %d CMB.\n", i); 1182184870Syongari goto fail; 1183184870Syongari } 1184184870Syongari ctx.ale_busaddr = 0; 1185184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1186184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map, 1187184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr, 1188184870Syongari ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1189184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1190184870Syongari device_printf(sc->ale_dev, "could not load DMA'able " 1191184870Syongari "memory for Rx page %d CMB.\n", i); 1192184870Syongari goto fail; 1193184870Syongari } 1194184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1195184870Syongari } 1196184870Syongari 1197184870Syongari /* 1198184870Syongari * Tx descriptors/RXF0/CMB DMA blocks share the same 1199184870Syongari * high address region of 64bit DMA address space. 1200184870Syongari */ 1201184870Syongari if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1202184870Syongari (error = ale_check_boundary(sc)) != 0) { 1203184870Syongari device_printf(sc->ale_dev, "4GB boundary crossed, " 1204184870Syongari "switching to 32bit DMA addressing mode.\n"); 1205184870Syongari ale_dma_free(sc); 1206184870Syongari /* 1207184870Syongari * Limit max allowable DMA address space to 32bit 1208184870Syongari * and try again. 1209184870Syongari */ 1210184870Syongari lowaddr = BUS_SPACE_MAXADDR_32BIT; 1211184870Syongari goto again; 1212184870Syongari } 1213184870Syongari 1214184870Syongari /* 1215184870Syongari * Create Tx buffer parent tag. 1216184870Syongari * AR81xx allows 64bit DMA addressing of Tx buffers so it 1217184870Syongari * needs separate parent DMA tag as parent DMA address space 1218184870Syongari * could be restricted to be within 32bit address space by 1219184870Syongari * 4GB boundary crossing. 1220184870Syongari */ 1221184870Syongari error = bus_dma_tag_create( 1222184870Syongari bus_get_dma_tag(sc->ale_dev), /* parent */ 1223184870Syongari 1, 0, /* alignment, boundary */ 1224184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1225184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1226184870Syongari NULL, NULL, /* filter, filterarg */ 1227184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1228184870Syongari 0, /* nsegments */ 1229184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1230184870Syongari 0, /* flags */ 1231184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1232184870Syongari &sc->ale_cdata.ale_buffer_tag); 1233184870Syongari if (error != 0) { 1234184870Syongari device_printf(sc->ale_dev, 1235184870Syongari "could not create parent buffer DMA tag.\n"); 1236184870Syongari goto fail; 1237184870Syongari } 1238184870Syongari 1239184870Syongari /* Create DMA tag for Tx buffers. */ 1240184870Syongari error = bus_dma_tag_create( 1241184870Syongari sc->ale_cdata.ale_buffer_tag, /* parent */ 1242184870Syongari 1, 0, /* alignment, boundary */ 1243184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1244184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1245184870Syongari NULL, NULL, /* filter, filterarg */ 1246184870Syongari ALE_TSO_MAXSIZE, /* maxsize */ 1247184870Syongari ALE_MAXTXSEGS, /* nsegments */ 1248184870Syongari ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1249184870Syongari 0, /* flags */ 1250184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1251184870Syongari &sc->ale_cdata.ale_tx_tag); 1252184870Syongari if (error != 0) { 1253184870Syongari device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1254184870Syongari goto fail; 1255184870Syongari } 1256184870Syongari 1257184870Syongari /* Create DMA maps for Tx buffers. */ 1258184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 1259184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 1260184870Syongari txd->tx_m = NULL; 1261184870Syongari txd->tx_dmamap = NULL; 1262184870Syongari error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1263184870Syongari &txd->tx_dmamap); 1264184870Syongari if (error != 0) { 1265184870Syongari device_printf(sc->ale_dev, 1266184870Syongari "could not create Tx dmamap.\n"); 1267184870Syongari goto fail; 1268184870Syongari } 1269184870Syongari } 1270184870Syongari 1271184870Syongarifail: 1272184870Syongari return (error); 1273184870Syongari} 1274184870Syongari 1275184870Syongaristatic void 1276184870Syongariale_dma_free(struct ale_softc *sc) 1277184870Syongari{ 1278184870Syongari struct ale_txdesc *txd; 1279184870Syongari int i; 1280184870Syongari 1281184870Syongari /* Tx buffers. */ 1282184870Syongari if (sc->ale_cdata.ale_tx_tag != NULL) { 1283184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 1284184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 1285184870Syongari if (txd->tx_dmamap != NULL) { 1286184870Syongari bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1287184870Syongari txd->tx_dmamap); 1288184870Syongari txd->tx_dmamap = NULL; 1289184870Syongari } 1290184870Syongari } 1291184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1292184870Syongari sc->ale_cdata.ale_tx_tag = NULL; 1293184870Syongari } 1294184870Syongari /* Tx descriptor ring. */ 1295184870Syongari if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1296184870Syongari if (sc->ale_cdata.ale_tx_ring_map != NULL) 1297184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1298184870Syongari sc->ale_cdata.ale_tx_ring_map); 1299184870Syongari if (sc->ale_cdata.ale_tx_ring_map != NULL && 1300184870Syongari sc->ale_cdata.ale_tx_ring != NULL) 1301184870Syongari bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1302184870Syongari sc->ale_cdata.ale_tx_ring, 1303184870Syongari sc->ale_cdata.ale_tx_ring_map); 1304184870Syongari sc->ale_cdata.ale_tx_ring = NULL; 1305184870Syongari sc->ale_cdata.ale_tx_ring_map = NULL; 1306184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1307184870Syongari sc->ale_cdata.ale_tx_ring_tag = NULL; 1308184870Syongari } 1309184870Syongari /* Rx page block. */ 1310184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1311184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1312184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1313184870Syongari bus_dmamap_unload( 1314184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag, 1315184870Syongari sc->ale_cdata.ale_rx_page[i].page_map); 1316184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1317184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1318184870Syongari bus_dmamem_free( 1319184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag, 1320184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr, 1321184870Syongari sc->ale_cdata.ale_rx_page[i].page_map); 1322184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1323184870Syongari sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1324184870Syongari bus_dma_tag_destroy( 1325184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag); 1326184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1327184870Syongari } 1328184870Syongari } 1329184870Syongari /* Rx CMB. */ 1330184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1331184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1332184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1333184870Syongari bus_dmamap_unload( 1334184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag, 1335184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map); 1336184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1337184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1338184870Syongari bus_dmamem_free( 1339184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag, 1340184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr, 1341184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map); 1342184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1343184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1344184870Syongari bus_dma_tag_destroy( 1345184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag); 1346184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1347184870Syongari } 1348184870Syongari } 1349184870Syongari /* Tx CMB. */ 1350184870Syongari if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1351184870Syongari if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1352184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1353184870Syongari sc->ale_cdata.ale_tx_cmb_map); 1354184870Syongari if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1355184870Syongari sc->ale_cdata.ale_tx_cmb != NULL) 1356184870Syongari bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1357184870Syongari sc->ale_cdata.ale_tx_cmb, 1358184870Syongari sc->ale_cdata.ale_tx_cmb_map); 1359184870Syongari sc->ale_cdata.ale_tx_cmb = NULL; 1360184870Syongari sc->ale_cdata.ale_tx_cmb_map = NULL; 1361184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1362184870Syongari sc->ale_cdata.ale_tx_cmb_tag = NULL; 1363184870Syongari } 1364184870Syongari if (sc->ale_cdata.ale_buffer_tag != NULL) { 1365184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1366184870Syongari sc->ale_cdata.ale_buffer_tag = NULL; 1367184870Syongari } 1368184870Syongari if (sc->ale_cdata.ale_parent_tag != NULL) { 1369184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1370184870Syongari sc->ale_cdata.ale_parent_tag = NULL; 1371184870Syongari } 1372184870Syongari} 1373184870Syongari 1374184870Syongaristatic int 1375184870Syongariale_shutdown(device_t dev) 1376184870Syongari{ 1377184870Syongari 1378184870Syongari return (ale_suspend(dev)); 1379184870Syongari} 1380184870Syongari 1381184870Syongari/* 1382184870Syongari * Note, this driver resets the link speed to 10/100Mbps by 1383184870Syongari * restarting auto-negotiation in suspend/shutdown phase but we 1384184870Syongari * don't know whether that auto-negotiation would succeed or not 1385184870Syongari * as driver has no control after powering off/suspend operation. 1386184870Syongari * If the renegotiation fail WOL may not work. Running at 1Gbps 1387184870Syongari * will draw more power than 375mA at 3.3V which is specified in 1388184870Syongari * PCI specification and that would result in complete 1389184870Syongari * shutdowning power to ethernet controller. 1390184870Syongari * 1391184870Syongari * TODO 1392184870Syongari * Save current negotiated media speed/duplex/flow-control to 1393184870Syongari * softc and restore the same link again after resuming. PHY 1394184870Syongari * handling such as power down/resetting to 100Mbps may be better 1395184870Syongari * handled in suspend method in phy driver. 1396184870Syongari */ 1397184870Syongaristatic void 1398184870Syongariale_setlinkspeed(struct ale_softc *sc) 1399184870Syongari{ 1400184870Syongari struct mii_data *mii; 1401184870Syongari int aneg, i; 1402184870Syongari 1403184870Syongari mii = device_get_softc(sc->ale_miibus); 1404184870Syongari mii_pollstat(mii); 1405184870Syongari aneg = 0; 1406184870Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1407184870Syongari (IFM_ACTIVE | IFM_AVALID)) { 1408184870Syongari switch IFM_SUBTYPE(mii->mii_media_active) { 1409184870Syongari case IFM_10_T: 1410184870Syongari case IFM_100_TX: 1411184870Syongari return; 1412184870Syongari case IFM_1000_T: 1413184870Syongari aneg++; 1414184870Syongari break; 1415184870Syongari default: 1416184870Syongari break; 1417184870Syongari } 1418184870Syongari } 1419184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1420184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1421184870Syongari MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1422184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1423184870Syongari MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1424184870Syongari DELAY(1000); 1425184870Syongari if (aneg != 0) { 1426184870Syongari /* 1427184870Syongari * Poll link state until ale(4) get a 10/100Mbps link. 1428184870Syongari */ 1429184870Syongari for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1430184870Syongari mii_pollstat(mii); 1431184870Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1432184870Syongari == (IFM_ACTIVE | IFM_AVALID)) { 1433184870Syongari switch (IFM_SUBTYPE( 1434184870Syongari mii->mii_media_active)) { 1435184870Syongari case IFM_10_T: 1436184870Syongari case IFM_100_TX: 1437184870Syongari ale_mac_config(sc); 1438184870Syongari return; 1439184870Syongari default: 1440184870Syongari break; 1441184870Syongari } 1442184870Syongari } 1443184870Syongari ALE_UNLOCK(sc); 1444184870Syongari pause("alelnk", hz); 1445184870Syongari ALE_LOCK(sc); 1446184870Syongari } 1447184870Syongari if (i == MII_ANEGTICKS_GIGE) 1448184870Syongari device_printf(sc->ale_dev, 1449184870Syongari "establishing a link failed, WOL may not work!"); 1450184870Syongari } 1451184870Syongari /* 1452184870Syongari * No link, force MAC to have 100Mbps, full-duplex link. 1453184870Syongari * This is the last resort and may/may not work. 1454184870Syongari */ 1455184870Syongari mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1456184870Syongari mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1457184870Syongari ale_mac_config(sc); 1458184870Syongari} 1459184870Syongari 1460184870Syongaristatic void 1461184870Syongariale_setwol(struct ale_softc *sc) 1462184870Syongari{ 1463184870Syongari struct ifnet *ifp; 1464184870Syongari uint32_t reg, pmcs; 1465184870Syongari uint16_t pmstat; 1466184870Syongari int pmc; 1467184870Syongari 1468184870Syongari ALE_LOCK_ASSERT(sc); 1469184870Syongari 1470219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1471184870Syongari /* Disable WOL. */ 1472184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1473184870Syongari reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1474184870Syongari reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1475184870Syongari CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1476184870Syongari /* Force PHY power down. */ 1477184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1478184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1479184870Syongari GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1480184870Syongari GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1481184870Syongari GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1482184870Syongari return; 1483184870Syongari } 1484184870Syongari 1485184870Syongari ifp = sc->ale_ifp; 1486184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1487184870Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1488184870Syongari ale_setlinkspeed(sc); 1489184870Syongari } 1490184870Syongari 1491184870Syongari pmcs = 0; 1492184870Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1493184870Syongari pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1494184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1495184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 1496184870Syongari reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1497184870Syongari MAC_CFG_BCAST); 1498184870Syongari if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1499184870Syongari reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1500184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1501184870Syongari reg |= MAC_CFG_RX_ENB; 1502184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1503184870Syongari 1504184870Syongari if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1505184870Syongari /* WOL disabled, PHY power down. */ 1506184870Syongari reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1507184870Syongari reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1508184870Syongari CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1509184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1510184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1511184870Syongari GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1512184870Syongari GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1513184870Syongari GPHY_CTRL_PWDOWN_HW); 1514184870Syongari } 1515184870Syongari /* Request PME. */ 1516184870Syongari pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1517184870Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1518184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1519184870Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1520184870Syongari pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1521184870Syongari} 1522184870Syongari 1523184870Syongaristatic int 1524184870Syongariale_suspend(device_t dev) 1525184870Syongari{ 1526184870Syongari struct ale_softc *sc; 1527184870Syongari 1528184870Syongari sc = device_get_softc(dev); 1529184870Syongari 1530184870Syongari ALE_LOCK(sc); 1531184870Syongari ale_stop(sc); 1532184870Syongari ale_setwol(sc); 1533184870Syongari ALE_UNLOCK(sc); 1534184870Syongari 1535184870Syongari return (0); 1536184870Syongari} 1537184870Syongari 1538184870Syongaristatic int 1539184870Syongariale_resume(device_t dev) 1540184870Syongari{ 1541184870Syongari struct ale_softc *sc; 1542184870Syongari struct ifnet *ifp; 1543184870Syongari int pmc; 1544189379Syongari uint16_t pmstat; 1545184870Syongari 1546184870Syongari sc = device_get_softc(dev); 1547184870Syongari 1548184870Syongari ALE_LOCK(sc); 1549219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1550184870Syongari /* Disable PME and clear PME status. */ 1551184870Syongari pmstat = pci_read_config(sc->ale_dev, 1552184870Syongari pmc + PCIR_POWER_STATUS, 2); 1553184870Syongari if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1554184870Syongari pmstat &= ~PCIM_PSTAT_PMEENABLE; 1555184870Syongari pci_write_config(sc->ale_dev, 1556184870Syongari pmc + PCIR_POWER_STATUS, pmstat, 2); 1557184870Syongari } 1558184870Syongari } 1559184870Syongari /* Reset PHY. */ 1560184870Syongari ale_phy_reset(sc); 1561184870Syongari ifp = sc->ale_ifp; 1562184870Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1563184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1564184870Syongari ale_init_locked(sc); 1565184870Syongari } 1566184870Syongari ALE_UNLOCK(sc); 1567184870Syongari 1568184870Syongari return (0); 1569184870Syongari} 1570184870Syongari 1571184870Syongaristatic int 1572184870Syongariale_encap(struct ale_softc *sc, struct mbuf **m_head) 1573184870Syongari{ 1574184870Syongari struct ale_txdesc *txd, *txd_last; 1575184870Syongari struct tx_desc *desc; 1576184870Syongari struct mbuf *m; 1577184870Syongari struct ip *ip; 1578184870Syongari struct tcphdr *tcp; 1579184870Syongari bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1580184870Syongari bus_dmamap_t map; 1581207251Syongari uint32_t cflags, hdrlen, ip_off, poff, vtag; 1582184870Syongari int error, i, nsegs, prod, si; 1583184870Syongari 1584184870Syongari ALE_LOCK_ASSERT(sc); 1585184870Syongari 1586184870Syongari M_ASSERTPKTHDR((*m_head)); 1587184870Syongari 1588184870Syongari m = *m_head; 1589184870Syongari ip = NULL; 1590184870Syongari tcp = NULL; 1591184870Syongari cflags = vtag = 0; 1592184870Syongari ip_off = poff = 0; 1593184870Syongari if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1594184870Syongari /* 1595184870Syongari * AR81xx requires offset of TCP/UDP payload in its Tx 1596184870Syongari * descriptor to perform hardware Tx checksum offload. 1597184870Syongari * Additionally, TSO requires IP/TCP header size and 1598184870Syongari * modification of IP/TCP header in order to make TSO 1599184870Syongari * engine work. This kind of operation takes many CPU 1600184870Syongari * cycles on FreeBSD so fast host CPU is required to 1601184870Syongari * get smooth TSO performance. 1602184870Syongari */ 1603184870Syongari struct ether_header *eh; 1604184870Syongari 1605184870Syongari if (M_WRITABLE(m) == 0) { 1606184870Syongari /* Get a writable copy. */ 1607184870Syongari m = m_dup(*m_head, M_DONTWAIT); 1608184870Syongari /* Release original mbufs. */ 1609184870Syongari m_freem(*m_head); 1610184870Syongari if (m == NULL) { 1611184870Syongari *m_head = NULL; 1612184870Syongari return (ENOBUFS); 1613184870Syongari } 1614184870Syongari *m_head = m; 1615184870Syongari } 1616184870Syongari 1617184870Syongari /* 1618184870Syongari * Buggy-controller requires 4 byte aligned Tx buffer 1619184870Syongari * to make custom checksum offload work. 1620184870Syongari */ 1621184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1622184870Syongari (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1623184870Syongari (mtod(m, intptr_t) & 3) != 0) { 1624184870Syongari m = m_defrag(*m_head, M_DONTWAIT); 1625184870Syongari if (m == NULL) { 1626184870Syongari *m_head = NULL; 1627184870Syongari return (ENOBUFS); 1628184870Syongari } 1629184870Syongari *m_head = m; 1630184870Syongari } 1631184870Syongari 1632184870Syongari ip_off = sizeof(struct ether_header); 1633184870Syongari m = m_pullup(m, ip_off); 1634184870Syongari if (m == NULL) { 1635184870Syongari *m_head = NULL; 1636184870Syongari return (ENOBUFS); 1637184870Syongari } 1638184870Syongari eh = mtod(m, struct ether_header *); 1639184870Syongari /* 1640184870Syongari * Check if hardware VLAN insertion is off. 1641184870Syongari * Additional check for LLC/SNAP frame? 1642184870Syongari */ 1643184870Syongari if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1644184870Syongari ip_off = sizeof(struct ether_vlan_header); 1645184870Syongari m = m_pullup(m, ip_off); 1646184870Syongari if (m == NULL) { 1647184870Syongari *m_head = NULL; 1648184870Syongari return (ENOBUFS); 1649184870Syongari } 1650184870Syongari } 1651184870Syongari m = m_pullup(m, ip_off + sizeof(struct ip)); 1652184870Syongari if (m == NULL) { 1653184870Syongari *m_head = NULL; 1654184870Syongari return (ENOBUFS); 1655184870Syongari } 1656184870Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1657184870Syongari poff = ip_off + (ip->ip_hl << 2); 1658184870Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1659184870Syongari /* 1660184870Syongari * XXX 1661184870Syongari * AR81xx requires the first descriptor should 1662184870Syongari * not include any TCP playload for TSO case. 1663184870Syongari * (i.e. ethernet header + IP + TCP header only) 1664184870Syongari * m_pullup(9) above will ensure this too. 1665184870Syongari * However it's not correct if the first mbuf 1666184870Syongari * of the chain does not use cluster. 1667184870Syongari */ 1668184870Syongari m = m_pullup(m, poff + sizeof(struct tcphdr)); 1669184870Syongari if (m == NULL) { 1670184870Syongari *m_head = NULL; 1671184870Syongari return (ENOBUFS); 1672184870Syongari } 1673213844Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1674184870Syongari tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1675207251Syongari m = m_pullup(m, poff + (tcp->th_off << 2)); 1676207251Syongari if (m == NULL) { 1677207251Syongari *m_head = NULL; 1678207251Syongari return (ENOBUFS); 1679207251Syongari } 1680184870Syongari /* 1681184870Syongari * AR81xx requires IP/TCP header size and offset as 1682184870Syongari * well as TCP pseudo checksum which complicates 1683184870Syongari * TSO configuration. I guess this comes from the 1684184870Syongari * adherence to Microsoft NDIS Large Send 1685184870Syongari * specification which requires insertion of 1686184870Syongari * pseudo checksum by upper stack. The pseudo 1687184870Syongari * checksum that NDIS refers to doesn't include 1688184870Syongari * TCP payload length so ale(4) should recompute 1689184870Syongari * the pseudo checksum here. Hopefully this wouldn't 1690184870Syongari * be much burden on modern CPUs. 1691184870Syongari * Reset IP checksum and recompute TCP pseudo 1692184870Syongari * checksum as NDIS specification said. 1693184870Syongari */ 1694184870Syongari ip->ip_sum = 0; 1695184870Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1696184870Syongari ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1697184870Syongari } 1698184870Syongari *m_head = m; 1699184870Syongari } 1700184870Syongari 1701184870Syongari si = prod = sc->ale_cdata.ale_tx_prod; 1702184870Syongari txd = &sc->ale_cdata.ale_txdesc[prod]; 1703184870Syongari txd_last = txd; 1704184870Syongari map = txd->tx_dmamap; 1705184870Syongari 1706184870Syongari error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1707184870Syongari *m_head, txsegs, &nsegs, 0); 1708184870Syongari if (error == EFBIG) { 1709184870Syongari m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); 1710184870Syongari if (m == NULL) { 1711184870Syongari m_freem(*m_head); 1712184870Syongari *m_head = NULL; 1713184870Syongari return (ENOMEM); 1714184870Syongari } 1715184870Syongari *m_head = m; 1716184870Syongari error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1717184870Syongari *m_head, txsegs, &nsegs, 0); 1718184870Syongari if (error != 0) { 1719184870Syongari m_freem(*m_head); 1720184870Syongari *m_head = NULL; 1721184870Syongari return (error); 1722184870Syongari } 1723184870Syongari } else if (error != 0) 1724184870Syongari return (error); 1725184870Syongari if (nsegs == 0) { 1726184870Syongari m_freem(*m_head); 1727184870Syongari *m_head = NULL; 1728184870Syongari return (EIO); 1729184870Syongari } 1730184870Syongari 1731184870Syongari /* Check descriptor overrun. */ 1732207251Syongari if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1733184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1734184870Syongari return (ENOBUFS); 1735184870Syongari } 1736184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1737184870Syongari 1738184870Syongari m = *m_head; 1739206876Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1740206876Syongari /* Request TSO and set MSS. */ 1741206876Syongari cflags |= ALE_TD_TSO; 1742206876Syongari cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1743206876Syongari /* Set IP/TCP header size. */ 1744206876Syongari cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1745206876Syongari cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1746206876Syongari } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1747184870Syongari /* 1748184870Syongari * AR81xx supports Tx custom checksum offload feature 1749184870Syongari * that offloads single 16bit checksum computation. 1750184870Syongari * So you can choose one among IP, TCP and UDP. 1751184870Syongari * Normally driver sets checksum start/insertion 1752184870Syongari * position from the information of TCP/UDP frame as 1753184870Syongari * TCP/UDP checksum takes more time than that of IP. 1754184870Syongari * However it seems that custom checksum offload 1755184870Syongari * requires 4 bytes aligned Tx buffers due to hardware 1756184870Syongari * bug. 1757184870Syongari * AR81xx also supports explicit Tx checksum computation 1758184870Syongari * if it is told that the size of IP header and TCP 1759184870Syongari * header(for UDP, the header size does not matter 1760184870Syongari * because it's fixed length). However with this scheme 1761184870Syongari * TSO does not work so you have to choose one either 1762184870Syongari * TSO or explicit Tx checksum offload. I chosen TSO 1763184870Syongari * plus custom checksum offload with work-around which 1764184870Syongari * will cover most common usage for this consumer 1765184870Syongari * ethernet controller. The work-around takes a lot of 1766184870Syongari * CPU cycles if Tx buffer is not aligned on 4 bytes 1767184870Syongari * boundary, though. 1768184870Syongari */ 1769184870Syongari cflags |= ALE_TD_CXSUM; 1770184870Syongari /* Set checksum start offset. */ 1771184870Syongari cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1772184870Syongari /* Set checksum insertion position of TCP/UDP. */ 1773184870Syongari cflags |= ((poff + m->m_pkthdr.csum_data) << 1774184870Syongari ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1775184870Syongari } 1776184870Syongari 1777184870Syongari /* Configure VLAN hardware tag insertion. */ 1778184870Syongari if ((m->m_flags & M_VLANTAG) != 0) { 1779184870Syongari vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1780184870Syongari vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1781184870Syongari cflags |= ALE_TD_INSERT_VLAN_TAG; 1782184870Syongari } 1783184870Syongari 1784207251Syongari i = 0; 1785207251Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1786207251Syongari /* 1787207251Syongari * Make sure the first fragment contains 1788207251Syongari * only ethernet and IP/TCP header with options. 1789207251Syongari */ 1790207251Syongari hdrlen = poff + (tcp->th_off << 2); 1791184870Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1792184870Syongari desc->addr = htole64(txsegs[i].ds_addr); 1793207251Syongari desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1794207251Syongari desc->flags = htole32(cflags); 1795207251Syongari sc->ale_cdata.ale_tx_cnt++; 1796207251Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1797207251Syongari if (m->m_len - hdrlen > 0) { 1798207251Syongari /* Handle remaining payload of the first fragment. */ 1799207251Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1800207251Syongari desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1801207251Syongari desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1802207251Syongari vtag); 1803207251Syongari desc->flags = htole32(cflags); 1804207251Syongari sc->ale_cdata.ale_tx_cnt++; 1805207251Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1806207251Syongari } 1807207251Syongari i = 1; 1808207251Syongari } 1809207251Syongari for (; i < nsegs; i++) { 1810207251Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1811207251Syongari desc->addr = htole64(txsegs[i].ds_addr); 1812184870Syongari desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1813184870Syongari desc->flags = htole32(cflags); 1814184870Syongari sc->ale_cdata.ale_tx_cnt++; 1815184870Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1816184870Syongari } 1817184870Syongari /* Update producer index. */ 1818184870Syongari sc->ale_cdata.ale_tx_prod = prod; 1819184870Syongari /* Set TSO header on the first descriptor. */ 1820184870Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1821184870Syongari desc = &sc->ale_cdata.ale_tx_ring[si]; 1822184870Syongari desc->flags |= htole32(ALE_TD_TSO_HDR); 1823184870Syongari } 1824184870Syongari 1825184870Syongari /* Finally set EOP on the last descriptor. */ 1826184870Syongari prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1827184870Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1828184870Syongari desc->flags |= htole32(ALE_TD_EOP); 1829184870Syongari 1830184870Syongari /* Swap dmamap of the first and the last. */ 1831184870Syongari txd = &sc->ale_cdata.ale_txdesc[prod]; 1832184870Syongari map = txd_last->tx_dmamap; 1833184870Syongari txd_last->tx_dmamap = txd->tx_dmamap; 1834184870Syongari txd->tx_dmamap = map; 1835184870Syongari txd->tx_m = m; 1836184870Syongari 1837184870Syongari /* Sync descriptors. */ 1838184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1839184870Syongari sc->ale_cdata.ale_tx_ring_map, 1840184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1841184870Syongari 1842184870Syongari return (0); 1843184870Syongari} 1844184870Syongari 1845184870Syongaristatic void 1846216925Sjhbale_start(struct ifnet *ifp) 1847184870Syongari{ 1848216925Sjhb struct ale_softc *sc; 1849184870Syongari 1850216925Sjhb sc = ifp->if_softc; 1851216925Sjhb ALE_LOCK(sc); 1852216925Sjhb ale_start_locked(ifp); 1853216925Sjhb ALE_UNLOCK(sc); 1854184870Syongari} 1855184870Syongari 1856184870Syongaristatic void 1857216925Sjhbale_start_locked(struct ifnet *ifp) 1858184870Syongari{ 1859184870Syongari struct ale_softc *sc; 1860184870Syongari struct mbuf *m_head; 1861184870Syongari int enq; 1862184870Syongari 1863184870Syongari sc = ifp->if_softc; 1864184870Syongari 1865216925Sjhb ALE_LOCK_ASSERT(sc); 1866184870Syongari 1867184870Syongari /* Reclaim transmitted frames. */ 1868184870Syongari if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1869184870Syongari ale_txeof(sc); 1870184870Syongari 1871184870Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1872216925Sjhb IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1873184870Syongari return; 1874184870Syongari 1875184870Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1876184870Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1877184870Syongari if (m_head == NULL) 1878184870Syongari break; 1879184870Syongari /* 1880184870Syongari * Pack the data into the transmit ring. If we 1881184870Syongari * don't have room, set the OACTIVE flag and wait 1882184870Syongari * for the NIC to drain the ring. 1883184870Syongari */ 1884184870Syongari if (ale_encap(sc, &m_head)) { 1885184870Syongari if (m_head == NULL) 1886184870Syongari break; 1887184870Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1888184870Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1889184870Syongari break; 1890184870Syongari } 1891184870Syongari 1892184870Syongari enq++; 1893184870Syongari /* 1894184870Syongari * If there's a BPF listener, bounce a copy of this frame 1895184870Syongari * to him. 1896184870Syongari */ 1897184870Syongari ETHER_BPF_MTAP(ifp, m_head); 1898184870Syongari } 1899184870Syongari 1900184870Syongari if (enq > 0) { 1901184870Syongari /* Kick. */ 1902184870Syongari CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1903184870Syongari sc->ale_cdata.ale_tx_prod); 1904184870Syongari /* Set a timeout in case the chip goes out to lunch. */ 1905184870Syongari sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1906184870Syongari } 1907184870Syongari} 1908184870Syongari 1909184870Syongaristatic void 1910184870Syongariale_watchdog(struct ale_softc *sc) 1911184870Syongari{ 1912184870Syongari struct ifnet *ifp; 1913184870Syongari 1914184870Syongari ALE_LOCK_ASSERT(sc); 1915184870Syongari 1916184870Syongari if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1917184870Syongari return; 1918184870Syongari 1919184870Syongari ifp = sc->ale_ifp; 1920184870Syongari if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1921184870Syongari if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1922184870Syongari ifp->if_oerrors++; 1923184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1924184870Syongari ale_init_locked(sc); 1925184870Syongari return; 1926184870Syongari } 1927184870Syongari if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1928184870Syongari ifp->if_oerrors++; 1929184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1930184870Syongari ale_init_locked(sc); 1931184870Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1932216925Sjhb ale_start_locked(ifp); 1933184870Syongari} 1934184870Syongari 1935184870Syongaristatic int 1936184870Syongariale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1937184870Syongari{ 1938184870Syongari struct ale_softc *sc; 1939184870Syongari struct ifreq *ifr; 1940184870Syongari struct mii_data *mii; 1941184870Syongari int error, mask; 1942184870Syongari 1943184870Syongari sc = ifp->if_softc; 1944184870Syongari ifr = (struct ifreq *)data; 1945184870Syongari error = 0; 1946184870Syongari switch (cmd) { 1947184870Syongari case SIOCSIFMTU: 1948184870Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1949184870Syongari ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1950184870Syongari ifr->ifr_mtu > ETHERMTU)) 1951184870Syongari error = EINVAL; 1952184870Syongari else if (ifp->if_mtu != ifr->ifr_mtu) { 1953184870Syongari ALE_LOCK(sc); 1954184870Syongari ifp->if_mtu = ifr->ifr_mtu; 1955184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1956184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1957184870Syongari ale_init_locked(sc); 1958184870Syongari } 1959184870Syongari ALE_UNLOCK(sc); 1960184870Syongari } 1961184870Syongari break; 1962184870Syongari case SIOCSIFFLAGS: 1963184870Syongari ALE_LOCK(sc); 1964184870Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1965184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1966184870Syongari if (((ifp->if_flags ^ sc->ale_if_flags) 1967184870Syongari & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1968184870Syongari ale_rxfilter(sc); 1969184870Syongari } else { 1970217542Sjhb ale_init_locked(sc); 1971184870Syongari } 1972184870Syongari } else { 1973184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1974184870Syongari ale_stop(sc); 1975184870Syongari } 1976184870Syongari sc->ale_if_flags = ifp->if_flags; 1977184870Syongari ALE_UNLOCK(sc); 1978184870Syongari break; 1979184870Syongari case SIOCADDMULTI: 1980184870Syongari case SIOCDELMULTI: 1981184870Syongari ALE_LOCK(sc); 1982184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1983184870Syongari ale_rxfilter(sc); 1984184870Syongari ALE_UNLOCK(sc); 1985184870Syongari break; 1986184870Syongari case SIOCSIFMEDIA: 1987184870Syongari case SIOCGIFMEDIA: 1988184870Syongari mii = device_get_softc(sc->ale_miibus); 1989184870Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1990184870Syongari break; 1991184870Syongari case SIOCSIFCAP: 1992184870Syongari ALE_LOCK(sc); 1993184870Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1994184870Syongari if ((mask & IFCAP_TXCSUM) != 0 && 1995184870Syongari (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1996184870Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 1997184870Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1998184870Syongari ifp->if_hwassist |= ALE_CSUM_FEATURES; 1999184870Syongari else 2000184870Syongari ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2001184870Syongari } 2002184870Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2003184870Syongari (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2004184870Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2005184870Syongari if ((mask & IFCAP_TSO4) != 0 && 2006184870Syongari (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2007184870Syongari ifp->if_capenable ^= IFCAP_TSO4; 2008184870Syongari if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2009184870Syongari ifp->if_hwassist |= CSUM_TSO; 2010184870Syongari else 2011184870Syongari ifp->if_hwassist &= ~CSUM_TSO; 2012184870Syongari } 2013184870Syongari 2014184870Syongari if ((mask & IFCAP_WOL_MCAST) != 0 && 2015184870Syongari (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2016184870Syongari ifp->if_capenable ^= IFCAP_WOL_MCAST; 2017184870Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2018184870Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2019184870Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2020184870Syongari if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2021184870Syongari (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2022184870Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2023184870Syongari if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2024184870Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2025184870Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2026204378Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2027204378Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2028204378Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2029204378Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2030204378Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2031204378Syongari ale_rxvlan(sc); 2032204378Syongari } 2033184870Syongari ALE_UNLOCK(sc); 2034184870Syongari VLAN_CAPABILITIES(ifp); 2035184870Syongari break; 2036184870Syongari default: 2037184870Syongari error = ether_ioctl(ifp, cmd, data); 2038184870Syongari break; 2039184870Syongari } 2040184870Syongari 2041184870Syongari return (error); 2042184870Syongari} 2043184870Syongari 2044184870Syongaristatic void 2045184870Syongariale_mac_config(struct ale_softc *sc) 2046184870Syongari{ 2047184870Syongari struct mii_data *mii; 2048184870Syongari uint32_t reg; 2049184870Syongari 2050184870Syongari ALE_LOCK_ASSERT(sc); 2051184870Syongari 2052184870Syongari mii = device_get_softc(sc->ale_miibus); 2053184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 2054184870Syongari reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2055184870Syongari MAC_CFG_SPEED_MASK); 2056184870Syongari /* Reprogram MAC with resolved speed/duplex. */ 2057184870Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 2058184870Syongari case IFM_10_T: 2059184870Syongari case IFM_100_TX: 2060184870Syongari reg |= MAC_CFG_SPEED_10_100; 2061184870Syongari break; 2062184870Syongari case IFM_1000_T: 2063184870Syongari reg |= MAC_CFG_SPEED_1000; 2064184870Syongari break; 2065184870Syongari } 2066184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2067184870Syongari reg |= MAC_CFG_FULL_DUPLEX; 2068184870Syongari#ifdef notyet 2069184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2070184870Syongari reg |= MAC_CFG_TX_FC; 2071184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2072184870Syongari reg |= MAC_CFG_RX_FC; 2073184870Syongari#endif 2074184870Syongari } 2075184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2076184870Syongari} 2077184870Syongari 2078184870Syongaristatic void 2079184870Syongariale_link_task(void *arg, int pending) 2080184870Syongari{ 2081184870Syongari struct ale_softc *sc; 2082184870Syongari struct mii_data *mii; 2083184870Syongari struct ifnet *ifp; 2084184870Syongari uint32_t reg; 2085184870Syongari 2086184870Syongari sc = (struct ale_softc *)arg; 2087184870Syongari 2088184870Syongari ALE_LOCK(sc); 2089184870Syongari mii = device_get_softc(sc->ale_miibus); 2090184870Syongari ifp = sc->ale_ifp; 2091184870Syongari if (mii == NULL || ifp == NULL || 2092184870Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2093184870Syongari ALE_UNLOCK(sc); 2094184870Syongari return; 2095184870Syongari } 2096184870Syongari 2097184870Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 2098184870Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2099184870Syongari (IFM_ACTIVE | IFM_AVALID)) { 2100184870Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 2101184870Syongari case IFM_10_T: 2102184870Syongari case IFM_100_TX: 2103184870Syongari sc->ale_flags |= ALE_FLAG_LINK; 2104184870Syongari break; 2105184870Syongari case IFM_1000_T: 2106184870Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 2107184870Syongari sc->ale_flags |= ALE_FLAG_LINK; 2108184870Syongari break; 2109184870Syongari default: 2110184870Syongari break; 2111184870Syongari } 2112184870Syongari } 2113184870Syongari 2114184870Syongari /* Stop Rx/Tx MACs. */ 2115184870Syongari ale_stop_mac(sc); 2116184870Syongari 2117184870Syongari /* Program MACs with resolved speed/duplex/flow-control. */ 2118184870Syongari if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 2119184870Syongari ale_mac_config(sc); 2120184870Syongari /* Reenable Tx/Rx MACs. */ 2121184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 2122184870Syongari reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2123184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2124184870Syongari } 2125184870Syongari 2126184870Syongari ALE_UNLOCK(sc); 2127184870Syongari} 2128184870Syongari 2129184870Syongaristatic void 2130184870Syongariale_stats_clear(struct ale_softc *sc) 2131184870Syongari{ 2132184870Syongari struct smb sb; 2133184870Syongari uint32_t *reg; 2134184870Syongari int i; 2135184870Syongari 2136184870Syongari for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2137184870Syongari CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2138184870Syongari i += sizeof(uint32_t); 2139184870Syongari } 2140184870Syongari /* Read Tx statistics. */ 2141184870Syongari for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2142184870Syongari CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2143184870Syongari i += sizeof(uint32_t); 2144184870Syongari } 2145184870Syongari} 2146184870Syongari 2147184870Syongaristatic void 2148184870Syongariale_stats_update(struct ale_softc *sc) 2149184870Syongari{ 2150184870Syongari struct ale_hw_stats *stat; 2151184870Syongari struct smb sb, *smb; 2152184870Syongari struct ifnet *ifp; 2153184870Syongari uint32_t *reg; 2154184870Syongari int i; 2155184870Syongari 2156184870Syongari ALE_LOCK_ASSERT(sc); 2157184870Syongari 2158184870Syongari ifp = sc->ale_ifp; 2159184870Syongari stat = &sc->ale_stats; 2160184870Syongari smb = &sb; 2161184870Syongari 2162184870Syongari /* Read Rx statistics. */ 2163184870Syongari for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2164184870Syongari *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2165184870Syongari i += sizeof(uint32_t); 2166184870Syongari } 2167184870Syongari /* Read Tx statistics. */ 2168184870Syongari for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2169184870Syongari *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2170184870Syongari i += sizeof(uint32_t); 2171184870Syongari } 2172184870Syongari 2173184870Syongari /* Rx stats. */ 2174184870Syongari stat->rx_frames += smb->rx_frames; 2175184870Syongari stat->rx_bcast_frames += smb->rx_bcast_frames; 2176184870Syongari stat->rx_mcast_frames += smb->rx_mcast_frames; 2177184870Syongari stat->rx_pause_frames += smb->rx_pause_frames; 2178184870Syongari stat->rx_control_frames += smb->rx_control_frames; 2179184870Syongari stat->rx_crcerrs += smb->rx_crcerrs; 2180184870Syongari stat->rx_lenerrs += smb->rx_lenerrs; 2181184870Syongari stat->rx_bytes += smb->rx_bytes; 2182184870Syongari stat->rx_runts += smb->rx_runts; 2183184870Syongari stat->rx_fragments += smb->rx_fragments; 2184184870Syongari stat->rx_pkts_64 += smb->rx_pkts_64; 2185184870Syongari stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2186184870Syongari stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2187184870Syongari stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2188184870Syongari stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2189184870Syongari stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2190184870Syongari stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2191184870Syongari stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2192184870Syongari stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2193184870Syongari stat->rx_rrs_errs += smb->rx_rrs_errs; 2194184870Syongari stat->rx_alignerrs += smb->rx_alignerrs; 2195184870Syongari stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2196184870Syongari stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2197184870Syongari stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2198184870Syongari 2199184870Syongari /* Tx stats. */ 2200184870Syongari stat->tx_frames += smb->tx_frames; 2201184870Syongari stat->tx_bcast_frames += smb->tx_bcast_frames; 2202184870Syongari stat->tx_mcast_frames += smb->tx_mcast_frames; 2203184870Syongari stat->tx_pause_frames += smb->tx_pause_frames; 2204184870Syongari stat->tx_excess_defer += smb->tx_excess_defer; 2205184870Syongari stat->tx_control_frames += smb->tx_control_frames; 2206184870Syongari stat->tx_deferred += smb->tx_deferred; 2207184870Syongari stat->tx_bytes += smb->tx_bytes; 2208184870Syongari stat->tx_pkts_64 += smb->tx_pkts_64; 2209184870Syongari stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2210184870Syongari stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2211184870Syongari stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2212184870Syongari stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2213184870Syongari stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2214184870Syongari stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2215184870Syongari stat->tx_single_colls += smb->tx_single_colls; 2216184870Syongari stat->tx_multi_colls += smb->tx_multi_colls; 2217184870Syongari stat->tx_late_colls += smb->tx_late_colls; 2218184870Syongari stat->tx_excess_colls += smb->tx_excess_colls; 2219184870Syongari stat->tx_abort += smb->tx_abort; 2220184870Syongari stat->tx_underrun += smb->tx_underrun; 2221184870Syongari stat->tx_desc_underrun += smb->tx_desc_underrun; 2222184870Syongari stat->tx_lenerrs += smb->tx_lenerrs; 2223184870Syongari stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2224184870Syongari stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2225184870Syongari stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2226184870Syongari 2227184870Syongari /* Update counters in ifnet. */ 2228184870Syongari ifp->if_opackets += smb->tx_frames; 2229184870Syongari 2230184870Syongari ifp->if_collisions += smb->tx_single_colls + 2231184870Syongari smb->tx_multi_colls * 2 + smb->tx_late_colls + 2232184870Syongari smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2233184870Syongari 2234184870Syongari /* 2235184870Syongari * XXX 2236184870Syongari * tx_pkts_truncated counter looks suspicious. It constantly 2237184870Syongari * increments with no sign of Tx errors. This may indicate 2238184870Syongari * the counter name is not correct one so I've removed the 2239184870Syongari * counter in output errors. 2240184870Syongari */ 2241184870Syongari ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2242184870Syongari smb->tx_underrun; 2243184870Syongari 2244184870Syongari ifp->if_ipackets += smb->rx_frames; 2245184870Syongari 2246184870Syongari ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2247184870Syongari smb->rx_runts + smb->rx_pkts_truncated + 2248184870Syongari smb->rx_fifo_oflows + smb->rx_rrs_errs + 2249184870Syongari smb->rx_alignerrs; 2250184870Syongari} 2251184870Syongari 2252184870Syongaristatic int 2253184870Syongariale_intr(void *arg) 2254184870Syongari{ 2255184870Syongari struct ale_softc *sc; 2256184870Syongari uint32_t status; 2257184870Syongari 2258184870Syongari sc = (struct ale_softc *)arg; 2259184870Syongari 2260184870Syongari status = CSR_READ_4(sc, ALE_INTR_STATUS); 2261184870Syongari if ((status & ALE_INTRS) == 0) 2262184870Syongari return (FILTER_STRAY); 2263184870Syongari /* Disable interrupts. */ 2264184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2265184870Syongari taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2266184870Syongari 2267184870Syongari return (FILTER_HANDLED); 2268184870Syongari} 2269184870Syongari 2270184870Syongaristatic void 2271184870Syongariale_int_task(void *arg, int pending) 2272184870Syongari{ 2273184870Syongari struct ale_softc *sc; 2274184870Syongari struct ifnet *ifp; 2275184870Syongari uint32_t status; 2276184870Syongari int more; 2277184870Syongari 2278184870Syongari sc = (struct ale_softc *)arg; 2279184870Syongari 2280184870Syongari status = CSR_READ_4(sc, ALE_INTR_STATUS); 2281217542Sjhb ALE_LOCK(sc); 2282216438Syongari if (sc->ale_morework != 0) 2283184870Syongari status |= INTR_RX_PKT; 2284184870Syongari if ((status & ALE_INTRS) == 0) 2285184870Syongari goto done; 2286184870Syongari 2287184870Syongari /* Acknowledge interrupts but still disable interrupts. */ 2288184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2289184870Syongari 2290184870Syongari ifp = sc->ale_ifp; 2291184870Syongari more = 0; 2292184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2293184870Syongari more = ale_rxeof(sc, sc->ale_process_limit); 2294184870Syongari if (more == EAGAIN) 2295216438Syongari sc->ale_morework = 1; 2296184870Syongari else if (more == EIO) { 2297184870Syongari sc->ale_stats.reset_brk_seq++; 2298184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2299184870Syongari ale_init_locked(sc); 2300184870Syongari ALE_UNLOCK(sc); 2301184870Syongari return; 2302184870Syongari } 2303184870Syongari 2304184870Syongari if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2305184870Syongari if ((status & INTR_DMA_RD_TO_RST) != 0) 2306184870Syongari device_printf(sc->ale_dev, 2307184870Syongari "DMA read error! -- resetting\n"); 2308184870Syongari if ((status & INTR_DMA_WR_TO_RST) != 0) 2309184870Syongari device_printf(sc->ale_dev, 2310184870Syongari "DMA write error! -- resetting\n"); 2311184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2312184870Syongari ale_init_locked(sc); 2313184870Syongari ALE_UNLOCK(sc); 2314184870Syongari return; 2315184870Syongari } 2316184870Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2317216925Sjhb ale_start_locked(ifp); 2318184870Syongari } 2319184870Syongari 2320184870Syongari if (more == EAGAIN || 2321184870Syongari (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2322217542Sjhb ALE_UNLOCK(sc); 2323184870Syongari taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2324184870Syongari return; 2325184870Syongari } 2326184870Syongari 2327184870Syongaridone: 2328217542Sjhb ALE_UNLOCK(sc); 2329217542Sjhb 2330184870Syongari /* Re-enable interrupts. */ 2331184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2332184870Syongari} 2333184870Syongari 2334184870Syongaristatic void 2335184870Syongariale_txeof(struct ale_softc *sc) 2336184870Syongari{ 2337184870Syongari struct ifnet *ifp; 2338184870Syongari struct ale_txdesc *txd; 2339184870Syongari uint32_t cons, prod; 2340184870Syongari int prog; 2341184870Syongari 2342184870Syongari ALE_LOCK_ASSERT(sc); 2343184870Syongari 2344184870Syongari ifp = sc->ale_ifp; 2345184870Syongari 2346184870Syongari if (sc->ale_cdata.ale_tx_cnt == 0) 2347184870Syongari return; 2348184870Syongari 2349184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2350184870Syongari sc->ale_cdata.ale_tx_ring_map, 2351184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2352184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2353184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2354184870Syongari sc->ale_cdata.ale_tx_cmb_map, 2355184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2356184870Syongari prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2357184870Syongari } else 2358184870Syongari prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2359184870Syongari cons = sc->ale_cdata.ale_tx_cons; 2360184870Syongari /* 2361184870Syongari * Go through our Tx list and free mbufs for those 2362184870Syongari * frames which have been transmitted. 2363184870Syongari */ 2364184870Syongari for (prog = 0; cons != prod; prog++, 2365184870Syongari ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2366184870Syongari if (sc->ale_cdata.ale_tx_cnt <= 0) 2367184870Syongari break; 2368184870Syongari prog++; 2369184870Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2370184870Syongari sc->ale_cdata.ale_tx_cnt--; 2371184870Syongari txd = &sc->ale_cdata.ale_txdesc[cons]; 2372184870Syongari if (txd->tx_m != NULL) { 2373184870Syongari /* Reclaim transmitted mbufs. */ 2374184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2375184870Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2376184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2377184870Syongari txd->tx_dmamap); 2378184870Syongari m_freem(txd->tx_m); 2379184870Syongari txd->tx_m = NULL; 2380184870Syongari } 2381184870Syongari } 2382184870Syongari 2383184870Syongari if (prog > 0) { 2384184870Syongari sc->ale_cdata.ale_tx_cons = cons; 2385184870Syongari /* 2386184870Syongari * Unarm watchdog timer only when there is no pending 2387184870Syongari * Tx descriptors in queue. 2388184870Syongari */ 2389184870Syongari if (sc->ale_cdata.ale_tx_cnt == 0) 2390184870Syongari sc->ale_watchdog_timer = 0; 2391184870Syongari } 2392184870Syongari} 2393184870Syongari 2394184870Syongaristatic void 2395184870Syongariale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2396184870Syongari uint32_t length, uint32_t *prod) 2397184870Syongari{ 2398184870Syongari struct ale_rx_page *rx_page; 2399184870Syongari 2400184870Syongari rx_page = *page; 2401184870Syongari /* Update consumer position. */ 2402184870Syongari rx_page->cons += roundup(length + sizeof(struct rx_rs), 2403184870Syongari ALE_RX_PAGE_ALIGN); 2404184870Syongari if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2405184870Syongari /* 2406184870Syongari * End of Rx page reached, let hardware reuse 2407184870Syongari * this page. 2408184870Syongari */ 2409184870Syongari rx_page->cons = 0; 2410184870Syongari *rx_page->cmb_addr = 0; 2411184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2412184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2413184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2414184870Syongari RXF_VALID); 2415184870Syongari /* Switch to alternate Rx page. */ 2416184870Syongari sc->ale_cdata.ale_rx_curp ^= 1; 2417184870Syongari rx_page = *page = 2418184870Syongari &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2419184870Syongari /* Page flipped, sync CMB and Rx page. */ 2420184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2421184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2422184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2423184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2424184870Syongari /* Sync completed, cache updated producer index. */ 2425184870Syongari *prod = *rx_page->cmb_addr; 2426184870Syongari } 2427184870Syongari} 2428184870Syongari 2429184870Syongari 2430184870Syongari/* 2431184870Syongari * It seems that AR81xx controller can compute partial checksum. 2432184870Syongari * The partial checksum value can be used to accelerate checksum 2433184870Syongari * computation for fragmented TCP/UDP packets. Upper network stack 2434184870Syongari * already takes advantage of the partial checksum value in IP 2435184870Syongari * reassembly stage. But I'm not sure the correctness of the 2436184870Syongari * partial hardware checksum assistance due to lack of data sheet. 2437184870Syongari * In addition, the Rx feature of controller that requires copying 2438184870Syongari * for every frames effectively nullifies one of most nice offload 2439184870Syongari * capability of controller. 2440184870Syongari */ 2441184870Syongaristatic void 2442184870Syongariale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2443184870Syongari{ 2444184870Syongari struct ifnet *ifp; 2445184870Syongari struct ip *ip; 2446184870Syongari char *p; 2447184870Syongari 2448184870Syongari ifp = sc->ale_ifp; 2449184870Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2450184870Syongari if ((status & ALE_RD_IPCSUM_NOK) == 0) 2451184870Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2452184870Syongari 2453184870Syongari if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2454184870Syongari if (((status & ALE_RD_IPV4_FRAG) == 0) && 2455184870Syongari ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2456184870Syongari ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2457184870Syongari m->m_pkthdr.csum_flags |= 2458184870Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2459184870Syongari m->m_pkthdr.csum_data = 0xffff; 2460184870Syongari } 2461184870Syongari } else { 2462184870Syongari if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2463184870Syongari (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2464184870Syongari p = mtod(m, char *); 2465184870Syongari p += ETHER_HDR_LEN; 2466184870Syongari if ((status & ALE_RD_802_3) != 0) 2467184870Syongari p += LLC_SNAPFRAMELEN; 2468184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2469184870Syongari (status & ALE_RD_VLAN) != 0) 2470184870Syongari p += ETHER_VLAN_ENCAP_LEN; 2471184870Syongari ip = (struct ip *)p; 2472184870Syongari if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2473184870Syongari return; 2474184870Syongari m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2475184870Syongari CSUM_PSEUDO_HDR; 2476184870Syongari m->m_pkthdr.csum_data = 0xffff; 2477184870Syongari } 2478184870Syongari } 2479184870Syongari /* 2480184870Syongari * Don't mark bad checksum for TCP/UDP frames 2481184870Syongari * as fragmented frames may always have set 2482184870Syongari * bad checksummed bit of frame status. 2483184870Syongari */ 2484184870Syongari} 2485184870Syongari 2486184870Syongari/* Process received frames. */ 2487184870Syongaristatic int 2488184870Syongariale_rxeof(struct ale_softc *sc, int count) 2489184870Syongari{ 2490184870Syongari struct ale_rx_page *rx_page; 2491184870Syongari struct rx_rs *rs; 2492184870Syongari struct ifnet *ifp; 2493184870Syongari struct mbuf *m; 2494184870Syongari uint32_t length, prod, seqno, status, vtags; 2495184870Syongari int prog; 2496184870Syongari 2497184870Syongari ifp = sc->ale_ifp; 2498184870Syongari rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2499184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2500184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2501184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2502184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2503184870Syongari /* 2504184870Syongari * Don't directly access producer index as hardware may 2505184870Syongari * update it while Rx handler is in progress. It would 2506184870Syongari * be even better if there is a way to let hardware 2507184870Syongari * know how far driver processed its received frames. 2508184870Syongari * Alternatively, hardware could provide a way to disable 2509184870Syongari * CMB updates until driver acknowledges the end of CMB 2510184870Syongari * access. 2511184870Syongari */ 2512184870Syongari prod = *rx_page->cmb_addr; 2513184870Syongari for (prog = 0; prog < count; prog++) { 2514184870Syongari if (rx_page->cons >= prod) 2515184870Syongari break; 2516184870Syongari rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2517184870Syongari seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2518184870Syongari if (sc->ale_cdata.ale_rx_seqno != seqno) { 2519184870Syongari /* 2520184870Syongari * Normally I believe this should not happen unless 2521184870Syongari * severe driver bug or corrupted memory. However 2522184870Syongari * it seems to happen under certain conditions which 2523184870Syongari * is triggered by abrupt Rx events such as initiation 2524184870Syongari * of bulk transfer of remote host. It's not easy to 2525184870Syongari * reproduce this and I doubt it could be related 2526184870Syongari * with FIFO overflow of hardware or activity of Tx 2527184870Syongari * CMB updates. I also remember similar behaviour 2528184870Syongari * seen on RealTek 8139 which uses resembling Rx 2529184870Syongari * scheme. 2530184870Syongari */ 2531184870Syongari if (bootverbose) 2532184870Syongari device_printf(sc->ale_dev, 2533184870Syongari "garbled seq: %u, expected: %u -- " 2534184870Syongari "resetting!\n", seqno, 2535184870Syongari sc->ale_cdata.ale_rx_seqno); 2536184870Syongari return (EIO); 2537184870Syongari } 2538184870Syongari /* Frame received. */ 2539184870Syongari sc->ale_cdata.ale_rx_seqno++; 2540184870Syongari length = ALE_RX_BYTES(le32toh(rs->length)); 2541184870Syongari status = le32toh(rs->flags); 2542184870Syongari if ((status & ALE_RD_ERROR) != 0) { 2543184870Syongari /* 2544184870Syongari * We want to pass the following frames to upper 2545184870Syongari * layer regardless of error status of Rx return 2546184870Syongari * status. 2547184870Syongari * 2548184870Syongari * o IP/TCP/UDP checksum is bad. 2549184870Syongari * o frame length and protocol specific length 2550184870Syongari * does not match. 2551184870Syongari */ 2552184870Syongari if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2553184870Syongari ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2554184870Syongari ALE_RD_TRUNC)) != 0) { 2555184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2556184870Syongari continue; 2557184870Syongari } 2558184870Syongari } 2559184870Syongari /* 2560184870Syongari * m_devget(9) is major bottle-neck of ale(4)(It comes 2561184870Syongari * from hardware limitation). For jumbo frames we could 2562184870Syongari * get a slightly better performance if driver use 2563184870Syongari * m_getjcl(9) with proper buffer size argument. However 2564184870Syongari * that would make code more complicated and I don't 2565184870Syongari * think users would expect good Rx performance numbers 2566184870Syongari * on these low-end consumer ethernet controller. 2567184870Syongari */ 2568184870Syongari m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2569184870Syongari ETHER_ALIGN, ifp, NULL); 2570184870Syongari if (m == NULL) { 2571184870Syongari ifp->if_iqdrops++; 2572184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2573184870Syongari continue; 2574184870Syongari } 2575184870Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2576184870Syongari (status & ALE_RD_IPV4) != 0) 2577184870Syongari ale_rxcsum(sc, m, status); 2578184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2579184870Syongari (status & ALE_RD_VLAN) != 0) { 2580184870Syongari vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2581184870Syongari m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2582184870Syongari m->m_flags |= M_VLANTAG; 2583184870Syongari } 2584184870Syongari 2585184870Syongari /* Pass it to upper layer. */ 2586217542Sjhb ALE_UNLOCK(sc); 2587184870Syongari (*ifp->if_input)(ifp, m); 2588217542Sjhb ALE_LOCK(sc); 2589184870Syongari 2590184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2591184870Syongari } 2592184870Syongari 2593184870Syongari return (count > 0 ? 0 : EAGAIN); 2594184870Syongari} 2595184870Syongari 2596184870Syongaristatic void 2597184870Syongariale_tick(void *arg) 2598184870Syongari{ 2599184870Syongari struct ale_softc *sc; 2600184870Syongari struct mii_data *mii; 2601184870Syongari 2602184870Syongari sc = (struct ale_softc *)arg; 2603184870Syongari 2604184870Syongari ALE_LOCK_ASSERT(sc); 2605184870Syongari 2606184870Syongari mii = device_get_softc(sc->ale_miibus); 2607184870Syongari mii_tick(mii); 2608184870Syongari ale_stats_update(sc); 2609184870Syongari /* 2610184870Syongari * Reclaim Tx buffers that have been transferred. It's not 2611184870Syongari * needed here but it would release allocated mbuf chains 2612184870Syongari * faster and limit the maximum delay to a hz. 2613184870Syongari */ 2614184870Syongari ale_txeof(sc); 2615184870Syongari ale_watchdog(sc); 2616184870Syongari callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2617184870Syongari} 2618184870Syongari 2619184870Syongaristatic void 2620184870Syongariale_reset(struct ale_softc *sc) 2621184870Syongari{ 2622184870Syongari uint32_t reg; 2623184870Syongari int i; 2624184870Syongari 2625184870Syongari /* Initialize PCIe module. From Linux. */ 2626184870Syongari CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2627184870Syongari 2628184870Syongari CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2629184870Syongari for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2630184870Syongari DELAY(10); 2631184870Syongari if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2632184870Syongari break; 2633184870Syongari } 2634184870Syongari if (i == 0) 2635184870Syongari device_printf(sc->ale_dev, "master reset timeout!\n"); 2636184870Syongari 2637184870Syongari for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2638184870Syongari if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2639184870Syongari break; 2640184870Syongari DELAY(10); 2641184870Syongari } 2642184870Syongari 2643184870Syongari if (i == 0) 2644184870Syongari device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2645184870Syongari} 2646184870Syongari 2647184870Syongaristatic void 2648184870Syongariale_init(void *xsc) 2649184870Syongari{ 2650184870Syongari struct ale_softc *sc; 2651184870Syongari 2652184870Syongari sc = (struct ale_softc *)xsc; 2653184870Syongari ALE_LOCK(sc); 2654184870Syongari ale_init_locked(sc); 2655184870Syongari ALE_UNLOCK(sc); 2656184870Syongari} 2657184870Syongari 2658184870Syongaristatic void 2659184870Syongariale_init_locked(struct ale_softc *sc) 2660184870Syongari{ 2661184870Syongari struct ifnet *ifp; 2662184870Syongari struct mii_data *mii; 2663184870Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 2664184870Syongari bus_addr_t paddr; 2665184870Syongari uint32_t reg, rxf_hi, rxf_lo; 2666184870Syongari 2667184870Syongari ALE_LOCK_ASSERT(sc); 2668184870Syongari 2669184870Syongari ifp = sc->ale_ifp; 2670184870Syongari mii = device_get_softc(sc->ale_miibus); 2671184870Syongari 2672184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2673184870Syongari return; 2674184870Syongari /* 2675184870Syongari * Cancel any pending I/O. 2676184870Syongari */ 2677184870Syongari ale_stop(sc); 2678184870Syongari /* 2679184870Syongari * Reset the chip to a known state. 2680184870Syongari */ 2681184870Syongari ale_reset(sc); 2682184870Syongari /* Initialize Tx descriptors, DMA memory blocks. */ 2683184870Syongari ale_init_rx_pages(sc); 2684184870Syongari ale_init_tx_ring(sc); 2685184870Syongari 2686184870Syongari /* Reprogram the station address. */ 2687184870Syongari bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2688184870Syongari CSR_WRITE_4(sc, ALE_PAR0, 2689184870Syongari eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2690184870Syongari CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2691184870Syongari /* 2692184870Syongari * Clear WOL status and disable all WOL feature as WOL 2693184870Syongari * would interfere Rx operation under normal environments. 2694184870Syongari */ 2695184870Syongari CSR_READ_4(sc, ALE_WOL_CFG); 2696184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2697184870Syongari /* 2698184870Syongari * Set Tx descriptor/RXF0/CMB base addresses. They share 2699184870Syongari * the same high address part of DMAable region. 2700184870Syongari */ 2701184870Syongari paddr = sc->ale_cdata.ale_tx_ring_paddr; 2702184870Syongari CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2703184870Syongari CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2704184870Syongari CSR_WRITE_4(sc, ALE_TPD_CNT, 2705184870Syongari (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2706184870Syongari /* Set Rx page base address, note we use single queue. */ 2707184870Syongari paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2708184870Syongari CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2709184870Syongari paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2710184870Syongari CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2711184870Syongari /* Set Tx/Rx CMB addresses. */ 2712184870Syongari paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2713184870Syongari CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2714184870Syongari paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2715184870Syongari CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2716184870Syongari paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2717184870Syongari CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2718184870Syongari /* Mark RXF0 is valid. */ 2719184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2720184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2721184870Syongari /* 2722184870Syongari * No need to initialize RFX1/RXF2/RXF3. We don't use 2723184870Syongari * multi-queue yet. 2724184870Syongari */ 2725184870Syongari 2726184870Syongari /* Set Rx page size, excluding guard frame size. */ 2727184870Syongari CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2728184870Syongari /* Tell hardware that we're ready to load DMA blocks. */ 2729184870Syongari CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2730184870Syongari 2731184870Syongari /* Set Rx/Tx interrupt trigger threshold. */ 2732184870Syongari CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2733184870Syongari (4 << INT_TRIG_TX_THRESH_SHIFT)); 2734184870Syongari /* 2735184870Syongari * XXX 2736184870Syongari * Set interrupt trigger timer, its purpose and relation 2737184870Syongari * with interrupt moderation mechanism is not clear yet. 2738184870Syongari */ 2739184870Syongari CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2740184870Syongari ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2741184870Syongari (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2742184870Syongari 2743184870Syongari /* Configure interrupt moderation timer. */ 2744184870Syongari reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2745184870Syongari reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2746184870Syongari CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2747184870Syongari reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2748184870Syongari reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2749184870Syongari reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2750184870Syongari if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2751184870Syongari reg |= MASTER_IM_RX_TIMER_ENB; 2752184870Syongari if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2753184870Syongari reg |= MASTER_IM_TX_TIMER_ENB; 2754184870Syongari CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2755184870Syongari CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2756184870Syongari 2757184870Syongari /* Set Maximum frame size of controller. */ 2758184870Syongari if (ifp->if_mtu < ETHERMTU) 2759184870Syongari sc->ale_max_frame_size = ETHERMTU; 2760184870Syongari else 2761184870Syongari sc->ale_max_frame_size = ifp->if_mtu; 2762184870Syongari sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2763184870Syongari ETHER_CRC_LEN; 2764184870Syongari CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2765184870Syongari /* Configure IPG/IFG parameters. */ 2766184870Syongari CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2767184870Syongari ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2768184870Syongari ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2769184870Syongari ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2770184870Syongari ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2771184870Syongari /* Set parameters for half-duplex media. */ 2772184870Syongari CSR_WRITE_4(sc, ALE_HDPX_CFG, 2773184870Syongari ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2774184870Syongari HDPX_CFG_LCOL_MASK) | 2775184870Syongari ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2776184870Syongari HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2777184870Syongari ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2778184870Syongari HDPX_CFG_ABEBT_MASK) | 2779184870Syongari ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2780184870Syongari HDPX_CFG_JAMIPG_MASK)); 2781184870Syongari 2782184870Syongari /* Configure Tx jumbo frame parameters. */ 2783184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2784184870Syongari if (ifp->if_mtu < ETHERMTU) 2785184870Syongari reg = sc->ale_max_frame_size; 2786184870Syongari else if (ifp->if_mtu < 6 * 1024) 2787184870Syongari reg = (sc->ale_max_frame_size * 2) / 3; 2788184870Syongari else 2789184870Syongari reg = sc->ale_max_frame_size / 2; 2790184870Syongari CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2791184870Syongari roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2792184870Syongari TX_JUMBO_THRESH_UNIT_SHIFT); 2793184870Syongari } 2794184870Syongari /* Configure TxQ. */ 2795185577Syongari reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2796185577Syongari << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2797184870Syongari reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2798184870Syongari TXQ_CFG_TPD_BURST_MASK; 2799184870Syongari CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2800184870Syongari 2801184870Syongari /* Configure Rx jumbo frame & flow control parameters. */ 2802184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2803184870Syongari reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2804184870Syongari CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2805184870Syongari (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2806184870Syongari RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2807184870Syongari ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2808184870Syongari RX_JUMBO_LKAH_MASK)); 2809184870Syongari reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2810184870Syongari rxf_hi = (reg * 7) / 10; 2811184870Syongari rxf_lo = (reg * 3)/ 10; 2812184870Syongari CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2813184870Syongari ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2814184870Syongari RX_FIFO_PAUSE_THRESH_LO_MASK) | 2815184870Syongari ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2816184870Syongari RX_FIFO_PAUSE_THRESH_HI_MASK)); 2817184870Syongari } 2818184870Syongari 2819184870Syongari /* Disable RSS. */ 2820184870Syongari CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2821184870Syongari CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2822184870Syongari 2823184870Syongari /* Configure RxQ. */ 2824184870Syongari CSR_WRITE_4(sc, ALE_RXQ_CFG, 2825184870Syongari RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2826184870Syongari 2827184870Syongari /* Configure DMA parameters. */ 2828184870Syongari reg = 0; 2829184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2830184870Syongari reg |= DMA_CFG_TXCMB_ENB; 2831184870Syongari CSR_WRITE_4(sc, ALE_DMA_CFG, 2832184870Syongari DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2833184870Syongari sc->ale_dma_rd_burst | reg | 2834184870Syongari sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2835184870Syongari ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2836184870Syongari DMA_CFG_RD_DELAY_CNT_MASK) | 2837184870Syongari ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2838184870Syongari DMA_CFG_WR_DELAY_CNT_MASK)); 2839184870Syongari 2840184870Syongari /* 2841184870Syongari * Hardware can be configured to issue SMB interrupt based 2842184870Syongari * on programmed interval. Since there is a callout that is 2843184870Syongari * invoked for every hz in driver we use that instead of 2844184870Syongari * relying on periodic SMB interrupt. 2845184870Syongari */ 2846184870Syongari CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2847184870Syongari /* Clear MAC statistics. */ 2848184870Syongari ale_stats_clear(sc); 2849184870Syongari 2850184870Syongari /* 2851184870Syongari * Configure Tx/Rx MACs. 2852184870Syongari * - Auto-padding for short frames. 2853184870Syongari * - Enable CRC generation. 2854184870Syongari * Actual reconfiguration of MAC for resolved speed/duplex 2855184870Syongari * is followed after detection of link establishment. 2856184870Syongari * AR81xx always does checksum computation regardless of 2857184870Syongari * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2858184870Syongari * cause Rx handling issue for fragmented IP datagrams due 2859184870Syongari * to silicon bug. 2860184870Syongari */ 2861184870Syongari reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2862184870Syongari ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2863184870Syongari MAC_CFG_PREAMBLE_MASK); 2864184870Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2865184870Syongari reg |= MAC_CFG_SPEED_10_100; 2866184870Syongari else 2867184870Syongari reg |= MAC_CFG_SPEED_1000; 2868184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2869184870Syongari 2870184870Syongari /* Set up the receive filter. */ 2871184870Syongari ale_rxfilter(sc); 2872184870Syongari ale_rxvlan(sc); 2873184870Syongari 2874184870Syongari /* Acknowledge all pending interrupts and clear it. */ 2875184870Syongari CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2876184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2877184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2878184870Syongari 2879184870Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 2880184870Syongari /* Switch to the current media. */ 2881184870Syongari mii_mediachg(mii); 2882184870Syongari 2883184870Syongari callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2884184870Syongari 2885184870Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2886184870Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2887184870Syongari} 2888184870Syongari 2889184870Syongaristatic void 2890184870Syongariale_stop(struct ale_softc *sc) 2891184870Syongari{ 2892184870Syongari struct ifnet *ifp; 2893184870Syongari struct ale_txdesc *txd; 2894184870Syongari uint32_t reg; 2895184870Syongari int i; 2896184870Syongari 2897184870Syongari ALE_LOCK_ASSERT(sc); 2898184870Syongari /* 2899184870Syongari * Mark the interface down and cancel the watchdog timer. 2900184870Syongari */ 2901184870Syongari ifp = sc->ale_ifp; 2902184870Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2903184870Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 2904184870Syongari callout_stop(&sc->ale_tick_ch); 2905184870Syongari sc->ale_watchdog_timer = 0; 2906184870Syongari ale_stats_update(sc); 2907184870Syongari /* Disable interrupts. */ 2908184870Syongari CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2909184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2910184870Syongari /* Disable queue processing and DMA. */ 2911184870Syongari reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2912184870Syongari reg &= ~TXQ_CFG_ENB; 2913184870Syongari CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2914184870Syongari reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2915184870Syongari reg &= ~RXQ_CFG_ENB; 2916184870Syongari CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2917184870Syongari reg = CSR_READ_4(sc, ALE_DMA_CFG); 2918184870Syongari reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2919184870Syongari CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2920184870Syongari DELAY(1000); 2921184870Syongari /* Stop Rx/Tx MACs. */ 2922184870Syongari ale_stop_mac(sc); 2923184870Syongari /* Disable interrupts which might be touched in taskq handler. */ 2924184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2925184870Syongari 2926184870Syongari /* 2927184870Syongari * Free TX mbufs still in the queues. 2928184870Syongari */ 2929184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 2930184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 2931184870Syongari if (txd->tx_m != NULL) { 2932184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2933184870Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2934184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2935184870Syongari txd->tx_dmamap); 2936184870Syongari m_freem(txd->tx_m); 2937184870Syongari txd->tx_m = NULL; 2938184870Syongari } 2939184870Syongari } 2940184870Syongari} 2941184870Syongari 2942184870Syongaristatic void 2943184870Syongariale_stop_mac(struct ale_softc *sc) 2944184870Syongari{ 2945184870Syongari uint32_t reg; 2946184870Syongari int i; 2947184870Syongari 2948184870Syongari ALE_LOCK_ASSERT(sc); 2949184870Syongari 2950184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 2951184870Syongari if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2952184870Syongari reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2953184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2954184870Syongari } 2955184870Syongari 2956184870Syongari for (i = ALE_TIMEOUT; i > 0; i--) { 2957184870Syongari reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2958184870Syongari if (reg == 0) 2959184870Syongari break; 2960184870Syongari DELAY(10); 2961184870Syongari } 2962184870Syongari if (i == 0) 2963184870Syongari device_printf(sc->ale_dev, 2964184870Syongari "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2965184870Syongari} 2966184870Syongari 2967184870Syongaristatic void 2968184870Syongariale_init_tx_ring(struct ale_softc *sc) 2969184870Syongari{ 2970184870Syongari struct ale_txdesc *txd; 2971184870Syongari int i; 2972184870Syongari 2973184870Syongari ALE_LOCK_ASSERT(sc); 2974184870Syongari 2975184870Syongari sc->ale_cdata.ale_tx_prod = 0; 2976184870Syongari sc->ale_cdata.ale_tx_cons = 0; 2977184870Syongari sc->ale_cdata.ale_tx_cnt = 0; 2978184870Syongari 2979184870Syongari bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2980184870Syongari bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2981184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 2982184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 2983184870Syongari txd->tx_m = NULL; 2984184870Syongari } 2985184870Syongari *sc->ale_cdata.ale_tx_cmb = 0; 2986184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2987184870Syongari sc->ale_cdata.ale_tx_cmb_map, 2988184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2989184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2990184870Syongari sc->ale_cdata.ale_tx_ring_map, 2991184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2992184870Syongari} 2993184870Syongari 2994184870Syongaristatic void 2995184870Syongariale_init_rx_pages(struct ale_softc *sc) 2996184870Syongari{ 2997184870Syongari struct ale_rx_page *rx_page; 2998184870Syongari int i; 2999184870Syongari 3000184870Syongari ALE_LOCK_ASSERT(sc); 3001184870Syongari 3002216438Syongari sc->ale_morework = 0; 3003184870Syongari sc->ale_cdata.ale_rx_seqno = 0; 3004184870Syongari sc->ale_cdata.ale_rx_curp = 0; 3005184870Syongari 3006184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 3007184870Syongari rx_page = &sc->ale_cdata.ale_rx_page[i]; 3008184870Syongari bzero(rx_page->page_addr, sc->ale_pagesize); 3009184870Syongari bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 3010184870Syongari rx_page->cons = 0; 3011184870Syongari *rx_page->cmb_addr = 0; 3012184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 3013184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3014184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 3015184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3016184870Syongari } 3017184870Syongari} 3018184870Syongari 3019184870Syongaristatic void 3020184870Syongariale_rxvlan(struct ale_softc *sc) 3021184870Syongari{ 3022184870Syongari struct ifnet *ifp; 3023184870Syongari uint32_t reg; 3024184870Syongari 3025184870Syongari ALE_LOCK_ASSERT(sc); 3026184870Syongari 3027184870Syongari ifp = sc->ale_ifp; 3028184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 3029184870Syongari reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3030184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3031184870Syongari reg |= MAC_CFG_VLAN_TAG_STRIP; 3032184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3033184870Syongari} 3034184870Syongari 3035184870Syongaristatic void 3036184870Syongariale_rxfilter(struct ale_softc *sc) 3037184870Syongari{ 3038184870Syongari struct ifnet *ifp; 3039184870Syongari struct ifmultiaddr *ifma; 3040184870Syongari uint32_t crc; 3041184870Syongari uint32_t mchash[2]; 3042184870Syongari uint32_t rxcfg; 3043184870Syongari 3044184870Syongari ALE_LOCK_ASSERT(sc); 3045184870Syongari 3046184870Syongari ifp = sc->ale_ifp; 3047184870Syongari 3048184870Syongari rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3049184870Syongari rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3050184870Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 3051184870Syongari rxcfg |= MAC_CFG_BCAST; 3052184870Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3053184870Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 3054184870Syongari rxcfg |= MAC_CFG_PROMISC; 3055184870Syongari if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3056184870Syongari rxcfg |= MAC_CFG_ALLMULTI; 3057184870Syongari CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3058184870Syongari CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3059184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3060184870Syongari return; 3061184870Syongari } 3062184870Syongari 3063184870Syongari /* Program new filter. */ 3064184870Syongari bzero(mchash, sizeof(mchash)); 3065184870Syongari 3066195049Srwatson if_maddr_rlock(ifp); 3067184870Syongari TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3068184870Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 3069184870Syongari continue; 3070197627Syongari crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3071184870Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 3072184870Syongari mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3073184870Syongari } 3074195049Srwatson if_maddr_runlock(ifp); 3075184870Syongari 3076184870Syongari CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3077184870Syongari CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3078184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3079184870Syongari} 3080184870Syongari 3081184870Syongaristatic int 3082184870Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3083184870Syongari{ 3084184870Syongari int error, value; 3085184870Syongari 3086184870Syongari if (arg1 == NULL) 3087184870Syongari return (EINVAL); 3088184870Syongari value = *(int *)arg1; 3089184870Syongari error = sysctl_handle_int(oidp, &value, 0, req); 3090184870Syongari if (error || req->newptr == NULL) 3091184870Syongari return (error); 3092184870Syongari if (value < low || value > high) 3093184870Syongari return (EINVAL); 3094184870Syongari *(int *)arg1 = value; 3095184870Syongari 3096184870Syongari return (0); 3097184870Syongari} 3098184870Syongari 3099184870Syongaristatic int 3100184870Syongarisysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3101184870Syongari{ 3102184870Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3103184870Syongari ALE_PROC_MIN, ALE_PROC_MAX)); 3104184870Syongari} 3105184870Syongari 3106184870Syongaristatic int 3107184870Syongarisysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3108184870Syongari{ 3109184870Syongari 3110184870Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3111184870Syongari ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3112184870Syongari} 3113