if_ale.c revision 219902
1184870Syongari/*- 2184870Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3184870Syongari * All rights reserved. 4184870Syongari * 5184870Syongari * Redistribution and use in source and binary forms, with or without 6184870Syongari * modification, are permitted provided that the following conditions 7184870Syongari * are met: 8184870Syongari * 1. Redistributions of source code must retain the above copyright 9184870Syongari * notice unmodified, this list of conditions, and the following 10184870Syongari * disclaimer. 11184870Syongari * 2. Redistributions in binary form must reproduce the above copyright 12184870Syongari * notice, this list of conditions and the following disclaimer in the 13184870Syongari * documentation and/or other materials provided with the distribution. 14184870Syongari * 15184870Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16184870Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17184870Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18184870Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19184870Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20184870Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21184870Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22184870Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23184870Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24184870Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25184870Syongari * SUCH DAMAGE. 26184870Syongari */ 27184870Syongari 28184870Syongari/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29184870Syongari 30184870Syongari#include <sys/cdefs.h> 31184870Syongari__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 219902 2011-03-23 13:10:15Z jhb $"); 32184870Syongari 33184870Syongari#include <sys/param.h> 34184870Syongari#include <sys/systm.h> 35184870Syongari#include <sys/bus.h> 36184870Syongari#include <sys/endian.h> 37184870Syongari#include <sys/kernel.h> 38184870Syongari#include <sys/malloc.h> 39184870Syongari#include <sys/mbuf.h> 40184870Syongari#include <sys/module.h> 41184870Syongari#include <sys/rman.h> 42184870Syongari#include <sys/queue.h> 43184870Syongari#include <sys/socket.h> 44184870Syongari#include <sys/sockio.h> 45184870Syongari#include <sys/sysctl.h> 46184870Syongari#include <sys/taskqueue.h> 47184870Syongari 48184870Syongari#include <net/bpf.h> 49184870Syongari#include <net/if.h> 50184870Syongari#include <net/if_arp.h> 51184870Syongari#include <net/ethernet.h> 52184870Syongari#include <net/if_dl.h> 53184870Syongari#include <net/if_llc.h> 54184870Syongari#include <net/if_media.h> 55184870Syongari#include <net/if_types.h> 56184870Syongari#include <net/if_vlan_var.h> 57184870Syongari 58184870Syongari#include <netinet/in.h> 59184870Syongari#include <netinet/in_systm.h> 60184870Syongari#include <netinet/ip.h> 61184870Syongari#include <netinet/tcp.h> 62184870Syongari 63184870Syongari#include <dev/mii/mii.h> 64184870Syongari#include <dev/mii/miivar.h> 65184870Syongari 66184870Syongari#include <dev/pci/pcireg.h> 67184870Syongari#include <dev/pci/pcivar.h> 68184870Syongari 69184870Syongari#include <machine/bus.h> 70184870Syongari#include <machine/in_cksum.h> 71184870Syongari 72184870Syongari#include <dev/ale/if_alereg.h> 73184870Syongari#include <dev/ale/if_alevar.h> 74184870Syongari 75184870Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 76184870Syongari#include "miibus_if.h" 77184870Syongari 78184870Syongari/* For more information about Tx checksum offload issues see ale_encap(). */ 79184870Syongari#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 80184870Syongari 81184870SyongariMODULE_DEPEND(ale, pci, 1, 1, 1); 82184870SyongariMODULE_DEPEND(ale, ether, 1, 1, 1); 83184870SyongariMODULE_DEPEND(ale, miibus, 1, 1, 1); 84184870Syongari 85184870Syongari/* Tunables. */ 86184870Syongaristatic int msi_disable = 0; 87184870Syongaristatic int msix_disable = 0; 88184870SyongariTUNABLE_INT("hw.ale.msi_disable", &msi_disable); 89184870SyongariTUNABLE_INT("hw.ale.msix_disable", &msix_disable); 90184870Syongari 91184870Syongari/* 92184870Syongari * Devices supported by this driver. 93184870Syongari */ 94184870Syongaristatic struct ale_dev { 95184870Syongari uint16_t ale_vendorid; 96184870Syongari uint16_t ale_deviceid; 97184870Syongari const char *ale_name; 98184870Syongari} ale_devs[] = { 99184870Syongari { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 100184870Syongari "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 101184870Syongari}; 102184870Syongari 103184870Syongaristatic int ale_attach(device_t); 104184870Syongaristatic int ale_check_boundary(struct ale_softc *); 105184870Syongaristatic int ale_detach(device_t); 106184870Syongaristatic int ale_dma_alloc(struct ale_softc *); 107184870Syongaristatic void ale_dma_free(struct ale_softc *); 108184870Syongaristatic void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109184870Syongaristatic int ale_encap(struct ale_softc *, struct mbuf **); 110184870Syongaristatic void ale_get_macaddr(struct ale_softc *); 111184870Syongaristatic void ale_init(void *); 112184870Syongaristatic void ale_init_locked(struct ale_softc *); 113184870Syongaristatic void ale_init_rx_pages(struct ale_softc *); 114184870Syongaristatic void ale_init_tx_ring(struct ale_softc *); 115184870Syongaristatic void ale_int_task(void *, int); 116184870Syongaristatic int ale_intr(void *); 117184870Syongaristatic int ale_ioctl(struct ifnet *, u_long, caddr_t); 118184870Syongaristatic void ale_link_task(void *, int); 119184870Syongaristatic void ale_mac_config(struct ale_softc *); 120184870Syongaristatic int ale_miibus_readreg(device_t, int, int); 121184870Syongaristatic void ale_miibus_statchg(device_t); 122184870Syongaristatic int ale_miibus_writereg(device_t, int, int, int); 123184870Syongaristatic int ale_mediachange(struct ifnet *); 124184870Syongaristatic void ale_mediastatus(struct ifnet *, struct ifmediareq *); 125184870Syongaristatic void ale_phy_reset(struct ale_softc *); 126184870Syongaristatic int ale_probe(device_t); 127184870Syongaristatic void ale_reset(struct ale_softc *); 128184870Syongaristatic int ale_resume(device_t); 129184870Syongaristatic void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 130184870Syongari uint32_t, uint32_t *); 131184870Syongaristatic void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 132184870Syongaristatic int ale_rxeof(struct ale_softc *sc, int); 133184870Syongaristatic void ale_rxfilter(struct ale_softc *); 134184870Syongaristatic void ale_rxvlan(struct ale_softc *); 135184870Syongaristatic void ale_setlinkspeed(struct ale_softc *); 136184870Syongaristatic void ale_setwol(struct ale_softc *); 137184870Syongaristatic int ale_shutdown(device_t); 138184870Syongaristatic void ale_start(struct ifnet *); 139216925Sjhbstatic void ale_start_locked(struct ifnet *); 140184870Syongaristatic void ale_stats_clear(struct ale_softc *); 141184870Syongaristatic void ale_stats_update(struct ale_softc *); 142184870Syongaristatic void ale_stop(struct ale_softc *); 143184870Syongaristatic void ale_stop_mac(struct ale_softc *); 144184870Syongaristatic int ale_suspend(device_t); 145184870Syongaristatic void ale_sysctl_node(struct ale_softc *); 146184870Syongaristatic void ale_tick(void *); 147184870Syongaristatic void ale_txeof(struct ale_softc *); 148184870Syongaristatic void ale_watchdog(struct ale_softc *); 149184870Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150184870Syongaristatic int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 151184870Syongaristatic int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 152184870Syongari 153184870Syongaristatic device_method_t ale_methods[] = { 154184870Syongari /* Device interface. */ 155184870Syongari DEVMETHOD(device_probe, ale_probe), 156184870Syongari DEVMETHOD(device_attach, ale_attach), 157184870Syongari DEVMETHOD(device_detach, ale_detach), 158184870Syongari DEVMETHOD(device_shutdown, ale_shutdown), 159184870Syongari DEVMETHOD(device_suspend, ale_suspend), 160184870Syongari DEVMETHOD(device_resume, ale_resume), 161184870Syongari 162184870Syongari /* MII interface. */ 163184870Syongari DEVMETHOD(miibus_readreg, ale_miibus_readreg), 164184870Syongari DEVMETHOD(miibus_writereg, ale_miibus_writereg), 165184870Syongari DEVMETHOD(miibus_statchg, ale_miibus_statchg), 166184870Syongari 167184870Syongari { NULL, NULL } 168184870Syongari}; 169184870Syongari 170184870Syongaristatic driver_t ale_driver = { 171184870Syongari "ale", 172184870Syongari ale_methods, 173184870Syongari sizeof(struct ale_softc) 174184870Syongari}; 175184870Syongari 176184870Syongaristatic devclass_t ale_devclass; 177184870Syongari 178184870SyongariDRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0); 179184870SyongariDRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 180184870Syongari 181184870Syongaristatic struct resource_spec ale_res_spec_mem[] = { 182184870Syongari { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 183184870Syongari { -1, 0, 0 } 184184870Syongari}; 185184870Syongari 186184870Syongaristatic struct resource_spec ale_irq_spec_legacy[] = { 187184870Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 188184870Syongari { -1, 0, 0 } 189184870Syongari}; 190184870Syongari 191184870Syongaristatic struct resource_spec ale_irq_spec_msi[] = { 192184870Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 193184870Syongari { -1, 0, 0 } 194184870Syongari}; 195184870Syongari 196184870Syongaristatic struct resource_spec ale_irq_spec_msix[] = { 197184870Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 198184870Syongari { -1, 0, 0 } 199184870Syongari}; 200184870Syongari 201184870Syongaristatic int 202184870Syongariale_miibus_readreg(device_t dev, int phy, int reg) 203184870Syongari{ 204184870Syongari struct ale_softc *sc; 205184870Syongari uint32_t v; 206184870Syongari int i; 207184870Syongari 208184870Syongari sc = device_get_softc(dev); 209184870Syongari 210184870Syongari CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 211184870Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 212184870Syongari for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 213184870Syongari DELAY(5); 214184870Syongari v = CSR_READ_4(sc, ALE_MDIO); 215184870Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 216184870Syongari break; 217184870Syongari } 218184870Syongari 219184870Syongari if (i == 0) { 220184870Syongari device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 221184870Syongari return (0); 222184870Syongari } 223184870Syongari 224184870Syongari return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 225184870Syongari} 226184870Syongari 227184870Syongaristatic int 228184870Syongariale_miibus_writereg(device_t dev, int phy, int reg, int val) 229184870Syongari{ 230184870Syongari struct ale_softc *sc; 231184870Syongari uint32_t v; 232184870Syongari int i; 233184870Syongari 234184870Syongari sc = device_get_softc(dev); 235184870Syongari 236184870Syongari CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 237184870Syongari (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 238184870Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 239184870Syongari for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 240184870Syongari DELAY(5); 241184870Syongari v = CSR_READ_4(sc, ALE_MDIO); 242184870Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 243184870Syongari break; 244184870Syongari } 245184870Syongari 246184870Syongari if (i == 0) 247184870Syongari device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 248184870Syongari 249184870Syongari return (0); 250184870Syongari} 251184870Syongari 252184870Syongaristatic void 253184870Syongariale_miibus_statchg(device_t dev) 254184870Syongari{ 255184870Syongari struct ale_softc *sc; 256184870Syongari 257184870Syongari sc = device_get_softc(dev); 258184870Syongari 259184870Syongari taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task); 260184870Syongari} 261184870Syongari 262184870Syongaristatic void 263184870Syongariale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 264184870Syongari{ 265184870Syongari struct ale_softc *sc; 266184870Syongari struct mii_data *mii; 267184870Syongari 268184870Syongari sc = ifp->if_softc; 269184870Syongari ALE_LOCK(sc); 270184870Syongari mii = device_get_softc(sc->ale_miibus); 271184870Syongari 272184870Syongari mii_pollstat(mii); 273184870Syongari ALE_UNLOCK(sc); 274184870Syongari ifmr->ifm_status = mii->mii_media_status; 275184870Syongari ifmr->ifm_active = mii->mii_media_active; 276184870Syongari} 277184870Syongari 278184870Syongaristatic int 279184870Syongariale_mediachange(struct ifnet *ifp) 280184870Syongari{ 281184870Syongari struct ale_softc *sc; 282184870Syongari struct mii_data *mii; 283184870Syongari struct mii_softc *miisc; 284184870Syongari int error; 285184870Syongari 286184870Syongari sc = ifp->if_softc; 287184870Syongari ALE_LOCK(sc); 288184870Syongari mii = device_get_softc(sc->ale_miibus); 289184870Syongari if (mii->mii_instance != 0) { 290184870Syongari LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 291184870Syongari mii_phy_reset(miisc); 292184870Syongari } 293184870Syongari error = mii_mediachg(mii); 294184870Syongari ALE_UNLOCK(sc); 295184870Syongari 296184870Syongari return (error); 297184870Syongari} 298184870Syongari 299184870Syongaristatic int 300184870Syongariale_probe(device_t dev) 301184870Syongari{ 302184870Syongari struct ale_dev *sp; 303184870Syongari int i; 304184870Syongari uint16_t vendor, devid; 305184870Syongari 306184870Syongari vendor = pci_get_vendor(dev); 307184870Syongari devid = pci_get_device(dev); 308184870Syongari sp = ale_devs; 309184870Syongari for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 310184870Syongari if (vendor == sp->ale_vendorid && 311184870Syongari devid == sp->ale_deviceid) { 312184870Syongari device_set_desc(dev, sp->ale_name); 313184870Syongari return (BUS_PROBE_DEFAULT); 314184870Syongari } 315184870Syongari sp++; 316184870Syongari } 317184870Syongari 318184870Syongari return (ENXIO); 319184870Syongari} 320184870Syongari 321184870Syongaristatic void 322184870Syongariale_get_macaddr(struct ale_softc *sc) 323184870Syongari{ 324184870Syongari uint32_t ea[2], reg; 325184870Syongari int i, vpdc; 326184870Syongari 327184870Syongari reg = CSR_READ_4(sc, ALE_SPI_CTRL); 328184870Syongari if ((reg & SPI_VPD_ENB) != 0) { 329184870Syongari reg &= ~SPI_VPD_ENB; 330184870Syongari CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 331184870Syongari } 332184870Syongari 333219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 334184870Syongari /* 335184870Syongari * PCI VPD capability found, let TWSI reload EEPROM. 336184870Syongari * This will set ethernet address of controller. 337184870Syongari */ 338184870Syongari CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 339184870Syongari TWSI_CTRL_SW_LD_START); 340184870Syongari for (i = 100; i > 0; i--) { 341184870Syongari DELAY(1000); 342184870Syongari reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 343184870Syongari if ((reg & TWSI_CTRL_SW_LD_START) == 0) 344184870Syongari break; 345184870Syongari } 346184870Syongari if (i == 0) 347184870Syongari device_printf(sc->ale_dev, 348184870Syongari "reloading EEPROM timeout!\n"); 349184870Syongari } else { 350184870Syongari if (bootverbose) 351184870Syongari device_printf(sc->ale_dev, 352184870Syongari "PCI VPD capability not found!\n"); 353184870Syongari } 354184870Syongari 355184870Syongari ea[0] = CSR_READ_4(sc, ALE_PAR0); 356184870Syongari ea[1] = CSR_READ_4(sc, ALE_PAR1); 357184870Syongari sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 358184870Syongari sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 359184870Syongari sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 360184870Syongari sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 361184870Syongari sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 362184870Syongari sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 363184870Syongari} 364184870Syongari 365184870Syongaristatic void 366184870Syongariale_phy_reset(struct ale_softc *sc) 367184870Syongari{ 368184870Syongari 369184870Syongari /* Reset magic from Linux. */ 370184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 371184870Syongari GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 372184870Syongari GPHY_CTRL_PHY_PLL_ON); 373184870Syongari DELAY(1000); 374184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 375184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 376184870Syongari GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 377184870Syongari DELAY(1000); 378185576Syongari 379185576Syongari#define ATPHY_DBG_ADDR 0x1D 380185576Syongari#define ATPHY_DBG_DATA 0x1E 381185576Syongari 382185576Syongari /* Enable hibernation mode. */ 383185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 384185576Syongari ATPHY_DBG_ADDR, 0x0B); 385185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 386185576Syongari ATPHY_DBG_DATA, 0xBC00); 387185576Syongari /* Set Class A/B for all modes. */ 388185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 389185576Syongari ATPHY_DBG_ADDR, 0x00); 390185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 391185576Syongari ATPHY_DBG_DATA, 0x02EF); 392185576Syongari /* Enable 10BT power saving. */ 393185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 394185576Syongari ATPHY_DBG_ADDR, 0x12); 395185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 396185576Syongari ATPHY_DBG_DATA, 0x4C04); 397185576Syongari /* Adjust 1000T power. */ 398185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 399185576Syongari ATPHY_DBG_ADDR, 0x04); 400185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 401185576Syongari ATPHY_DBG_ADDR, 0x8BBB); 402185576Syongari /* 10BT center tap voltage. */ 403185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 404185576Syongari ATPHY_DBG_ADDR, 0x05); 405185576Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 406185576Syongari ATPHY_DBG_ADDR, 0x2C46); 407185576Syongari 408185576Syongari#undef ATPHY_DBG_ADDR 409185576Syongari#undef ATPHY_DBG_DATA 410185576Syongari DELAY(1000); 411184870Syongari} 412184870Syongari 413184870Syongaristatic int 414184870Syongariale_attach(device_t dev) 415184870Syongari{ 416184870Syongari struct ale_softc *sc; 417184870Syongari struct ifnet *ifp; 418184870Syongari uint16_t burst; 419184870Syongari int error, i, msic, msixc, pmc; 420184870Syongari uint32_t rxf_len, txf_len; 421184870Syongari 422184870Syongari error = 0; 423184870Syongari sc = device_get_softc(dev); 424184870Syongari sc->ale_dev = dev; 425184870Syongari 426184870Syongari mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 427184870Syongari MTX_DEF); 428184870Syongari callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 429184870Syongari TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 430184870Syongari TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc); 431184870Syongari 432184870Syongari /* Map the device. */ 433184870Syongari pci_enable_busmaster(dev); 434184870Syongari sc->ale_res_spec = ale_res_spec_mem; 435184870Syongari sc->ale_irq_spec = ale_irq_spec_legacy; 436184870Syongari error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 437184870Syongari if (error != 0) { 438184870Syongari device_printf(dev, "cannot allocate memory resources.\n"); 439184870Syongari goto fail; 440184870Syongari } 441184870Syongari 442184870Syongari /* Set PHY address. */ 443184870Syongari sc->ale_phyaddr = ALE_PHY_ADDR; 444184870Syongari 445184870Syongari /* Reset PHY. */ 446184870Syongari ale_phy_reset(sc); 447184870Syongari 448184870Syongari /* Reset the ethernet controller. */ 449184870Syongari ale_reset(sc); 450184870Syongari 451184870Syongari /* Get PCI and chip id/revision. */ 452184870Syongari sc->ale_rev = pci_get_revid(dev); 453184870Syongari if (sc->ale_rev >= 0xF0) { 454184870Syongari /* L2E Rev. B. AR8114 */ 455184870Syongari sc->ale_flags |= ALE_FLAG_FASTETHER; 456184870Syongari } else { 457184870Syongari if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 458184870Syongari /* L1E AR8121 */ 459184870Syongari sc->ale_flags |= ALE_FLAG_JUMBO; 460184870Syongari } else { 461184870Syongari /* L2E Rev. A. AR8113 */ 462184870Syongari sc->ale_flags |= ALE_FLAG_FASTETHER; 463184870Syongari } 464184870Syongari } 465184870Syongari /* 466184870Syongari * All known controllers seems to require 4 bytes alignment 467184870Syongari * of Tx buffers to make Tx checksum offload with custom 468184870Syongari * checksum generation method work. 469184870Syongari */ 470184870Syongari sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 471184870Syongari /* 472184870Syongari * All known controllers seems to have issues on Rx checksum 473184870Syongari * offload for fragmented IP datagrams. 474184870Syongari */ 475184870Syongari sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 476184870Syongari /* 477184870Syongari * Don't use Tx CMB. It is known to cause RRS update failure 478184870Syongari * under certain circumstances. Typical phenomenon of the 479184870Syongari * issue would be unexpected sequence number encountered in 480184870Syongari * Rx handler. 481184870Syongari */ 482184870Syongari sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 483184870Syongari sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 484184870Syongari MASTER_CHIP_REV_SHIFT; 485184870Syongari if (bootverbose) { 486184870Syongari device_printf(dev, "PCI device revision : 0x%04x\n", 487184870Syongari sc->ale_rev); 488184870Syongari device_printf(dev, "Chip id/revision : 0x%04x\n", 489184870Syongari sc->ale_chip_rev); 490184870Syongari } 491184870Syongari txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 492184870Syongari rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 493184870Syongari /* 494184870Syongari * Uninitialized hardware returns an invalid chip id/revision 495184870Syongari * as well as 0xFFFFFFFF for Tx/Rx fifo length. 496184870Syongari */ 497184870Syongari if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 498184870Syongari rxf_len == 0xFFFFFFF) { 499184870Syongari device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 500184870Syongari "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 501184870Syongari txf_len, rxf_len); 502184870Syongari error = ENXIO; 503184870Syongari goto fail; 504184870Syongari } 505184870Syongari device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 506184870Syongari 507184870Syongari /* Allocate IRQ resources. */ 508184870Syongari msixc = pci_msix_count(dev); 509184870Syongari msic = pci_msi_count(dev); 510184870Syongari if (bootverbose) { 511184870Syongari device_printf(dev, "MSIX count : %d\n", msixc); 512184870Syongari device_printf(dev, "MSI count : %d\n", msic); 513184870Syongari } 514184870Syongari 515184870Syongari /* Prefer MSIX over MSI. */ 516184870Syongari if (msix_disable == 0 || msi_disable == 0) { 517184870Syongari if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 518184870Syongari pci_alloc_msix(dev, &msixc) == 0) { 519184870Syongari if (msic == ALE_MSIX_MESSAGES) { 520184870Syongari device_printf(dev, "Using %d MSIX messages.\n", 521184870Syongari msixc); 522184870Syongari sc->ale_flags |= ALE_FLAG_MSIX; 523184870Syongari sc->ale_irq_spec = ale_irq_spec_msix; 524184870Syongari } else 525184870Syongari pci_release_msi(dev); 526184870Syongari } 527184870Syongari if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 528184870Syongari msic == ALE_MSI_MESSAGES && 529184870Syongari pci_alloc_msi(dev, &msic) == 0) { 530184870Syongari if (msic == ALE_MSI_MESSAGES) { 531184870Syongari device_printf(dev, "Using %d MSI messages.\n", 532184870Syongari msic); 533184870Syongari sc->ale_flags |= ALE_FLAG_MSI; 534184870Syongari sc->ale_irq_spec = ale_irq_spec_msi; 535184870Syongari } else 536184870Syongari pci_release_msi(dev); 537184870Syongari } 538184870Syongari } 539184870Syongari 540184870Syongari error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 541184870Syongari if (error != 0) { 542184870Syongari device_printf(dev, "cannot allocate IRQ resources.\n"); 543184870Syongari goto fail; 544184870Syongari } 545184870Syongari 546184870Syongari /* Get DMA parameters from PCIe device control register. */ 547219902Sjhb if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 548184870Syongari sc->ale_flags |= ALE_FLAG_PCIE; 549184870Syongari burst = pci_read_config(dev, i + 0x08, 2); 550184870Syongari /* Max read request size. */ 551184870Syongari sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 552184870Syongari DMA_CFG_RD_BURST_SHIFT; 553184870Syongari /* Max payload size. */ 554184870Syongari sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 555184870Syongari DMA_CFG_WR_BURST_SHIFT; 556184870Syongari if (bootverbose) { 557184870Syongari device_printf(dev, "Read request size : %d bytes.\n", 558184870Syongari 128 << ((burst >> 12) & 0x07)); 559184870Syongari device_printf(dev, "TLP payload size : %d bytes.\n", 560184870Syongari 128 << ((burst >> 5) & 0x07)); 561184870Syongari } 562184870Syongari } else { 563184870Syongari sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 564184870Syongari sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 565184870Syongari } 566184870Syongari 567184870Syongari /* Create device sysctl node. */ 568184870Syongari ale_sysctl_node(sc); 569184870Syongari 570184870Syongari if ((error = ale_dma_alloc(sc) != 0)) 571184870Syongari goto fail; 572184870Syongari 573184870Syongari /* Load station address. */ 574184870Syongari ale_get_macaddr(sc); 575184870Syongari 576184870Syongari ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 577184870Syongari if (ifp == NULL) { 578184870Syongari device_printf(dev, "cannot allocate ifnet structure.\n"); 579184870Syongari error = ENXIO; 580184870Syongari goto fail; 581184870Syongari } 582184870Syongari 583184870Syongari ifp->if_softc = sc; 584184870Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 585184870Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 586184870Syongari ifp->if_ioctl = ale_ioctl; 587184870Syongari ifp->if_start = ale_start; 588184870Syongari ifp->if_init = ale_init; 589184870Syongari ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 590184870Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 591184870Syongari IFQ_SET_READY(&ifp->if_snd); 592184870Syongari ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 593184870Syongari ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 594219902Sjhb if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 595184870Syongari sc->ale_flags |= ALE_FLAG_PMCAP; 596184870Syongari ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 597184870Syongari } 598184870Syongari ifp->if_capenable = ifp->if_capabilities; 599184870Syongari 600184870Syongari /* Set up MII bus. */ 601213893Smarius error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 602213893Smarius ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 603213893Smarius 0); 604213893Smarius if (error != 0) { 605213893Smarius device_printf(dev, "attaching PHYs failed\n"); 606184870Syongari goto fail; 607184870Syongari } 608184870Syongari 609184870Syongari ether_ifattach(ifp, sc->ale_eaddr); 610184870Syongari 611184870Syongari /* VLAN capability setup. */ 612204378Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 613204378Syongari IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 614184870Syongari ifp->if_capenable = ifp->if_capabilities; 615195153Syongari /* 616195153Syongari * Even though controllers supported by ale(3) have Rx checksum 617195153Syongari * offload bug the workaround for fragmented frames seemed to 618195153Syongari * work so far. However it seems Rx checksum offload does not 619195153Syongari * work under certain conditions. So disable Rx checksum offload 620195153Syongari * until I find more clue about it but allow users to override it. 621195153Syongari */ 622195153Syongari ifp->if_capenable &= ~IFCAP_RXCSUM; 623184870Syongari 624184870Syongari /* Tell the upper layer(s) we support long frames. */ 625184870Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 626184870Syongari 627184870Syongari /* Create local taskq. */ 628184870Syongari sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 629184870Syongari taskqueue_thread_enqueue, &sc->ale_tq); 630184870Syongari if (sc->ale_tq == NULL) { 631184870Syongari device_printf(dev, "could not create taskqueue.\n"); 632184870Syongari ether_ifdetach(ifp); 633184870Syongari error = ENXIO; 634184870Syongari goto fail; 635184870Syongari } 636184870Syongari taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 637184870Syongari device_get_nameunit(sc->ale_dev)); 638184870Syongari 639184870Syongari if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 640184870Syongari msic = ALE_MSIX_MESSAGES; 641184870Syongari else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 642184870Syongari msic = ALE_MSI_MESSAGES; 643184870Syongari else 644184870Syongari msic = 1; 645184870Syongari for (i = 0; i < msic; i++) { 646184870Syongari error = bus_setup_intr(dev, sc->ale_irq[i], 647184870Syongari INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 648184870Syongari &sc->ale_intrhand[i]); 649184870Syongari if (error != 0) 650184870Syongari break; 651184870Syongari } 652184870Syongari if (error != 0) { 653184870Syongari device_printf(dev, "could not set up interrupt handler.\n"); 654184870Syongari taskqueue_free(sc->ale_tq); 655184870Syongari sc->ale_tq = NULL; 656184870Syongari ether_ifdetach(ifp); 657184870Syongari goto fail; 658184870Syongari } 659184870Syongari 660184870Syongarifail: 661184870Syongari if (error != 0) 662184870Syongari ale_detach(dev); 663184870Syongari 664184870Syongari return (error); 665184870Syongari} 666184870Syongari 667184870Syongaristatic int 668184870Syongariale_detach(device_t dev) 669184870Syongari{ 670184870Syongari struct ale_softc *sc; 671184870Syongari struct ifnet *ifp; 672184870Syongari int i, msic; 673184870Syongari 674184870Syongari sc = device_get_softc(dev); 675184870Syongari 676184870Syongari ifp = sc->ale_ifp; 677184870Syongari if (device_is_attached(dev)) { 678217542Sjhb ether_ifdetach(ifp); 679184870Syongari ALE_LOCK(sc); 680184870Syongari ale_stop(sc); 681184870Syongari ALE_UNLOCK(sc); 682184870Syongari callout_drain(&sc->ale_tick_ch); 683184870Syongari taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 684184870Syongari taskqueue_drain(taskqueue_swi, &sc->ale_link_task); 685184870Syongari } 686184870Syongari 687184870Syongari if (sc->ale_tq != NULL) { 688184870Syongari taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 689184870Syongari taskqueue_free(sc->ale_tq); 690184870Syongari sc->ale_tq = NULL; 691184870Syongari } 692184870Syongari 693184870Syongari if (sc->ale_miibus != NULL) { 694184870Syongari device_delete_child(dev, sc->ale_miibus); 695184870Syongari sc->ale_miibus = NULL; 696184870Syongari } 697184870Syongari bus_generic_detach(dev); 698184870Syongari ale_dma_free(sc); 699184870Syongari 700184870Syongari if (ifp != NULL) { 701184870Syongari if_free(ifp); 702184870Syongari sc->ale_ifp = NULL; 703184870Syongari } 704184870Syongari 705184870Syongari if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 706184870Syongari msic = ALE_MSIX_MESSAGES; 707184870Syongari else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 708184870Syongari msic = ALE_MSI_MESSAGES; 709184870Syongari else 710184870Syongari msic = 1; 711184870Syongari for (i = 0; i < msic; i++) { 712184870Syongari if (sc->ale_intrhand[i] != NULL) { 713184870Syongari bus_teardown_intr(dev, sc->ale_irq[i], 714184870Syongari sc->ale_intrhand[i]); 715184870Syongari sc->ale_intrhand[i] = NULL; 716184870Syongari } 717184870Syongari } 718184870Syongari 719184870Syongari bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 720184870Syongari if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 721184870Syongari pci_release_msi(dev); 722184870Syongari bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 723184870Syongari mtx_destroy(&sc->ale_mtx); 724184870Syongari 725184870Syongari return (0); 726184870Syongari} 727184870Syongari 728184870Syongari#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 729184870Syongari SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 730184870Syongari 731217323Smdf#if __FreeBSD_version >= 900030 732184870Syongari#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 733217323Smdf SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 734217323Smdf#elif __FreeBSD_version > 800000 735217323Smdf#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 736184870Syongari SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 737184870Syongari#else 738184870Syongari#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 739184870Syongari SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 740184870Syongari#endif 741184870Syongari 742184870Syongaristatic void 743184870Syongariale_sysctl_node(struct ale_softc *sc) 744184870Syongari{ 745184870Syongari struct sysctl_ctx_list *ctx; 746184870Syongari struct sysctl_oid_list *child, *parent; 747184870Syongari struct sysctl_oid *tree; 748184870Syongari struct ale_hw_stats *stats; 749184870Syongari int error; 750184870Syongari 751184870Syongari stats = &sc->ale_stats; 752184870Syongari ctx = device_get_sysctl_ctx(sc->ale_dev); 753184870Syongari child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 754184870Syongari 755184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 756184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 757184870Syongari sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 758184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 759184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 760184870Syongari sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 761184870Syongari /* Pull in device tunables. */ 762184870Syongari sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 763184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 764184870Syongari device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 765184870Syongari if (error == 0) { 766184870Syongari if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 767184870Syongari sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 768184870Syongari device_printf(sc->ale_dev, "int_rx_mod value out of " 769184870Syongari "range; using default: %d\n", 770184870Syongari ALE_IM_RX_TIMER_DEFAULT); 771184870Syongari sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 772184870Syongari } 773184870Syongari } 774184870Syongari sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 775184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 776184870Syongari device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 777184870Syongari if (error == 0) { 778184870Syongari if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 779184870Syongari sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 780184870Syongari device_printf(sc->ale_dev, "int_tx_mod value out of " 781184870Syongari "range; using default: %d\n", 782184870Syongari ALE_IM_TX_TIMER_DEFAULT); 783184870Syongari sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 784184870Syongari } 785184870Syongari } 786184870Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 787184870Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 788184870Syongari sysctl_hw_ale_proc_limit, "I", 789184870Syongari "max number of Rx events to process"); 790184870Syongari /* Pull in device tunables. */ 791184870Syongari sc->ale_process_limit = ALE_PROC_DEFAULT; 792184870Syongari error = resource_int_value(device_get_name(sc->ale_dev), 793184870Syongari device_get_unit(sc->ale_dev), "process_limit", 794184870Syongari &sc->ale_process_limit); 795184870Syongari if (error == 0) { 796184870Syongari if (sc->ale_process_limit < ALE_PROC_MIN || 797184870Syongari sc->ale_process_limit > ALE_PROC_MAX) { 798184870Syongari device_printf(sc->ale_dev, 799184870Syongari "process_limit value out of range; " 800184870Syongari "using default: %d\n", ALE_PROC_DEFAULT); 801184870Syongari sc->ale_process_limit = ALE_PROC_DEFAULT; 802184870Syongari } 803184870Syongari } 804184870Syongari 805184870Syongari /* Misc statistics. */ 806184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 807184870Syongari &stats->reset_brk_seq, 808184870Syongari "Controller resets due to broken Rx sequnce number"); 809184870Syongari 810184870Syongari tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 811184870Syongari NULL, "ATE statistics"); 812184870Syongari parent = SYSCTL_CHILDREN(tree); 813184870Syongari 814184870Syongari /* Rx statistics. */ 815184870Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 816184870Syongari NULL, "Rx MAC statistics"); 817184870Syongari child = SYSCTL_CHILDREN(tree); 818184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 819184870Syongari &stats->rx_frames, "Good frames"); 820184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 821184870Syongari &stats->rx_bcast_frames, "Good broadcast frames"); 822184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 823184870Syongari &stats->rx_mcast_frames, "Good multicast frames"); 824184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 825184870Syongari &stats->rx_pause_frames, "Pause control frames"); 826184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 827184870Syongari &stats->rx_control_frames, "Control frames"); 828184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 829184870Syongari &stats->rx_crcerrs, "CRC errors"); 830184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 831184870Syongari &stats->rx_lenerrs, "Frames with length mismatched"); 832184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 833184870Syongari &stats->rx_bytes, "Good octets"); 834184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 835184870Syongari &stats->rx_bcast_bytes, "Good broadcast octets"); 836184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 837184870Syongari &stats->rx_mcast_bytes, "Good multicast octets"); 838184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 839184870Syongari &stats->rx_runts, "Too short frames"); 840184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 841184870Syongari &stats->rx_fragments, "Fragmented frames"); 842184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 843184870Syongari &stats->rx_pkts_64, "64 bytes frames"); 844184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 845184870Syongari &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 846184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 847184870Syongari &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 848184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 849184870Syongari &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 850184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 851184870Syongari &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 852184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 853184870Syongari &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 854184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 855184870Syongari &stats->rx_pkts_1519_max, "1519 to max frames"); 856184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 857184870Syongari &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 858184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 859184870Syongari &stats->rx_fifo_oflows, "FIFO overflows"); 860184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 861184870Syongari &stats->rx_rrs_errs, "Return status write-back errors"); 862184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 863184870Syongari &stats->rx_alignerrs, "Alignment errors"); 864184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 865184870Syongari &stats->rx_pkts_filtered, 866184870Syongari "Frames dropped due to address filtering"); 867184870Syongari 868184870Syongari /* Tx statistics. */ 869184870Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 870184870Syongari NULL, "Tx MAC statistics"); 871184870Syongari child = SYSCTL_CHILDREN(tree); 872184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 873184870Syongari &stats->tx_frames, "Good frames"); 874184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 875184870Syongari &stats->tx_bcast_frames, "Good broadcast frames"); 876184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 877184870Syongari &stats->tx_mcast_frames, "Good multicast frames"); 878184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 879184870Syongari &stats->tx_pause_frames, "Pause control frames"); 880184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 881184870Syongari &stats->tx_control_frames, "Control frames"); 882184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 883184870Syongari &stats->tx_excess_defer, "Frames with excessive derferrals"); 884184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 885184870Syongari &stats->tx_excess_defer, "Frames with derferrals"); 886184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 887184870Syongari &stats->tx_bytes, "Good octets"); 888184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 889184870Syongari &stats->tx_bcast_bytes, "Good broadcast octets"); 890184870Syongari ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 891184870Syongari &stats->tx_mcast_bytes, "Good multicast octets"); 892184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 893184870Syongari &stats->tx_pkts_64, "64 bytes frames"); 894184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 895184870Syongari &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 896184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 897184870Syongari &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 898184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 899184870Syongari &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 900184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 901184870Syongari &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 902184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 903184870Syongari &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 904184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 905184870Syongari &stats->tx_pkts_1519_max, "1519 to max frames"); 906184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 907184870Syongari &stats->tx_single_colls, "Single collisions"); 908184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 909184870Syongari &stats->tx_multi_colls, "Multiple collisions"); 910184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 911184870Syongari &stats->tx_late_colls, "Late collisions"); 912184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 913184870Syongari &stats->tx_excess_colls, "Excessive collisions"); 914184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 915184870Syongari &stats->tx_abort, "Aborted frames due to Excessive collisions"); 916184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 917184870Syongari &stats->tx_underrun, "FIFO underruns"); 918184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 919184870Syongari &stats->tx_desc_underrun, "Descriptor write-back errors"); 920184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 921184870Syongari &stats->tx_lenerrs, "Frames with length mismatched"); 922184870Syongari ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 923184870Syongari &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 924184870Syongari} 925184870Syongari 926184870Syongari#undef ALE_SYSCTL_STAT_ADD32 927184870Syongari#undef ALE_SYSCTL_STAT_ADD64 928184870Syongari 929184870Syongaristruct ale_dmamap_arg { 930184870Syongari bus_addr_t ale_busaddr; 931184870Syongari}; 932184870Syongari 933184870Syongaristatic void 934184870Syongariale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 935184870Syongari{ 936184870Syongari struct ale_dmamap_arg *ctx; 937184870Syongari 938184870Syongari if (error != 0) 939184870Syongari return; 940184870Syongari 941184870Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 942184870Syongari 943184870Syongari ctx = (struct ale_dmamap_arg *)arg; 944184870Syongari ctx->ale_busaddr = segs[0].ds_addr; 945184870Syongari} 946184870Syongari 947184870Syongari/* 948184870Syongari * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 949184870Syongari * which specifies high address region of DMA blocks. Therefore these 950184870Syongari * blocks should have the same high address of given 4GB address 951184870Syongari * space(i.e. crossing 4GB boundary is not allowed). 952184870Syongari */ 953184870Syongaristatic int 954184870Syongariale_check_boundary(struct ale_softc *sc) 955184870Syongari{ 956184870Syongari bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 957184870Syongari bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 958184870Syongari 959184870Syongari rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 960184870Syongari sc->ale_pagesize; 961184870Syongari rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 962184870Syongari sc->ale_pagesize; 963184870Syongari tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 964184870Syongari tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 965184870Syongari rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 966184870Syongari rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 967184870Syongari 968184870Syongari if ((ALE_ADDR_HI(tx_ring_end) != 969184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 970184870Syongari (ALE_ADDR_HI(rx_page_end[0]) != 971184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 972184870Syongari (ALE_ADDR_HI(rx_page_end[1]) != 973184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 974184870Syongari (ALE_ADDR_HI(tx_cmb_end) != 975184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 976184870Syongari (ALE_ADDR_HI(rx_cmb_end[0]) != 977184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 978184870Syongari (ALE_ADDR_HI(rx_cmb_end[1]) != 979184870Syongari ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 980184870Syongari return (EFBIG); 981184870Syongari 982184870Syongari if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 983184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 984184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 985184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 986184870Syongari (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 987184870Syongari return (EFBIG); 988184870Syongari 989184870Syongari return (0); 990184870Syongari} 991184870Syongari 992184870Syongaristatic int 993184870Syongariale_dma_alloc(struct ale_softc *sc) 994184870Syongari{ 995184870Syongari struct ale_txdesc *txd; 996184870Syongari bus_addr_t lowaddr; 997184870Syongari struct ale_dmamap_arg ctx; 998184870Syongari int error, guard_size, i; 999184870Syongari 1000184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1001184870Syongari guard_size = ALE_JUMBO_FRAMELEN; 1002184870Syongari else 1003184870Syongari guard_size = ALE_MAX_FRAMELEN; 1004184870Syongari sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1005184870Syongari ALE_RX_PAGE_ALIGN); 1006184870Syongari lowaddr = BUS_SPACE_MAXADDR; 1007184870Syongariagain: 1008184870Syongari /* Create parent DMA tag. */ 1009184870Syongari error = bus_dma_tag_create( 1010184870Syongari bus_get_dma_tag(sc->ale_dev), /* parent */ 1011184870Syongari 1, 0, /* alignment, boundary */ 1012184870Syongari lowaddr, /* lowaddr */ 1013184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1014184870Syongari NULL, NULL, /* filter, filterarg */ 1015184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1016184870Syongari 0, /* nsegments */ 1017184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1018184870Syongari 0, /* flags */ 1019184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1020184870Syongari &sc->ale_cdata.ale_parent_tag); 1021184870Syongari if (error != 0) { 1022184870Syongari device_printf(sc->ale_dev, 1023184870Syongari "could not create parent DMA tag.\n"); 1024184870Syongari goto fail; 1025184870Syongari } 1026184870Syongari 1027184870Syongari /* Create DMA tag for Tx descriptor ring. */ 1028184870Syongari error = bus_dma_tag_create( 1029184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1030184870Syongari ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1031184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1032184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1033184870Syongari NULL, NULL, /* filter, filterarg */ 1034184870Syongari ALE_TX_RING_SZ, /* maxsize */ 1035184870Syongari 1, /* nsegments */ 1036184870Syongari ALE_TX_RING_SZ, /* maxsegsize */ 1037184870Syongari 0, /* flags */ 1038184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1039184870Syongari &sc->ale_cdata.ale_tx_ring_tag); 1040184870Syongari if (error != 0) { 1041184870Syongari device_printf(sc->ale_dev, 1042184870Syongari "could not create Tx ring DMA tag.\n"); 1043184870Syongari goto fail; 1044184870Syongari } 1045184870Syongari 1046184870Syongari /* Create DMA tag for Rx pages. */ 1047184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1048184870Syongari error = bus_dma_tag_create( 1049184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1050184870Syongari ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1051184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1052184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1053184870Syongari NULL, NULL, /* filter, filterarg */ 1054184870Syongari sc->ale_pagesize, /* maxsize */ 1055184870Syongari 1, /* nsegments */ 1056184870Syongari sc->ale_pagesize, /* maxsegsize */ 1057184870Syongari 0, /* flags */ 1058184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1059184870Syongari &sc->ale_cdata.ale_rx_page[i].page_tag); 1060184870Syongari if (error != 0) { 1061184870Syongari device_printf(sc->ale_dev, 1062184870Syongari "could not create Rx page %d DMA tag.\n", i); 1063184870Syongari goto fail; 1064184870Syongari } 1065184870Syongari } 1066184870Syongari 1067184870Syongari /* Create DMA tag for Tx coalescing message block. */ 1068184870Syongari error = bus_dma_tag_create( 1069184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1070184870Syongari ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1071184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1072184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1073184870Syongari NULL, NULL, /* filter, filterarg */ 1074184870Syongari ALE_TX_CMB_SZ, /* maxsize */ 1075184870Syongari 1, /* nsegments */ 1076184870Syongari ALE_TX_CMB_SZ, /* maxsegsize */ 1077184870Syongari 0, /* flags */ 1078184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1079184870Syongari &sc->ale_cdata.ale_tx_cmb_tag); 1080184870Syongari if (error != 0) { 1081184870Syongari device_printf(sc->ale_dev, 1082184870Syongari "could not create Tx CMB DMA tag.\n"); 1083184870Syongari goto fail; 1084184870Syongari } 1085184870Syongari 1086184870Syongari /* Create DMA tag for Rx coalescing message block. */ 1087184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1088184870Syongari error = bus_dma_tag_create( 1089184870Syongari sc->ale_cdata.ale_parent_tag, /* parent */ 1090184870Syongari ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1091184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1092184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1093184870Syongari NULL, NULL, /* filter, filterarg */ 1094184870Syongari ALE_RX_CMB_SZ, /* maxsize */ 1095184870Syongari 1, /* nsegments */ 1096184870Syongari ALE_RX_CMB_SZ, /* maxsegsize */ 1097184870Syongari 0, /* flags */ 1098184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1099184870Syongari &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1100184870Syongari if (error != 0) { 1101184870Syongari device_printf(sc->ale_dev, 1102184870Syongari "could not create Rx page %d CMB DMA tag.\n", i); 1103184870Syongari goto fail; 1104184870Syongari } 1105184870Syongari } 1106184870Syongari 1107184870Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1108184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1109184870Syongari (void **)&sc->ale_cdata.ale_tx_ring, 1110184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1111184870Syongari &sc->ale_cdata.ale_tx_ring_map); 1112184870Syongari if (error != 0) { 1113184870Syongari device_printf(sc->ale_dev, 1114184870Syongari "could not allocate DMA'able memory for Tx ring.\n"); 1115184870Syongari goto fail; 1116184870Syongari } 1117184870Syongari ctx.ale_busaddr = 0; 1118184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1119184870Syongari sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1120184870Syongari ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1121184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1122184870Syongari device_printf(sc->ale_dev, 1123184870Syongari "could not load DMA'able memory for Tx ring.\n"); 1124184870Syongari goto fail; 1125184870Syongari } 1126184870Syongari sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1127184870Syongari 1128184870Syongari /* Rx pages. */ 1129184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1130184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1131184870Syongari (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1132184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1133184870Syongari &sc->ale_cdata.ale_rx_page[i].page_map); 1134184870Syongari if (error != 0) { 1135184870Syongari device_printf(sc->ale_dev, 1136184870Syongari "could not allocate DMA'able memory for " 1137184870Syongari "Rx page %d.\n", i); 1138184870Syongari goto fail; 1139184870Syongari } 1140184870Syongari ctx.ale_busaddr = 0; 1141184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1142184870Syongari sc->ale_cdata.ale_rx_page[i].page_map, 1143184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr, 1144184870Syongari sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1145184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1146184870Syongari device_printf(sc->ale_dev, 1147184870Syongari "could not load DMA'able memory for " 1148184870Syongari "Rx page %d.\n", i); 1149184870Syongari goto fail; 1150184870Syongari } 1151184870Syongari sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1152184870Syongari } 1153184870Syongari 1154184870Syongari /* Tx CMB. */ 1155184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1156184870Syongari (void **)&sc->ale_cdata.ale_tx_cmb, 1157184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1158184870Syongari &sc->ale_cdata.ale_tx_cmb_map); 1159184870Syongari if (error != 0) { 1160184870Syongari device_printf(sc->ale_dev, 1161184870Syongari "could not allocate DMA'able memory for Tx CMB.\n"); 1162184870Syongari goto fail; 1163184870Syongari } 1164184870Syongari ctx.ale_busaddr = 0; 1165184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1166184870Syongari sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1167184870Syongari ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1168184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1169184870Syongari device_printf(sc->ale_dev, 1170184870Syongari "could not load DMA'able memory for Tx CMB.\n"); 1171184870Syongari goto fail; 1172184870Syongari } 1173184870Syongari sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1174184870Syongari 1175184870Syongari /* Rx CMB. */ 1176184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1177184870Syongari error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1178184870Syongari (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1179184870Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1180184870Syongari &sc->ale_cdata.ale_rx_page[i].cmb_map); 1181184870Syongari if (error != 0) { 1182184870Syongari device_printf(sc->ale_dev, "could not allocate " 1183184870Syongari "DMA'able memory for Rx page %d CMB.\n", i); 1184184870Syongari goto fail; 1185184870Syongari } 1186184870Syongari ctx.ale_busaddr = 0; 1187184870Syongari error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1188184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map, 1189184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr, 1190184870Syongari ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1191184870Syongari if (error != 0 || ctx.ale_busaddr == 0) { 1192184870Syongari device_printf(sc->ale_dev, "could not load DMA'able " 1193184870Syongari "memory for Rx page %d CMB.\n", i); 1194184870Syongari goto fail; 1195184870Syongari } 1196184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1197184870Syongari } 1198184870Syongari 1199184870Syongari /* 1200184870Syongari * Tx descriptors/RXF0/CMB DMA blocks share the same 1201184870Syongari * high address region of 64bit DMA address space. 1202184870Syongari */ 1203184870Syongari if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1204184870Syongari (error = ale_check_boundary(sc)) != 0) { 1205184870Syongari device_printf(sc->ale_dev, "4GB boundary crossed, " 1206184870Syongari "switching to 32bit DMA addressing mode.\n"); 1207184870Syongari ale_dma_free(sc); 1208184870Syongari /* 1209184870Syongari * Limit max allowable DMA address space to 32bit 1210184870Syongari * and try again. 1211184870Syongari */ 1212184870Syongari lowaddr = BUS_SPACE_MAXADDR_32BIT; 1213184870Syongari goto again; 1214184870Syongari } 1215184870Syongari 1216184870Syongari /* 1217184870Syongari * Create Tx buffer parent tag. 1218184870Syongari * AR81xx allows 64bit DMA addressing of Tx buffers so it 1219184870Syongari * needs separate parent DMA tag as parent DMA address space 1220184870Syongari * could be restricted to be within 32bit address space by 1221184870Syongari * 4GB boundary crossing. 1222184870Syongari */ 1223184870Syongari error = bus_dma_tag_create( 1224184870Syongari bus_get_dma_tag(sc->ale_dev), /* parent */ 1225184870Syongari 1, 0, /* alignment, boundary */ 1226184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1227184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1228184870Syongari NULL, NULL, /* filter, filterarg */ 1229184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1230184870Syongari 0, /* nsegments */ 1231184870Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1232184870Syongari 0, /* flags */ 1233184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1234184870Syongari &sc->ale_cdata.ale_buffer_tag); 1235184870Syongari if (error != 0) { 1236184870Syongari device_printf(sc->ale_dev, 1237184870Syongari "could not create parent buffer DMA tag.\n"); 1238184870Syongari goto fail; 1239184870Syongari } 1240184870Syongari 1241184870Syongari /* Create DMA tag for Tx buffers. */ 1242184870Syongari error = bus_dma_tag_create( 1243184870Syongari sc->ale_cdata.ale_buffer_tag, /* parent */ 1244184870Syongari 1, 0, /* alignment, boundary */ 1245184870Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1246184870Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1247184870Syongari NULL, NULL, /* filter, filterarg */ 1248184870Syongari ALE_TSO_MAXSIZE, /* maxsize */ 1249184870Syongari ALE_MAXTXSEGS, /* nsegments */ 1250184870Syongari ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1251184870Syongari 0, /* flags */ 1252184870Syongari NULL, NULL, /* lockfunc, lockarg */ 1253184870Syongari &sc->ale_cdata.ale_tx_tag); 1254184870Syongari if (error != 0) { 1255184870Syongari device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1256184870Syongari goto fail; 1257184870Syongari } 1258184870Syongari 1259184870Syongari /* Create DMA maps for Tx buffers. */ 1260184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 1261184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 1262184870Syongari txd->tx_m = NULL; 1263184870Syongari txd->tx_dmamap = NULL; 1264184870Syongari error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1265184870Syongari &txd->tx_dmamap); 1266184870Syongari if (error != 0) { 1267184870Syongari device_printf(sc->ale_dev, 1268184870Syongari "could not create Tx dmamap.\n"); 1269184870Syongari goto fail; 1270184870Syongari } 1271184870Syongari } 1272184870Syongari 1273184870Syongarifail: 1274184870Syongari return (error); 1275184870Syongari} 1276184870Syongari 1277184870Syongaristatic void 1278184870Syongariale_dma_free(struct ale_softc *sc) 1279184870Syongari{ 1280184870Syongari struct ale_txdesc *txd; 1281184870Syongari int i; 1282184870Syongari 1283184870Syongari /* Tx buffers. */ 1284184870Syongari if (sc->ale_cdata.ale_tx_tag != NULL) { 1285184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 1286184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 1287184870Syongari if (txd->tx_dmamap != NULL) { 1288184870Syongari bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1289184870Syongari txd->tx_dmamap); 1290184870Syongari txd->tx_dmamap = NULL; 1291184870Syongari } 1292184870Syongari } 1293184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1294184870Syongari sc->ale_cdata.ale_tx_tag = NULL; 1295184870Syongari } 1296184870Syongari /* Tx descriptor ring. */ 1297184870Syongari if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1298184870Syongari if (sc->ale_cdata.ale_tx_ring_map != NULL) 1299184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1300184870Syongari sc->ale_cdata.ale_tx_ring_map); 1301184870Syongari if (sc->ale_cdata.ale_tx_ring_map != NULL && 1302184870Syongari sc->ale_cdata.ale_tx_ring != NULL) 1303184870Syongari bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1304184870Syongari sc->ale_cdata.ale_tx_ring, 1305184870Syongari sc->ale_cdata.ale_tx_ring_map); 1306184870Syongari sc->ale_cdata.ale_tx_ring = NULL; 1307184870Syongari sc->ale_cdata.ale_tx_ring_map = NULL; 1308184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1309184870Syongari sc->ale_cdata.ale_tx_ring_tag = NULL; 1310184870Syongari } 1311184870Syongari /* Rx page block. */ 1312184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1313184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1314184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1315184870Syongari bus_dmamap_unload( 1316184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag, 1317184870Syongari sc->ale_cdata.ale_rx_page[i].page_map); 1318184870Syongari if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1319184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1320184870Syongari bus_dmamem_free( 1321184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag, 1322184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr, 1323184870Syongari sc->ale_cdata.ale_rx_page[i].page_map); 1324184870Syongari sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1325184870Syongari sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1326184870Syongari bus_dma_tag_destroy( 1327184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag); 1328184870Syongari sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1329184870Syongari } 1330184870Syongari } 1331184870Syongari /* Rx CMB. */ 1332184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 1333184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1334184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1335184870Syongari bus_dmamap_unload( 1336184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag, 1337184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map); 1338184870Syongari if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1339184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1340184870Syongari bus_dmamem_free( 1341184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag, 1342184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr, 1343184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map); 1344184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1345184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1346184870Syongari bus_dma_tag_destroy( 1347184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag); 1348184870Syongari sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1349184870Syongari } 1350184870Syongari } 1351184870Syongari /* Tx CMB. */ 1352184870Syongari if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1353184870Syongari if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1354184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1355184870Syongari sc->ale_cdata.ale_tx_cmb_map); 1356184870Syongari if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1357184870Syongari sc->ale_cdata.ale_tx_cmb != NULL) 1358184870Syongari bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1359184870Syongari sc->ale_cdata.ale_tx_cmb, 1360184870Syongari sc->ale_cdata.ale_tx_cmb_map); 1361184870Syongari sc->ale_cdata.ale_tx_cmb = NULL; 1362184870Syongari sc->ale_cdata.ale_tx_cmb_map = NULL; 1363184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1364184870Syongari sc->ale_cdata.ale_tx_cmb_tag = NULL; 1365184870Syongari } 1366184870Syongari if (sc->ale_cdata.ale_buffer_tag != NULL) { 1367184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1368184870Syongari sc->ale_cdata.ale_buffer_tag = NULL; 1369184870Syongari } 1370184870Syongari if (sc->ale_cdata.ale_parent_tag != NULL) { 1371184870Syongari bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1372184870Syongari sc->ale_cdata.ale_parent_tag = NULL; 1373184870Syongari } 1374184870Syongari} 1375184870Syongari 1376184870Syongaristatic int 1377184870Syongariale_shutdown(device_t dev) 1378184870Syongari{ 1379184870Syongari 1380184870Syongari return (ale_suspend(dev)); 1381184870Syongari} 1382184870Syongari 1383184870Syongari/* 1384184870Syongari * Note, this driver resets the link speed to 10/100Mbps by 1385184870Syongari * restarting auto-negotiation in suspend/shutdown phase but we 1386184870Syongari * don't know whether that auto-negotiation would succeed or not 1387184870Syongari * as driver has no control after powering off/suspend operation. 1388184870Syongari * If the renegotiation fail WOL may not work. Running at 1Gbps 1389184870Syongari * will draw more power than 375mA at 3.3V which is specified in 1390184870Syongari * PCI specification and that would result in complete 1391184870Syongari * shutdowning power to ethernet controller. 1392184870Syongari * 1393184870Syongari * TODO 1394184870Syongari * Save current negotiated media speed/duplex/flow-control to 1395184870Syongari * softc and restore the same link again after resuming. PHY 1396184870Syongari * handling such as power down/resetting to 100Mbps may be better 1397184870Syongari * handled in suspend method in phy driver. 1398184870Syongari */ 1399184870Syongaristatic void 1400184870Syongariale_setlinkspeed(struct ale_softc *sc) 1401184870Syongari{ 1402184870Syongari struct mii_data *mii; 1403184870Syongari int aneg, i; 1404184870Syongari 1405184870Syongari mii = device_get_softc(sc->ale_miibus); 1406184870Syongari mii_pollstat(mii); 1407184870Syongari aneg = 0; 1408184870Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1409184870Syongari (IFM_ACTIVE | IFM_AVALID)) { 1410184870Syongari switch IFM_SUBTYPE(mii->mii_media_active) { 1411184870Syongari case IFM_10_T: 1412184870Syongari case IFM_100_TX: 1413184870Syongari return; 1414184870Syongari case IFM_1000_T: 1415184870Syongari aneg++; 1416184870Syongari break; 1417184870Syongari default: 1418184870Syongari break; 1419184870Syongari } 1420184870Syongari } 1421184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1422184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1423184870Syongari MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1424184870Syongari ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1425184870Syongari MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1426184870Syongari DELAY(1000); 1427184870Syongari if (aneg != 0) { 1428184870Syongari /* 1429184870Syongari * Poll link state until ale(4) get a 10/100Mbps link. 1430184870Syongari */ 1431184870Syongari for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1432184870Syongari mii_pollstat(mii); 1433184870Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1434184870Syongari == (IFM_ACTIVE | IFM_AVALID)) { 1435184870Syongari switch (IFM_SUBTYPE( 1436184870Syongari mii->mii_media_active)) { 1437184870Syongari case IFM_10_T: 1438184870Syongari case IFM_100_TX: 1439184870Syongari ale_mac_config(sc); 1440184870Syongari return; 1441184870Syongari default: 1442184870Syongari break; 1443184870Syongari } 1444184870Syongari } 1445184870Syongari ALE_UNLOCK(sc); 1446184870Syongari pause("alelnk", hz); 1447184870Syongari ALE_LOCK(sc); 1448184870Syongari } 1449184870Syongari if (i == MII_ANEGTICKS_GIGE) 1450184870Syongari device_printf(sc->ale_dev, 1451184870Syongari "establishing a link failed, WOL may not work!"); 1452184870Syongari } 1453184870Syongari /* 1454184870Syongari * No link, force MAC to have 100Mbps, full-duplex link. 1455184870Syongari * This is the last resort and may/may not work. 1456184870Syongari */ 1457184870Syongari mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1458184870Syongari mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1459184870Syongari ale_mac_config(sc); 1460184870Syongari} 1461184870Syongari 1462184870Syongaristatic void 1463184870Syongariale_setwol(struct ale_softc *sc) 1464184870Syongari{ 1465184870Syongari struct ifnet *ifp; 1466184870Syongari uint32_t reg, pmcs; 1467184870Syongari uint16_t pmstat; 1468184870Syongari int pmc; 1469184870Syongari 1470184870Syongari ALE_LOCK_ASSERT(sc); 1471184870Syongari 1472219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1473184870Syongari /* Disable WOL. */ 1474184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1475184870Syongari reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1476184870Syongari reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1477184870Syongari CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1478184870Syongari /* Force PHY power down. */ 1479184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1480184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1481184870Syongari GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1482184870Syongari GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1483184870Syongari GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1484184870Syongari return; 1485184870Syongari } 1486184870Syongari 1487184870Syongari ifp = sc->ale_ifp; 1488184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1489184870Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1490184870Syongari ale_setlinkspeed(sc); 1491184870Syongari } 1492184870Syongari 1493184870Syongari pmcs = 0; 1494184870Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1495184870Syongari pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1496184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1497184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 1498184870Syongari reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1499184870Syongari MAC_CFG_BCAST); 1500184870Syongari if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1501184870Syongari reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1502184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1503184870Syongari reg |= MAC_CFG_RX_ENB; 1504184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1505184870Syongari 1506184870Syongari if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1507184870Syongari /* WOL disabled, PHY power down. */ 1508184870Syongari reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1509184870Syongari reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1510184870Syongari CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1511184870Syongari CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1512184870Syongari GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1513184870Syongari GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1514184870Syongari GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1515184870Syongari GPHY_CTRL_PWDOWN_HW); 1516184870Syongari } 1517184870Syongari /* Request PME. */ 1518184870Syongari pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1519184870Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1520184870Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1521184870Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1522184870Syongari pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1523184870Syongari} 1524184870Syongari 1525184870Syongaristatic int 1526184870Syongariale_suspend(device_t dev) 1527184870Syongari{ 1528184870Syongari struct ale_softc *sc; 1529184870Syongari 1530184870Syongari sc = device_get_softc(dev); 1531184870Syongari 1532184870Syongari ALE_LOCK(sc); 1533184870Syongari ale_stop(sc); 1534184870Syongari ale_setwol(sc); 1535184870Syongari ALE_UNLOCK(sc); 1536184870Syongari 1537184870Syongari return (0); 1538184870Syongari} 1539184870Syongari 1540184870Syongaristatic int 1541184870Syongariale_resume(device_t dev) 1542184870Syongari{ 1543184870Syongari struct ale_softc *sc; 1544184870Syongari struct ifnet *ifp; 1545184870Syongari int pmc; 1546189379Syongari uint16_t pmstat; 1547184870Syongari 1548184870Syongari sc = device_get_softc(dev); 1549184870Syongari 1550184870Syongari ALE_LOCK(sc); 1551219902Sjhb if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1552184870Syongari /* Disable PME and clear PME status. */ 1553184870Syongari pmstat = pci_read_config(sc->ale_dev, 1554184870Syongari pmc + PCIR_POWER_STATUS, 2); 1555184870Syongari if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1556184870Syongari pmstat &= ~PCIM_PSTAT_PMEENABLE; 1557184870Syongari pci_write_config(sc->ale_dev, 1558184870Syongari pmc + PCIR_POWER_STATUS, pmstat, 2); 1559184870Syongari } 1560184870Syongari } 1561184870Syongari /* Reset PHY. */ 1562184870Syongari ale_phy_reset(sc); 1563184870Syongari ifp = sc->ale_ifp; 1564184870Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1565184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1566184870Syongari ale_init_locked(sc); 1567184870Syongari } 1568184870Syongari ALE_UNLOCK(sc); 1569184870Syongari 1570184870Syongari return (0); 1571184870Syongari} 1572184870Syongari 1573184870Syongaristatic int 1574184870Syongariale_encap(struct ale_softc *sc, struct mbuf **m_head) 1575184870Syongari{ 1576184870Syongari struct ale_txdesc *txd, *txd_last; 1577184870Syongari struct tx_desc *desc; 1578184870Syongari struct mbuf *m; 1579184870Syongari struct ip *ip; 1580184870Syongari struct tcphdr *tcp; 1581184870Syongari bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1582184870Syongari bus_dmamap_t map; 1583207251Syongari uint32_t cflags, hdrlen, ip_off, poff, vtag; 1584184870Syongari int error, i, nsegs, prod, si; 1585184870Syongari 1586184870Syongari ALE_LOCK_ASSERT(sc); 1587184870Syongari 1588184870Syongari M_ASSERTPKTHDR((*m_head)); 1589184870Syongari 1590184870Syongari m = *m_head; 1591184870Syongari ip = NULL; 1592184870Syongari tcp = NULL; 1593184870Syongari cflags = vtag = 0; 1594184870Syongari ip_off = poff = 0; 1595184870Syongari if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1596184870Syongari /* 1597184870Syongari * AR81xx requires offset of TCP/UDP payload in its Tx 1598184870Syongari * descriptor to perform hardware Tx checksum offload. 1599184870Syongari * Additionally, TSO requires IP/TCP header size and 1600184870Syongari * modification of IP/TCP header in order to make TSO 1601184870Syongari * engine work. This kind of operation takes many CPU 1602184870Syongari * cycles on FreeBSD so fast host CPU is required to 1603184870Syongari * get smooth TSO performance. 1604184870Syongari */ 1605184870Syongari struct ether_header *eh; 1606184870Syongari 1607184870Syongari if (M_WRITABLE(m) == 0) { 1608184870Syongari /* Get a writable copy. */ 1609184870Syongari m = m_dup(*m_head, M_DONTWAIT); 1610184870Syongari /* Release original mbufs. */ 1611184870Syongari m_freem(*m_head); 1612184870Syongari if (m == NULL) { 1613184870Syongari *m_head = NULL; 1614184870Syongari return (ENOBUFS); 1615184870Syongari } 1616184870Syongari *m_head = m; 1617184870Syongari } 1618184870Syongari 1619184870Syongari /* 1620184870Syongari * Buggy-controller requires 4 byte aligned Tx buffer 1621184870Syongari * to make custom checksum offload work. 1622184870Syongari */ 1623184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1624184870Syongari (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1625184870Syongari (mtod(m, intptr_t) & 3) != 0) { 1626184870Syongari m = m_defrag(*m_head, M_DONTWAIT); 1627184870Syongari if (m == NULL) { 1628184870Syongari *m_head = NULL; 1629184870Syongari return (ENOBUFS); 1630184870Syongari } 1631184870Syongari *m_head = m; 1632184870Syongari } 1633184870Syongari 1634184870Syongari ip_off = sizeof(struct ether_header); 1635184870Syongari m = m_pullup(m, ip_off); 1636184870Syongari if (m == NULL) { 1637184870Syongari *m_head = NULL; 1638184870Syongari return (ENOBUFS); 1639184870Syongari } 1640184870Syongari eh = mtod(m, struct ether_header *); 1641184870Syongari /* 1642184870Syongari * Check if hardware VLAN insertion is off. 1643184870Syongari * Additional check for LLC/SNAP frame? 1644184870Syongari */ 1645184870Syongari if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1646184870Syongari ip_off = sizeof(struct ether_vlan_header); 1647184870Syongari m = m_pullup(m, ip_off); 1648184870Syongari if (m == NULL) { 1649184870Syongari *m_head = NULL; 1650184870Syongari return (ENOBUFS); 1651184870Syongari } 1652184870Syongari } 1653184870Syongari m = m_pullup(m, ip_off + sizeof(struct ip)); 1654184870Syongari if (m == NULL) { 1655184870Syongari *m_head = NULL; 1656184870Syongari return (ENOBUFS); 1657184870Syongari } 1658184870Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1659184870Syongari poff = ip_off + (ip->ip_hl << 2); 1660184870Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1661184870Syongari /* 1662184870Syongari * XXX 1663184870Syongari * AR81xx requires the first descriptor should 1664184870Syongari * not include any TCP playload for TSO case. 1665184870Syongari * (i.e. ethernet header + IP + TCP header only) 1666184870Syongari * m_pullup(9) above will ensure this too. 1667184870Syongari * However it's not correct if the first mbuf 1668184870Syongari * of the chain does not use cluster. 1669184870Syongari */ 1670184870Syongari m = m_pullup(m, poff + sizeof(struct tcphdr)); 1671184870Syongari if (m == NULL) { 1672184870Syongari *m_head = NULL; 1673184870Syongari return (ENOBUFS); 1674184870Syongari } 1675213844Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1676184870Syongari tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1677207251Syongari m = m_pullup(m, poff + (tcp->th_off << 2)); 1678207251Syongari if (m == NULL) { 1679207251Syongari *m_head = NULL; 1680207251Syongari return (ENOBUFS); 1681207251Syongari } 1682184870Syongari /* 1683184870Syongari * AR81xx requires IP/TCP header size and offset as 1684184870Syongari * well as TCP pseudo checksum which complicates 1685184870Syongari * TSO configuration. I guess this comes from the 1686184870Syongari * adherence to Microsoft NDIS Large Send 1687184870Syongari * specification which requires insertion of 1688184870Syongari * pseudo checksum by upper stack. The pseudo 1689184870Syongari * checksum that NDIS refers to doesn't include 1690184870Syongari * TCP payload length so ale(4) should recompute 1691184870Syongari * the pseudo checksum here. Hopefully this wouldn't 1692184870Syongari * be much burden on modern CPUs. 1693184870Syongari * Reset IP checksum and recompute TCP pseudo 1694184870Syongari * checksum as NDIS specification said. 1695184870Syongari */ 1696184870Syongari ip->ip_sum = 0; 1697184870Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1698184870Syongari ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1699184870Syongari } 1700184870Syongari *m_head = m; 1701184870Syongari } 1702184870Syongari 1703184870Syongari si = prod = sc->ale_cdata.ale_tx_prod; 1704184870Syongari txd = &sc->ale_cdata.ale_txdesc[prod]; 1705184870Syongari txd_last = txd; 1706184870Syongari map = txd->tx_dmamap; 1707184870Syongari 1708184870Syongari error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1709184870Syongari *m_head, txsegs, &nsegs, 0); 1710184870Syongari if (error == EFBIG) { 1711184870Syongari m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); 1712184870Syongari if (m == NULL) { 1713184870Syongari m_freem(*m_head); 1714184870Syongari *m_head = NULL; 1715184870Syongari return (ENOMEM); 1716184870Syongari } 1717184870Syongari *m_head = m; 1718184870Syongari error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1719184870Syongari *m_head, txsegs, &nsegs, 0); 1720184870Syongari if (error != 0) { 1721184870Syongari m_freem(*m_head); 1722184870Syongari *m_head = NULL; 1723184870Syongari return (error); 1724184870Syongari } 1725184870Syongari } else if (error != 0) 1726184870Syongari return (error); 1727184870Syongari if (nsegs == 0) { 1728184870Syongari m_freem(*m_head); 1729184870Syongari *m_head = NULL; 1730184870Syongari return (EIO); 1731184870Syongari } 1732184870Syongari 1733184870Syongari /* Check descriptor overrun. */ 1734207251Syongari if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1735184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1736184870Syongari return (ENOBUFS); 1737184870Syongari } 1738184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1739184870Syongari 1740184870Syongari m = *m_head; 1741206876Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1742206876Syongari /* Request TSO and set MSS. */ 1743206876Syongari cflags |= ALE_TD_TSO; 1744206876Syongari cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1745206876Syongari /* Set IP/TCP header size. */ 1746206876Syongari cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1747206876Syongari cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1748206876Syongari } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1749184870Syongari /* 1750184870Syongari * AR81xx supports Tx custom checksum offload feature 1751184870Syongari * that offloads single 16bit checksum computation. 1752184870Syongari * So you can choose one among IP, TCP and UDP. 1753184870Syongari * Normally driver sets checksum start/insertion 1754184870Syongari * position from the information of TCP/UDP frame as 1755184870Syongari * TCP/UDP checksum takes more time than that of IP. 1756184870Syongari * However it seems that custom checksum offload 1757184870Syongari * requires 4 bytes aligned Tx buffers due to hardware 1758184870Syongari * bug. 1759184870Syongari * AR81xx also supports explicit Tx checksum computation 1760184870Syongari * if it is told that the size of IP header and TCP 1761184870Syongari * header(for UDP, the header size does not matter 1762184870Syongari * because it's fixed length). However with this scheme 1763184870Syongari * TSO does not work so you have to choose one either 1764184870Syongari * TSO or explicit Tx checksum offload. I chosen TSO 1765184870Syongari * plus custom checksum offload with work-around which 1766184870Syongari * will cover most common usage for this consumer 1767184870Syongari * ethernet controller. The work-around takes a lot of 1768184870Syongari * CPU cycles if Tx buffer is not aligned on 4 bytes 1769184870Syongari * boundary, though. 1770184870Syongari */ 1771184870Syongari cflags |= ALE_TD_CXSUM; 1772184870Syongari /* Set checksum start offset. */ 1773184870Syongari cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1774184870Syongari /* Set checksum insertion position of TCP/UDP. */ 1775184870Syongari cflags |= ((poff + m->m_pkthdr.csum_data) << 1776184870Syongari ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1777184870Syongari } 1778184870Syongari 1779184870Syongari /* Configure VLAN hardware tag insertion. */ 1780184870Syongari if ((m->m_flags & M_VLANTAG) != 0) { 1781184870Syongari vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1782184870Syongari vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1783184870Syongari cflags |= ALE_TD_INSERT_VLAN_TAG; 1784184870Syongari } 1785184870Syongari 1786207251Syongari i = 0; 1787207251Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1788207251Syongari /* 1789207251Syongari * Make sure the first fragment contains 1790207251Syongari * only ethernet and IP/TCP header with options. 1791207251Syongari */ 1792207251Syongari hdrlen = poff + (tcp->th_off << 2); 1793184870Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1794184870Syongari desc->addr = htole64(txsegs[i].ds_addr); 1795207251Syongari desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1796207251Syongari desc->flags = htole32(cflags); 1797207251Syongari sc->ale_cdata.ale_tx_cnt++; 1798207251Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1799207251Syongari if (m->m_len - hdrlen > 0) { 1800207251Syongari /* Handle remaining payload of the first fragment. */ 1801207251Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1802207251Syongari desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1803207251Syongari desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1804207251Syongari vtag); 1805207251Syongari desc->flags = htole32(cflags); 1806207251Syongari sc->ale_cdata.ale_tx_cnt++; 1807207251Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1808207251Syongari } 1809207251Syongari i = 1; 1810207251Syongari } 1811207251Syongari for (; i < nsegs; i++) { 1812207251Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1813207251Syongari desc->addr = htole64(txsegs[i].ds_addr); 1814184870Syongari desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1815184870Syongari desc->flags = htole32(cflags); 1816184870Syongari sc->ale_cdata.ale_tx_cnt++; 1817184870Syongari ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1818184870Syongari } 1819184870Syongari /* Update producer index. */ 1820184870Syongari sc->ale_cdata.ale_tx_prod = prod; 1821184870Syongari /* Set TSO header on the first descriptor. */ 1822184870Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1823184870Syongari desc = &sc->ale_cdata.ale_tx_ring[si]; 1824184870Syongari desc->flags |= htole32(ALE_TD_TSO_HDR); 1825184870Syongari } 1826184870Syongari 1827184870Syongari /* Finally set EOP on the last descriptor. */ 1828184870Syongari prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1829184870Syongari desc = &sc->ale_cdata.ale_tx_ring[prod]; 1830184870Syongari desc->flags |= htole32(ALE_TD_EOP); 1831184870Syongari 1832184870Syongari /* Swap dmamap of the first and the last. */ 1833184870Syongari txd = &sc->ale_cdata.ale_txdesc[prod]; 1834184870Syongari map = txd_last->tx_dmamap; 1835184870Syongari txd_last->tx_dmamap = txd->tx_dmamap; 1836184870Syongari txd->tx_dmamap = map; 1837184870Syongari txd->tx_m = m; 1838184870Syongari 1839184870Syongari /* Sync descriptors. */ 1840184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1841184870Syongari sc->ale_cdata.ale_tx_ring_map, 1842184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1843184870Syongari 1844184870Syongari return (0); 1845184870Syongari} 1846184870Syongari 1847184870Syongaristatic void 1848216925Sjhbale_start(struct ifnet *ifp) 1849184870Syongari{ 1850216925Sjhb struct ale_softc *sc; 1851184870Syongari 1852216925Sjhb sc = ifp->if_softc; 1853216925Sjhb ALE_LOCK(sc); 1854216925Sjhb ale_start_locked(ifp); 1855216925Sjhb ALE_UNLOCK(sc); 1856184870Syongari} 1857184870Syongari 1858184870Syongaristatic void 1859216925Sjhbale_start_locked(struct ifnet *ifp) 1860184870Syongari{ 1861184870Syongari struct ale_softc *sc; 1862184870Syongari struct mbuf *m_head; 1863184870Syongari int enq; 1864184870Syongari 1865184870Syongari sc = ifp->if_softc; 1866184870Syongari 1867216925Sjhb ALE_LOCK_ASSERT(sc); 1868184870Syongari 1869184870Syongari /* Reclaim transmitted frames. */ 1870184870Syongari if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1871184870Syongari ale_txeof(sc); 1872184870Syongari 1873184870Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1874216925Sjhb IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1875184870Syongari return; 1876184870Syongari 1877184870Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1878184870Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1879184870Syongari if (m_head == NULL) 1880184870Syongari break; 1881184870Syongari /* 1882184870Syongari * Pack the data into the transmit ring. If we 1883184870Syongari * don't have room, set the OACTIVE flag and wait 1884184870Syongari * for the NIC to drain the ring. 1885184870Syongari */ 1886184870Syongari if (ale_encap(sc, &m_head)) { 1887184870Syongari if (m_head == NULL) 1888184870Syongari break; 1889184870Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1890184870Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1891184870Syongari break; 1892184870Syongari } 1893184870Syongari 1894184870Syongari enq++; 1895184870Syongari /* 1896184870Syongari * If there's a BPF listener, bounce a copy of this frame 1897184870Syongari * to him. 1898184870Syongari */ 1899184870Syongari ETHER_BPF_MTAP(ifp, m_head); 1900184870Syongari } 1901184870Syongari 1902184870Syongari if (enq > 0) { 1903184870Syongari /* Kick. */ 1904184870Syongari CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1905184870Syongari sc->ale_cdata.ale_tx_prod); 1906184870Syongari /* Set a timeout in case the chip goes out to lunch. */ 1907184870Syongari sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1908184870Syongari } 1909184870Syongari} 1910184870Syongari 1911184870Syongaristatic void 1912184870Syongariale_watchdog(struct ale_softc *sc) 1913184870Syongari{ 1914184870Syongari struct ifnet *ifp; 1915184870Syongari 1916184870Syongari ALE_LOCK_ASSERT(sc); 1917184870Syongari 1918184870Syongari if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1919184870Syongari return; 1920184870Syongari 1921184870Syongari ifp = sc->ale_ifp; 1922184870Syongari if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1923184870Syongari if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1924184870Syongari ifp->if_oerrors++; 1925184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1926184870Syongari ale_init_locked(sc); 1927184870Syongari return; 1928184870Syongari } 1929184870Syongari if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1930184870Syongari ifp->if_oerrors++; 1931184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1932184870Syongari ale_init_locked(sc); 1933184870Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1934216925Sjhb ale_start_locked(ifp); 1935184870Syongari} 1936184870Syongari 1937184870Syongaristatic int 1938184870Syongariale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1939184870Syongari{ 1940184870Syongari struct ale_softc *sc; 1941184870Syongari struct ifreq *ifr; 1942184870Syongari struct mii_data *mii; 1943184870Syongari int error, mask; 1944184870Syongari 1945184870Syongari sc = ifp->if_softc; 1946184870Syongari ifr = (struct ifreq *)data; 1947184870Syongari error = 0; 1948184870Syongari switch (cmd) { 1949184870Syongari case SIOCSIFMTU: 1950184870Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1951184870Syongari ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1952184870Syongari ifr->ifr_mtu > ETHERMTU)) 1953184870Syongari error = EINVAL; 1954184870Syongari else if (ifp->if_mtu != ifr->ifr_mtu) { 1955184870Syongari ALE_LOCK(sc); 1956184870Syongari ifp->if_mtu = ifr->ifr_mtu; 1957184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1958184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1959184870Syongari ale_init_locked(sc); 1960184870Syongari } 1961184870Syongari ALE_UNLOCK(sc); 1962184870Syongari } 1963184870Syongari break; 1964184870Syongari case SIOCSIFFLAGS: 1965184870Syongari ALE_LOCK(sc); 1966184870Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1967184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1968184870Syongari if (((ifp->if_flags ^ sc->ale_if_flags) 1969184870Syongari & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1970184870Syongari ale_rxfilter(sc); 1971184870Syongari } else { 1972217542Sjhb ale_init_locked(sc); 1973184870Syongari } 1974184870Syongari } else { 1975184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1976184870Syongari ale_stop(sc); 1977184870Syongari } 1978184870Syongari sc->ale_if_flags = ifp->if_flags; 1979184870Syongari ALE_UNLOCK(sc); 1980184870Syongari break; 1981184870Syongari case SIOCADDMULTI: 1982184870Syongari case SIOCDELMULTI: 1983184870Syongari ALE_LOCK(sc); 1984184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1985184870Syongari ale_rxfilter(sc); 1986184870Syongari ALE_UNLOCK(sc); 1987184870Syongari break; 1988184870Syongari case SIOCSIFMEDIA: 1989184870Syongari case SIOCGIFMEDIA: 1990184870Syongari mii = device_get_softc(sc->ale_miibus); 1991184870Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1992184870Syongari break; 1993184870Syongari case SIOCSIFCAP: 1994184870Syongari ALE_LOCK(sc); 1995184870Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1996184870Syongari if ((mask & IFCAP_TXCSUM) != 0 && 1997184870Syongari (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1998184870Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 1999184870Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2000184870Syongari ifp->if_hwassist |= ALE_CSUM_FEATURES; 2001184870Syongari else 2002184870Syongari ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2003184870Syongari } 2004184870Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2005184870Syongari (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2006184870Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2007184870Syongari if ((mask & IFCAP_TSO4) != 0 && 2008184870Syongari (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2009184870Syongari ifp->if_capenable ^= IFCAP_TSO4; 2010184870Syongari if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2011184870Syongari ifp->if_hwassist |= CSUM_TSO; 2012184870Syongari else 2013184870Syongari ifp->if_hwassist &= ~CSUM_TSO; 2014184870Syongari } 2015184870Syongari 2016184870Syongari if ((mask & IFCAP_WOL_MCAST) != 0 && 2017184870Syongari (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2018184870Syongari ifp->if_capenable ^= IFCAP_WOL_MCAST; 2019184870Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2020184870Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2021184870Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2022184870Syongari if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2023184870Syongari (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2024184870Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2025184870Syongari if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2026184870Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2027184870Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2028204378Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2029204378Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2030204378Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2031204378Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2032204378Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2033204378Syongari ale_rxvlan(sc); 2034204378Syongari } 2035184870Syongari ALE_UNLOCK(sc); 2036184870Syongari VLAN_CAPABILITIES(ifp); 2037184870Syongari break; 2038184870Syongari default: 2039184870Syongari error = ether_ioctl(ifp, cmd, data); 2040184870Syongari break; 2041184870Syongari } 2042184870Syongari 2043184870Syongari return (error); 2044184870Syongari} 2045184870Syongari 2046184870Syongaristatic void 2047184870Syongariale_mac_config(struct ale_softc *sc) 2048184870Syongari{ 2049184870Syongari struct mii_data *mii; 2050184870Syongari uint32_t reg; 2051184870Syongari 2052184870Syongari ALE_LOCK_ASSERT(sc); 2053184870Syongari 2054184870Syongari mii = device_get_softc(sc->ale_miibus); 2055184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 2056184870Syongari reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2057184870Syongari MAC_CFG_SPEED_MASK); 2058184870Syongari /* Reprogram MAC with resolved speed/duplex. */ 2059184870Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 2060184870Syongari case IFM_10_T: 2061184870Syongari case IFM_100_TX: 2062184870Syongari reg |= MAC_CFG_SPEED_10_100; 2063184870Syongari break; 2064184870Syongari case IFM_1000_T: 2065184870Syongari reg |= MAC_CFG_SPEED_1000; 2066184870Syongari break; 2067184870Syongari } 2068184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2069184870Syongari reg |= MAC_CFG_FULL_DUPLEX; 2070184870Syongari#ifdef notyet 2071184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2072184870Syongari reg |= MAC_CFG_TX_FC; 2073184870Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2074184870Syongari reg |= MAC_CFG_RX_FC; 2075184870Syongari#endif 2076184870Syongari } 2077184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2078184870Syongari} 2079184870Syongari 2080184870Syongaristatic void 2081184870Syongariale_link_task(void *arg, int pending) 2082184870Syongari{ 2083184870Syongari struct ale_softc *sc; 2084184870Syongari struct mii_data *mii; 2085184870Syongari struct ifnet *ifp; 2086184870Syongari uint32_t reg; 2087184870Syongari 2088184870Syongari sc = (struct ale_softc *)arg; 2089184870Syongari 2090184870Syongari ALE_LOCK(sc); 2091184870Syongari mii = device_get_softc(sc->ale_miibus); 2092184870Syongari ifp = sc->ale_ifp; 2093184870Syongari if (mii == NULL || ifp == NULL || 2094184870Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2095184870Syongari ALE_UNLOCK(sc); 2096184870Syongari return; 2097184870Syongari } 2098184870Syongari 2099184870Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 2100184870Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2101184870Syongari (IFM_ACTIVE | IFM_AVALID)) { 2102184870Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 2103184870Syongari case IFM_10_T: 2104184870Syongari case IFM_100_TX: 2105184870Syongari sc->ale_flags |= ALE_FLAG_LINK; 2106184870Syongari break; 2107184870Syongari case IFM_1000_T: 2108184870Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 2109184870Syongari sc->ale_flags |= ALE_FLAG_LINK; 2110184870Syongari break; 2111184870Syongari default: 2112184870Syongari break; 2113184870Syongari } 2114184870Syongari } 2115184870Syongari 2116184870Syongari /* Stop Rx/Tx MACs. */ 2117184870Syongari ale_stop_mac(sc); 2118184870Syongari 2119184870Syongari /* Program MACs with resolved speed/duplex/flow-control. */ 2120184870Syongari if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 2121184870Syongari ale_mac_config(sc); 2122184870Syongari /* Reenable Tx/Rx MACs. */ 2123184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 2124184870Syongari reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2125184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2126184870Syongari } 2127184870Syongari 2128184870Syongari ALE_UNLOCK(sc); 2129184870Syongari} 2130184870Syongari 2131184870Syongaristatic void 2132184870Syongariale_stats_clear(struct ale_softc *sc) 2133184870Syongari{ 2134184870Syongari struct smb sb; 2135184870Syongari uint32_t *reg; 2136184870Syongari int i; 2137184870Syongari 2138184870Syongari for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2139184870Syongari CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2140184870Syongari i += sizeof(uint32_t); 2141184870Syongari } 2142184870Syongari /* Read Tx statistics. */ 2143184870Syongari for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2144184870Syongari CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2145184870Syongari i += sizeof(uint32_t); 2146184870Syongari } 2147184870Syongari} 2148184870Syongari 2149184870Syongaristatic void 2150184870Syongariale_stats_update(struct ale_softc *sc) 2151184870Syongari{ 2152184870Syongari struct ale_hw_stats *stat; 2153184870Syongari struct smb sb, *smb; 2154184870Syongari struct ifnet *ifp; 2155184870Syongari uint32_t *reg; 2156184870Syongari int i; 2157184870Syongari 2158184870Syongari ALE_LOCK_ASSERT(sc); 2159184870Syongari 2160184870Syongari ifp = sc->ale_ifp; 2161184870Syongari stat = &sc->ale_stats; 2162184870Syongari smb = &sb; 2163184870Syongari 2164184870Syongari /* Read Rx statistics. */ 2165184870Syongari for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2166184870Syongari *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2167184870Syongari i += sizeof(uint32_t); 2168184870Syongari } 2169184870Syongari /* Read Tx statistics. */ 2170184870Syongari for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2171184870Syongari *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2172184870Syongari i += sizeof(uint32_t); 2173184870Syongari } 2174184870Syongari 2175184870Syongari /* Rx stats. */ 2176184870Syongari stat->rx_frames += smb->rx_frames; 2177184870Syongari stat->rx_bcast_frames += smb->rx_bcast_frames; 2178184870Syongari stat->rx_mcast_frames += smb->rx_mcast_frames; 2179184870Syongari stat->rx_pause_frames += smb->rx_pause_frames; 2180184870Syongari stat->rx_control_frames += smb->rx_control_frames; 2181184870Syongari stat->rx_crcerrs += smb->rx_crcerrs; 2182184870Syongari stat->rx_lenerrs += smb->rx_lenerrs; 2183184870Syongari stat->rx_bytes += smb->rx_bytes; 2184184870Syongari stat->rx_runts += smb->rx_runts; 2185184870Syongari stat->rx_fragments += smb->rx_fragments; 2186184870Syongari stat->rx_pkts_64 += smb->rx_pkts_64; 2187184870Syongari stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2188184870Syongari stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2189184870Syongari stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2190184870Syongari stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2191184870Syongari stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2192184870Syongari stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2193184870Syongari stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2194184870Syongari stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2195184870Syongari stat->rx_rrs_errs += smb->rx_rrs_errs; 2196184870Syongari stat->rx_alignerrs += smb->rx_alignerrs; 2197184870Syongari stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2198184870Syongari stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2199184870Syongari stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2200184870Syongari 2201184870Syongari /* Tx stats. */ 2202184870Syongari stat->tx_frames += smb->tx_frames; 2203184870Syongari stat->tx_bcast_frames += smb->tx_bcast_frames; 2204184870Syongari stat->tx_mcast_frames += smb->tx_mcast_frames; 2205184870Syongari stat->tx_pause_frames += smb->tx_pause_frames; 2206184870Syongari stat->tx_excess_defer += smb->tx_excess_defer; 2207184870Syongari stat->tx_control_frames += smb->tx_control_frames; 2208184870Syongari stat->tx_deferred += smb->tx_deferred; 2209184870Syongari stat->tx_bytes += smb->tx_bytes; 2210184870Syongari stat->tx_pkts_64 += smb->tx_pkts_64; 2211184870Syongari stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2212184870Syongari stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2213184870Syongari stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2214184870Syongari stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2215184870Syongari stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2216184870Syongari stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2217184870Syongari stat->tx_single_colls += smb->tx_single_colls; 2218184870Syongari stat->tx_multi_colls += smb->tx_multi_colls; 2219184870Syongari stat->tx_late_colls += smb->tx_late_colls; 2220184870Syongari stat->tx_excess_colls += smb->tx_excess_colls; 2221184870Syongari stat->tx_abort += smb->tx_abort; 2222184870Syongari stat->tx_underrun += smb->tx_underrun; 2223184870Syongari stat->tx_desc_underrun += smb->tx_desc_underrun; 2224184870Syongari stat->tx_lenerrs += smb->tx_lenerrs; 2225184870Syongari stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2226184870Syongari stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2227184870Syongari stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2228184870Syongari 2229184870Syongari /* Update counters in ifnet. */ 2230184870Syongari ifp->if_opackets += smb->tx_frames; 2231184870Syongari 2232184870Syongari ifp->if_collisions += smb->tx_single_colls + 2233184870Syongari smb->tx_multi_colls * 2 + smb->tx_late_colls + 2234184870Syongari smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2235184870Syongari 2236184870Syongari /* 2237184870Syongari * XXX 2238184870Syongari * tx_pkts_truncated counter looks suspicious. It constantly 2239184870Syongari * increments with no sign of Tx errors. This may indicate 2240184870Syongari * the counter name is not correct one so I've removed the 2241184870Syongari * counter in output errors. 2242184870Syongari */ 2243184870Syongari ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2244184870Syongari smb->tx_underrun; 2245184870Syongari 2246184870Syongari ifp->if_ipackets += smb->rx_frames; 2247184870Syongari 2248184870Syongari ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2249184870Syongari smb->rx_runts + smb->rx_pkts_truncated + 2250184870Syongari smb->rx_fifo_oflows + smb->rx_rrs_errs + 2251184870Syongari smb->rx_alignerrs; 2252184870Syongari} 2253184870Syongari 2254184870Syongaristatic int 2255184870Syongariale_intr(void *arg) 2256184870Syongari{ 2257184870Syongari struct ale_softc *sc; 2258184870Syongari uint32_t status; 2259184870Syongari 2260184870Syongari sc = (struct ale_softc *)arg; 2261184870Syongari 2262184870Syongari status = CSR_READ_4(sc, ALE_INTR_STATUS); 2263184870Syongari if ((status & ALE_INTRS) == 0) 2264184870Syongari return (FILTER_STRAY); 2265184870Syongari /* Disable interrupts. */ 2266184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2267184870Syongari taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2268184870Syongari 2269184870Syongari return (FILTER_HANDLED); 2270184870Syongari} 2271184870Syongari 2272184870Syongaristatic void 2273184870Syongariale_int_task(void *arg, int pending) 2274184870Syongari{ 2275184870Syongari struct ale_softc *sc; 2276184870Syongari struct ifnet *ifp; 2277184870Syongari uint32_t status; 2278184870Syongari int more; 2279184870Syongari 2280184870Syongari sc = (struct ale_softc *)arg; 2281184870Syongari 2282184870Syongari status = CSR_READ_4(sc, ALE_INTR_STATUS); 2283217542Sjhb ALE_LOCK(sc); 2284216438Syongari if (sc->ale_morework != 0) 2285184870Syongari status |= INTR_RX_PKT; 2286184870Syongari if ((status & ALE_INTRS) == 0) 2287184870Syongari goto done; 2288184870Syongari 2289184870Syongari /* Acknowledge interrupts but still disable interrupts. */ 2290184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2291184870Syongari 2292184870Syongari ifp = sc->ale_ifp; 2293184870Syongari more = 0; 2294184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2295184870Syongari more = ale_rxeof(sc, sc->ale_process_limit); 2296184870Syongari if (more == EAGAIN) 2297216438Syongari sc->ale_morework = 1; 2298184870Syongari else if (more == EIO) { 2299184870Syongari sc->ale_stats.reset_brk_seq++; 2300184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2301184870Syongari ale_init_locked(sc); 2302184870Syongari ALE_UNLOCK(sc); 2303184870Syongari return; 2304184870Syongari } 2305184870Syongari 2306184870Syongari if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2307184870Syongari if ((status & INTR_DMA_RD_TO_RST) != 0) 2308184870Syongari device_printf(sc->ale_dev, 2309184870Syongari "DMA read error! -- resetting\n"); 2310184870Syongari if ((status & INTR_DMA_WR_TO_RST) != 0) 2311184870Syongari device_printf(sc->ale_dev, 2312184870Syongari "DMA write error! -- resetting\n"); 2313184870Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2314184870Syongari ale_init_locked(sc); 2315184870Syongari ALE_UNLOCK(sc); 2316184870Syongari return; 2317184870Syongari } 2318184870Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2319216925Sjhb ale_start_locked(ifp); 2320184870Syongari } 2321184870Syongari 2322184870Syongari if (more == EAGAIN || 2323184870Syongari (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2324217542Sjhb ALE_UNLOCK(sc); 2325184870Syongari taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2326184870Syongari return; 2327184870Syongari } 2328184870Syongari 2329184870Syongaridone: 2330217542Sjhb ALE_UNLOCK(sc); 2331217542Sjhb 2332184870Syongari /* Re-enable interrupts. */ 2333184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2334184870Syongari} 2335184870Syongari 2336184870Syongaristatic void 2337184870Syongariale_txeof(struct ale_softc *sc) 2338184870Syongari{ 2339184870Syongari struct ifnet *ifp; 2340184870Syongari struct ale_txdesc *txd; 2341184870Syongari uint32_t cons, prod; 2342184870Syongari int prog; 2343184870Syongari 2344184870Syongari ALE_LOCK_ASSERT(sc); 2345184870Syongari 2346184870Syongari ifp = sc->ale_ifp; 2347184870Syongari 2348184870Syongari if (sc->ale_cdata.ale_tx_cnt == 0) 2349184870Syongari return; 2350184870Syongari 2351184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2352184870Syongari sc->ale_cdata.ale_tx_ring_map, 2353184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2354184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2355184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2356184870Syongari sc->ale_cdata.ale_tx_cmb_map, 2357184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2358184870Syongari prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2359184870Syongari } else 2360184870Syongari prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2361184870Syongari cons = sc->ale_cdata.ale_tx_cons; 2362184870Syongari /* 2363184870Syongari * Go through our Tx list and free mbufs for those 2364184870Syongari * frames which have been transmitted. 2365184870Syongari */ 2366184870Syongari for (prog = 0; cons != prod; prog++, 2367184870Syongari ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2368184870Syongari if (sc->ale_cdata.ale_tx_cnt <= 0) 2369184870Syongari break; 2370184870Syongari prog++; 2371184870Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2372184870Syongari sc->ale_cdata.ale_tx_cnt--; 2373184870Syongari txd = &sc->ale_cdata.ale_txdesc[cons]; 2374184870Syongari if (txd->tx_m != NULL) { 2375184870Syongari /* Reclaim transmitted mbufs. */ 2376184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2377184870Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2378184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2379184870Syongari txd->tx_dmamap); 2380184870Syongari m_freem(txd->tx_m); 2381184870Syongari txd->tx_m = NULL; 2382184870Syongari } 2383184870Syongari } 2384184870Syongari 2385184870Syongari if (prog > 0) { 2386184870Syongari sc->ale_cdata.ale_tx_cons = cons; 2387184870Syongari /* 2388184870Syongari * Unarm watchdog timer only when there is no pending 2389184870Syongari * Tx descriptors in queue. 2390184870Syongari */ 2391184870Syongari if (sc->ale_cdata.ale_tx_cnt == 0) 2392184870Syongari sc->ale_watchdog_timer = 0; 2393184870Syongari } 2394184870Syongari} 2395184870Syongari 2396184870Syongaristatic void 2397184870Syongariale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2398184870Syongari uint32_t length, uint32_t *prod) 2399184870Syongari{ 2400184870Syongari struct ale_rx_page *rx_page; 2401184870Syongari 2402184870Syongari rx_page = *page; 2403184870Syongari /* Update consumer position. */ 2404184870Syongari rx_page->cons += roundup(length + sizeof(struct rx_rs), 2405184870Syongari ALE_RX_PAGE_ALIGN); 2406184870Syongari if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2407184870Syongari /* 2408184870Syongari * End of Rx page reached, let hardware reuse 2409184870Syongari * this page. 2410184870Syongari */ 2411184870Syongari rx_page->cons = 0; 2412184870Syongari *rx_page->cmb_addr = 0; 2413184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2414184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2415184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2416184870Syongari RXF_VALID); 2417184870Syongari /* Switch to alternate Rx page. */ 2418184870Syongari sc->ale_cdata.ale_rx_curp ^= 1; 2419184870Syongari rx_page = *page = 2420184870Syongari &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2421184870Syongari /* Page flipped, sync CMB and Rx page. */ 2422184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2423184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2424184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2425184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2426184870Syongari /* Sync completed, cache updated producer index. */ 2427184870Syongari *prod = *rx_page->cmb_addr; 2428184870Syongari } 2429184870Syongari} 2430184870Syongari 2431184870Syongari 2432184870Syongari/* 2433184870Syongari * It seems that AR81xx controller can compute partial checksum. 2434184870Syongari * The partial checksum value can be used to accelerate checksum 2435184870Syongari * computation for fragmented TCP/UDP packets. Upper network stack 2436184870Syongari * already takes advantage of the partial checksum value in IP 2437184870Syongari * reassembly stage. But I'm not sure the correctness of the 2438184870Syongari * partial hardware checksum assistance due to lack of data sheet. 2439184870Syongari * In addition, the Rx feature of controller that requires copying 2440184870Syongari * for every frames effectively nullifies one of most nice offload 2441184870Syongari * capability of controller. 2442184870Syongari */ 2443184870Syongaristatic void 2444184870Syongariale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2445184870Syongari{ 2446184870Syongari struct ifnet *ifp; 2447184870Syongari struct ip *ip; 2448184870Syongari char *p; 2449184870Syongari 2450184870Syongari ifp = sc->ale_ifp; 2451184870Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2452184870Syongari if ((status & ALE_RD_IPCSUM_NOK) == 0) 2453184870Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2454184870Syongari 2455184870Syongari if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2456184870Syongari if (((status & ALE_RD_IPV4_FRAG) == 0) && 2457184870Syongari ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2458184870Syongari ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2459184870Syongari m->m_pkthdr.csum_flags |= 2460184870Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2461184870Syongari m->m_pkthdr.csum_data = 0xffff; 2462184870Syongari } 2463184870Syongari } else { 2464184870Syongari if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2465184870Syongari (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2466184870Syongari p = mtod(m, char *); 2467184870Syongari p += ETHER_HDR_LEN; 2468184870Syongari if ((status & ALE_RD_802_3) != 0) 2469184870Syongari p += LLC_SNAPFRAMELEN; 2470184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2471184870Syongari (status & ALE_RD_VLAN) != 0) 2472184870Syongari p += ETHER_VLAN_ENCAP_LEN; 2473184870Syongari ip = (struct ip *)p; 2474184870Syongari if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2475184870Syongari return; 2476184870Syongari m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2477184870Syongari CSUM_PSEUDO_HDR; 2478184870Syongari m->m_pkthdr.csum_data = 0xffff; 2479184870Syongari } 2480184870Syongari } 2481184870Syongari /* 2482184870Syongari * Don't mark bad checksum for TCP/UDP frames 2483184870Syongari * as fragmented frames may always have set 2484184870Syongari * bad checksummed bit of frame status. 2485184870Syongari */ 2486184870Syongari} 2487184870Syongari 2488184870Syongari/* Process received frames. */ 2489184870Syongaristatic int 2490184870Syongariale_rxeof(struct ale_softc *sc, int count) 2491184870Syongari{ 2492184870Syongari struct ale_rx_page *rx_page; 2493184870Syongari struct rx_rs *rs; 2494184870Syongari struct ifnet *ifp; 2495184870Syongari struct mbuf *m; 2496184870Syongari uint32_t length, prod, seqno, status, vtags; 2497184870Syongari int prog; 2498184870Syongari 2499184870Syongari ifp = sc->ale_ifp; 2500184870Syongari rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2501184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2502184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2503184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2504184870Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2505184870Syongari /* 2506184870Syongari * Don't directly access producer index as hardware may 2507184870Syongari * update it while Rx handler is in progress. It would 2508184870Syongari * be even better if there is a way to let hardware 2509184870Syongari * know how far driver processed its received frames. 2510184870Syongari * Alternatively, hardware could provide a way to disable 2511184870Syongari * CMB updates until driver acknowledges the end of CMB 2512184870Syongari * access. 2513184870Syongari */ 2514184870Syongari prod = *rx_page->cmb_addr; 2515184870Syongari for (prog = 0; prog < count; prog++) { 2516184870Syongari if (rx_page->cons >= prod) 2517184870Syongari break; 2518184870Syongari rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2519184870Syongari seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2520184870Syongari if (sc->ale_cdata.ale_rx_seqno != seqno) { 2521184870Syongari /* 2522184870Syongari * Normally I believe this should not happen unless 2523184870Syongari * severe driver bug or corrupted memory. However 2524184870Syongari * it seems to happen under certain conditions which 2525184870Syongari * is triggered by abrupt Rx events such as initiation 2526184870Syongari * of bulk transfer of remote host. It's not easy to 2527184870Syongari * reproduce this and I doubt it could be related 2528184870Syongari * with FIFO overflow of hardware or activity of Tx 2529184870Syongari * CMB updates. I also remember similar behaviour 2530184870Syongari * seen on RealTek 8139 which uses resembling Rx 2531184870Syongari * scheme. 2532184870Syongari */ 2533184870Syongari if (bootverbose) 2534184870Syongari device_printf(sc->ale_dev, 2535184870Syongari "garbled seq: %u, expected: %u -- " 2536184870Syongari "resetting!\n", seqno, 2537184870Syongari sc->ale_cdata.ale_rx_seqno); 2538184870Syongari return (EIO); 2539184870Syongari } 2540184870Syongari /* Frame received. */ 2541184870Syongari sc->ale_cdata.ale_rx_seqno++; 2542184870Syongari length = ALE_RX_BYTES(le32toh(rs->length)); 2543184870Syongari status = le32toh(rs->flags); 2544184870Syongari if ((status & ALE_RD_ERROR) != 0) { 2545184870Syongari /* 2546184870Syongari * We want to pass the following frames to upper 2547184870Syongari * layer regardless of error status of Rx return 2548184870Syongari * status. 2549184870Syongari * 2550184870Syongari * o IP/TCP/UDP checksum is bad. 2551184870Syongari * o frame length and protocol specific length 2552184870Syongari * does not match. 2553184870Syongari */ 2554184870Syongari if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2555184870Syongari ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2556184870Syongari ALE_RD_TRUNC)) != 0) { 2557184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2558184870Syongari continue; 2559184870Syongari } 2560184870Syongari } 2561184870Syongari /* 2562184870Syongari * m_devget(9) is major bottle-neck of ale(4)(It comes 2563184870Syongari * from hardware limitation). For jumbo frames we could 2564184870Syongari * get a slightly better performance if driver use 2565184870Syongari * m_getjcl(9) with proper buffer size argument. However 2566184870Syongari * that would make code more complicated and I don't 2567184870Syongari * think users would expect good Rx performance numbers 2568184870Syongari * on these low-end consumer ethernet controller. 2569184870Syongari */ 2570184870Syongari m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2571184870Syongari ETHER_ALIGN, ifp, NULL); 2572184870Syongari if (m == NULL) { 2573184870Syongari ifp->if_iqdrops++; 2574184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2575184870Syongari continue; 2576184870Syongari } 2577184870Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2578184870Syongari (status & ALE_RD_IPV4) != 0) 2579184870Syongari ale_rxcsum(sc, m, status); 2580184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2581184870Syongari (status & ALE_RD_VLAN) != 0) { 2582184870Syongari vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2583184870Syongari m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2584184870Syongari m->m_flags |= M_VLANTAG; 2585184870Syongari } 2586184870Syongari 2587184870Syongari /* Pass it to upper layer. */ 2588217542Sjhb ALE_UNLOCK(sc); 2589184870Syongari (*ifp->if_input)(ifp, m); 2590217542Sjhb ALE_LOCK(sc); 2591184870Syongari 2592184870Syongari ale_rx_update_page(sc, &rx_page, length, &prod); 2593184870Syongari } 2594184870Syongari 2595184870Syongari return (count > 0 ? 0 : EAGAIN); 2596184870Syongari} 2597184870Syongari 2598184870Syongaristatic void 2599184870Syongariale_tick(void *arg) 2600184870Syongari{ 2601184870Syongari struct ale_softc *sc; 2602184870Syongari struct mii_data *mii; 2603184870Syongari 2604184870Syongari sc = (struct ale_softc *)arg; 2605184870Syongari 2606184870Syongari ALE_LOCK_ASSERT(sc); 2607184870Syongari 2608184870Syongari mii = device_get_softc(sc->ale_miibus); 2609184870Syongari mii_tick(mii); 2610184870Syongari ale_stats_update(sc); 2611184870Syongari /* 2612184870Syongari * Reclaim Tx buffers that have been transferred. It's not 2613184870Syongari * needed here but it would release allocated mbuf chains 2614184870Syongari * faster and limit the maximum delay to a hz. 2615184870Syongari */ 2616184870Syongari ale_txeof(sc); 2617184870Syongari ale_watchdog(sc); 2618184870Syongari callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2619184870Syongari} 2620184870Syongari 2621184870Syongaristatic void 2622184870Syongariale_reset(struct ale_softc *sc) 2623184870Syongari{ 2624184870Syongari uint32_t reg; 2625184870Syongari int i; 2626184870Syongari 2627184870Syongari /* Initialize PCIe module. From Linux. */ 2628184870Syongari CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2629184870Syongari 2630184870Syongari CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2631184870Syongari for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2632184870Syongari DELAY(10); 2633184870Syongari if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2634184870Syongari break; 2635184870Syongari } 2636184870Syongari if (i == 0) 2637184870Syongari device_printf(sc->ale_dev, "master reset timeout!\n"); 2638184870Syongari 2639184870Syongari for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2640184870Syongari if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2641184870Syongari break; 2642184870Syongari DELAY(10); 2643184870Syongari } 2644184870Syongari 2645184870Syongari if (i == 0) 2646184870Syongari device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2647184870Syongari} 2648184870Syongari 2649184870Syongaristatic void 2650184870Syongariale_init(void *xsc) 2651184870Syongari{ 2652184870Syongari struct ale_softc *sc; 2653184870Syongari 2654184870Syongari sc = (struct ale_softc *)xsc; 2655184870Syongari ALE_LOCK(sc); 2656184870Syongari ale_init_locked(sc); 2657184870Syongari ALE_UNLOCK(sc); 2658184870Syongari} 2659184870Syongari 2660184870Syongaristatic void 2661184870Syongariale_init_locked(struct ale_softc *sc) 2662184870Syongari{ 2663184870Syongari struct ifnet *ifp; 2664184870Syongari struct mii_data *mii; 2665184870Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 2666184870Syongari bus_addr_t paddr; 2667184870Syongari uint32_t reg, rxf_hi, rxf_lo; 2668184870Syongari 2669184870Syongari ALE_LOCK_ASSERT(sc); 2670184870Syongari 2671184870Syongari ifp = sc->ale_ifp; 2672184870Syongari mii = device_get_softc(sc->ale_miibus); 2673184870Syongari 2674184870Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2675184870Syongari return; 2676184870Syongari /* 2677184870Syongari * Cancel any pending I/O. 2678184870Syongari */ 2679184870Syongari ale_stop(sc); 2680184870Syongari /* 2681184870Syongari * Reset the chip to a known state. 2682184870Syongari */ 2683184870Syongari ale_reset(sc); 2684184870Syongari /* Initialize Tx descriptors, DMA memory blocks. */ 2685184870Syongari ale_init_rx_pages(sc); 2686184870Syongari ale_init_tx_ring(sc); 2687184870Syongari 2688184870Syongari /* Reprogram the station address. */ 2689184870Syongari bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2690184870Syongari CSR_WRITE_4(sc, ALE_PAR0, 2691184870Syongari eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2692184870Syongari CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2693184870Syongari /* 2694184870Syongari * Clear WOL status and disable all WOL feature as WOL 2695184870Syongari * would interfere Rx operation under normal environments. 2696184870Syongari */ 2697184870Syongari CSR_READ_4(sc, ALE_WOL_CFG); 2698184870Syongari CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2699184870Syongari /* 2700184870Syongari * Set Tx descriptor/RXF0/CMB base addresses. They share 2701184870Syongari * the same high address part of DMAable region. 2702184870Syongari */ 2703184870Syongari paddr = sc->ale_cdata.ale_tx_ring_paddr; 2704184870Syongari CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2705184870Syongari CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2706184870Syongari CSR_WRITE_4(sc, ALE_TPD_CNT, 2707184870Syongari (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2708184870Syongari /* Set Rx page base address, note we use single queue. */ 2709184870Syongari paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2710184870Syongari CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2711184870Syongari paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2712184870Syongari CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2713184870Syongari /* Set Tx/Rx CMB addresses. */ 2714184870Syongari paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2715184870Syongari CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2716184870Syongari paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2717184870Syongari CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2718184870Syongari paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2719184870Syongari CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2720184870Syongari /* Mark RXF0 is valid. */ 2721184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2722184870Syongari CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2723184870Syongari /* 2724184870Syongari * No need to initialize RFX1/RXF2/RXF3. We don't use 2725184870Syongari * multi-queue yet. 2726184870Syongari */ 2727184870Syongari 2728184870Syongari /* Set Rx page size, excluding guard frame size. */ 2729184870Syongari CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2730184870Syongari /* Tell hardware that we're ready to load DMA blocks. */ 2731184870Syongari CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2732184870Syongari 2733184870Syongari /* Set Rx/Tx interrupt trigger threshold. */ 2734184870Syongari CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2735184870Syongari (4 << INT_TRIG_TX_THRESH_SHIFT)); 2736184870Syongari /* 2737184870Syongari * XXX 2738184870Syongari * Set interrupt trigger timer, its purpose and relation 2739184870Syongari * with interrupt moderation mechanism is not clear yet. 2740184870Syongari */ 2741184870Syongari CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2742184870Syongari ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2743184870Syongari (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2744184870Syongari 2745184870Syongari /* Configure interrupt moderation timer. */ 2746184870Syongari reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2747184870Syongari reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2748184870Syongari CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2749184870Syongari reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2750184870Syongari reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2751184870Syongari reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2752184870Syongari if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2753184870Syongari reg |= MASTER_IM_RX_TIMER_ENB; 2754184870Syongari if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2755184870Syongari reg |= MASTER_IM_TX_TIMER_ENB; 2756184870Syongari CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2757184870Syongari CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2758184870Syongari 2759184870Syongari /* Set Maximum frame size of controller. */ 2760184870Syongari if (ifp->if_mtu < ETHERMTU) 2761184870Syongari sc->ale_max_frame_size = ETHERMTU; 2762184870Syongari else 2763184870Syongari sc->ale_max_frame_size = ifp->if_mtu; 2764184870Syongari sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2765184870Syongari ETHER_CRC_LEN; 2766184870Syongari CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2767184870Syongari /* Configure IPG/IFG parameters. */ 2768184870Syongari CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2769184870Syongari ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2770184870Syongari ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2771184870Syongari ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2772184870Syongari ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2773184870Syongari /* Set parameters for half-duplex media. */ 2774184870Syongari CSR_WRITE_4(sc, ALE_HDPX_CFG, 2775184870Syongari ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2776184870Syongari HDPX_CFG_LCOL_MASK) | 2777184870Syongari ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2778184870Syongari HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2779184870Syongari ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2780184870Syongari HDPX_CFG_ABEBT_MASK) | 2781184870Syongari ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2782184870Syongari HDPX_CFG_JAMIPG_MASK)); 2783184870Syongari 2784184870Syongari /* Configure Tx jumbo frame parameters. */ 2785184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2786184870Syongari if (ifp->if_mtu < ETHERMTU) 2787184870Syongari reg = sc->ale_max_frame_size; 2788184870Syongari else if (ifp->if_mtu < 6 * 1024) 2789184870Syongari reg = (sc->ale_max_frame_size * 2) / 3; 2790184870Syongari else 2791184870Syongari reg = sc->ale_max_frame_size / 2; 2792184870Syongari CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2793184870Syongari roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2794184870Syongari TX_JUMBO_THRESH_UNIT_SHIFT); 2795184870Syongari } 2796184870Syongari /* Configure TxQ. */ 2797185577Syongari reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2798185577Syongari << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2799184870Syongari reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2800184870Syongari TXQ_CFG_TPD_BURST_MASK; 2801184870Syongari CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2802184870Syongari 2803184870Syongari /* Configure Rx jumbo frame & flow control parameters. */ 2804184870Syongari if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2805184870Syongari reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2806184870Syongari CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2807184870Syongari (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2808184870Syongari RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2809184870Syongari ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2810184870Syongari RX_JUMBO_LKAH_MASK)); 2811184870Syongari reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2812184870Syongari rxf_hi = (reg * 7) / 10; 2813184870Syongari rxf_lo = (reg * 3)/ 10; 2814184870Syongari CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2815184870Syongari ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2816184870Syongari RX_FIFO_PAUSE_THRESH_LO_MASK) | 2817184870Syongari ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2818184870Syongari RX_FIFO_PAUSE_THRESH_HI_MASK)); 2819184870Syongari } 2820184870Syongari 2821184870Syongari /* Disable RSS. */ 2822184870Syongari CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2823184870Syongari CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2824184870Syongari 2825184870Syongari /* Configure RxQ. */ 2826184870Syongari CSR_WRITE_4(sc, ALE_RXQ_CFG, 2827184870Syongari RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2828184870Syongari 2829184870Syongari /* Configure DMA parameters. */ 2830184870Syongari reg = 0; 2831184870Syongari if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2832184870Syongari reg |= DMA_CFG_TXCMB_ENB; 2833184870Syongari CSR_WRITE_4(sc, ALE_DMA_CFG, 2834184870Syongari DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2835184870Syongari sc->ale_dma_rd_burst | reg | 2836184870Syongari sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2837184870Syongari ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2838184870Syongari DMA_CFG_RD_DELAY_CNT_MASK) | 2839184870Syongari ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2840184870Syongari DMA_CFG_WR_DELAY_CNT_MASK)); 2841184870Syongari 2842184870Syongari /* 2843184870Syongari * Hardware can be configured to issue SMB interrupt based 2844184870Syongari * on programmed interval. Since there is a callout that is 2845184870Syongari * invoked for every hz in driver we use that instead of 2846184870Syongari * relying on periodic SMB interrupt. 2847184870Syongari */ 2848184870Syongari CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2849184870Syongari /* Clear MAC statistics. */ 2850184870Syongari ale_stats_clear(sc); 2851184870Syongari 2852184870Syongari /* 2853184870Syongari * Configure Tx/Rx MACs. 2854184870Syongari * - Auto-padding for short frames. 2855184870Syongari * - Enable CRC generation. 2856184870Syongari * Actual reconfiguration of MAC for resolved speed/duplex 2857184870Syongari * is followed after detection of link establishment. 2858184870Syongari * AR81xx always does checksum computation regardless of 2859184870Syongari * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2860184870Syongari * cause Rx handling issue for fragmented IP datagrams due 2861184870Syongari * to silicon bug. 2862184870Syongari */ 2863184870Syongari reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2864184870Syongari ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2865184870Syongari MAC_CFG_PREAMBLE_MASK); 2866184870Syongari if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2867184870Syongari reg |= MAC_CFG_SPEED_10_100; 2868184870Syongari else 2869184870Syongari reg |= MAC_CFG_SPEED_1000; 2870184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2871184870Syongari 2872184870Syongari /* Set up the receive filter. */ 2873184870Syongari ale_rxfilter(sc); 2874184870Syongari ale_rxvlan(sc); 2875184870Syongari 2876184870Syongari /* Acknowledge all pending interrupts and clear it. */ 2877184870Syongari CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2878184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2879184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2880184870Syongari 2881184870Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 2882184870Syongari /* Switch to the current media. */ 2883184870Syongari mii_mediachg(mii); 2884184870Syongari 2885184870Syongari callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2886184870Syongari 2887184870Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2888184870Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2889184870Syongari} 2890184870Syongari 2891184870Syongaristatic void 2892184870Syongariale_stop(struct ale_softc *sc) 2893184870Syongari{ 2894184870Syongari struct ifnet *ifp; 2895184870Syongari struct ale_txdesc *txd; 2896184870Syongari uint32_t reg; 2897184870Syongari int i; 2898184870Syongari 2899184870Syongari ALE_LOCK_ASSERT(sc); 2900184870Syongari /* 2901184870Syongari * Mark the interface down and cancel the watchdog timer. 2902184870Syongari */ 2903184870Syongari ifp = sc->ale_ifp; 2904184870Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2905184870Syongari sc->ale_flags &= ~ALE_FLAG_LINK; 2906184870Syongari callout_stop(&sc->ale_tick_ch); 2907184870Syongari sc->ale_watchdog_timer = 0; 2908184870Syongari ale_stats_update(sc); 2909184870Syongari /* Disable interrupts. */ 2910184870Syongari CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2911184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2912184870Syongari /* Disable queue processing and DMA. */ 2913184870Syongari reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2914184870Syongari reg &= ~TXQ_CFG_ENB; 2915184870Syongari CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2916184870Syongari reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2917184870Syongari reg &= ~RXQ_CFG_ENB; 2918184870Syongari CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2919184870Syongari reg = CSR_READ_4(sc, ALE_DMA_CFG); 2920184870Syongari reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2921184870Syongari CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2922184870Syongari DELAY(1000); 2923184870Syongari /* Stop Rx/Tx MACs. */ 2924184870Syongari ale_stop_mac(sc); 2925184870Syongari /* Disable interrupts which might be touched in taskq handler. */ 2926184870Syongari CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2927184870Syongari 2928184870Syongari /* 2929184870Syongari * Free TX mbufs still in the queues. 2930184870Syongari */ 2931184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 2932184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 2933184870Syongari if (txd->tx_m != NULL) { 2934184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2935184870Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2936184870Syongari bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2937184870Syongari txd->tx_dmamap); 2938184870Syongari m_freem(txd->tx_m); 2939184870Syongari txd->tx_m = NULL; 2940184870Syongari } 2941184870Syongari } 2942184870Syongari} 2943184870Syongari 2944184870Syongaristatic void 2945184870Syongariale_stop_mac(struct ale_softc *sc) 2946184870Syongari{ 2947184870Syongari uint32_t reg; 2948184870Syongari int i; 2949184870Syongari 2950184870Syongari ALE_LOCK_ASSERT(sc); 2951184870Syongari 2952184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 2953184870Syongari if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2954184870Syongari reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2955184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2956184870Syongari } 2957184870Syongari 2958184870Syongari for (i = ALE_TIMEOUT; i > 0; i--) { 2959184870Syongari reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2960184870Syongari if (reg == 0) 2961184870Syongari break; 2962184870Syongari DELAY(10); 2963184870Syongari } 2964184870Syongari if (i == 0) 2965184870Syongari device_printf(sc->ale_dev, 2966184870Syongari "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2967184870Syongari} 2968184870Syongari 2969184870Syongaristatic void 2970184870Syongariale_init_tx_ring(struct ale_softc *sc) 2971184870Syongari{ 2972184870Syongari struct ale_txdesc *txd; 2973184870Syongari int i; 2974184870Syongari 2975184870Syongari ALE_LOCK_ASSERT(sc); 2976184870Syongari 2977184870Syongari sc->ale_cdata.ale_tx_prod = 0; 2978184870Syongari sc->ale_cdata.ale_tx_cons = 0; 2979184870Syongari sc->ale_cdata.ale_tx_cnt = 0; 2980184870Syongari 2981184870Syongari bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2982184870Syongari bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2983184870Syongari for (i = 0; i < ALE_TX_RING_CNT; i++) { 2984184870Syongari txd = &sc->ale_cdata.ale_txdesc[i]; 2985184870Syongari txd->tx_m = NULL; 2986184870Syongari } 2987184870Syongari *sc->ale_cdata.ale_tx_cmb = 0; 2988184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2989184870Syongari sc->ale_cdata.ale_tx_cmb_map, 2990184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2991184870Syongari bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2992184870Syongari sc->ale_cdata.ale_tx_ring_map, 2993184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2994184870Syongari} 2995184870Syongari 2996184870Syongaristatic void 2997184870Syongariale_init_rx_pages(struct ale_softc *sc) 2998184870Syongari{ 2999184870Syongari struct ale_rx_page *rx_page; 3000184870Syongari int i; 3001184870Syongari 3002184870Syongari ALE_LOCK_ASSERT(sc); 3003184870Syongari 3004216438Syongari sc->ale_morework = 0; 3005184870Syongari sc->ale_cdata.ale_rx_seqno = 0; 3006184870Syongari sc->ale_cdata.ale_rx_curp = 0; 3007184870Syongari 3008184870Syongari for (i = 0; i < ALE_RX_PAGES; i++) { 3009184870Syongari rx_page = &sc->ale_cdata.ale_rx_page[i]; 3010184870Syongari bzero(rx_page->page_addr, sc->ale_pagesize); 3011184870Syongari bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 3012184870Syongari rx_page->cons = 0; 3013184870Syongari *rx_page->cmb_addr = 0; 3014184870Syongari bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 3015184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3016184870Syongari bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 3017184870Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3018184870Syongari } 3019184870Syongari} 3020184870Syongari 3021184870Syongaristatic void 3022184870Syongariale_rxvlan(struct ale_softc *sc) 3023184870Syongari{ 3024184870Syongari struct ifnet *ifp; 3025184870Syongari uint32_t reg; 3026184870Syongari 3027184870Syongari ALE_LOCK_ASSERT(sc); 3028184870Syongari 3029184870Syongari ifp = sc->ale_ifp; 3030184870Syongari reg = CSR_READ_4(sc, ALE_MAC_CFG); 3031184870Syongari reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3032184870Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3033184870Syongari reg |= MAC_CFG_VLAN_TAG_STRIP; 3034184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3035184870Syongari} 3036184870Syongari 3037184870Syongaristatic void 3038184870Syongariale_rxfilter(struct ale_softc *sc) 3039184870Syongari{ 3040184870Syongari struct ifnet *ifp; 3041184870Syongari struct ifmultiaddr *ifma; 3042184870Syongari uint32_t crc; 3043184870Syongari uint32_t mchash[2]; 3044184870Syongari uint32_t rxcfg; 3045184870Syongari 3046184870Syongari ALE_LOCK_ASSERT(sc); 3047184870Syongari 3048184870Syongari ifp = sc->ale_ifp; 3049184870Syongari 3050184870Syongari rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3051184870Syongari rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3052184870Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 3053184870Syongari rxcfg |= MAC_CFG_BCAST; 3054184870Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3055184870Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 3056184870Syongari rxcfg |= MAC_CFG_PROMISC; 3057184870Syongari if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3058184870Syongari rxcfg |= MAC_CFG_ALLMULTI; 3059184870Syongari CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3060184870Syongari CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3061184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3062184870Syongari return; 3063184870Syongari } 3064184870Syongari 3065184870Syongari /* Program new filter. */ 3066184870Syongari bzero(mchash, sizeof(mchash)); 3067184870Syongari 3068195049Srwatson if_maddr_rlock(ifp); 3069184870Syongari TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3070184870Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 3071184870Syongari continue; 3072197627Syongari crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3073184870Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 3074184870Syongari mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3075184870Syongari } 3076195049Srwatson if_maddr_runlock(ifp); 3077184870Syongari 3078184870Syongari CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3079184870Syongari CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3080184870Syongari CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3081184870Syongari} 3082184870Syongari 3083184870Syongaristatic int 3084184870Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3085184870Syongari{ 3086184870Syongari int error, value; 3087184870Syongari 3088184870Syongari if (arg1 == NULL) 3089184870Syongari return (EINVAL); 3090184870Syongari value = *(int *)arg1; 3091184870Syongari error = sysctl_handle_int(oidp, &value, 0, req); 3092184870Syongari if (error || req->newptr == NULL) 3093184870Syongari return (error); 3094184870Syongari if (value < low || value > high) 3095184870Syongari return (EINVAL); 3096184870Syongari *(int *)arg1 = value; 3097184870Syongari 3098184870Syongari return (0); 3099184870Syongari} 3100184870Syongari 3101184870Syongaristatic int 3102184870Syongarisysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3103184870Syongari{ 3104184870Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3105184870Syongari ALE_PROC_MIN, ALE_PROC_MAX)); 3106184870Syongari} 3107184870Syongari 3108184870Syongaristatic int 3109184870Syongarisysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3110184870Syongari{ 3111184870Syongari 3112184870Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3113184870Syongari ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3114184870Syongari} 3115