if_ale.c revision 204378
1144091Sdas/*- 2144091Sdas * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3144091Sdas * All rights reserved. 4144091Sdas * 5144091Sdas * Redistribution and use in source and binary forms, with or without 6144091Sdas * modification, are permitted provided that the following conditions 7144091Sdas * are met: 8144091Sdas * 1. Redistributions of source code must retain the above copyright 9144091Sdas * notice unmodified, this list of conditions, and the following 10144091Sdas * disclaimer. 11144091Sdas * 2. Redistributions in binary form must reproduce the above copyright 12144091Sdas * notice, this list of conditions and the following disclaimer in the 13144091Sdas * documentation and/or other materials provided with the distribution. 14144091Sdas * 15144091Sdas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16144091Sdas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17144091Sdas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18144091Sdas * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19144091Sdas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20144091Sdas * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21144091Sdas * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22144091Sdas * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23144091Sdas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24144091Sdas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25144091Sdas * SUCH DAMAGE. 26144091Sdas */ 27144091Sdas 28144091Sdas/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29144091Sdas 30144091Sdas#include <sys/cdefs.h> 31144091Sdas__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 204378 2010-02-26 22:46:36Z yongari $"); 32144091Sdas 33144091Sdas#include <sys/param.h> 34144091Sdas#include <sys/systm.h> 35144091Sdas#include <sys/bus.h> 36144091Sdas#include <sys/endian.h> 37144091Sdas#include <sys/kernel.h> 38144091Sdas#include <sys/malloc.h> 39144091Sdas#include <sys/mbuf.h> 40144091Sdas#include <sys/module.h> 41144091Sdas#include <sys/rman.h> 42144091Sdas#include <sys/queue.h> 43144091Sdas#include <sys/socket.h> 44144091Sdas#include <sys/sockio.h> 45144091Sdas#include <sys/sysctl.h> 46144091Sdas#include <sys/taskqueue.h> 47144091Sdas 48144091Sdas#include <net/bpf.h> 49144091Sdas#include <net/if.h> 50144091Sdas#include <net/if_arp.h> 51144091Sdas#include <net/ethernet.h> 52144091Sdas#include <net/if_dl.h> 53144091Sdas#include <net/if_llc.h> 54144091Sdas#include <net/if_media.h> 55144091Sdas#include <net/if_types.h> 56144091Sdas#include <net/if_vlan_var.h> 57144091Sdas 58144091Sdas#include <netinet/in.h> 59144091Sdas#include <netinet/in_systm.h> 60144091Sdas#include <netinet/ip.h> 61144091Sdas#include <netinet/tcp.h> 62144091Sdas 63144091Sdas#include <dev/mii/mii.h> 64144091Sdas#include <dev/mii/miivar.h> 65144091Sdas 66192760Sattilio#include <dev/pci/pcireg.h> 67217108Skib#include <dev/pci/pcivar.h> 68217108Skib 69#include <machine/atomic.h> 70#include <machine/bus.h> 71#include <machine/in_cksum.h> 72 73#include <dev/ale/if_alereg.h> 74#include <dev/ale/if_alevar.h> 75 76/* "device miibus" required. See GENERIC if you get errors here. */ 77#include "miibus_if.h" 78 79/* For more information about Tx checksum offload issues see ale_encap(). */ 80#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82MODULE_DEPEND(ale, pci, 1, 1, 1); 83MODULE_DEPEND(ale, ether, 1, 1, 1); 84MODULE_DEPEND(ale, miibus, 1, 1, 1); 85 86/* Tunables. */ 87static int msi_disable = 0; 88static int msix_disable = 0; 89TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 90TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 91 92/* 93 * Devices supported by this driver. 94 */ 95static struct ale_dev { 96 uint16_t ale_vendorid; 97 uint16_t ale_deviceid; 98 const char *ale_name; 99} ale_devs[] = { 100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 102}; 103 104static int ale_attach(device_t); 105static int ale_check_boundary(struct ale_softc *); 106static int ale_detach(device_t); 107static int ale_dma_alloc(struct ale_softc *); 108static void ale_dma_free(struct ale_softc *); 109static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 110static int ale_encap(struct ale_softc *, struct mbuf **); 111static void ale_get_macaddr(struct ale_softc *); 112static void ale_init(void *); 113static void ale_init_locked(struct ale_softc *); 114static void ale_init_rx_pages(struct ale_softc *); 115static void ale_init_tx_ring(struct ale_softc *); 116static void ale_int_task(void *, int); 117static int ale_intr(void *); 118static int ale_ioctl(struct ifnet *, u_long, caddr_t); 119static void ale_link_task(void *, int); 120static void ale_mac_config(struct ale_softc *); 121static int ale_miibus_readreg(device_t, int, int); 122static void ale_miibus_statchg(device_t); 123static int ale_miibus_writereg(device_t, int, int, int); 124static int ale_mediachange(struct ifnet *); 125static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 126static void ale_phy_reset(struct ale_softc *); 127static int ale_probe(device_t); 128static void ale_reset(struct ale_softc *); 129static int ale_resume(device_t); 130static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 131 uint32_t, uint32_t *); 132static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 133static int ale_rxeof(struct ale_softc *sc, int); 134static void ale_rxfilter(struct ale_softc *); 135static void ale_rxvlan(struct ale_softc *); 136static void ale_setlinkspeed(struct ale_softc *); 137static void ale_setwol(struct ale_softc *); 138static int ale_shutdown(device_t); 139static void ale_start(struct ifnet *); 140static void ale_stats_clear(struct ale_softc *); 141static void ale_stats_update(struct ale_softc *); 142static void ale_stop(struct ale_softc *); 143static void ale_stop_mac(struct ale_softc *); 144static int ale_suspend(device_t); 145static void ale_sysctl_node(struct ale_softc *); 146static void ale_tick(void *); 147static void ale_tx_task(void *, int); 148static void ale_txeof(struct ale_softc *); 149static void ale_watchdog(struct ale_softc *); 150static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 151static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 152static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 153 154static device_method_t ale_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, ale_probe), 157 DEVMETHOD(device_attach, ale_attach), 158 DEVMETHOD(device_detach, ale_detach), 159 DEVMETHOD(device_shutdown, ale_shutdown), 160 DEVMETHOD(device_suspend, ale_suspend), 161 DEVMETHOD(device_resume, ale_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 165 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 166 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 167 168 { NULL, NULL } 169}; 170 171static driver_t ale_driver = { 172 "ale", 173 ale_methods, 174 sizeof(struct ale_softc) 175}; 176 177static devclass_t ale_devclass; 178 179DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0); 180DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 181 182static struct resource_spec ale_res_spec_mem[] = { 183 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 184 { -1, 0, 0 } 185}; 186 187static struct resource_spec ale_irq_spec_legacy[] = { 188 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 189 { -1, 0, 0 } 190}; 191 192static struct resource_spec ale_irq_spec_msi[] = { 193 { SYS_RES_IRQ, 1, RF_ACTIVE }, 194 { -1, 0, 0 } 195}; 196 197static struct resource_spec ale_irq_spec_msix[] = { 198 { SYS_RES_IRQ, 1, RF_ACTIVE }, 199 { -1, 0, 0 } 200}; 201 202static int 203ale_miibus_readreg(device_t dev, int phy, int reg) 204{ 205 struct ale_softc *sc; 206 uint32_t v; 207 int i; 208 209 sc = device_get_softc(dev); 210 211 if (phy != sc->ale_phyaddr) 212 return (0); 213 214 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 217 DELAY(5); 218 v = CSR_READ_4(sc, ALE_MDIO); 219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220 break; 221 } 222 223 if (i == 0) { 224 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 225 return (0); 226 } 227 228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229} 230 231static int 232ale_miibus_writereg(device_t dev, int phy, int reg, int val) 233{ 234 struct ale_softc *sc; 235 uint32_t v; 236 int i; 237 238 sc = device_get_softc(dev); 239 240 if (phy != sc->ale_phyaddr) 241 return (0); 242 243 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 244 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 245 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 246 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 247 DELAY(5); 248 v = CSR_READ_4(sc, ALE_MDIO); 249 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 250 break; 251 } 252 253 if (i == 0) 254 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 255 256 return (0); 257} 258 259static void 260ale_miibus_statchg(device_t dev) 261{ 262 struct ale_softc *sc; 263 264 sc = device_get_softc(dev); 265 266 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task); 267} 268 269static void 270ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 271{ 272 struct ale_softc *sc; 273 struct mii_data *mii; 274 275 sc = ifp->if_softc; 276 ALE_LOCK(sc); 277 mii = device_get_softc(sc->ale_miibus); 278 279 mii_pollstat(mii); 280 ALE_UNLOCK(sc); 281 ifmr->ifm_status = mii->mii_media_status; 282 ifmr->ifm_active = mii->mii_media_active; 283} 284 285static int 286ale_mediachange(struct ifnet *ifp) 287{ 288 struct ale_softc *sc; 289 struct mii_data *mii; 290 struct mii_softc *miisc; 291 int error; 292 293 sc = ifp->if_softc; 294 ALE_LOCK(sc); 295 mii = device_get_softc(sc->ale_miibus); 296 if (mii->mii_instance != 0) { 297 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 298 mii_phy_reset(miisc); 299 } 300 error = mii_mediachg(mii); 301 ALE_UNLOCK(sc); 302 303 return (error); 304} 305 306static int 307ale_probe(device_t dev) 308{ 309 struct ale_dev *sp; 310 int i; 311 uint16_t vendor, devid; 312 313 vendor = pci_get_vendor(dev); 314 devid = pci_get_device(dev); 315 sp = ale_devs; 316 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 317 if (vendor == sp->ale_vendorid && 318 devid == sp->ale_deviceid) { 319 device_set_desc(dev, sp->ale_name); 320 return (BUS_PROBE_DEFAULT); 321 } 322 sp++; 323 } 324 325 return (ENXIO); 326} 327 328static void 329ale_get_macaddr(struct ale_softc *sc) 330{ 331 uint32_t ea[2], reg; 332 int i, vpdc; 333 334 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 335 if ((reg & SPI_VPD_ENB) != 0) { 336 reg &= ~SPI_VPD_ENB; 337 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 338 } 339 340 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 341 /* 342 * PCI VPD capability found, let TWSI reload EEPROM. 343 * This will set ethernet address of controller. 344 */ 345 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 346 TWSI_CTRL_SW_LD_START); 347 for (i = 100; i > 0; i--) { 348 DELAY(1000); 349 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 350 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 351 break; 352 } 353 if (i == 0) 354 device_printf(sc->ale_dev, 355 "reloading EEPROM timeout!\n"); 356 } else { 357 if (bootverbose) 358 device_printf(sc->ale_dev, 359 "PCI VPD capability not found!\n"); 360 } 361 362 ea[0] = CSR_READ_4(sc, ALE_PAR0); 363 ea[1] = CSR_READ_4(sc, ALE_PAR1); 364 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 365 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 366 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 367 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 368 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 369 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 370} 371 372static void 373ale_phy_reset(struct ale_softc *sc) 374{ 375 376 /* Reset magic from Linux. */ 377 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 378 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 379 GPHY_CTRL_PHY_PLL_ON); 380 DELAY(1000); 381 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 382 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 383 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 384 DELAY(1000); 385 386#define ATPHY_DBG_ADDR 0x1D 387#define ATPHY_DBG_DATA 0x1E 388 389 /* Enable hibernation mode. */ 390 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 391 ATPHY_DBG_ADDR, 0x0B); 392 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 393 ATPHY_DBG_DATA, 0xBC00); 394 /* Set Class A/B for all modes. */ 395 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 396 ATPHY_DBG_ADDR, 0x00); 397 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 398 ATPHY_DBG_DATA, 0x02EF); 399 /* Enable 10BT power saving. */ 400 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 401 ATPHY_DBG_ADDR, 0x12); 402 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 403 ATPHY_DBG_DATA, 0x4C04); 404 /* Adjust 1000T power. */ 405 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 406 ATPHY_DBG_ADDR, 0x04); 407 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 408 ATPHY_DBG_ADDR, 0x8BBB); 409 /* 10BT center tap voltage. */ 410 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 411 ATPHY_DBG_ADDR, 0x05); 412 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 413 ATPHY_DBG_ADDR, 0x2C46); 414 415#undef ATPHY_DBG_ADDR 416#undef ATPHY_DBG_DATA 417 DELAY(1000); 418} 419 420static int 421ale_attach(device_t dev) 422{ 423 struct ale_softc *sc; 424 struct ifnet *ifp; 425 uint16_t burst; 426 int error, i, msic, msixc, pmc; 427 uint32_t rxf_len, txf_len; 428 429 error = 0; 430 sc = device_get_softc(dev); 431 sc->ale_dev = dev; 432 433 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 434 MTX_DEF); 435 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 436 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 437 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc); 438 439 /* Map the device. */ 440 pci_enable_busmaster(dev); 441 sc->ale_res_spec = ale_res_spec_mem; 442 sc->ale_irq_spec = ale_irq_spec_legacy; 443 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 444 if (error != 0) { 445 device_printf(dev, "cannot allocate memory resources.\n"); 446 goto fail; 447 } 448 449 /* Set PHY address. */ 450 sc->ale_phyaddr = ALE_PHY_ADDR; 451 452 /* Reset PHY. */ 453 ale_phy_reset(sc); 454 455 /* Reset the ethernet controller. */ 456 ale_reset(sc); 457 458 /* Get PCI and chip id/revision. */ 459 sc->ale_rev = pci_get_revid(dev); 460 if (sc->ale_rev >= 0xF0) { 461 /* L2E Rev. B. AR8114 */ 462 sc->ale_flags |= ALE_FLAG_FASTETHER; 463 } else { 464 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 465 /* L1E AR8121 */ 466 sc->ale_flags |= ALE_FLAG_JUMBO; 467 } else { 468 /* L2E Rev. A. AR8113 */ 469 sc->ale_flags |= ALE_FLAG_FASTETHER; 470 } 471 } 472 /* 473 * All known controllers seems to require 4 bytes alignment 474 * of Tx buffers to make Tx checksum offload with custom 475 * checksum generation method work. 476 */ 477 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 478 /* 479 * All known controllers seems to have issues on Rx checksum 480 * offload for fragmented IP datagrams. 481 */ 482 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 483 /* 484 * Don't use Tx CMB. It is known to cause RRS update failure 485 * under certain circumstances. Typical phenomenon of the 486 * issue would be unexpected sequence number encountered in 487 * Rx handler. 488 */ 489 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 490 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 491 MASTER_CHIP_REV_SHIFT; 492 if (bootverbose) { 493 device_printf(dev, "PCI device revision : 0x%04x\n", 494 sc->ale_rev); 495 device_printf(dev, "Chip id/revision : 0x%04x\n", 496 sc->ale_chip_rev); 497 } 498 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 499 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 500 /* 501 * Uninitialized hardware returns an invalid chip id/revision 502 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 503 */ 504 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 505 rxf_len == 0xFFFFFFF) { 506 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 507 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 508 txf_len, rxf_len); 509 error = ENXIO; 510 goto fail; 511 } 512 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 513 514 /* Allocate IRQ resources. */ 515 msixc = pci_msix_count(dev); 516 msic = pci_msi_count(dev); 517 if (bootverbose) { 518 device_printf(dev, "MSIX count : %d\n", msixc); 519 device_printf(dev, "MSI count : %d\n", msic); 520 } 521 522 /* Prefer MSIX over MSI. */ 523 if (msix_disable == 0 || msi_disable == 0) { 524 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 525 pci_alloc_msix(dev, &msixc) == 0) { 526 if (msic == ALE_MSIX_MESSAGES) { 527 device_printf(dev, "Using %d MSIX messages.\n", 528 msixc); 529 sc->ale_flags |= ALE_FLAG_MSIX; 530 sc->ale_irq_spec = ale_irq_spec_msix; 531 } else 532 pci_release_msi(dev); 533 } 534 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 535 msic == ALE_MSI_MESSAGES && 536 pci_alloc_msi(dev, &msic) == 0) { 537 if (msic == ALE_MSI_MESSAGES) { 538 device_printf(dev, "Using %d MSI messages.\n", 539 msic); 540 sc->ale_flags |= ALE_FLAG_MSI; 541 sc->ale_irq_spec = ale_irq_spec_msi; 542 } else 543 pci_release_msi(dev); 544 } 545 } 546 547 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 548 if (error != 0) { 549 device_printf(dev, "cannot allocate IRQ resources.\n"); 550 goto fail; 551 } 552 553 /* Get DMA parameters from PCIe device control register. */ 554 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 555 sc->ale_flags |= ALE_FLAG_PCIE; 556 burst = pci_read_config(dev, i + 0x08, 2); 557 /* Max read request size. */ 558 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 559 DMA_CFG_RD_BURST_SHIFT; 560 /* Max payload size. */ 561 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 562 DMA_CFG_WR_BURST_SHIFT; 563 if (bootverbose) { 564 device_printf(dev, "Read request size : %d bytes.\n", 565 128 << ((burst >> 12) & 0x07)); 566 device_printf(dev, "TLP payload size : %d bytes.\n", 567 128 << ((burst >> 5) & 0x07)); 568 } 569 } else { 570 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 571 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 572 } 573 574 /* Create device sysctl node. */ 575 ale_sysctl_node(sc); 576 577 if ((error = ale_dma_alloc(sc) != 0)) 578 goto fail; 579 580 /* Load station address. */ 581 ale_get_macaddr(sc); 582 583 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 584 if (ifp == NULL) { 585 device_printf(dev, "cannot allocate ifnet structure.\n"); 586 error = ENXIO; 587 goto fail; 588 } 589 590 ifp->if_softc = sc; 591 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 592 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 593 ifp->if_ioctl = ale_ioctl; 594 ifp->if_start = ale_start; 595 ifp->if_init = ale_init; 596 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 597 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 598 IFQ_SET_READY(&ifp->if_snd); 599 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 600 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 601 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 602 sc->ale_flags |= ALE_FLAG_PMCAP; 603 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 604 } 605 ifp->if_capenable = ifp->if_capabilities; 606 607 /* Set up MII bus. */ 608 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange, 609 ale_mediastatus)) != 0) { 610 device_printf(dev, "no PHY found!\n"); 611 goto fail; 612 } 613 614 ether_ifattach(ifp, sc->ale_eaddr); 615 616 /* VLAN capability setup. */ 617 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 618 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 619 ifp->if_capenable = ifp->if_capabilities; 620 /* 621 * Even though controllers supported by ale(3) have Rx checksum 622 * offload bug the workaround for fragmented frames seemed to 623 * work so far. However it seems Rx checksum offload does not 624 * work under certain conditions. So disable Rx checksum offload 625 * until I find more clue about it but allow users to override it. 626 */ 627 ifp->if_capenable &= ~IFCAP_RXCSUM; 628 629 /* Tell the upper layer(s) we support long frames. */ 630 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 631 632 /* Create local taskq. */ 633 TASK_INIT(&sc->ale_tx_task, 1, ale_tx_task, ifp); 634 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 635 taskqueue_thread_enqueue, &sc->ale_tq); 636 if (sc->ale_tq == NULL) { 637 device_printf(dev, "could not create taskqueue.\n"); 638 ether_ifdetach(ifp); 639 error = ENXIO; 640 goto fail; 641 } 642 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 643 device_get_nameunit(sc->ale_dev)); 644 645 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 646 msic = ALE_MSIX_MESSAGES; 647 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 648 msic = ALE_MSI_MESSAGES; 649 else 650 msic = 1; 651 for (i = 0; i < msic; i++) { 652 error = bus_setup_intr(dev, sc->ale_irq[i], 653 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 654 &sc->ale_intrhand[i]); 655 if (error != 0) 656 break; 657 } 658 if (error != 0) { 659 device_printf(dev, "could not set up interrupt handler.\n"); 660 taskqueue_free(sc->ale_tq); 661 sc->ale_tq = NULL; 662 ether_ifdetach(ifp); 663 goto fail; 664 } 665 666fail: 667 if (error != 0) 668 ale_detach(dev); 669 670 return (error); 671} 672 673static int 674ale_detach(device_t dev) 675{ 676 struct ale_softc *sc; 677 struct ifnet *ifp; 678 int i, msic; 679 680 sc = device_get_softc(dev); 681 682 ifp = sc->ale_ifp; 683 if (device_is_attached(dev)) { 684 ALE_LOCK(sc); 685 sc->ale_flags |= ALE_FLAG_DETACH; 686 ale_stop(sc); 687 ALE_UNLOCK(sc); 688 callout_drain(&sc->ale_tick_ch); 689 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 690 taskqueue_drain(sc->ale_tq, &sc->ale_tx_task); 691 taskqueue_drain(taskqueue_swi, &sc->ale_link_task); 692 ether_ifdetach(ifp); 693 } 694 695 if (sc->ale_tq != NULL) { 696 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 697 taskqueue_free(sc->ale_tq); 698 sc->ale_tq = NULL; 699 } 700 701 if (sc->ale_miibus != NULL) { 702 device_delete_child(dev, sc->ale_miibus); 703 sc->ale_miibus = NULL; 704 } 705 bus_generic_detach(dev); 706 ale_dma_free(sc); 707 708 if (ifp != NULL) { 709 if_free(ifp); 710 sc->ale_ifp = NULL; 711 } 712 713 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 714 msic = ALE_MSIX_MESSAGES; 715 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 716 msic = ALE_MSI_MESSAGES; 717 else 718 msic = 1; 719 for (i = 0; i < msic; i++) { 720 if (sc->ale_intrhand[i] != NULL) { 721 bus_teardown_intr(dev, sc->ale_irq[i], 722 sc->ale_intrhand[i]); 723 sc->ale_intrhand[i] = NULL; 724 } 725 } 726 727 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 728 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 729 pci_release_msi(dev); 730 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 731 mtx_destroy(&sc->ale_mtx); 732 733 return (0); 734} 735 736#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 737 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 738 739#if __FreeBSD_version > 800000 740#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 741 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 742#else 743#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 744 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 745#endif 746 747static void 748ale_sysctl_node(struct ale_softc *sc) 749{ 750 struct sysctl_ctx_list *ctx; 751 struct sysctl_oid_list *child, *parent; 752 struct sysctl_oid *tree; 753 struct ale_hw_stats *stats; 754 int error; 755 756 stats = &sc->ale_stats; 757 ctx = device_get_sysctl_ctx(sc->ale_dev); 758 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 759 760 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 761 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 762 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 763 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 764 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 765 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 766 /* Pull in device tunables. */ 767 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 768 error = resource_int_value(device_get_name(sc->ale_dev), 769 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 770 if (error == 0) { 771 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 772 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 773 device_printf(sc->ale_dev, "int_rx_mod value out of " 774 "range; using default: %d\n", 775 ALE_IM_RX_TIMER_DEFAULT); 776 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 777 } 778 } 779 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 780 error = resource_int_value(device_get_name(sc->ale_dev), 781 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 782 if (error == 0) { 783 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 784 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 785 device_printf(sc->ale_dev, "int_tx_mod value out of " 786 "range; using default: %d\n", 787 ALE_IM_TX_TIMER_DEFAULT); 788 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 789 } 790 } 791 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 792 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 793 sysctl_hw_ale_proc_limit, "I", 794 "max number of Rx events to process"); 795 /* Pull in device tunables. */ 796 sc->ale_process_limit = ALE_PROC_DEFAULT; 797 error = resource_int_value(device_get_name(sc->ale_dev), 798 device_get_unit(sc->ale_dev), "process_limit", 799 &sc->ale_process_limit); 800 if (error == 0) { 801 if (sc->ale_process_limit < ALE_PROC_MIN || 802 sc->ale_process_limit > ALE_PROC_MAX) { 803 device_printf(sc->ale_dev, 804 "process_limit value out of range; " 805 "using default: %d\n", ALE_PROC_DEFAULT); 806 sc->ale_process_limit = ALE_PROC_DEFAULT; 807 } 808 } 809 810 /* Misc statistics. */ 811 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 812 &stats->reset_brk_seq, 813 "Controller resets due to broken Rx sequnce number"); 814 815 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 816 NULL, "ATE statistics"); 817 parent = SYSCTL_CHILDREN(tree); 818 819 /* Rx statistics. */ 820 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 821 NULL, "Rx MAC statistics"); 822 child = SYSCTL_CHILDREN(tree); 823 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 824 &stats->rx_frames, "Good frames"); 825 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 826 &stats->rx_bcast_frames, "Good broadcast frames"); 827 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 828 &stats->rx_mcast_frames, "Good multicast frames"); 829 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 830 &stats->rx_pause_frames, "Pause control frames"); 831 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 832 &stats->rx_control_frames, "Control frames"); 833 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 834 &stats->rx_crcerrs, "CRC errors"); 835 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 836 &stats->rx_lenerrs, "Frames with length mismatched"); 837 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 838 &stats->rx_bytes, "Good octets"); 839 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 840 &stats->rx_bcast_bytes, "Good broadcast octets"); 841 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 842 &stats->rx_mcast_bytes, "Good multicast octets"); 843 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 844 &stats->rx_runts, "Too short frames"); 845 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 846 &stats->rx_fragments, "Fragmented frames"); 847 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 848 &stats->rx_pkts_64, "64 bytes frames"); 849 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 850 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 851 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 852 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 853 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 854 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 855 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 856 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 858 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 860 &stats->rx_pkts_1519_max, "1519 to max frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 862 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 864 &stats->rx_fifo_oflows, "FIFO overflows"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 866 &stats->rx_rrs_errs, "Return status write-back errors"); 867 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 868 &stats->rx_alignerrs, "Alignment errors"); 869 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 870 &stats->rx_pkts_filtered, 871 "Frames dropped due to address filtering"); 872 873 /* Tx statistics. */ 874 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 875 NULL, "Tx MAC statistics"); 876 child = SYSCTL_CHILDREN(tree); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 878 &stats->tx_frames, "Good frames"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 880 &stats->tx_bcast_frames, "Good broadcast frames"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 882 &stats->tx_mcast_frames, "Good multicast frames"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 884 &stats->tx_pause_frames, "Pause control frames"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 886 &stats->tx_control_frames, "Control frames"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 888 &stats->tx_excess_defer, "Frames with excessive derferrals"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 890 &stats->tx_excess_defer, "Frames with derferrals"); 891 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 892 &stats->tx_bytes, "Good octets"); 893 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 894 &stats->tx_bcast_bytes, "Good broadcast octets"); 895 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 896 &stats->tx_mcast_bytes, "Good multicast octets"); 897 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 898 &stats->tx_pkts_64, "64 bytes frames"); 899 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 900 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 901 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 902 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 903 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 904 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 905 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 906 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 907 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 908 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 909 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 910 &stats->tx_pkts_1519_max, "1519 to max frames"); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 912 &stats->tx_single_colls, "Single collisions"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 914 &stats->tx_multi_colls, "Multiple collisions"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 916 &stats->tx_late_colls, "Late collisions"); 917 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 918 &stats->tx_excess_colls, "Excessive collisions"); 919 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 920 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 921 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 922 &stats->tx_underrun, "FIFO underruns"); 923 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 924 &stats->tx_desc_underrun, "Descriptor write-back errors"); 925 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 926 &stats->tx_lenerrs, "Frames with length mismatched"); 927 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 928 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 929} 930 931#undef ALE_SYSCTL_STAT_ADD32 932#undef ALE_SYSCTL_STAT_ADD64 933 934struct ale_dmamap_arg { 935 bus_addr_t ale_busaddr; 936}; 937 938static void 939ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 940{ 941 struct ale_dmamap_arg *ctx; 942 943 if (error != 0) 944 return; 945 946 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 947 948 ctx = (struct ale_dmamap_arg *)arg; 949 ctx->ale_busaddr = segs[0].ds_addr; 950} 951 952/* 953 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 954 * which specifies high address region of DMA blocks. Therefore these 955 * blocks should have the same high address of given 4GB address 956 * space(i.e. crossing 4GB boundary is not allowed). 957 */ 958static int 959ale_check_boundary(struct ale_softc *sc) 960{ 961 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 962 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 963 964 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 965 sc->ale_pagesize; 966 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 967 sc->ale_pagesize; 968 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 969 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 970 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 971 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 972 973 if ((ALE_ADDR_HI(tx_ring_end) != 974 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 975 (ALE_ADDR_HI(rx_page_end[0]) != 976 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 977 (ALE_ADDR_HI(rx_page_end[1]) != 978 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 979 (ALE_ADDR_HI(tx_cmb_end) != 980 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 981 (ALE_ADDR_HI(rx_cmb_end[0]) != 982 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 983 (ALE_ADDR_HI(rx_cmb_end[1]) != 984 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 985 return (EFBIG); 986 987 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 988 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 989 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 990 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 991 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 992 return (EFBIG); 993 994 return (0); 995} 996 997static int 998ale_dma_alloc(struct ale_softc *sc) 999{ 1000 struct ale_txdesc *txd; 1001 bus_addr_t lowaddr; 1002 struct ale_dmamap_arg ctx; 1003 int error, guard_size, i; 1004 1005 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1006 guard_size = ALE_JUMBO_FRAMELEN; 1007 else 1008 guard_size = ALE_MAX_FRAMELEN; 1009 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1010 ALE_RX_PAGE_ALIGN); 1011 lowaddr = BUS_SPACE_MAXADDR; 1012again: 1013 /* Create parent DMA tag. */ 1014 error = bus_dma_tag_create( 1015 bus_get_dma_tag(sc->ale_dev), /* parent */ 1016 1, 0, /* alignment, boundary */ 1017 lowaddr, /* lowaddr */ 1018 BUS_SPACE_MAXADDR, /* highaddr */ 1019 NULL, NULL, /* filter, filterarg */ 1020 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1021 0, /* nsegments */ 1022 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1023 0, /* flags */ 1024 NULL, NULL, /* lockfunc, lockarg */ 1025 &sc->ale_cdata.ale_parent_tag); 1026 if (error != 0) { 1027 device_printf(sc->ale_dev, 1028 "could not create parent DMA tag.\n"); 1029 goto fail; 1030 } 1031 1032 /* Create DMA tag for Tx descriptor ring. */ 1033 error = bus_dma_tag_create( 1034 sc->ale_cdata.ale_parent_tag, /* parent */ 1035 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1036 BUS_SPACE_MAXADDR, /* lowaddr */ 1037 BUS_SPACE_MAXADDR, /* highaddr */ 1038 NULL, NULL, /* filter, filterarg */ 1039 ALE_TX_RING_SZ, /* maxsize */ 1040 1, /* nsegments */ 1041 ALE_TX_RING_SZ, /* maxsegsize */ 1042 0, /* flags */ 1043 NULL, NULL, /* lockfunc, lockarg */ 1044 &sc->ale_cdata.ale_tx_ring_tag); 1045 if (error != 0) { 1046 device_printf(sc->ale_dev, 1047 "could not create Tx ring DMA tag.\n"); 1048 goto fail; 1049 } 1050 1051 /* Create DMA tag for Rx pages. */ 1052 for (i = 0; i < ALE_RX_PAGES; i++) { 1053 error = bus_dma_tag_create( 1054 sc->ale_cdata.ale_parent_tag, /* parent */ 1055 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1056 BUS_SPACE_MAXADDR, /* lowaddr */ 1057 BUS_SPACE_MAXADDR, /* highaddr */ 1058 NULL, NULL, /* filter, filterarg */ 1059 sc->ale_pagesize, /* maxsize */ 1060 1, /* nsegments */ 1061 sc->ale_pagesize, /* maxsegsize */ 1062 0, /* flags */ 1063 NULL, NULL, /* lockfunc, lockarg */ 1064 &sc->ale_cdata.ale_rx_page[i].page_tag); 1065 if (error != 0) { 1066 device_printf(sc->ale_dev, 1067 "could not create Rx page %d DMA tag.\n", i); 1068 goto fail; 1069 } 1070 } 1071 1072 /* Create DMA tag for Tx coalescing message block. */ 1073 error = bus_dma_tag_create( 1074 sc->ale_cdata.ale_parent_tag, /* parent */ 1075 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1076 BUS_SPACE_MAXADDR, /* lowaddr */ 1077 BUS_SPACE_MAXADDR, /* highaddr */ 1078 NULL, NULL, /* filter, filterarg */ 1079 ALE_TX_CMB_SZ, /* maxsize */ 1080 1, /* nsegments */ 1081 ALE_TX_CMB_SZ, /* maxsegsize */ 1082 0, /* flags */ 1083 NULL, NULL, /* lockfunc, lockarg */ 1084 &sc->ale_cdata.ale_tx_cmb_tag); 1085 if (error != 0) { 1086 device_printf(sc->ale_dev, 1087 "could not create Tx CMB DMA tag.\n"); 1088 goto fail; 1089 } 1090 1091 /* Create DMA tag for Rx coalescing message block. */ 1092 for (i = 0; i < ALE_RX_PAGES; i++) { 1093 error = bus_dma_tag_create( 1094 sc->ale_cdata.ale_parent_tag, /* parent */ 1095 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1096 BUS_SPACE_MAXADDR, /* lowaddr */ 1097 BUS_SPACE_MAXADDR, /* highaddr */ 1098 NULL, NULL, /* filter, filterarg */ 1099 ALE_RX_CMB_SZ, /* maxsize */ 1100 1, /* nsegments */ 1101 ALE_RX_CMB_SZ, /* maxsegsize */ 1102 0, /* flags */ 1103 NULL, NULL, /* lockfunc, lockarg */ 1104 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1105 if (error != 0) { 1106 device_printf(sc->ale_dev, 1107 "could not create Rx page %d CMB DMA tag.\n", i); 1108 goto fail; 1109 } 1110 } 1111 1112 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1113 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1114 (void **)&sc->ale_cdata.ale_tx_ring, 1115 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1116 &sc->ale_cdata.ale_tx_ring_map); 1117 if (error != 0) { 1118 device_printf(sc->ale_dev, 1119 "could not allocate DMA'able memory for Tx ring.\n"); 1120 goto fail; 1121 } 1122 ctx.ale_busaddr = 0; 1123 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1124 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1125 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1126 if (error != 0 || ctx.ale_busaddr == 0) { 1127 device_printf(sc->ale_dev, 1128 "could not load DMA'able memory for Tx ring.\n"); 1129 goto fail; 1130 } 1131 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1132 1133 /* Rx pages. */ 1134 for (i = 0; i < ALE_RX_PAGES; i++) { 1135 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1136 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1137 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1138 &sc->ale_cdata.ale_rx_page[i].page_map); 1139 if (error != 0) { 1140 device_printf(sc->ale_dev, 1141 "could not allocate DMA'able memory for " 1142 "Rx page %d.\n", i); 1143 goto fail; 1144 } 1145 ctx.ale_busaddr = 0; 1146 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1147 sc->ale_cdata.ale_rx_page[i].page_map, 1148 sc->ale_cdata.ale_rx_page[i].page_addr, 1149 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1150 if (error != 0 || ctx.ale_busaddr == 0) { 1151 device_printf(sc->ale_dev, 1152 "could not load DMA'able memory for " 1153 "Rx page %d.\n", i); 1154 goto fail; 1155 } 1156 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1157 } 1158 1159 /* Tx CMB. */ 1160 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1161 (void **)&sc->ale_cdata.ale_tx_cmb, 1162 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1163 &sc->ale_cdata.ale_tx_cmb_map); 1164 if (error != 0) { 1165 device_printf(sc->ale_dev, 1166 "could not allocate DMA'able memory for Tx CMB.\n"); 1167 goto fail; 1168 } 1169 ctx.ale_busaddr = 0; 1170 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1171 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1172 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1173 if (error != 0 || ctx.ale_busaddr == 0) { 1174 device_printf(sc->ale_dev, 1175 "could not load DMA'able memory for Tx CMB.\n"); 1176 goto fail; 1177 } 1178 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1179 1180 /* Rx CMB. */ 1181 for (i = 0; i < ALE_RX_PAGES; i++) { 1182 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1183 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1184 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1185 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1186 if (error != 0) { 1187 device_printf(sc->ale_dev, "could not allocate " 1188 "DMA'able memory for Rx page %d CMB.\n", i); 1189 goto fail; 1190 } 1191 ctx.ale_busaddr = 0; 1192 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1193 sc->ale_cdata.ale_rx_page[i].cmb_map, 1194 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1195 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1196 if (error != 0 || ctx.ale_busaddr == 0) { 1197 device_printf(sc->ale_dev, "could not load DMA'able " 1198 "memory for Rx page %d CMB.\n", i); 1199 goto fail; 1200 } 1201 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1202 } 1203 1204 /* 1205 * Tx descriptors/RXF0/CMB DMA blocks share the same 1206 * high address region of 64bit DMA address space. 1207 */ 1208 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1209 (error = ale_check_boundary(sc)) != 0) { 1210 device_printf(sc->ale_dev, "4GB boundary crossed, " 1211 "switching to 32bit DMA addressing mode.\n"); 1212 ale_dma_free(sc); 1213 /* 1214 * Limit max allowable DMA address space to 32bit 1215 * and try again. 1216 */ 1217 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1218 goto again; 1219 } 1220 1221 /* 1222 * Create Tx buffer parent tag. 1223 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1224 * needs separate parent DMA tag as parent DMA address space 1225 * could be restricted to be within 32bit address space by 1226 * 4GB boundary crossing. 1227 */ 1228 error = bus_dma_tag_create( 1229 bus_get_dma_tag(sc->ale_dev), /* parent */ 1230 1, 0, /* alignment, boundary */ 1231 BUS_SPACE_MAXADDR, /* lowaddr */ 1232 BUS_SPACE_MAXADDR, /* highaddr */ 1233 NULL, NULL, /* filter, filterarg */ 1234 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1235 0, /* nsegments */ 1236 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1237 0, /* flags */ 1238 NULL, NULL, /* lockfunc, lockarg */ 1239 &sc->ale_cdata.ale_buffer_tag); 1240 if (error != 0) { 1241 device_printf(sc->ale_dev, 1242 "could not create parent buffer DMA tag.\n"); 1243 goto fail; 1244 } 1245 1246 /* Create DMA tag for Tx buffers. */ 1247 error = bus_dma_tag_create( 1248 sc->ale_cdata.ale_buffer_tag, /* parent */ 1249 1, 0, /* alignment, boundary */ 1250 BUS_SPACE_MAXADDR, /* lowaddr */ 1251 BUS_SPACE_MAXADDR, /* highaddr */ 1252 NULL, NULL, /* filter, filterarg */ 1253 ALE_TSO_MAXSIZE, /* maxsize */ 1254 ALE_MAXTXSEGS, /* nsegments */ 1255 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1256 0, /* flags */ 1257 NULL, NULL, /* lockfunc, lockarg */ 1258 &sc->ale_cdata.ale_tx_tag); 1259 if (error != 0) { 1260 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1261 goto fail; 1262 } 1263 1264 /* Create DMA maps for Tx buffers. */ 1265 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1266 txd = &sc->ale_cdata.ale_txdesc[i]; 1267 txd->tx_m = NULL; 1268 txd->tx_dmamap = NULL; 1269 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1270 &txd->tx_dmamap); 1271 if (error != 0) { 1272 device_printf(sc->ale_dev, 1273 "could not create Tx dmamap.\n"); 1274 goto fail; 1275 } 1276 } 1277 1278fail: 1279 return (error); 1280} 1281 1282static void 1283ale_dma_free(struct ale_softc *sc) 1284{ 1285 struct ale_txdesc *txd; 1286 int i; 1287 1288 /* Tx buffers. */ 1289 if (sc->ale_cdata.ale_tx_tag != NULL) { 1290 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1291 txd = &sc->ale_cdata.ale_txdesc[i]; 1292 if (txd->tx_dmamap != NULL) { 1293 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1294 txd->tx_dmamap); 1295 txd->tx_dmamap = NULL; 1296 } 1297 } 1298 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1299 sc->ale_cdata.ale_tx_tag = NULL; 1300 } 1301 /* Tx descriptor ring. */ 1302 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1303 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1304 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1305 sc->ale_cdata.ale_tx_ring_map); 1306 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1307 sc->ale_cdata.ale_tx_ring != NULL) 1308 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1309 sc->ale_cdata.ale_tx_ring, 1310 sc->ale_cdata.ale_tx_ring_map); 1311 sc->ale_cdata.ale_tx_ring = NULL; 1312 sc->ale_cdata.ale_tx_ring_map = NULL; 1313 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1314 sc->ale_cdata.ale_tx_ring_tag = NULL; 1315 } 1316 /* Rx page block. */ 1317 for (i = 0; i < ALE_RX_PAGES; i++) { 1318 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1319 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1320 bus_dmamap_unload( 1321 sc->ale_cdata.ale_rx_page[i].page_tag, 1322 sc->ale_cdata.ale_rx_page[i].page_map); 1323 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1324 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1325 bus_dmamem_free( 1326 sc->ale_cdata.ale_rx_page[i].page_tag, 1327 sc->ale_cdata.ale_rx_page[i].page_addr, 1328 sc->ale_cdata.ale_rx_page[i].page_map); 1329 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1330 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1331 bus_dma_tag_destroy( 1332 sc->ale_cdata.ale_rx_page[i].page_tag); 1333 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1334 } 1335 } 1336 /* Rx CMB. */ 1337 for (i = 0; i < ALE_RX_PAGES; i++) { 1338 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1339 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1340 bus_dmamap_unload( 1341 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1342 sc->ale_cdata.ale_rx_page[i].cmb_map); 1343 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1344 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1345 bus_dmamem_free( 1346 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1347 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1348 sc->ale_cdata.ale_rx_page[i].cmb_map); 1349 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1350 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1351 bus_dma_tag_destroy( 1352 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1353 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1354 } 1355 } 1356 /* Tx CMB. */ 1357 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1358 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1359 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1360 sc->ale_cdata.ale_tx_cmb_map); 1361 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1362 sc->ale_cdata.ale_tx_cmb != NULL) 1363 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1364 sc->ale_cdata.ale_tx_cmb, 1365 sc->ale_cdata.ale_tx_cmb_map); 1366 sc->ale_cdata.ale_tx_cmb = NULL; 1367 sc->ale_cdata.ale_tx_cmb_map = NULL; 1368 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1369 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1370 } 1371 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1372 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1373 sc->ale_cdata.ale_buffer_tag = NULL; 1374 } 1375 if (sc->ale_cdata.ale_parent_tag != NULL) { 1376 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1377 sc->ale_cdata.ale_parent_tag = NULL; 1378 } 1379} 1380 1381static int 1382ale_shutdown(device_t dev) 1383{ 1384 1385 return (ale_suspend(dev)); 1386} 1387 1388/* 1389 * Note, this driver resets the link speed to 10/100Mbps by 1390 * restarting auto-negotiation in suspend/shutdown phase but we 1391 * don't know whether that auto-negotiation would succeed or not 1392 * as driver has no control after powering off/suspend operation. 1393 * If the renegotiation fail WOL may not work. Running at 1Gbps 1394 * will draw more power than 375mA at 3.3V which is specified in 1395 * PCI specification and that would result in complete 1396 * shutdowning power to ethernet controller. 1397 * 1398 * TODO 1399 * Save current negotiated media speed/duplex/flow-control to 1400 * softc and restore the same link again after resuming. PHY 1401 * handling such as power down/resetting to 100Mbps may be better 1402 * handled in suspend method in phy driver. 1403 */ 1404static void 1405ale_setlinkspeed(struct ale_softc *sc) 1406{ 1407 struct mii_data *mii; 1408 int aneg, i; 1409 1410 mii = device_get_softc(sc->ale_miibus); 1411 mii_pollstat(mii); 1412 aneg = 0; 1413 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1414 (IFM_ACTIVE | IFM_AVALID)) { 1415 switch IFM_SUBTYPE(mii->mii_media_active) { 1416 case IFM_10_T: 1417 case IFM_100_TX: 1418 return; 1419 case IFM_1000_T: 1420 aneg++; 1421 break; 1422 default: 1423 break; 1424 } 1425 } 1426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1428 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1430 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1431 DELAY(1000); 1432 if (aneg != 0) { 1433 /* 1434 * Poll link state until ale(4) get a 10/100Mbps link. 1435 */ 1436 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1437 mii_pollstat(mii); 1438 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1439 == (IFM_ACTIVE | IFM_AVALID)) { 1440 switch (IFM_SUBTYPE( 1441 mii->mii_media_active)) { 1442 case IFM_10_T: 1443 case IFM_100_TX: 1444 ale_mac_config(sc); 1445 return; 1446 default: 1447 break; 1448 } 1449 } 1450 ALE_UNLOCK(sc); 1451 pause("alelnk", hz); 1452 ALE_LOCK(sc); 1453 } 1454 if (i == MII_ANEGTICKS_GIGE) 1455 device_printf(sc->ale_dev, 1456 "establishing a link failed, WOL may not work!"); 1457 } 1458 /* 1459 * No link, force MAC to have 100Mbps, full-duplex link. 1460 * This is the last resort and may/may not work. 1461 */ 1462 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1463 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1464 ale_mac_config(sc); 1465} 1466 1467static void 1468ale_setwol(struct ale_softc *sc) 1469{ 1470 struct ifnet *ifp; 1471 uint32_t reg, pmcs; 1472 uint16_t pmstat; 1473 int pmc; 1474 1475 ALE_LOCK_ASSERT(sc); 1476 1477 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1478 /* Disable WOL. */ 1479 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1480 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1481 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1482 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1483 /* Force PHY power down. */ 1484 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1485 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1486 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1487 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1488 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1489 return; 1490 } 1491 1492 ifp = sc->ale_ifp; 1493 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1494 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1495 ale_setlinkspeed(sc); 1496 } 1497 1498 pmcs = 0; 1499 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1500 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1501 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1502 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1503 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1504 MAC_CFG_BCAST); 1505 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1506 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1507 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1508 reg |= MAC_CFG_RX_ENB; 1509 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1510 1511 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1512 /* WOL disabled, PHY power down. */ 1513 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1514 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1515 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1516 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1517 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1518 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1519 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1520 GPHY_CTRL_PWDOWN_HW); 1521 } 1522 /* Request PME. */ 1523 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1524 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1525 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1526 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1527 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1528} 1529 1530static int 1531ale_suspend(device_t dev) 1532{ 1533 struct ale_softc *sc; 1534 1535 sc = device_get_softc(dev); 1536 1537 ALE_LOCK(sc); 1538 ale_stop(sc); 1539 ale_setwol(sc); 1540 ALE_UNLOCK(sc); 1541 1542 return (0); 1543} 1544 1545static int 1546ale_resume(device_t dev) 1547{ 1548 struct ale_softc *sc; 1549 struct ifnet *ifp; 1550 int pmc; 1551 uint16_t pmstat; 1552 1553 sc = device_get_softc(dev); 1554 1555 ALE_LOCK(sc); 1556 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1557 /* Disable PME and clear PME status. */ 1558 pmstat = pci_read_config(sc->ale_dev, 1559 pmc + PCIR_POWER_STATUS, 2); 1560 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1561 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1562 pci_write_config(sc->ale_dev, 1563 pmc + PCIR_POWER_STATUS, pmstat, 2); 1564 } 1565 } 1566 /* Reset PHY. */ 1567 ale_phy_reset(sc); 1568 ifp = sc->ale_ifp; 1569 if ((ifp->if_flags & IFF_UP) != 0) { 1570 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1571 ale_init_locked(sc); 1572 } 1573 ALE_UNLOCK(sc); 1574 1575 return (0); 1576} 1577 1578static int 1579ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1580{ 1581 struct ale_txdesc *txd, *txd_last; 1582 struct tx_desc *desc; 1583 struct mbuf *m; 1584 struct ip *ip; 1585 struct tcphdr *tcp; 1586 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1587 bus_dmamap_t map; 1588 uint32_t cflags, ip_off, poff, vtag; 1589 int error, i, nsegs, prod, si; 1590 1591 ALE_LOCK_ASSERT(sc); 1592 1593 M_ASSERTPKTHDR((*m_head)); 1594 1595 m = *m_head; 1596 ip = NULL; 1597 tcp = NULL; 1598 cflags = vtag = 0; 1599 ip_off = poff = 0; 1600 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1601 /* 1602 * AR81xx requires offset of TCP/UDP payload in its Tx 1603 * descriptor to perform hardware Tx checksum offload. 1604 * Additionally, TSO requires IP/TCP header size and 1605 * modification of IP/TCP header in order to make TSO 1606 * engine work. This kind of operation takes many CPU 1607 * cycles on FreeBSD so fast host CPU is required to 1608 * get smooth TSO performance. 1609 */ 1610 struct ether_header *eh; 1611 1612 if (M_WRITABLE(m) == 0) { 1613 /* Get a writable copy. */ 1614 m = m_dup(*m_head, M_DONTWAIT); 1615 /* Release original mbufs. */ 1616 m_freem(*m_head); 1617 if (m == NULL) { 1618 *m_head = NULL; 1619 return (ENOBUFS); 1620 } 1621 *m_head = m; 1622 } 1623 1624 /* 1625 * Buggy-controller requires 4 byte aligned Tx buffer 1626 * to make custom checksum offload work. 1627 */ 1628 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1629 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1630 (mtod(m, intptr_t) & 3) != 0) { 1631 m = m_defrag(*m_head, M_DONTWAIT); 1632 if (m == NULL) { 1633 *m_head = NULL; 1634 return (ENOBUFS); 1635 } 1636 *m_head = m; 1637 } 1638 1639 ip_off = sizeof(struct ether_header); 1640 m = m_pullup(m, ip_off); 1641 if (m == NULL) { 1642 *m_head = NULL; 1643 return (ENOBUFS); 1644 } 1645 eh = mtod(m, struct ether_header *); 1646 /* 1647 * Check if hardware VLAN insertion is off. 1648 * Additional check for LLC/SNAP frame? 1649 */ 1650 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1651 ip_off = sizeof(struct ether_vlan_header); 1652 m = m_pullup(m, ip_off); 1653 if (m == NULL) { 1654 *m_head = NULL; 1655 return (ENOBUFS); 1656 } 1657 } 1658 m = m_pullup(m, ip_off + sizeof(struct ip)); 1659 if (m == NULL) { 1660 *m_head = NULL; 1661 return (ENOBUFS); 1662 } 1663 ip = (struct ip *)(mtod(m, char *) + ip_off); 1664 poff = ip_off + (ip->ip_hl << 2); 1665 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1666 /* 1667 * XXX 1668 * AR81xx requires the first descriptor should 1669 * not include any TCP playload for TSO case. 1670 * (i.e. ethernet header + IP + TCP header only) 1671 * m_pullup(9) above will ensure this too. 1672 * However it's not correct if the first mbuf 1673 * of the chain does not use cluster. 1674 */ 1675 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1676 if (m == NULL) { 1677 *m_head = NULL; 1678 return (ENOBUFS); 1679 } 1680 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1681 /* 1682 * AR81xx requires IP/TCP header size and offset as 1683 * well as TCP pseudo checksum which complicates 1684 * TSO configuration. I guess this comes from the 1685 * adherence to Microsoft NDIS Large Send 1686 * specification which requires insertion of 1687 * pseudo checksum by upper stack. The pseudo 1688 * checksum that NDIS refers to doesn't include 1689 * TCP payload length so ale(4) should recompute 1690 * the pseudo checksum here. Hopefully this wouldn't 1691 * be much burden on modern CPUs. 1692 * Reset IP checksum and recompute TCP pseudo 1693 * checksum as NDIS specification said. 1694 */ 1695 ip->ip_sum = 0; 1696 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1697 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1698 } 1699 *m_head = m; 1700 } 1701 1702 si = prod = sc->ale_cdata.ale_tx_prod; 1703 txd = &sc->ale_cdata.ale_txdesc[prod]; 1704 txd_last = txd; 1705 map = txd->tx_dmamap; 1706 1707 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1708 *m_head, txsegs, &nsegs, 0); 1709 if (error == EFBIG) { 1710 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); 1711 if (m == NULL) { 1712 m_freem(*m_head); 1713 *m_head = NULL; 1714 return (ENOMEM); 1715 } 1716 *m_head = m; 1717 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1718 *m_head, txsegs, &nsegs, 0); 1719 if (error != 0) { 1720 m_freem(*m_head); 1721 *m_head = NULL; 1722 return (error); 1723 } 1724 } else if (error != 0) 1725 return (error); 1726 if (nsegs == 0) { 1727 m_freem(*m_head); 1728 *m_head = NULL; 1729 return (EIO); 1730 } 1731 1732 /* Check descriptor overrun. */ 1733 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 1734 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1735 return (ENOBUFS); 1736 } 1737 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1738 1739 m = *m_head; 1740 /* Configure Tx checksum offload. */ 1741 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1742 /* 1743 * AR81xx supports Tx custom checksum offload feature 1744 * that offloads single 16bit checksum computation. 1745 * So you can choose one among IP, TCP and UDP. 1746 * Normally driver sets checksum start/insertion 1747 * position from the information of TCP/UDP frame as 1748 * TCP/UDP checksum takes more time than that of IP. 1749 * However it seems that custom checksum offload 1750 * requires 4 bytes aligned Tx buffers due to hardware 1751 * bug. 1752 * AR81xx also supports explicit Tx checksum computation 1753 * if it is told that the size of IP header and TCP 1754 * header(for UDP, the header size does not matter 1755 * because it's fixed length). However with this scheme 1756 * TSO does not work so you have to choose one either 1757 * TSO or explicit Tx checksum offload. I chosen TSO 1758 * plus custom checksum offload with work-around which 1759 * will cover most common usage for this consumer 1760 * ethernet controller. The work-around takes a lot of 1761 * CPU cycles if Tx buffer is not aligned on 4 bytes 1762 * boundary, though. 1763 */ 1764 cflags |= ALE_TD_CXSUM; 1765 /* Set checksum start offset. */ 1766 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1767 /* Set checksum insertion position of TCP/UDP. */ 1768 cflags |= ((poff + m->m_pkthdr.csum_data) << 1769 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1770 } 1771 1772 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1773 /* Request TSO and set MSS. */ 1774 cflags |= ALE_TD_TSO; 1775 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1776 /* Set IP/TCP header size. */ 1777 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1778 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1779 } 1780 1781 /* Configure VLAN hardware tag insertion. */ 1782 if ((m->m_flags & M_VLANTAG) != 0) { 1783 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1784 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1785 cflags |= ALE_TD_INSERT_VLAN_TAG; 1786 } 1787 1788 desc = NULL; 1789 for (i = 0; i < nsegs; i++) { 1790 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1791 desc->addr = htole64(txsegs[i].ds_addr); 1792 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1793 desc->flags = htole32(cflags); 1794 sc->ale_cdata.ale_tx_cnt++; 1795 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1796 } 1797 /* Update producer index. */ 1798 sc->ale_cdata.ale_tx_prod = prod; 1799 /* Set TSO header on the first descriptor. */ 1800 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1801 desc = &sc->ale_cdata.ale_tx_ring[si]; 1802 desc->flags |= htole32(ALE_TD_TSO_HDR); 1803 } 1804 1805 /* Finally set EOP on the last descriptor. */ 1806 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1807 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1808 desc->flags |= htole32(ALE_TD_EOP); 1809 1810 /* Swap dmamap of the first and the last. */ 1811 txd = &sc->ale_cdata.ale_txdesc[prod]; 1812 map = txd_last->tx_dmamap; 1813 txd_last->tx_dmamap = txd->tx_dmamap; 1814 txd->tx_dmamap = map; 1815 txd->tx_m = m; 1816 1817 /* Sync descriptors. */ 1818 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1819 sc->ale_cdata.ale_tx_ring_map, 1820 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1821 1822 return (0); 1823} 1824 1825static void 1826ale_tx_task(void *arg, int pending) 1827{ 1828 struct ifnet *ifp; 1829 1830 ifp = (struct ifnet *)arg; 1831 ale_start(ifp); 1832} 1833 1834static void 1835ale_start(struct ifnet *ifp) 1836{ 1837 struct ale_softc *sc; 1838 struct mbuf *m_head; 1839 int enq; 1840 1841 sc = ifp->if_softc; 1842 1843 ALE_LOCK(sc); 1844 1845 /* Reclaim transmitted frames. */ 1846 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1847 ale_txeof(sc); 1848 1849 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1850 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) { 1851 ALE_UNLOCK(sc); 1852 return; 1853 } 1854 1855 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1856 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1857 if (m_head == NULL) 1858 break; 1859 /* 1860 * Pack the data into the transmit ring. If we 1861 * don't have room, set the OACTIVE flag and wait 1862 * for the NIC to drain the ring. 1863 */ 1864 if (ale_encap(sc, &m_head)) { 1865 if (m_head == NULL) 1866 break; 1867 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1868 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1869 break; 1870 } 1871 1872 enq++; 1873 /* 1874 * If there's a BPF listener, bounce a copy of this frame 1875 * to him. 1876 */ 1877 ETHER_BPF_MTAP(ifp, m_head); 1878 } 1879 1880 if (enq > 0) { 1881 /* Kick. */ 1882 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1883 sc->ale_cdata.ale_tx_prod); 1884 /* Set a timeout in case the chip goes out to lunch. */ 1885 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1886 } 1887 1888 ALE_UNLOCK(sc); 1889} 1890 1891static void 1892ale_watchdog(struct ale_softc *sc) 1893{ 1894 struct ifnet *ifp; 1895 1896 ALE_LOCK_ASSERT(sc); 1897 1898 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1899 return; 1900 1901 ifp = sc->ale_ifp; 1902 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1903 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1904 ifp->if_oerrors++; 1905 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1906 ale_init_locked(sc); 1907 return; 1908 } 1909 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1910 ifp->if_oerrors++; 1911 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1912 ale_init_locked(sc); 1913 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1914 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task); 1915} 1916 1917static int 1918ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1919{ 1920 struct ale_softc *sc; 1921 struct ifreq *ifr; 1922 struct mii_data *mii; 1923 int error, mask; 1924 1925 sc = ifp->if_softc; 1926 ifr = (struct ifreq *)data; 1927 error = 0; 1928 switch (cmd) { 1929 case SIOCSIFMTU: 1930 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1931 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1932 ifr->ifr_mtu > ETHERMTU)) 1933 error = EINVAL; 1934 else if (ifp->if_mtu != ifr->ifr_mtu) { 1935 ALE_LOCK(sc); 1936 ifp->if_mtu = ifr->ifr_mtu; 1937 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1938 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1939 ale_init_locked(sc); 1940 } 1941 ALE_UNLOCK(sc); 1942 } 1943 break; 1944 case SIOCSIFFLAGS: 1945 ALE_LOCK(sc); 1946 if ((ifp->if_flags & IFF_UP) != 0) { 1947 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1948 if (((ifp->if_flags ^ sc->ale_if_flags) 1949 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1950 ale_rxfilter(sc); 1951 } else { 1952 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0) 1953 ale_init_locked(sc); 1954 } 1955 } else { 1956 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1957 ale_stop(sc); 1958 } 1959 sc->ale_if_flags = ifp->if_flags; 1960 ALE_UNLOCK(sc); 1961 break; 1962 case SIOCADDMULTI: 1963 case SIOCDELMULTI: 1964 ALE_LOCK(sc); 1965 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1966 ale_rxfilter(sc); 1967 ALE_UNLOCK(sc); 1968 break; 1969 case SIOCSIFMEDIA: 1970 case SIOCGIFMEDIA: 1971 mii = device_get_softc(sc->ale_miibus); 1972 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1973 break; 1974 case SIOCSIFCAP: 1975 ALE_LOCK(sc); 1976 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1977 if ((mask & IFCAP_TXCSUM) != 0 && 1978 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1979 ifp->if_capenable ^= IFCAP_TXCSUM; 1980 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1981 ifp->if_hwassist |= ALE_CSUM_FEATURES; 1982 else 1983 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 1984 } 1985 if ((mask & IFCAP_RXCSUM) != 0 && 1986 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 1987 ifp->if_capenable ^= IFCAP_RXCSUM; 1988 if ((mask & IFCAP_TSO4) != 0 && 1989 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1990 ifp->if_capenable ^= IFCAP_TSO4; 1991 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1992 ifp->if_hwassist |= CSUM_TSO; 1993 else 1994 ifp->if_hwassist &= ~CSUM_TSO; 1995 } 1996 1997 if ((mask & IFCAP_WOL_MCAST) != 0 && 1998 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1999 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2000 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2001 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2002 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2003 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2004 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2005 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2006 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2007 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2008 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2009 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2010 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2011 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2012 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2013 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2014 ale_rxvlan(sc); 2015 } 2016 ALE_UNLOCK(sc); 2017 VLAN_CAPABILITIES(ifp); 2018 break; 2019 default: 2020 error = ether_ioctl(ifp, cmd, data); 2021 break; 2022 } 2023 2024 return (error); 2025} 2026 2027static void 2028ale_mac_config(struct ale_softc *sc) 2029{ 2030 struct mii_data *mii; 2031 uint32_t reg; 2032 2033 ALE_LOCK_ASSERT(sc); 2034 2035 mii = device_get_softc(sc->ale_miibus); 2036 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2037 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2038 MAC_CFG_SPEED_MASK); 2039 /* Reprogram MAC with resolved speed/duplex. */ 2040 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2041 case IFM_10_T: 2042 case IFM_100_TX: 2043 reg |= MAC_CFG_SPEED_10_100; 2044 break; 2045 case IFM_1000_T: 2046 reg |= MAC_CFG_SPEED_1000; 2047 break; 2048 } 2049 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2050 reg |= MAC_CFG_FULL_DUPLEX; 2051#ifdef notyet 2052 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2053 reg |= MAC_CFG_TX_FC; 2054 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2055 reg |= MAC_CFG_RX_FC; 2056#endif 2057 } 2058 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2059} 2060 2061static void 2062ale_link_task(void *arg, int pending) 2063{ 2064 struct ale_softc *sc; 2065 struct mii_data *mii; 2066 struct ifnet *ifp; 2067 uint32_t reg; 2068 2069 sc = (struct ale_softc *)arg; 2070 2071 ALE_LOCK(sc); 2072 mii = device_get_softc(sc->ale_miibus); 2073 ifp = sc->ale_ifp; 2074 if (mii == NULL || ifp == NULL || 2075 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2076 ALE_UNLOCK(sc); 2077 return; 2078 } 2079 2080 sc->ale_flags &= ~ALE_FLAG_LINK; 2081 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2082 (IFM_ACTIVE | IFM_AVALID)) { 2083 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2084 case IFM_10_T: 2085 case IFM_100_TX: 2086 sc->ale_flags |= ALE_FLAG_LINK; 2087 break; 2088 case IFM_1000_T: 2089 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 2090 sc->ale_flags |= ALE_FLAG_LINK; 2091 break; 2092 default: 2093 break; 2094 } 2095 } 2096 2097 /* Stop Rx/Tx MACs. */ 2098 ale_stop_mac(sc); 2099 2100 /* Program MACs with resolved speed/duplex/flow-control. */ 2101 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 2102 ale_mac_config(sc); 2103 /* Reenable Tx/Rx MACs. */ 2104 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2105 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2106 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2107 } 2108 2109 ALE_UNLOCK(sc); 2110} 2111 2112static void 2113ale_stats_clear(struct ale_softc *sc) 2114{ 2115 struct smb sb; 2116 uint32_t *reg; 2117 int i; 2118 2119 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2120 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2121 i += sizeof(uint32_t); 2122 } 2123 /* Read Tx statistics. */ 2124 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2125 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2126 i += sizeof(uint32_t); 2127 } 2128} 2129 2130static void 2131ale_stats_update(struct ale_softc *sc) 2132{ 2133 struct ale_hw_stats *stat; 2134 struct smb sb, *smb; 2135 struct ifnet *ifp; 2136 uint32_t *reg; 2137 int i; 2138 2139 ALE_LOCK_ASSERT(sc); 2140 2141 ifp = sc->ale_ifp; 2142 stat = &sc->ale_stats; 2143 smb = &sb; 2144 2145 /* Read Rx statistics. */ 2146 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2147 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2148 i += sizeof(uint32_t); 2149 } 2150 /* Read Tx statistics. */ 2151 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2152 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2153 i += sizeof(uint32_t); 2154 } 2155 2156 /* Rx stats. */ 2157 stat->rx_frames += smb->rx_frames; 2158 stat->rx_bcast_frames += smb->rx_bcast_frames; 2159 stat->rx_mcast_frames += smb->rx_mcast_frames; 2160 stat->rx_pause_frames += smb->rx_pause_frames; 2161 stat->rx_control_frames += smb->rx_control_frames; 2162 stat->rx_crcerrs += smb->rx_crcerrs; 2163 stat->rx_lenerrs += smb->rx_lenerrs; 2164 stat->rx_bytes += smb->rx_bytes; 2165 stat->rx_runts += smb->rx_runts; 2166 stat->rx_fragments += smb->rx_fragments; 2167 stat->rx_pkts_64 += smb->rx_pkts_64; 2168 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2169 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2170 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2171 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2172 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2173 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2174 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2175 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2176 stat->rx_rrs_errs += smb->rx_rrs_errs; 2177 stat->rx_alignerrs += smb->rx_alignerrs; 2178 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2179 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2180 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2181 2182 /* Tx stats. */ 2183 stat->tx_frames += smb->tx_frames; 2184 stat->tx_bcast_frames += smb->tx_bcast_frames; 2185 stat->tx_mcast_frames += smb->tx_mcast_frames; 2186 stat->tx_pause_frames += smb->tx_pause_frames; 2187 stat->tx_excess_defer += smb->tx_excess_defer; 2188 stat->tx_control_frames += smb->tx_control_frames; 2189 stat->tx_deferred += smb->tx_deferred; 2190 stat->tx_bytes += smb->tx_bytes; 2191 stat->tx_pkts_64 += smb->tx_pkts_64; 2192 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2193 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2194 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2195 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2196 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2197 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2198 stat->tx_single_colls += smb->tx_single_colls; 2199 stat->tx_multi_colls += smb->tx_multi_colls; 2200 stat->tx_late_colls += smb->tx_late_colls; 2201 stat->tx_excess_colls += smb->tx_excess_colls; 2202 stat->tx_abort += smb->tx_abort; 2203 stat->tx_underrun += smb->tx_underrun; 2204 stat->tx_desc_underrun += smb->tx_desc_underrun; 2205 stat->tx_lenerrs += smb->tx_lenerrs; 2206 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2207 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2208 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2209 2210 /* Update counters in ifnet. */ 2211 ifp->if_opackets += smb->tx_frames; 2212 2213 ifp->if_collisions += smb->tx_single_colls + 2214 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2215 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2216 2217 /* 2218 * XXX 2219 * tx_pkts_truncated counter looks suspicious. It constantly 2220 * increments with no sign of Tx errors. This may indicate 2221 * the counter name is not correct one so I've removed the 2222 * counter in output errors. 2223 */ 2224 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2225 smb->tx_underrun; 2226 2227 ifp->if_ipackets += smb->rx_frames; 2228 2229 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2230 smb->rx_runts + smb->rx_pkts_truncated + 2231 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2232 smb->rx_alignerrs; 2233} 2234 2235static int 2236ale_intr(void *arg) 2237{ 2238 struct ale_softc *sc; 2239 uint32_t status; 2240 2241 sc = (struct ale_softc *)arg; 2242 2243 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2244 if ((status & ALE_INTRS) == 0) 2245 return (FILTER_STRAY); 2246 /* Disable interrupts. */ 2247 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2248 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2249 2250 return (FILTER_HANDLED); 2251} 2252 2253static void 2254ale_int_task(void *arg, int pending) 2255{ 2256 struct ale_softc *sc; 2257 struct ifnet *ifp; 2258 uint32_t status; 2259 int more; 2260 2261 sc = (struct ale_softc *)arg; 2262 2263 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2264 more = atomic_readandclear_int(&sc->ale_morework); 2265 if (more != 0) 2266 status |= INTR_RX_PKT; 2267 if ((status & ALE_INTRS) == 0) 2268 goto done; 2269 2270 /* Acknowledge interrupts but still disable interrupts. */ 2271 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2272 2273 ifp = sc->ale_ifp; 2274 more = 0; 2275 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2276 more = ale_rxeof(sc, sc->ale_process_limit); 2277 if (more == EAGAIN) 2278 atomic_set_int(&sc->ale_morework, 1); 2279 else if (more == EIO) { 2280 ALE_LOCK(sc); 2281 sc->ale_stats.reset_brk_seq++; 2282 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2283 ale_init_locked(sc); 2284 ALE_UNLOCK(sc); 2285 return; 2286 } 2287 2288 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2289 if ((status & INTR_DMA_RD_TO_RST) != 0) 2290 device_printf(sc->ale_dev, 2291 "DMA read error! -- resetting\n"); 2292 if ((status & INTR_DMA_WR_TO_RST) != 0) 2293 device_printf(sc->ale_dev, 2294 "DMA write error! -- resetting\n"); 2295 ALE_LOCK(sc); 2296 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2297 ale_init_locked(sc); 2298 ALE_UNLOCK(sc); 2299 return; 2300 } 2301 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2302 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task); 2303 } 2304 2305 if (more == EAGAIN || 2306 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2307 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2308 return; 2309 } 2310 2311done: 2312 /* Re-enable interrupts. */ 2313 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2314} 2315 2316static void 2317ale_txeof(struct ale_softc *sc) 2318{ 2319 struct ifnet *ifp; 2320 struct ale_txdesc *txd; 2321 uint32_t cons, prod; 2322 int prog; 2323 2324 ALE_LOCK_ASSERT(sc); 2325 2326 ifp = sc->ale_ifp; 2327 2328 if (sc->ale_cdata.ale_tx_cnt == 0) 2329 return; 2330 2331 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2332 sc->ale_cdata.ale_tx_ring_map, 2333 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2334 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2335 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2336 sc->ale_cdata.ale_tx_cmb_map, 2337 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2338 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2339 } else 2340 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2341 cons = sc->ale_cdata.ale_tx_cons; 2342 /* 2343 * Go through our Tx list and free mbufs for those 2344 * frames which have been transmitted. 2345 */ 2346 for (prog = 0; cons != prod; prog++, 2347 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2348 if (sc->ale_cdata.ale_tx_cnt <= 0) 2349 break; 2350 prog++; 2351 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2352 sc->ale_cdata.ale_tx_cnt--; 2353 txd = &sc->ale_cdata.ale_txdesc[cons]; 2354 if (txd->tx_m != NULL) { 2355 /* Reclaim transmitted mbufs. */ 2356 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2357 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2358 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2359 txd->tx_dmamap); 2360 m_freem(txd->tx_m); 2361 txd->tx_m = NULL; 2362 } 2363 } 2364 2365 if (prog > 0) { 2366 sc->ale_cdata.ale_tx_cons = cons; 2367 /* 2368 * Unarm watchdog timer only when there is no pending 2369 * Tx descriptors in queue. 2370 */ 2371 if (sc->ale_cdata.ale_tx_cnt == 0) 2372 sc->ale_watchdog_timer = 0; 2373 } 2374} 2375 2376static void 2377ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2378 uint32_t length, uint32_t *prod) 2379{ 2380 struct ale_rx_page *rx_page; 2381 2382 rx_page = *page; 2383 /* Update consumer position. */ 2384 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2385 ALE_RX_PAGE_ALIGN); 2386 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2387 /* 2388 * End of Rx page reached, let hardware reuse 2389 * this page. 2390 */ 2391 rx_page->cons = 0; 2392 *rx_page->cmb_addr = 0; 2393 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2394 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2395 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2396 RXF_VALID); 2397 /* Switch to alternate Rx page. */ 2398 sc->ale_cdata.ale_rx_curp ^= 1; 2399 rx_page = *page = 2400 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2401 /* Page flipped, sync CMB and Rx page. */ 2402 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2403 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2404 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2405 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2406 /* Sync completed, cache updated producer index. */ 2407 *prod = *rx_page->cmb_addr; 2408 } 2409} 2410 2411 2412/* 2413 * It seems that AR81xx controller can compute partial checksum. 2414 * The partial checksum value can be used to accelerate checksum 2415 * computation for fragmented TCP/UDP packets. Upper network stack 2416 * already takes advantage of the partial checksum value in IP 2417 * reassembly stage. But I'm not sure the correctness of the 2418 * partial hardware checksum assistance due to lack of data sheet. 2419 * In addition, the Rx feature of controller that requires copying 2420 * for every frames effectively nullifies one of most nice offload 2421 * capability of controller. 2422 */ 2423static void 2424ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2425{ 2426 struct ifnet *ifp; 2427 struct ip *ip; 2428 char *p; 2429 2430 ifp = sc->ale_ifp; 2431 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2432 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2433 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2434 2435 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2436 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2437 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2438 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2439 m->m_pkthdr.csum_flags |= 2440 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2441 m->m_pkthdr.csum_data = 0xffff; 2442 } 2443 } else { 2444 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2445 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2446 p = mtod(m, char *); 2447 p += ETHER_HDR_LEN; 2448 if ((status & ALE_RD_802_3) != 0) 2449 p += LLC_SNAPFRAMELEN; 2450 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2451 (status & ALE_RD_VLAN) != 0) 2452 p += ETHER_VLAN_ENCAP_LEN; 2453 ip = (struct ip *)p; 2454 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2455 return; 2456 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2457 CSUM_PSEUDO_HDR; 2458 m->m_pkthdr.csum_data = 0xffff; 2459 } 2460 } 2461 /* 2462 * Don't mark bad checksum for TCP/UDP frames 2463 * as fragmented frames may always have set 2464 * bad checksummed bit of frame status. 2465 */ 2466} 2467 2468/* Process received frames. */ 2469static int 2470ale_rxeof(struct ale_softc *sc, int count) 2471{ 2472 struct ale_rx_page *rx_page; 2473 struct rx_rs *rs; 2474 struct ifnet *ifp; 2475 struct mbuf *m; 2476 uint32_t length, prod, seqno, status, vtags; 2477 int prog; 2478 2479 ifp = sc->ale_ifp; 2480 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2481 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2482 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2483 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2484 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2485 /* 2486 * Don't directly access producer index as hardware may 2487 * update it while Rx handler is in progress. It would 2488 * be even better if there is a way to let hardware 2489 * know how far driver processed its received frames. 2490 * Alternatively, hardware could provide a way to disable 2491 * CMB updates until driver acknowledges the end of CMB 2492 * access. 2493 */ 2494 prod = *rx_page->cmb_addr; 2495 for (prog = 0; prog < count; prog++) { 2496 if (rx_page->cons >= prod) 2497 break; 2498 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2499 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2500 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2501 /* 2502 * Normally I believe this should not happen unless 2503 * severe driver bug or corrupted memory. However 2504 * it seems to happen under certain conditions which 2505 * is triggered by abrupt Rx events such as initiation 2506 * of bulk transfer of remote host. It's not easy to 2507 * reproduce this and I doubt it could be related 2508 * with FIFO overflow of hardware or activity of Tx 2509 * CMB updates. I also remember similar behaviour 2510 * seen on RealTek 8139 which uses resembling Rx 2511 * scheme. 2512 */ 2513 if (bootverbose) 2514 device_printf(sc->ale_dev, 2515 "garbled seq: %u, expected: %u -- " 2516 "resetting!\n", seqno, 2517 sc->ale_cdata.ale_rx_seqno); 2518 return (EIO); 2519 } 2520 /* Frame received. */ 2521 sc->ale_cdata.ale_rx_seqno++; 2522 length = ALE_RX_BYTES(le32toh(rs->length)); 2523 status = le32toh(rs->flags); 2524 if ((status & ALE_RD_ERROR) != 0) { 2525 /* 2526 * We want to pass the following frames to upper 2527 * layer regardless of error status of Rx return 2528 * status. 2529 * 2530 * o IP/TCP/UDP checksum is bad. 2531 * o frame length and protocol specific length 2532 * does not match. 2533 */ 2534 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2535 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2536 ALE_RD_TRUNC)) != 0) { 2537 ale_rx_update_page(sc, &rx_page, length, &prod); 2538 continue; 2539 } 2540 } 2541 /* 2542 * m_devget(9) is major bottle-neck of ale(4)(It comes 2543 * from hardware limitation). For jumbo frames we could 2544 * get a slightly better performance if driver use 2545 * m_getjcl(9) with proper buffer size argument. However 2546 * that would make code more complicated and I don't 2547 * think users would expect good Rx performance numbers 2548 * on these low-end consumer ethernet controller. 2549 */ 2550 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2551 ETHER_ALIGN, ifp, NULL); 2552 if (m == NULL) { 2553 ifp->if_iqdrops++; 2554 ale_rx_update_page(sc, &rx_page, length, &prod); 2555 continue; 2556 } 2557 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2558 (status & ALE_RD_IPV4) != 0) 2559 ale_rxcsum(sc, m, status); 2560 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2561 (status & ALE_RD_VLAN) != 0) { 2562 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2563 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2564 m->m_flags |= M_VLANTAG; 2565 } 2566 2567 /* Pass it to upper layer. */ 2568 (*ifp->if_input)(ifp, m); 2569 2570 ale_rx_update_page(sc, &rx_page, length, &prod); 2571 } 2572 2573 return (count > 0 ? 0 : EAGAIN); 2574} 2575 2576static void 2577ale_tick(void *arg) 2578{ 2579 struct ale_softc *sc; 2580 struct mii_data *mii; 2581 2582 sc = (struct ale_softc *)arg; 2583 2584 ALE_LOCK_ASSERT(sc); 2585 2586 mii = device_get_softc(sc->ale_miibus); 2587 mii_tick(mii); 2588 ale_stats_update(sc); 2589 /* 2590 * Reclaim Tx buffers that have been transferred. It's not 2591 * needed here but it would release allocated mbuf chains 2592 * faster and limit the maximum delay to a hz. 2593 */ 2594 ale_txeof(sc); 2595 ale_watchdog(sc); 2596 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2597} 2598 2599static void 2600ale_reset(struct ale_softc *sc) 2601{ 2602 uint32_t reg; 2603 int i; 2604 2605 /* Initialize PCIe module. From Linux. */ 2606 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2607 2608 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2609 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2610 DELAY(10); 2611 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2612 break; 2613 } 2614 if (i == 0) 2615 device_printf(sc->ale_dev, "master reset timeout!\n"); 2616 2617 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2618 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2619 break; 2620 DELAY(10); 2621 } 2622 2623 if (i == 0) 2624 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2625} 2626 2627static void 2628ale_init(void *xsc) 2629{ 2630 struct ale_softc *sc; 2631 2632 sc = (struct ale_softc *)xsc; 2633 ALE_LOCK(sc); 2634 ale_init_locked(sc); 2635 ALE_UNLOCK(sc); 2636} 2637 2638static void 2639ale_init_locked(struct ale_softc *sc) 2640{ 2641 struct ifnet *ifp; 2642 struct mii_data *mii; 2643 uint8_t eaddr[ETHER_ADDR_LEN]; 2644 bus_addr_t paddr; 2645 uint32_t reg, rxf_hi, rxf_lo; 2646 2647 ALE_LOCK_ASSERT(sc); 2648 2649 ifp = sc->ale_ifp; 2650 mii = device_get_softc(sc->ale_miibus); 2651 2652 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2653 return; 2654 /* 2655 * Cancel any pending I/O. 2656 */ 2657 ale_stop(sc); 2658 /* 2659 * Reset the chip to a known state. 2660 */ 2661 ale_reset(sc); 2662 /* Initialize Tx descriptors, DMA memory blocks. */ 2663 ale_init_rx_pages(sc); 2664 ale_init_tx_ring(sc); 2665 2666 /* Reprogram the station address. */ 2667 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2668 CSR_WRITE_4(sc, ALE_PAR0, 2669 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2670 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2671 /* 2672 * Clear WOL status and disable all WOL feature as WOL 2673 * would interfere Rx operation under normal environments. 2674 */ 2675 CSR_READ_4(sc, ALE_WOL_CFG); 2676 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2677 /* 2678 * Set Tx descriptor/RXF0/CMB base addresses. They share 2679 * the same high address part of DMAable region. 2680 */ 2681 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2682 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2683 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2684 CSR_WRITE_4(sc, ALE_TPD_CNT, 2685 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2686 /* Set Rx page base address, note we use single queue. */ 2687 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2688 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2689 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2690 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2691 /* Set Tx/Rx CMB addresses. */ 2692 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2693 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2694 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2695 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2696 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2697 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2698 /* Mark RXF0 is valid. */ 2699 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2700 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2701 /* 2702 * No need to initialize RFX1/RXF2/RXF3. We don't use 2703 * multi-queue yet. 2704 */ 2705 2706 /* Set Rx page size, excluding guard frame size. */ 2707 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2708 /* Tell hardware that we're ready to load DMA blocks. */ 2709 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2710 2711 /* Set Rx/Tx interrupt trigger threshold. */ 2712 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2713 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2714 /* 2715 * XXX 2716 * Set interrupt trigger timer, its purpose and relation 2717 * with interrupt moderation mechanism is not clear yet. 2718 */ 2719 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2720 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2721 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2722 2723 /* Configure interrupt moderation timer. */ 2724 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2725 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2726 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2727 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2728 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2729 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2730 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2731 reg |= MASTER_IM_RX_TIMER_ENB; 2732 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2733 reg |= MASTER_IM_TX_TIMER_ENB; 2734 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2735 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2736 2737 /* Set Maximum frame size of controller. */ 2738 if (ifp->if_mtu < ETHERMTU) 2739 sc->ale_max_frame_size = ETHERMTU; 2740 else 2741 sc->ale_max_frame_size = ifp->if_mtu; 2742 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2743 ETHER_CRC_LEN; 2744 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2745 /* Configure IPG/IFG parameters. */ 2746 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2747 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2748 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2749 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2750 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2751 /* Set parameters for half-duplex media. */ 2752 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2753 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2754 HDPX_CFG_LCOL_MASK) | 2755 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2756 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2757 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2758 HDPX_CFG_ABEBT_MASK) | 2759 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2760 HDPX_CFG_JAMIPG_MASK)); 2761 2762 /* Configure Tx jumbo frame parameters. */ 2763 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2764 if (ifp->if_mtu < ETHERMTU) 2765 reg = sc->ale_max_frame_size; 2766 else if (ifp->if_mtu < 6 * 1024) 2767 reg = (sc->ale_max_frame_size * 2) / 3; 2768 else 2769 reg = sc->ale_max_frame_size / 2; 2770 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2771 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2772 TX_JUMBO_THRESH_UNIT_SHIFT); 2773 } 2774 /* Configure TxQ. */ 2775 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2776 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2777 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2778 TXQ_CFG_TPD_BURST_MASK; 2779 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2780 2781 /* Configure Rx jumbo frame & flow control parameters. */ 2782 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2783 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2784 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2785 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2786 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2787 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2788 RX_JUMBO_LKAH_MASK)); 2789 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2790 rxf_hi = (reg * 7) / 10; 2791 rxf_lo = (reg * 3)/ 10; 2792 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2793 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2794 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2795 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2796 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2797 } 2798 2799 /* Disable RSS. */ 2800 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2801 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2802 2803 /* Configure RxQ. */ 2804 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2805 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2806 2807 /* Configure DMA parameters. */ 2808 reg = 0; 2809 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2810 reg |= DMA_CFG_TXCMB_ENB; 2811 CSR_WRITE_4(sc, ALE_DMA_CFG, 2812 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2813 sc->ale_dma_rd_burst | reg | 2814 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2815 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2816 DMA_CFG_RD_DELAY_CNT_MASK) | 2817 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2818 DMA_CFG_WR_DELAY_CNT_MASK)); 2819 2820 /* 2821 * Hardware can be configured to issue SMB interrupt based 2822 * on programmed interval. Since there is a callout that is 2823 * invoked for every hz in driver we use that instead of 2824 * relying on periodic SMB interrupt. 2825 */ 2826 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2827 /* Clear MAC statistics. */ 2828 ale_stats_clear(sc); 2829 2830 /* 2831 * Configure Tx/Rx MACs. 2832 * - Auto-padding for short frames. 2833 * - Enable CRC generation. 2834 * Actual reconfiguration of MAC for resolved speed/duplex 2835 * is followed after detection of link establishment. 2836 * AR81xx always does checksum computation regardless of 2837 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2838 * cause Rx handling issue for fragmented IP datagrams due 2839 * to silicon bug. 2840 */ 2841 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2842 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2843 MAC_CFG_PREAMBLE_MASK); 2844 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2845 reg |= MAC_CFG_SPEED_10_100; 2846 else 2847 reg |= MAC_CFG_SPEED_1000; 2848 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2849 2850 /* Set up the receive filter. */ 2851 ale_rxfilter(sc); 2852 ale_rxvlan(sc); 2853 2854 /* Acknowledge all pending interrupts and clear it. */ 2855 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2856 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2857 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2858 2859 sc->ale_flags &= ~ALE_FLAG_LINK; 2860 /* Switch to the current media. */ 2861 mii_mediachg(mii); 2862 2863 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2864 2865 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2866 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2867} 2868 2869static void 2870ale_stop(struct ale_softc *sc) 2871{ 2872 struct ifnet *ifp; 2873 struct ale_txdesc *txd; 2874 uint32_t reg; 2875 int i; 2876 2877 ALE_LOCK_ASSERT(sc); 2878 /* 2879 * Mark the interface down and cancel the watchdog timer. 2880 */ 2881 ifp = sc->ale_ifp; 2882 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2883 sc->ale_flags &= ~ALE_FLAG_LINK; 2884 callout_stop(&sc->ale_tick_ch); 2885 sc->ale_watchdog_timer = 0; 2886 ale_stats_update(sc); 2887 /* Disable interrupts. */ 2888 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2889 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2890 /* Disable queue processing and DMA. */ 2891 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2892 reg &= ~TXQ_CFG_ENB; 2893 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2894 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2895 reg &= ~RXQ_CFG_ENB; 2896 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2897 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2898 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2899 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2900 DELAY(1000); 2901 /* Stop Rx/Tx MACs. */ 2902 ale_stop_mac(sc); 2903 /* Disable interrupts which might be touched in taskq handler. */ 2904 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2905 2906 /* 2907 * Free TX mbufs still in the queues. 2908 */ 2909 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2910 txd = &sc->ale_cdata.ale_txdesc[i]; 2911 if (txd->tx_m != NULL) { 2912 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2913 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2914 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2915 txd->tx_dmamap); 2916 m_freem(txd->tx_m); 2917 txd->tx_m = NULL; 2918 } 2919 } 2920} 2921 2922static void 2923ale_stop_mac(struct ale_softc *sc) 2924{ 2925 uint32_t reg; 2926 int i; 2927 2928 ALE_LOCK_ASSERT(sc); 2929 2930 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2931 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2932 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2933 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2934 } 2935 2936 for (i = ALE_TIMEOUT; i > 0; i--) { 2937 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2938 if (reg == 0) 2939 break; 2940 DELAY(10); 2941 } 2942 if (i == 0) 2943 device_printf(sc->ale_dev, 2944 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2945} 2946 2947static void 2948ale_init_tx_ring(struct ale_softc *sc) 2949{ 2950 struct ale_txdesc *txd; 2951 int i; 2952 2953 ALE_LOCK_ASSERT(sc); 2954 2955 sc->ale_cdata.ale_tx_prod = 0; 2956 sc->ale_cdata.ale_tx_cons = 0; 2957 sc->ale_cdata.ale_tx_cnt = 0; 2958 2959 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2960 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2961 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2962 txd = &sc->ale_cdata.ale_txdesc[i]; 2963 txd->tx_m = NULL; 2964 } 2965 *sc->ale_cdata.ale_tx_cmb = 0; 2966 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2967 sc->ale_cdata.ale_tx_cmb_map, 2968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2969 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2970 sc->ale_cdata.ale_tx_ring_map, 2971 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2972} 2973 2974static void 2975ale_init_rx_pages(struct ale_softc *sc) 2976{ 2977 struct ale_rx_page *rx_page; 2978 int i; 2979 2980 ALE_LOCK_ASSERT(sc); 2981 2982 atomic_set_int(&sc->ale_morework, 0); 2983 sc->ale_cdata.ale_rx_seqno = 0; 2984 sc->ale_cdata.ale_rx_curp = 0; 2985 2986 for (i = 0; i < ALE_RX_PAGES; i++) { 2987 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2988 bzero(rx_page->page_addr, sc->ale_pagesize); 2989 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2990 rx_page->cons = 0; 2991 *rx_page->cmb_addr = 0; 2992 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2994 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2995 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2996 } 2997} 2998 2999static void 3000ale_rxvlan(struct ale_softc *sc) 3001{ 3002 struct ifnet *ifp; 3003 uint32_t reg; 3004 3005 ALE_LOCK_ASSERT(sc); 3006 3007 ifp = sc->ale_ifp; 3008 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3009 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3010 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3011 reg |= MAC_CFG_VLAN_TAG_STRIP; 3012 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3013} 3014 3015static void 3016ale_rxfilter(struct ale_softc *sc) 3017{ 3018 struct ifnet *ifp; 3019 struct ifmultiaddr *ifma; 3020 uint32_t crc; 3021 uint32_t mchash[2]; 3022 uint32_t rxcfg; 3023 3024 ALE_LOCK_ASSERT(sc); 3025 3026 ifp = sc->ale_ifp; 3027 3028 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3029 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3030 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3031 rxcfg |= MAC_CFG_BCAST; 3032 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3033 if ((ifp->if_flags & IFF_PROMISC) != 0) 3034 rxcfg |= MAC_CFG_PROMISC; 3035 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3036 rxcfg |= MAC_CFG_ALLMULTI; 3037 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3038 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3039 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3040 return; 3041 } 3042 3043 /* Program new filter. */ 3044 bzero(mchash, sizeof(mchash)); 3045 3046 if_maddr_rlock(ifp); 3047 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3048 if (ifma->ifma_addr->sa_family != AF_LINK) 3049 continue; 3050 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3051 ifma->ifma_addr), ETHER_ADDR_LEN); 3052 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3053 } 3054 if_maddr_runlock(ifp); 3055 3056 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3057 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3058 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3059} 3060 3061static int 3062sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3063{ 3064 int error, value; 3065 3066 if (arg1 == NULL) 3067 return (EINVAL); 3068 value = *(int *)arg1; 3069 error = sysctl_handle_int(oidp, &value, 0, req); 3070 if (error || req->newptr == NULL) 3071 return (error); 3072 if (value < low || value > high) 3073 return (EINVAL); 3074 *(int *)arg1 = value; 3075 3076 return (0); 3077} 3078 3079static int 3080sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3081{ 3082 return (sysctl_int_range(oidp, arg1, arg2, req, 3083 ALE_PROC_MIN, ALE_PROC_MAX)); 3084} 3085 3086static int 3087sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3088{ 3089 3090 return (sysctl_int_range(oidp, arg1, arg2, req, 3091 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3092} 3093