1/*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/dev/alc/if_alc.c 314019 2017-02-21 03:27:59Z sephe $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/mbuf.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_llc.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58#include <net/if_vlan_var.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/ip.h> 63#include <netinet/tcp.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <machine/bus.h> 72#include <machine/in_cksum.h> 73 74#include <dev/alc/if_alcreg.h> 75#include <dev/alc/if_alcvar.h> 76 77/* "device miibus" required. See GENERIC if you get errors here. */ 78#include "miibus_if.h" 79#undef ALC_USE_CUSTOM_CSUM 80 81#ifdef ALC_USE_CUSTOM_CSUM 82#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83#else 84#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85#endif 86 87MODULE_DEPEND(alc, pci, 1, 1, 1); 88MODULE_DEPEND(alc, ether, 1, 1, 1); 89MODULE_DEPEND(alc, miibus, 1, 1, 1); 90 91/* Tunables. */ 92static int msi_disable = 0; 93static int msix_disable = 0; 94TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 96 97/* 98 * Devices supported by this driver. 99 */ 100static struct alc_ident alc_ident_table[] = { 101 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 102 "Atheros AR8131 PCIe Gigabit Ethernet" }, 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 104 "Atheros AR8132 PCIe Fast Ethernet" }, 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 106 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 108 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 110 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 112 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 114 "Atheros AR8161 PCIe Gigabit Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 116 "Atheros AR8162 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 118 "Atheros AR8171 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 120 "Atheros AR8172 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 122 "Killer E2200 Gigabit Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 124 "Killer E2400 Gigabit Ethernet" }, 125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 126 "Killer E2500 Gigabit Ethernet" }, 127 { 0, 0, 0, NULL} 128}; 129 130static void alc_aspm(struct alc_softc *, int, int); 131static void alc_aspm_813x(struct alc_softc *, int); 132static void alc_aspm_816x(struct alc_softc *, int); 133static int alc_attach(device_t); 134static int alc_check_boundary(struct alc_softc *); 135static void alc_config_msi(struct alc_softc *); 136static int alc_detach(device_t); 137static void alc_disable_l0s_l1(struct alc_softc *); 138static int alc_dma_alloc(struct alc_softc *); 139static void alc_dma_free(struct alc_softc *); 140static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 141static void alc_dsp_fixup(struct alc_softc *, int); 142static int alc_encap(struct alc_softc *, struct mbuf **); 143static struct alc_ident * 144 alc_find_ident(device_t); 145#ifndef __NO_STRICT_ALIGNMENT 146static struct mbuf * 147 alc_fixup_rx(struct ifnet *, struct mbuf *); 148#endif 149static void alc_get_macaddr(struct alc_softc *); 150static void alc_get_macaddr_813x(struct alc_softc *); 151static void alc_get_macaddr_816x(struct alc_softc *); 152static void alc_get_macaddr_par(struct alc_softc *); 153static void alc_init(void *); 154static void alc_init_cmb(struct alc_softc *); 155static void alc_init_locked(struct alc_softc *); 156static void alc_init_rr_ring(struct alc_softc *); 157static int alc_init_rx_ring(struct alc_softc *); 158static void alc_init_smb(struct alc_softc *); 159static void alc_init_tx_ring(struct alc_softc *); 160static void alc_int_task(void *, int); 161static int alc_intr(void *); 162static int alc_ioctl(struct ifnet *, u_long, caddr_t); 163static void alc_mac_config(struct alc_softc *); 164static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 165static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 166static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 167static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 168static int alc_miibus_readreg(device_t, int, int); 169static void alc_miibus_statchg(device_t); 170static int alc_miibus_writereg(device_t, int, int, int); 171static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 172static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 173static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 174static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 175static int alc_mediachange(struct ifnet *); 176static int alc_mediachange_locked(struct alc_softc *); 177static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 178static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 179static void alc_osc_reset(struct alc_softc *); 180static void alc_phy_down(struct alc_softc *); 181static void alc_phy_reset(struct alc_softc *); 182static void alc_phy_reset_813x(struct alc_softc *); 183static void alc_phy_reset_816x(struct alc_softc *); 184static int alc_probe(device_t); 185static void alc_reset(struct alc_softc *); 186static int alc_resume(device_t); 187static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 188static int alc_rxintr(struct alc_softc *, int); 189static void alc_rxfilter(struct alc_softc *); 190static void alc_rxvlan(struct alc_softc *); 191static void alc_setlinkspeed(struct alc_softc *); 192static void alc_setwol(struct alc_softc *); 193static void alc_setwol_813x(struct alc_softc *); 194static void alc_setwol_816x(struct alc_softc *); 195static int alc_shutdown(device_t); 196static void alc_start(struct ifnet *); 197static void alc_start_locked(struct ifnet *); 198static void alc_start_queue(struct alc_softc *); 199static void alc_stats_clear(struct alc_softc *); 200static void alc_stats_update(struct alc_softc *); 201static void alc_stop(struct alc_softc *); 202static void alc_stop_mac(struct alc_softc *); 203static void alc_stop_queue(struct alc_softc *); 204static int alc_suspend(device_t); 205static void alc_sysctl_node(struct alc_softc *); 206static void alc_tick(void *); 207static void alc_txeof(struct alc_softc *); 208static void alc_watchdog(struct alc_softc *); 209static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 210static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 211static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 212 213static device_method_t alc_methods[] = { 214 /* Device interface. */ 215 DEVMETHOD(device_probe, alc_probe), 216 DEVMETHOD(device_attach, alc_attach), 217 DEVMETHOD(device_detach, alc_detach), 218 DEVMETHOD(device_shutdown, alc_shutdown), 219 DEVMETHOD(device_suspend, alc_suspend), 220 DEVMETHOD(device_resume, alc_resume), 221 222 /* MII interface. */ 223 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 224 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 225 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 226 227 { NULL, NULL } 228}; 229 230static driver_t alc_driver = { 231 "alc", 232 alc_methods, 233 sizeof(struct alc_softc) 234}; 235 236static devclass_t alc_devclass; 237 238DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 239DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 240 241static struct resource_spec alc_res_spec_mem[] = { 242 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 243 { -1, 0, 0 } 244}; 245 246static struct resource_spec alc_irq_spec_legacy[] = { 247 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 248 { -1, 0, 0 } 249}; 250 251static struct resource_spec alc_irq_spec_msi[] = { 252 { SYS_RES_IRQ, 1, RF_ACTIVE }, 253 { -1, 0, 0 } 254}; 255 256static struct resource_spec alc_irq_spec_msix[] = { 257 { SYS_RES_IRQ, 1, RF_ACTIVE }, 258 { -1, 0, 0 } 259}; 260 261static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 262 263static int 264alc_miibus_readreg(device_t dev, int phy, int reg) 265{ 266 struct alc_softc *sc; 267 int v; 268 269 sc = device_get_softc(dev); 270 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 271 v = alc_mii_readreg_816x(sc, phy, reg); 272 else 273 v = alc_mii_readreg_813x(sc, phy, reg); 274 return (v); 275} 276 277static uint32_t 278alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 279{ 280 uint32_t v; 281 int i; 282 283 /* 284 * For AR8132 fast ethernet controller, do not report 1000baseT 285 * capability to mii(4). Even though AR8132 uses the same 286 * model/revision number of F1 gigabit PHY, the PHY has no 287 * ability to establish 1000baseT link. 288 */ 289 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 290 reg == MII_EXTSR) 291 return (0); 292 293 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 294 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 295 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 296 DELAY(5); 297 v = CSR_READ_4(sc, ALC_MDIO); 298 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 299 break; 300 } 301 302 if (i == 0) { 303 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 304 return (0); 305 } 306 307 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 308} 309 310static uint32_t 311alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 312{ 313 uint32_t clk, v; 314 int i; 315 316 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 317 clk = MDIO_CLK_25_128; 318 else 319 clk = MDIO_CLK_25_4; 320 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 321 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 322 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 323 DELAY(5); 324 v = CSR_READ_4(sc, ALC_MDIO); 325 if ((v & MDIO_OP_BUSY) == 0) 326 break; 327 } 328 329 if (i == 0) { 330 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 331 return (0); 332 } 333 334 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 335} 336 337static int 338alc_miibus_writereg(device_t dev, int phy, int reg, int val) 339{ 340 struct alc_softc *sc; 341 int v; 342 343 sc = device_get_softc(dev); 344 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 345 v = alc_mii_writereg_816x(sc, phy, reg, val); 346 else 347 v = alc_mii_writereg_813x(sc, phy, reg, val); 348 return (v); 349} 350 351static uint32_t 352alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 353{ 354 uint32_t v; 355 int i; 356 357 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 358 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 359 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 360 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 361 DELAY(5); 362 v = CSR_READ_4(sc, ALC_MDIO); 363 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 364 break; 365 } 366 367 if (i == 0) 368 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 369 370 return (0); 371} 372 373static uint32_t 374alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 375{ 376 uint32_t clk, v; 377 int i; 378 379 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 380 clk = MDIO_CLK_25_128; 381 else 382 clk = MDIO_CLK_25_4; 383 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 384 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 385 MDIO_SUP_PREAMBLE | clk); 386 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 387 DELAY(5); 388 v = CSR_READ_4(sc, ALC_MDIO); 389 if ((v & MDIO_OP_BUSY) == 0) 390 break; 391 } 392 393 if (i == 0) 394 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 395 396 return (0); 397} 398 399static void 400alc_miibus_statchg(device_t dev) 401{ 402 struct alc_softc *sc; 403 struct mii_data *mii; 404 struct ifnet *ifp; 405 uint32_t reg; 406 407 sc = device_get_softc(dev); 408 409 mii = device_get_softc(sc->alc_miibus); 410 ifp = sc->alc_ifp; 411 if (mii == NULL || ifp == NULL || 412 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 413 return; 414 415 sc->alc_flags &= ~ALC_FLAG_LINK; 416 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 417 (IFM_ACTIVE | IFM_AVALID)) { 418 switch (IFM_SUBTYPE(mii->mii_media_active)) { 419 case IFM_10_T: 420 case IFM_100_TX: 421 sc->alc_flags |= ALC_FLAG_LINK; 422 break; 423 case IFM_1000_T: 424 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 425 sc->alc_flags |= ALC_FLAG_LINK; 426 break; 427 default: 428 break; 429 } 430 } 431 /* Stop Rx/Tx MACs. */ 432 alc_stop_mac(sc); 433 434 /* Program MACs with resolved speed/duplex/flow-control. */ 435 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 436 alc_start_queue(sc); 437 alc_mac_config(sc); 438 /* Re-enable Tx/Rx MACs. */ 439 reg = CSR_READ_4(sc, ALC_MAC_CFG); 440 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 441 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 442 } 443 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 444 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 445} 446 447static uint32_t 448alc_miidbg_readreg(struct alc_softc *sc, int reg) 449{ 450 451 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 452 reg); 453 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 454 ALC_MII_DBG_DATA)); 455} 456 457static uint32_t 458alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 459{ 460 461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 462 reg); 463 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA, val)); 465} 466 467static uint32_t 468alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 469{ 470 uint32_t clk, v; 471 int i; 472 473 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 474 EXT_MDIO_DEVADDR(devaddr)); 475 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 476 clk = MDIO_CLK_25_128; 477 else 478 clk = MDIO_CLK_25_4; 479 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 480 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 481 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 482 DELAY(5); 483 v = CSR_READ_4(sc, ALC_MDIO); 484 if ((v & MDIO_OP_BUSY) == 0) 485 break; 486 } 487 488 if (i == 0) { 489 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 490 devaddr, reg); 491 return (0); 492 } 493 494 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 495} 496 497static uint32_t 498alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 499{ 500 uint32_t clk, v; 501 int i; 502 503 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 504 EXT_MDIO_DEVADDR(devaddr)); 505 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 506 clk = MDIO_CLK_25_128; 507 else 508 clk = MDIO_CLK_25_4; 509 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 510 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 511 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 512 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 513 DELAY(5); 514 v = CSR_READ_4(sc, ALC_MDIO); 515 if ((v & MDIO_OP_BUSY) == 0) 516 break; 517 } 518 519 if (i == 0) 520 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 521 devaddr, reg); 522 523 return (0); 524} 525 526static void 527alc_dsp_fixup(struct alc_softc *sc, int media) 528{ 529 uint16_t agc, len, val; 530 531 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 532 return; 533 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 534 return; 535 536 /* 537 * Vendor PHY magic. 538 * 1000BT/AZ, wrong cable length 539 */ 540 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 541 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 542 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 543 EXT_CLDCTL6_CAB_LEN_MASK; 544 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 545 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 546 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 547 agc > DBG_AGC_LONG1G_LIMT) || 548 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 549 agc > DBG_AGC_LONG1G_LIMT)) { 550 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 551 DBG_AZ_ANADECT_LONG); 552 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 553 MII_EXT_ANEG_AFE); 554 val |= ANEG_AFEE_10BT_100M_TH; 555 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 556 val); 557 } else { 558 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 559 DBG_AZ_ANADECT_DEFAULT); 560 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 561 MII_EXT_ANEG_AFE); 562 val &= ~ANEG_AFEE_10BT_100M_TH; 563 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 564 val); 565 } 566 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 567 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 568 if (media == IFM_1000_T) { 569 /* 570 * Giga link threshold, raise the tolerance of 571 * noise 50%. 572 */ 573 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 574 val &= ~DBG_MSE20DB_TH_MASK; 575 val |= (DBG_MSE20DB_TH_HI << 576 DBG_MSE20DB_TH_SHIFT); 577 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 578 } else if (media == IFM_100_TX) 579 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 580 DBG_MSE16DB_UP); 581 } 582 } else { 583 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 584 val &= ~ANEG_AFEE_10BT_100M_TH; 585 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 586 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 587 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 588 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 589 DBG_MSE16DB_DOWN); 590 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 591 val &= ~DBG_MSE20DB_TH_MASK; 592 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 593 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 594 } 595 } 596} 597 598static void 599alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 600{ 601 struct alc_softc *sc; 602 struct mii_data *mii; 603 604 sc = ifp->if_softc; 605 ALC_LOCK(sc); 606 if ((ifp->if_flags & IFF_UP) == 0) { 607 ALC_UNLOCK(sc); 608 return; 609 } 610 mii = device_get_softc(sc->alc_miibus); 611 612 mii_pollstat(mii); 613 ifmr->ifm_status = mii->mii_media_status; 614 ifmr->ifm_active = mii->mii_media_active; 615 ALC_UNLOCK(sc); 616} 617 618static int 619alc_mediachange(struct ifnet *ifp) 620{ 621 struct alc_softc *sc; 622 int error; 623 624 sc = ifp->if_softc; 625 ALC_LOCK(sc); 626 error = alc_mediachange_locked(sc); 627 ALC_UNLOCK(sc); 628 629 return (error); 630} 631 632static int 633alc_mediachange_locked(struct alc_softc *sc) 634{ 635 struct mii_data *mii; 636 struct mii_softc *miisc; 637 int error; 638 639 ALC_LOCK_ASSERT(sc); 640 641 mii = device_get_softc(sc->alc_miibus); 642 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 643 PHY_RESET(miisc); 644 error = mii_mediachg(mii); 645 646 return (error); 647} 648 649static struct alc_ident * 650alc_find_ident(device_t dev) 651{ 652 struct alc_ident *ident; 653 uint16_t vendor, devid; 654 655 vendor = pci_get_vendor(dev); 656 devid = pci_get_device(dev); 657 for (ident = alc_ident_table; ident->name != NULL; ident++) { 658 if (vendor == ident->vendorid && devid == ident->deviceid) 659 return (ident); 660 } 661 662 return (NULL); 663} 664 665static int 666alc_probe(device_t dev) 667{ 668 struct alc_ident *ident; 669 670 ident = alc_find_ident(dev); 671 if (ident != NULL) { 672 device_set_desc(dev, ident->name); 673 return (BUS_PROBE_DEFAULT); 674 } 675 676 return (ENXIO); 677} 678 679static void 680alc_get_macaddr(struct alc_softc *sc) 681{ 682 683 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 684 alc_get_macaddr_816x(sc); 685 else 686 alc_get_macaddr_813x(sc); 687} 688 689static void 690alc_get_macaddr_813x(struct alc_softc *sc) 691{ 692 uint32_t opt; 693 uint16_t val; 694 int eeprom, i; 695 696 eeprom = 0; 697 opt = CSR_READ_4(sc, ALC_OPT_CFG); 698 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 699 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 700 /* 701 * EEPROM found, let TWSI reload EEPROM configuration. 702 * This will set ethernet address of controller. 703 */ 704 eeprom++; 705 switch (sc->alc_ident->deviceid) { 706 case DEVICEID_ATHEROS_AR8131: 707 case DEVICEID_ATHEROS_AR8132: 708 if ((opt & OPT_CFG_CLK_ENB) == 0) { 709 opt |= OPT_CFG_CLK_ENB; 710 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 711 CSR_READ_4(sc, ALC_OPT_CFG); 712 DELAY(1000); 713 } 714 break; 715 case DEVICEID_ATHEROS_AR8151: 716 case DEVICEID_ATHEROS_AR8151_V2: 717 case DEVICEID_ATHEROS_AR8152_B: 718 case DEVICEID_ATHEROS_AR8152_B2: 719 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 720 ALC_MII_DBG_ADDR, 0x00); 721 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 722 ALC_MII_DBG_DATA); 723 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 724 ALC_MII_DBG_DATA, val & 0xFF7F); 725 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 726 ALC_MII_DBG_ADDR, 0x3B); 727 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 728 ALC_MII_DBG_DATA); 729 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 730 ALC_MII_DBG_DATA, val | 0x0008); 731 DELAY(20); 732 break; 733 } 734 735 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 736 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 737 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 738 CSR_READ_4(sc, ALC_WOL_CFG); 739 740 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 741 TWSI_CFG_SW_LD_START); 742 for (i = 100; i > 0; i--) { 743 DELAY(1000); 744 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 745 TWSI_CFG_SW_LD_START) == 0) 746 break; 747 } 748 if (i == 0) 749 device_printf(sc->alc_dev, 750 "reloading EEPROM timeout!\n"); 751 } else { 752 if (bootverbose) 753 device_printf(sc->alc_dev, "EEPROM not found!\n"); 754 } 755 if (eeprom != 0) { 756 switch (sc->alc_ident->deviceid) { 757 case DEVICEID_ATHEROS_AR8131: 758 case DEVICEID_ATHEROS_AR8132: 759 if ((opt & OPT_CFG_CLK_ENB) != 0) { 760 opt &= ~OPT_CFG_CLK_ENB; 761 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 762 CSR_READ_4(sc, ALC_OPT_CFG); 763 DELAY(1000); 764 } 765 break; 766 case DEVICEID_ATHEROS_AR8151: 767 case DEVICEID_ATHEROS_AR8151_V2: 768 case DEVICEID_ATHEROS_AR8152_B: 769 case DEVICEID_ATHEROS_AR8152_B2: 770 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 771 ALC_MII_DBG_ADDR, 0x00); 772 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 773 ALC_MII_DBG_DATA); 774 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 775 ALC_MII_DBG_DATA, val | 0x0080); 776 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 777 ALC_MII_DBG_ADDR, 0x3B); 778 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 779 ALC_MII_DBG_DATA); 780 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 781 ALC_MII_DBG_DATA, val & 0xFFF7); 782 DELAY(20); 783 break; 784 } 785 } 786 787 alc_get_macaddr_par(sc); 788} 789 790static void 791alc_get_macaddr_816x(struct alc_softc *sc) 792{ 793 uint32_t reg; 794 int i, reloaded; 795 796 reloaded = 0; 797 /* Try to reload station address via TWSI. */ 798 for (i = 100; i > 0; i--) { 799 reg = CSR_READ_4(sc, ALC_SLD); 800 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 801 break; 802 DELAY(1000); 803 } 804 if (i != 0) { 805 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 806 for (i = 100; i > 0; i--) { 807 DELAY(1000); 808 reg = CSR_READ_4(sc, ALC_SLD); 809 if ((reg & SLD_START) == 0) 810 break; 811 } 812 if (i != 0) 813 reloaded++; 814 else if (bootverbose) 815 device_printf(sc->alc_dev, 816 "reloading station address via TWSI timed out!\n"); 817 } 818 819 /* Try to reload station address from EEPROM or FLASH. */ 820 if (reloaded == 0) { 821 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 822 if ((reg & (EEPROM_LD_EEPROM_EXIST | 823 EEPROM_LD_FLASH_EXIST)) != 0) { 824 for (i = 100; i > 0; i--) { 825 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 826 if ((reg & (EEPROM_LD_PROGRESS | 827 EEPROM_LD_START)) == 0) 828 break; 829 DELAY(1000); 830 } 831 if (i != 0) { 832 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 833 EEPROM_LD_START); 834 for (i = 100; i > 0; i--) { 835 DELAY(1000); 836 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 837 if ((reg & EEPROM_LD_START) == 0) 838 break; 839 } 840 } else if (bootverbose) 841 device_printf(sc->alc_dev, 842 "reloading EEPROM/FLASH timed out!\n"); 843 } 844 } 845 846 alc_get_macaddr_par(sc); 847} 848 849static void 850alc_get_macaddr_par(struct alc_softc *sc) 851{ 852 uint32_t ea[2]; 853 854 ea[0] = CSR_READ_4(sc, ALC_PAR0); 855 ea[1] = CSR_READ_4(sc, ALC_PAR1); 856 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 857 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 858 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 859 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 860 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 861 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 862} 863 864static void 865alc_disable_l0s_l1(struct alc_softc *sc) 866{ 867 uint32_t pmcfg; 868 869 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 870 /* Another magic from vendor. */ 871 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 872 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 873 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 874 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 875 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 876 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 877 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 878 } 879} 880 881static void 882alc_phy_reset(struct alc_softc *sc) 883{ 884 885 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 886 alc_phy_reset_816x(sc); 887 else 888 alc_phy_reset_813x(sc); 889} 890 891static void 892alc_phy_reset_813x(struct alc_softc *sc) 893{ 894 uint16_t data; 895 896 /* Reset magic from Linux. */ 897 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 898 CSR_READ_2(sc, ALC_GPHY_CFG); 899 DELAY(10 * 1000); 900 901 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 902 GPHY_CFG_SEL_ANA_RESET); 903 CSR_READ_2(sc, ALC_GPHY_CFG); 904 DELAY(10 * 1000); 905 906 /* DSP fixup, Vendor magic. */ 907 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 908 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 909 ALC_MII_DBG_ADDR, 0x000A); 910 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 911 ALC_MII_DBG_DATA); 912 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 913 ALC_MII_DBG_DATA, data & 0xDFFF); 914 } 915 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 916 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 917 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 918 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 919 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 920 ALC_MII_DBG_ADDR, 0x003B); 921 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 922 ALC_MII_DBG_DATA); 923 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 924 ALC_MII_DBG_DATA, data & 0xFFF7); 925 DELAY(20 * 1000); 926 } 927 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 928 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 929 ALC_MII_DBG_ADDR, 0x0029); 930 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 931 ALC_MII_DBG_DATA, 0x929D); 932 } 933 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 934 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 935 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 936 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 937 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 938 ALC_MII_DBG_ADDR, 0x0029); 939 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 940 ALC_MII_DBG_DATA, 0xB6DD); 941 } 942 943 /* Load DSP codes, vendor magic. */ 944 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 945 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 946 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 947 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 948 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 949 ALC_MII_DBG_DATA, data); 950 951 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 952 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 953 ANA_SERDES_EN_LCKDT; 954 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 955 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 956 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 957 ALC_MII_DBG_DATA, data); 958 959 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 960 ANA_LONG_CABLE_TH_100_MASK) | 961 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 962 ANA_SHORT_CABLE_TH_100_SHIFT) | 963 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 964 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 965 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 966 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 967 ALC_MII_DBG_DATA, data); 968 969 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 970 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 971 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 972 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 974 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 975 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 976 ALC_MII_DBG_DATA, data); 977 978 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 979 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 980 ANA_OEN_125M; 981 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 982 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 983 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 984 ALC_MII_DBG_DATA, data); 985 DELAY(1000); 986 987 /* Disable hibernation. */ 988 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 989 0x0029); 990 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 991 ALC_MII_DBG_DATA); 992 data &= ~0x8000; 993 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 994 data); 995 996 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 997 0x000B); 998 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 999 ALC_MII_DBG_DATA); 1000 data &= ~0x8000; 1001 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1002 data); 1003} 1004 1005static void 1006alc_phy_reset_816x(struct alc_softc *sc) 1007{ 1008 uint32_t val; 1009 1010 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1011 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1012 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1013 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1014 val |= GPHY_CFG_SEL_ANA_RESET; 1015#ifdef notyet 1016 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1017#else 1018 /* Disable PHY hibernation. */ 1019 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1020#endif 1021 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1022 DELAY(10); 1023 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1024 DELAY(800); 1025 1026 /* Vendor PHY magic. */ 1027#ifdef notyet 1028 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1029 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1030 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1031 EXT_VDRVBIAS_DEFAULT); 1032#else 1033 /* Disable PHY hibernation. */ 1034 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1035 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1036 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1037 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1038 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1039#endif 1040 1041 /* XXX Disable EEE. */ 1042 val = CSR_READ_4(sc, ALC_LPI_CTL); 1043 val &= ~LPI_CTL_ENB; 1044 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1045 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1046 1047 /* PHY power saving. */ 1048 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1049 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1050 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1051 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1052 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1053 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1054 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1055 1056 /* RTL8139C, 120m issue. */ 1057 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1058 ANEG_NLP78_120M_DEFAULT); 1059 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1060 ANEG_S3DIG10_DEFAULT); 1061 1062 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1063 /* Turn off half amplitude. */ 1064 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1065 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1066 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1067 /* Turn off Green feature. */ 1068 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1069 val |= DBG_GREENCFG2_BP_GREEN; 1070 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1071 /* Turn off half bias. */ 1072 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1073 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1074 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1075 } 1076} 1077 1078static void 1079alc_phy_down(struct alc_softc *sc) 1080{ 1081 uint32_t gphy; 1082 1083 switch (sc->alc_ident->deviceid) { 1084 case DEVICEID_ATHEROS_AR8161: 1085 case DEVICEID_ATHEROS_E2200: 1086 case DEVICEID_ATHEROS_E2400: 1087 case DEVICEID_ATHEROS_E2500: 1088 case DEVICEID_ATHEROS_AR8162: 1089 case DEVICEID_ATHEROS_AR8171: 1090 case DEVICEID_ATHEROS_AR8172: 1091 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1092 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1093 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1094 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1095 GPHY_CFG_SEL_ANA_RESET; 1096 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1097 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1098 break; 1099 case DEVICEID_ATHEROS_AR8151: 1100 case DEVICEID_ATHEROS_AR8151_V2: 1101 case DEVICEID_ATHEROS_AR8152_B: 1102 case DEVICEID_ATHEROS_AR8152_B2: 1103 /* 1104 * GPHY power down caused more problems on AR8151 v2.0. 1105 * When driver is reloaded after GPHY power down, 1106 * accesses to PHY/MAC registers hung the system. Only 1107 * cold boot recovered from it. I'm not sure whether 1108 * AR8151 v1.0 also requires this one though. I don't 1109 * have AR8151 v1.0 controller in hand. 1110 * The only option left is to isolate the PHY and 1111 * initiates power down the PHY which in turn saves 1112 * more power when driver is unloaded. 1113 */ 1114 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1115 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1116 break; 1117 default: 1118 /* Force PHY down. */ 1119 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1120 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1121 GPHY_CFG_PWDOWN_HW); 1122 DELAY(1000); 1123 break; 1124 } 1125} 1126 1127static void 1128alc_aspm(struct alc_softc *sc, int init, int media) 1129{ 1130 1131 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1132 alc_aspm_816x(sc, init); 1133 else 1134 alc_aspm_813x(sc, media); 1135} 1136 1137static void 1138alc_aspm_813x(struct alc_softc *sc, int media) 1139{ 1140 uint32_t pmcfg; 1141 uint16_t linkcfg; 1142 1143 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1144 return; 1145 1146 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1147 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1148 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1149 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1150 PCIER_LINK_CTL); 1151 else 1152 linkcfg = 0; 1153 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1154 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1155 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1156 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1157 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1158 1159 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1160 /* Disable extended sync except AR8152 B v1.0 */ 1161 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1162 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1163 sc->alc_rev == ATHEROS_AR8152_B_V10) 1164 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1165 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1166 linkcfg); 1167 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1168 PM_CFG_HOTRST); 1169 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1170 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1171 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1172 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1173 PM_CFG_PM_REQ_TIMER_SHIFT); 1174 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1175 } 1176 1177 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1178 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1179 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1180 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1181 pmcfg |= PM_CFG_ASPM_L1_ENB; 1182 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1183 if (sc->alc_ident->deviceid == 1184 DEVICEID_ATHEROS_AR8152_B) 1185 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1186 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1187 PM_CFG_SERDES_PLL_L1_ENB | 1188 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1189 pmcfg |= PM_CFG_CLK_SWH_L1; 1190 if (media == IFM_100_TX || media == IFM_1000_T) { 1191 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1192 switch (sc->alc_ident->deviceid) { 1193 case DEVICEID_ATHEROS_AR8152_B: 1194 pmcfg |= (7 << 1195 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1196 break; 1197 case DEVICEID_ATHEROS_AR8152_B2: 1198 case DEVICEID_ATHEROS_AR8151_V2: 1199 pmcfg |= (4 << 1200 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1201 break; 1202 default: 1203 pmcfg |= (15 << 1204 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1205 break; 1206 } 1207 } 1208 } else { 1209 pmcfg |= PM_CFG_SERDES_L1_ENB | 1210 PM_CFG_SERDES_PLL_L1_ENB | 1211 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1212 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1213 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1214 } 1215 } else { 1216 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1217 PM_CFG_SERDES_PLL_L1_ENB); 1218 pmcfg |= PM_CFG_CLK_SWH_L1; 1219 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1220 pmcfg |= PM_CFG_ASPM_L1_ENB; 1221 } 1222 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1223} 1224 1225static void 1226alc_aspm_816x(struct alc_softc *sc, int init) 1227{ 1228 uint32_t pmcfg; 1229 1230 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1231 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1232 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1233 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1234 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1235 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1236 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1237 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1238 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1239 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1240 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1241 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1242 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1243 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1244 (sc->alc_rev & 0x01) != 0) 1245 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1246 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1247 /* Link up, enable both L0s, L1s. */ 1248 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1249 PM_CFG_MAC_ASPM_CHK; 1250 } else { 1251 if (init != 0) 1252 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1253 PM_CFG_MAC_ASPM_CHK; 1254 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1255 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1256 } 1257 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1258} 1259 1260static void 1261alc_init_pcie(struct alc_softc *sc) 1262{ 1263 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1264 uint32_t cap, ctl, val; 1265 int state; 1266 1267 /* Clear data link and flow-control protocol error. */ 1268 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1269 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1270 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1271 1272 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1273 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1274 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1275 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1276 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1277 PCIE_PHYMISC_FORCE_RCV_DET); 1278 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1279 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1280 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1281 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1282 PCIE_PHYMISC2_SERDES_TH_MASK); 1283 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1284 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1285 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1286 } 1287 /* Disable ASPM L0S and L1. */ 1288 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1289 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1290 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1291 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1292 sc->alc_rcb = DMA_CFG_RCB_128; 1293 if (bootverbose) 1294 device_printf(sc->alc_dev, "RCB %u bytes\n", 1295 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1296 state = ctl & PCIEM_LINK_CTL_ASPMC; 1297 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1298 sc->alc_flags |= ALC_FLAG_L0S; 1299 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1300 sc->alc_flags |= ALC_FLAG_L1S; 1301 if (bootverbose) 1302 device_printf(sc->alc_dev, "ASPM %s %s\n", 1303 aspm_state[state], 1304 state == 0 ? "disabled" : "enabled"); 1305 alc_disable_l0s_l1(sc); 1306 } else { 1307 if (bootverbose) 1308 device_printf(sc->alc_dev, 1309 "no ASPM support\n"); 1310 } 1311 } else { 1312 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1313 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1314 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1315 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1316 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1317 (sc->alc_rev & 0x01) != 0) { 1318 if ((val & MASTER_WAKEN_25M) == 0 || 1319 (val & MASTER_CLK_SEL_DIS) == 0) { 1320 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1321 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1322 } 1323 } else { 1324 if ((val & MASTER_WAKEN_25M) == 0 || 1325 (val & MASTER_CLK_SEL_DIS) != 0) { 1326 val |= MASTER_WAKEN_25M; 1327 val &= ~MASTER_CLK_SEL_DIS; 1328 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1329 } 1330 } 1331 } 1332 alc_aspm(sc, 1, IFM_UNKNOWN); 1333} 1334 1335static void 1336alc_config_msi(struct alc_softc *sc) 1337{ 1338 uint32_t ctl, mod; 1339 1340 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1341 /* 1342 * It seems interrupt moderation is controlled by 1343 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1344 * Driver uses RX interrupt moderation parameter to 1345 * program ALC_MSI_RETRANS_TIMER register. 1346 */ 1347 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1348 ctl &= ~MSI_RETRANS_TIMER_MASK; 1349 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1350 mod = ALC_USECS(sc->alc_int_rx_mod); 1351 if (mod == 0) 1352 mod = 1; 1353 ctl |= mod; 1354 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1355 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1356 MSI_RETRANS_MASK_SEL_STD); 1357 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1358 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1359 MSI_RETRANS_MASK_SEL_LINE); 1360 else 1361 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1362 } 1363} 1364 1365static int 1366alc_attach(device_t dev) 1367{ 1368 struct alc_softc *sc; 1369 struct ifnet *ifp; 1370 int base, error, i, msic, msixc; 1371 uint16_t burst; 1372 1373 error = 0; 1374 sc = device_get_softc(dev); 1375 sc->alc_dev = dev; 1376 sc->alc_rev = pci_get_revid(dev); 1377 1378 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1379 MTX_DEF); 1380 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1381 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1382 sc->alc_ident = alc_find_ident(dev); 1383 1384 /* Map the device. */ 1385 pci_enable_busmaster(dev); 1386 sc->alc_res_spec = alc_res_spec_mem; 1387 sc->alc_irq_spec = alc_irq_spec_legacy; 1388 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1389 if (error != 0) { 1390 device_printf(dev, "cannot allocate memory resources.\n"); 1391 goto fail; 1392 } 1393 1394 /* Set PHY address. */ 1395 sc->alc_phyaddr = ALC_PHY_ADDR; 1396 1397 /* 1398 * One odd thing is AR8132 uses the same PHY hardware(F1 1399 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1400 * the PHY supports 1000Mbps but that's not true. The PHY 1401 * used in AR8132 can't establish gigabit link even if it 1402 * shows the same PHY model/revision number of AR8131. 1403 */ 1404 switch (sc->alc_ident->deviceid) { 1405 case DEVICEID_ATHEROS_E2200: 1406 case DEVICEID_ATHEROS_E2400: 1407 case DEVICEID_ATHEROS_E2500: 1408 sc->alc_flags |= ALC_FLAG_E2X00; 1409 /* FALLTHROUGH */ 1410 case DEVICEID_ATHEROS_AR8161: 1411 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1412 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1413 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1414 /* FALLTHROUGH */ 1415 case DEVICEID_ATHEROS_AR8171: 1416 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1417 break; 1418 case DEVICEID_ATHEROS_AR8162: 1419 case DEVICEID_ATHEROS_AR8172: 1420 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1421 break; 1422 case DEVICEID_ATHEROS_AR8152_B: 1423 case DEVICEID_ATHEROS_AR8152_B2: 1424 sc->alc_flags |= ALC_FLAG_APS; 1425 /* FALLTHROUGH */ 1426 case DEVICEID_ATHEROS_AR8132: 1427 sc->alc_flags |= ALC_FLAG_FASTETHER; 1428 break; 1429 case DEVICEID_ATHEROS_AR8151: 1430 case DEVICEID_ATHEROS_AR8151_V2: 1431 sc->alc_flags |= ALC_FLAG_APS; 1432 /* FALLTHROUGH */ 1433 default: 1434 break; 1435 } 1436 sc->alc_flags |= ALC_FLAG_JUMBO; 1437 1438 /* 1439 * It seems that AR813x/AR815x has silicon bug for SMB. In 1440 * addition, Atheros said that enabling SMB wouldn't improve 1441 * performance. However I think it's bad to access lots of 1442 * registers to extract MAC statistics. 1443 */ 1444 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1445 /* 1446 * Don't use Tx CMB. It is known to have silicon bug. 1447 */ 1448 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1449 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1450 MASTER_CHIP_REV_SHIFT; 1451 if (bootverbose) { 1452 device_printf(dev, "PCI device revision : 0x%04x\n", 1453 sc->alc_rev); 1454 device_printf(dev, "Chip id/revision : 0x%04x\n", 1455 sc->alc_chip_rev); 1456 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1457 device_printf(dev, "AR816x revision : 0x%x\n", 1458 AR816X_REV(sc->alc_rev)); 1459 } 1460 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1461 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1462 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1463 1464 /* Initialize DMA parameters. */ 1465 sc->alc_dma_rd_burst = 0; 1466 sc->alc_dma_wr_burst = 0; 1467 sc->alc_rcb = DMA_CFG_RCB_64; 1468 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1469 sc->alc_flags |= ALC_FLAG_PCIE; 1470 sc->alc_expcap = base; 1471 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1472 sc->alc_dma_rd_burst = 1473 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1474 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1475 if (bootverbose) { 1476 device_printf(dev, "Read request size : %u bytes.\n", 1477 alc_dma_burst[sc->alc_dma_rd_burst]); 1478 device_printf(dev, "TLP payload size : %u bytes.\n", 1479 alc_dma_burst[sc->alc_dma_wr_burst]); 1480 } 1481 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1482 sc->alc_dma_rd_burst = 3; 1483 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1484 sc->alc_dma_wr_burst = 3; 1485 /* 1486 * Force maximum payload size to 128 bytes for 1487 * E2200/E2400/E2500. 1488 * Otherwise it triggers DMA write error. 1489 */ 1490 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1491 sc->alc_dma_wr_burst = 0; 1492 alc_init_pcie(sc); 1493 } 1494 1495 /* Reset PHY. */ 1496 alc_phy_reset(sc); 1497 1498 /* Reset the ethernet controller. */ 1499 alc_stop_mac(sc); 1500 alc_reset(sc); 1501 1502 /* Allocate IRQ resources. */ 1503 msixc = pci_msix_count(dev); 1504 msic = pci_msi_count(dev); 1505 if (bootverbose) { 1506 device_printf(dev, "MSIX count : %d\n", msixc); 1507 device_printf(dev, "MSI count : %d\n", msic); 1508 } 1509 if (msixc > 1) 1510 msixc = 1; 1511 if (msic > 1) 1512 msic = 1; 1513 /* 1514 * Prefer MSIX over MSI. 1515 * AR816x controller has a silicon bug that MSI interrupt 1516 * does not assert if PCIM_CMD_INTxDIS bit of command 1517 * register is set. pci(4) was taught to handle that case. 1518 */ 1519 if (msix_disable == 0 || msi_disable == 0) { 1520 if (msix_disable == 0 && msixc > 0 && 1521 pci_alloc_msix(dev, &msixc) == 0) { 1522 if (msic == 1) { 1523 device_printf(dev, 1524 "Using %d MSIX message(s).\n", msixc); 1525 sc->alc_flags |= ALC_FLAG_MSIX; 1526 sc->alc_irq_spec = alc_irq_spec_msix; 1527 } else 1528 pci_release_msi(dev); 1529 } 1530 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1531 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1532 if (msic == 1) { 1533 device_printf(dev, 1534 "Using %d MSI message(s).\n", msic); 1535 sc->alc_flags |= ALC_FLAG_MSI; 1536 sc->alc_irq_spec = alc_irq_spec_msi; 1537 } else 1538 pci_release_msi(dev); 1539 } 1540 } 1541 1542 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1543 if (error != 0) { 1544 device_printf(dev, "cannot allocate IRQ resources.\n"); 1545 goto fail; 1546 } 1547 1548 /* Create device sysctl node. */ 1549 alc_sysctl_node(sc); 1550 1551 if ((error = alc_dma_alloc(sc)) != 0) 1552 goto fail; 1553 1554 /* Load station address. */ 1555 alc_get_macaddr(sc); 1556 1557 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1558 if (ifp == NULL) { 1559 device_printf(dev, "cannot allocate ifnet structure.\n"); 1560 error = ENXIO; 1561 goto fail; 1562 } 1563 1564 ifp->if_softc = sc; 1565 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1566 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1567 ifp->if_ioctl = alc_ioctl; 1568 ifp->if_start = alc_start; 1569 ifp->if_init = alc_init; 1570 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1571 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1572 IFQ_SET_READY(&ifp->if_snd); 1573 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1574 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1575 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1576 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1577 sc->alc_flags |= ALC_FLAG_PM; 1578 sc->alc_pmcap = base; 1579 } 1580 ifp->if_capenable = ifp->if_capabilities; 1581 1582 /* Set up MII bus. */ 1583 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1584 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1585 MIIF_DOPAUSE); 1586 if (error != 0) { 1587 device_printf(dev, "attaching PHYs failed\n"); 1588 goto fail; 1589 } 1590 1591 ether_ifattach(ifp, sc->alc_eaddr); 1592 1593 /* VLAN capability setup. */ 1594 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1595 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1596 ifp->if_capenable = ifp->if_capabilities; 1597 /* 1598 * XXX 1599 * It seems enabling Tx checksum offloading makes more trouble. 1600 * Sometimes the controller does not receive any frames when 1601 * Tx checksum offloading is enabled. I'm not sure whether this 1602 * is a bug in Tx checksum offloading logic or I got broken 1603 * sample boards. To safety, don't enable Tx checksum offloading 1604 * by default but give chance to users to toggle it if they know 1605 * their controllers work without problems. 1606 * Fortunately, Tx checksum offloading for AR816x family 1607 * seems to work. 1608 */ 1609 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1610 ifp->if_capenable &= ~IFCAP_TXCSUM; 1611 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1612 } 1613 1614 /* Tell the upper layer(s) we support long frames. */ 1615 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1616 1617 /* Create local taskq. */ 1618 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1619 taskqueue_thread_enqueue, &sc->alc_tq); 1620 if (sc->alc_tq == NULL) { 1621 device_printf(dev, "could not create taskqueue.\n"); 1622 ether_ifdetach(ifp); 1623 error = ENXIO; 1624 goto fail; 1625 } 1626 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1627 device_get_nameunit(sc->alc_dev)); 1628 1629 alc_config_msi(sc); 1630 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1631 msic = ALC_MSIX_MESSAGES; 1632 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1633 msic = ALC_MSI_MESSAGES; 1634 else 1635 msic = 1; 1636 for (i = 0; i < msic; i++) { 1637 error = bus_setup_intr(dev, sc->alc_irq[i], 1638 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1639 &sc->alc_intrhand[i]); 1640 if (error != 0) 1641 break; 1642 } 1643 if (error != 0) { 1644 device_printf(dev, "could not set up interrupt handler.\n"); 1645 taskqueue_free(sc->alc_tq); 1646 sc->alc_tq = NULL; 1647 ether_ifdetach(ifp); 1648 goto fail; 1649 } 1650 1651fail: 1652 if (error != 0) 1653 alc_detach(dev); 1654 1655 return (error); 1656} 1657 1658static int 1659alc_detach(device_t dev) 1660{ 1661 struct alc_softc *sc; 1662 struct ifnet *ifp; 1663 int i, msic; 1664 1665 sc = device_get_softc(dev); 1666 1667 ifp = sc->alc_ifp; 1668 if (device_is_attached(dev)) { 1669 ether_ifdetach(ifp); 1670 ALC_LOCK(sc); 1671 alc_stop(sc); 1672 ALC_UNLOCK(sc); 1673 callout_drain(&sc->alc_tick_ch); 1674 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1675 } 1676 1677 if (sc->alc_tq != NULL) { 1678 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1679 taskqueue_free(sc->alc_tq); 1680 sc->alc_tq = NULL; 1681 } 1682 1683 if (sc->alc_miibus != NULL) { 1684 device_delete_child(dev, sc->alc_miibus); 1685 sc->alc_miibus = NULL; 1686 } 1687 bus_generic_detach(dev); 1688 alc_dma_free(sc); 1689 1690 if (ifp != NULL) { 1691 if_free(ifp); 1692 sc->alc_ifp = NULL; 1693 } 1694 1695 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1696 msic = ALC_MSIX_MESSAGES; 1697 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1698 msic = ALC_MSI_MESSAGES; 1699 else 1700 msic = 1; 1701 for (i = 0; i < msic; i++) { 1702 if (sc->alc_intrhand[i] != NULL) { 1703 bus_teardown_intr(dev, sc->alc_irq[i], 1704 sc->alc_intrhand[i]); 1705 sc->alc_intrhand[i] = NULL; 1706 } 1707 } 1708 if (sc->alc_res[0] != NULL) 1709 alc_phy_down(sc); 1710 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1711 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1712 pci_release_msi(dev); 1713 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1714 mtx_destroy(&sc->alc_mtx); 1715 1716 return (0); 1717} 1718 1719#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1720 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1721#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1722 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1723 1724static void 1725alc_sysctl_node(struct alc_softc *sc) 1726{ 1727 struct sysctl_ctx_list *ctx; 1728 struct sysctl_oid_list *child, *parent; 1729 struct sysctl_oid *tree; 1730 struct alc_hw_stats *stats; 1731 int error; 1732 1733 stats = &sc->alc_stats; 1734 ctx = device_get_sysctl_ctx(sc->alc_dev); 1735 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1736 1737 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1738 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1739 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1740 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1741 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1742 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1743 /* Pull in device tunables. */ 1744 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1745 error = resource_int_value(device_get_name(sc->alc_dev), 1746 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1747 if (error == 0) { 1748 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1749 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1750 device_printf(sc->alc_dev, "int_rx_mod value out of " 1751 "range; using default: %d\n", 1752 ALC_IM_RX_TIMER_DEFAULT); 1753 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1754 } 1755 } 1756 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1757 error = resource_int_value(device_get_name(sc->alc_dev), 1758 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1759 if (error == 0) { 1760 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1761 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1762 device_printf(sc->alc_dev, "int_tx_mod value out of " 1763 "range; using default: %d\n", 1764 ALC_IM_TX_TIMER_DEFAULT); 1765 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1766 } 1767 } 1768 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1769 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1770 sysctl_hw_alc_proc_limit, "I", 1771 "max number of Rx events to process"); 1772 /* Pull in device tunables. */ 1773 sc->alc_process_limit = ALC_PROC_DEFAULT; 1774 error = resource_int_value(device_get_name(sc->alc_dev), 1775 device_get_unit(sc->alc_dev), "process_limit", 1776 &sc->alc_process_limit); 1777 if (error == 0) { 1778 if (sc->alc_process_limit < ALC_PROC_MIN || 1779 sc->alc_process_limit > ALC_PROC_MAX) { 1780 device_printf(sc->alc_dev, 1781 "process_limit value out of range; " 1782 "using default: %d\n", ALC_PROC_DEFAULT); 1783 sc->alc_process_limit = ALC_PROC_DEFAULT; 1784 } 1785 } 1786 1787 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1788 NULL, "ALC statistics"); 1789 parent = SYSCTL_CHILDREN(tree); 1790 1791 /* Rx statistics. */ 1792 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1793 NULL, "Rx MAC statistics"); 1794 child = SYSCTL_CHILDREN(tree); 1795 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1796 &stats->rx_frames, "Good frames"); 1797 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1798 &stats->rx_bcast_frames, "Good broadcast frames"); 1799 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1800 &stats->rx_mcast_frames, "Good multicast frames"); 1801 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1802 &stats->rx_pause_frames, "Pause control frames"); 1803 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1804 &stats->rx_control_frames, "Control frames"); 1805 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1806 &stats->rx_crcerrs, "CRC errors"); 1807 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1808 &stats->rx_lenerrs, "Frames with length mismatched"); 1809 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1810 &stats->rx_bytes, "Good octets"); 1811 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1812 &stats->rx_bcast_bytes, "Good broadcast octets"); 1813 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1814 &stats->rx_mcast_bytes, "Good multicast octets"); 1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1816 &stats->rx_runts, "Too short frames"); 1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1818 &stats->rx_fragments, "Fragmented frames"); 1819 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1820 &stats->rx_pkts_64, "64 bytes frames"); 1821 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1822 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1823 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1824 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1825 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1826 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1827 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1828 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1830 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1832 &stats->rx_pkts_1519_max, "1519 to max frames"); 1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1834 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1836 &stats->rx_fifo_oflows, "FIFO overflows"); 1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1838 &stats->rx_rrs_errs, "Return status write-back errors"); 1839 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1840 &stats->rx_alignerrs, "Alignment errors"); 1841 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1842 &stats->rx_pkts_filtered, 1843 "Frames dropped due to address filtering"); 1844 1845 /* Tx statistics. */ 1846 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1847 NULL, "Tx MAC statistics"); 1848 child = SYSCTL_CHILDREN(tree); 1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1850 &stats->tx_frames, "Good frames"); 1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1852 &stats->tx_bcast_frames, "Good broadcast frames"); 1853 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1854 &stats->tx_mcast_frames, "Good multicast frames"); 1855 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1856 &stats->tx_pause_frames, "Pause control frames"); 1857 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1858 &stats->tx_control_frames, "Control frames"); 1859 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1860 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1861 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1862 &stats->tx_excess_defer, "Frames with derferrals"); 1863 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1864 &stats->tx_bytes, "Good octets"); 1865 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1866 &stats->tx_bcast_bytes, "Good broadcast octets"); 1867 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1868 &stats->tx_mcast_bytes, "Good multicast octets"); 1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1870 &stats->tx_pkts_64, "64 bytes frames"); 1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1872 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1873 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1874 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1875 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1876 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1877 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1878 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1879 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1880 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1881 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1882 &stats->tx_pkts_1519_max, "1519 to max frames"); 1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1884 &stats->tx_single_colls, "Single collisions"); 1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1886 &stats->tx_multi_colls, "Multiple collisions"); 1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1888 &stats->tx_late_colls, "Late collisions"); 1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1890 &stats->tx_excess_colls, "Excessive collisions"); 1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1892 &stats->tx_underrun, "FIFO underruns"); 1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1894 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1895 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1896 &stats->tx_lenerrs, "Frames with length mismatched"); 1897 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1898 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1899} 1900 1901#undef ALC_SYSCTL_STAT_ADD32 1902#undef ALC_SYSCTL_STAT_ADD64 1903 1904struct alc_dmamap_arg { 1905 bus_addr_t alc_busaddr; 1906}; 1907 1908static void 1909alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1910{ 1911 struct alc_dmamap_arg *ctx; 1912 1913 if (error != 0) 1914 return; 1915 1916 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1917 1918 ctx = (struct alc_dmamap_arg *)arg; 1919 ctx->alc_busaddr = segs[0].ds_addr; 1920} 1921 1922/* 1923 * Normal and high Tx descriptors shares single Tx high address. 1924 * Four Rx descriptor/return rings and CMB shares the same Rx 1925 * high address. 1926 */ 1927static int 1928alc_check_boundary(struct alc_softc *sc) 1929{ 1930 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1931 1932 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1933 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1934 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1935 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1936 1937 /* 4GB boundary crossing is not allowed. */ 1938 if ((ALC_ADDR_HI(rx_ring_end) != 1939 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1940 (ALC_ADDR_HI(rr_ring_end) != 1941 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1942 (ALC_ADDR_HI(cmb_end) != 1943 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1944 (ALC_ADDR_HI(tx_ring_end) != 1945 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1946 return (EFBIG); 1947 /* 1948 * Make sure Rx return descriptor/Rx descriptor/CMB use 1949 * the same high address. 1950 */ 1951 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1952 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1953 return (EFBIG); 1954 1955 return (0); 1956} 1957 1958static int 1959alc_dma_alloc(struct alc_softc *sc) 1960{ 1961 struct alc_txdesc *txd; 1962 struct alc_rxdesc *rxd; 1963 bus_addr_t lowaddr; 1964 struct alc_dmamap_arg ctx; 1965 int error, i; 1966 1967 lowaddr = BUS_SPACE_MAXADDR; 1968again: 1969 /* Create parent DMA tag. */ 1970 error = bus_dma_tag_create( 1971 bus_get_dma_tag(sc->alc_dev), /* parent */ 1972 1, 0, /* alignment, boundary */ 1973 lowaddr, /* lowaddr */ 1974 BUS_SPACE_MAXADDR, /* highaddr */ 1975 NULL, NULL, /* filter, filterarg */ 1976 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1977 0, /* nsegments */ 1978 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1979 0, /* flags */ 1980 NULL, NULL, /* lockfunc, lockarg */ 1981 &sc->alc_cdata.alc_parent_tag); 1982 if (error != 0) { 1983 device_printf(sc->alc_dev, 1984 "could not create parent DMA tag.\n"); 1985 goto fail; 1986 } 1987 1988 /* Create DMA tag for Tx descriptor ring. */ 1989 error = bus_dma_tag_create( 1990 sc->alc_cdata.alc_parent_tag, /* parent */ 1991 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1992 BUS_SPACE_MAXADDR, /* lowaddr */ 1993 BUS_SPACE_MAXADDR, /* highaddr */ 1994 NULL, NULL, /* filter, filterarg */ 1995 ALC_TX_RING_SZ, /* maxsize */ 1996 1, /* nsegments */ 1997 ALC_TX_RING_SZ, /* maxsegsize */ 1998 0, /* flags */ 1999 NULL, NULL, /* lockfunc, lockarg */ 2000 &sc->alc_cdata.alc_tx_ring_tag); 2001 if (error != 0) { 2002 device_printf(sc->alc_dev, 2003 "could not create Tx ring DMA tag.\n"); 2004 goto fail; 2005 } 2006 2007 /* Create DMA tag for Rx free descriptor ring. */ 2008 error = bus_dma_tag_create( 2009 sc->alc_cdata.alc_parent_tag, /* parent */ 2010 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2011 BUS_SPACE_MAXADDR, /* lowaddr */ 2012 BUS_SPACE_MAXADDR, /* highaddr */ 2013 NULL, NULL, /* filter, filterarg */ 2014 ALC_RX_RING_SZ, /* maxsize */ 2015 1, /* nsegments */ 2016 ALC_RX_RING_SZ, /* maxsegsize */ 2017 0, /* flags */ 2018 NULL, NULL, /* lockfunc, lockarg */ 2019 &sc->alc_cdata.alc_rx_ring_tag); 2020 if (error != 0) { 2021 device_printf(sc->alc_dev, 2022 "could not create Rx ring DMA tag.\n"); 2023 goto fail; 2024 } 2025 /* Create DMA tag for Rx return descriptor ring. */ 2026 error = bus_dma_tag_create( 2027 sc->alc_cdata.alc_parent_tag, /* parent */ 2028 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2029 BUS_SPACE_MAXADDR, /* lowaddr */ 2030 BUS_SPACE_MAXADDR, /* highaddr */ 2031 NULL, NULL, /* filter, filterarg */ 2032 ALC_RR_RING_SZ, /* maxsize */ 2033 1, /* nsegments */ 2034 ALC_RR_RING_SZ, /* maxsegsize */ 2035 0, /* flags */ 2036 NULL, NULL, /* lockfunc, lockarg */ 2037 &sc->alc_cdata.alc_rr_ring_tag); 2038 if (error != 0) { 2039 device_printf(sc->alc_dev, 2040 "could not create Rx return ring DMA tag.\n"); 2041 goto fail; 2042 } 2043 2044 /* Create DMA tag for coalescing message block. */ 2045 error = bus_dma_tag_create( 2046 sc->alc_cdata.alc_parent_tag, /* parent */ 2047 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2048 BUS_SPACE_MAXADDR, /* lowaddr */ 2049 BUS_SPACE_MAXADDR, /* highaddr */ 2050 NULL, NULL, /* filter, filterarg */ 2051 ALC_CMB_SZ, /* maxsize */ 2052 1, /* nsegments */ 2053 ALC_CMB_SZ, /* maxsegsize */ 2054 0, /* flags */ 2055 NULL, NULL, /* lockfunc, lockarg */ 2056 &sc->alc_cdata.alc_cmb_tag); 2057 if (error != 0) { 2058 device_printf(sc->alc_dev, 2059 "could not create CMB DMA tag.\n"); 2060 goto fail; 2061 } 2062 /* Create DMA tag for status message block. */ 2063 error = bus_dma_tag_create( 2064 sc->alc_cdata.alc_parent_tag, /* parent */ 2065 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2066 BUS_SPACE_MAXADDR, /* lowaddr */ 2067 BUS_SPACE_MAXADDR, /* highaddr */ 2068 NULL, NULL, /* filter, filterarg */ 2069 ALC_SMB_SZ, /* maxsize */ 2070 1, /* nsegments */ 2071 ALC_SMB_SZ, /* maxsegsize */ 2072 0, /* flags */ 2073 NULL, NULL, /* lockfunc, lockarg */ 2074 &sc->alc_cdata.alc_smb_tag); 2075 if (error != 0) { 2076 device_printf(sc->alc_dev, 2077 "could not create SMB DMA tag.\n"); 2078 goto fail; 2079 } 2080 2081 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2082 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2083 (void **)&sc->alc_rdata.alc_tx_ring, 2084 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2085 &sc->alc_cdata.alc_tx_ring_map); 2086 if (error != 0) { 2087 device_printf(sc->alc_dev, 2088 "could not allocate DMA'able memory for Tx ring.\n"); 2089 goto fail; 2090 } 2091 ctx.alc_busaddr = 0; 2092 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2093 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2094 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2095 if (error != 0 || ctx.alc_busaddr == 0) { 2096 device_printf(sc->alc_dev, 2097 "could not load DMA'able memory for Tx ring.\n"); 2098 goto fail; 2099 } 2100 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2101 2102 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2103 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2104 (void **)&sc->alc_rdata.alc_rx_ring, 2105 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2106 &sc->alc_cdata.alc_rx_ring_map); 2107 if (error != 0) { 2108 device_printf(sc->alc_dev, 2109 "could not allocate DMA'able memory for Rx ring.\n"); 2110 goto fail; 2111 } 2112 ctx.alc_busaddr = 0; 2113 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2114 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2115 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2116 if (error != 0 || ctx.alc_busaddr == 0) { 2117 device_printf(sc->alc_dev, 2118 "could not load DMA'able memory for Rx ring.\n"); 2119 goto fail; 2120 } 2121 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2122 2123 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2124 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2125 (void **)&sc->alc_rdata.alc_rr_ring, 2126 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2127 &sc->alc_cdata.alc_rr_ring_map); 2128 if (error != 0) { 2129 device_printf(sc->alc_dev, 2130 "could not allocate DMA'able memory for Rx return ring.\n"); 2131 goto fail; 2132 } 2133 ctx.alc_busaddr = 0; 2134 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2135 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2136 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2137 if (error != 0 || ctx.alc_busaddr == 0) { 2138 device_printf(sc->alc_dev, 2139 "could not load DMA'able memory for Tx ring.\n"); 2140 goto fail; 2141 } 2142 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2143 2144 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2145 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2146 (void **)&sc->alc_rdata.alc_cmb, 2147 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2148 &sc->alc_cdata.alc_cmb_map); 2149 if (error != 0) { 2150 device_printf(sc->alc_dev, 2151 "could not allocate DMA'able memory for CMB.\n"); 2152 goto fail; 2153 } 2154 ctx.alc_busaddr = 0; 2155 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2156 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2157 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2158 if (error != 0 || ctx.alc_busaddr == 0) { 2159 device_printf(sc->alc_dev, 2160 "could not load DMA'able memory for CMB.\n"); 2161 goto fail; 2162 } 2163 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2164 2165 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2166 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2167 (void **)&sc->alc_rdata.alc_smb, 2168 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2169 &sc->alc_cdata.alc_smb_map); 2170 if (error != 0) { 2171 device_printf(sc->alc_dev, 2172 "could not allocate DMA'able memory for SMB.\n"); 2173 goto fail; 2174 } 2175 ctx.alc_busaddr = 0; 2176 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2177 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2178 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2179 if (error != 0 || ctx.alc_busaddr == 0) { 2180 device_printf(sc->alc_dev, 2181 "could not load DMA'able memory for CMB.\n"); 2182 goto fail; 2183 } 2184 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2185 2186 /* Make sure we've not crossed 4GB boundary. */ 2187 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2188 (error = alc_check_boundary(sc)) != 0) { 2189 device_printf(sc->alc_dev, "4GB boundary crossed, " 2190 "switching to 32bit DMA addressing mode.\n"); 2191 alc_dma_free(sc); 2192 /* 2193 * Limit max allowable DMA address space to 32bit 2194 * and try again. 2195 */ 2196 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2197 goto again; 2198 } 2199 2200 /* 2201 * Create Tx buffer parent tag. 2202 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2203 * so it needs separate parent DMA tag as parent DMA address 2204 * space could be restricted to be within 32bit address space 2205 * by 4GB boundary crossing. 2206 */ 2207 error = bus_dma_tag_create( 2208 bus_get_dma_tag(sc->alc_dev), /* parent */ 2209 1, 0, /* alignment, boundary */ 2210 BUS_SPACE_MAXADDR, /* lowaddr */ 2211 BUS_SPACE_MAXADDR, /* highaddr */ 2212 NULL, NULL, /* filter, filterarg */ 2213 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2214 0, /* nsegments */ 2215 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2216 0, /* flags */ 2217 NULL, NULL, /* lockfunc, lockarg */ 2218 &sc->alc_cdata.alc_buffer_tag); 2219 if (error != 0) { 2220 device_printf(sc->alc_dev, 2221 "could not create parent buffer DMA tag.\n"); 2222 goto fail; 2223 } 2224 2225 /* Create DMA tag for Tx buffers. */ 2226 error = bus_dma_tag_create( 2227 sc->alc_cdata.alc_buffer_tag, /* parent */ 2228 1, 0, /* alignment, boundary */ 2229 BUS_SPACE_MAXADDR, /* lowaddr */ 2230 BUS_SPACE_MAXADDR, /* highaddr */ 2231 NULL, NULL, /* filter, filterarg */ 2232 ALC_TSO_MAXSIZE, /* maxsize */ 2233 ALC_MAXTXSEGS, /* nsegments */ 2234 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2235 0, /* flags */ 2236 NULL, NULL, /* lockfunc, lockarg */ 2237 &sc->alc_cdata.alc_tx_tag); 2238 if (error != 0) { 2239 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2240 goto fail; 2241 } 2242 2243 /* Create DMA tag for Rx buffers. */ 2244 error = bus_dma_tag_create( 2245 sc->alc_cdata.alc_buffer_tag, /* parent */ 2246 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2247 BUS_SPACE_MAXADDR, /* lowaddr */ 2248 BUS_SPACE_MAXADDR, /* highaddr */ 2249 NULL, NULL, /* filter, filterarg */ 2250 MCLBYTES, /* maxsize */ 2251 1, /* nsegments */ 2252 MCLBYTES, /* maxsegsize */ 2253 0, /* flags */ 2254 NULL, NULL, /* lockfunc, lockarg */ 2255 &sc->alc_cdata.alc_rx_tag); 2256 if (error != 0) { 2257 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2258 goto fail; 2259 } 2260 /* Create DMA maps for Tx buffers. */ 2261 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2262 txd = &sc->alc_cdata.alc_txdesc[i]; 2263 txd->tx_m = NULL; 2264 txd->tx_dmamap = NULL; 2265 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2266 &txd->tx_dmamap); 2267 if (error != 0) { 2268 device_printf(sc->alc_dev, 2269 "could not create Tx dmamap.\n"); 2270 goto fail; 2271 } 2272 } 2273 /* Create DMA maps for Rx buffers. */ 2274 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2275 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2276 device_printf(sc->alc_dev, 2277 "could not create spare Rx dmamap.\n"); 2278 goto fail; 2279 } 2280 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2281 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2282 rxd->rx_m = NULL; 2283 rxd->rx_dmamap = NULL; 2284 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2285 &rxd->rx_dmamap); 2286 if (error != 0) { 2287 device_printf(sc->alc_dev, 2288 "could not create Rx dmamap.\n"); 2289 goto fail; 2290 } 2291 } 2292 2293fail: 2294 return (error); 2295} 2296 2297static void 2298alc_dma_free(struct alc_softc *sc) 2299{ 2300 struct alc_txdesc *txd; 2301 struct alc_rxdesc *rxd; 2302 int i; 2303 2304 /* Tx buffers. */ 2305 if (sc->alc_cdata.alc_tx_tag != NULL) { 2306 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2307 txd = &sc->alc_cdata.alc_txdesc[i]; 2308 if (txd->tx_dmamap != NULL) { 2309 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2310 txd->tx_dmamap); 2311 txd->tx_dmamap = NULL; 2312 } 2313 } 2314 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2315 sc->alc_cdata.alc_tx_tag = NULL; 2316 } 2317 /* Rx buffers */ 2318 if (sc->alc_cdata.alc_rx_tag != NULL) { 2319 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2320 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2321 if (rxd->rx_dmamap != NULL) { 2322 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2323 rxd->rx_dmamap); 2324 rxd->rx_dmamap = NULL; 2325 } 2326 } 2327 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2328 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2329 sc->alc_cdata.alc_rx_sparemap); 2330 sc->alc_cdata.alc_rx_sparemap = NULL; 2331 } 2332 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2333 sc->alc_cdata.alc_rx_tag = NULL; 2334 } 2335 /* Tx descriptor ring. */ 2336 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2337 if (sc->alc_cdata.alc_tx_ring_map != NULL) 2338 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2339 sc->alc_cdata.alc_tx_ring_map); 2340 if (sc->alc_cdata.alc_tx_ring_map != NULL && 2341 sc->alc_rdata.alc_tx_ring != NULL) 2342 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2343 sc->alc_rdata.alc_tx_ring, 2344 sc->alc_cdata.alc_tx_ring_map); 2345 sc->alc_rdata.alc_tx_ring = NULL; 2346 sc->alc_cdata.alc_tx_ring_map = NULL; 2347 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2348 sc->alc_cdata.alc_tx_ring_tag = NULL; 2349 } 2350 /* Rx ring. */ 2351 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2352 if (sc->alc_cdata.alc_rx_ring_map != NULL) 2353 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2354 sc->alc_cdata.alc_rx_ring_map); 2355 if (sc->alc_cdata.alc_rx_ring_map != NULL && 2356 sc->alc_rdata.alc_rx_ring != NULL) 2357 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2358 sc->alc_rdata.alc_rx_ring, 2359 sc->alc_cdata.alc_rx_ring_map); 2360 sc->alc_rdata.alc_rx_ring = NULL; 2361 sc->alc_cdata.alc_rx_ring_map = NULL; 2362 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2363 sc->alc_cdata.alc_rx_ring_tag = NULL; 2364 } 2365 /* Rx return ring. */ 2366 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2367 if (sc->alc_cdata.alc_rr_ring_map != NULL) 2368 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2369 sc->alc_cdata.alc_rr_ring_map); 2370 if (sc->alc_cdata.alc_rr_ring_map != NULL && 2371 sc->alc_rdata.alc_rr_ring != NULL) 2372 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2373 sc->alc_rdata.alc_rr_ring, 2374 sc->alc_cdata.alc_rr_ring_map); 2375 sc->alc_rdata.alc_rr_ring = NULL; 2376 sc->alc_cdata.alc_rr_ring_map = NULL; 2377 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2378 sc->alc_cdata.alc_rr_ring_tag = NULL; 2379 } 2380 /* CMB block */ 2381 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2382 if (sc->alc_cdata.alc_cmb_map != NULL) 2383 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2384 sc->alc_cdata.alc_cmb_map); 2385 if (sc->alc_cdata.alc_cmb_map != NULL && 2386 sc->alc_rdata.alc_cmb != NULL) 2387 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2388 sc->alc_rdata.alc_cmb, 2389 sc->alc_cdata.alc_cmb_map); 2390 sc->alc_rdata.alc_cmb = NULL; 2391 sc->alc_cdata.alc_cmb_map = NULL; 2392 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2393 sc->alc_cdata.alc_cmb_tag = NULL; 2394 } 2395 /* SMB block */ 2396 if (sc->alc_cdata.alc_smb_tag != NULL) { 2397 if (sc->alc_cdata.alc_smb_map != NULL) 2398 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2399 sc->alc_cdata.alc_smb_map); 2400 if (sc->alc_cdata.alc_smb_map != NULL && 2401 sc->alc_rdata.alc_smb != NULL) 2402 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2403 sc->alc_rdata.alc_smb, 2404 sc->alc_cdata.alc_smb_map); 2405 sc->alc_rdata.alc_smb = NULL; 2406 sc->alc_cdata.alc_smb_map = NULL; 2407 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2408 sc->alc_cdata.alc_smb_tag = NULL; 2409 } 2410 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2411 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2412 sc->alc_cdata.alc_buffer_tag = NULL; 2413 } 2414 if (sc->alc_cdata.alc_parent_tag != NULL) { 2415 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2416 sc->alc_cdata.alc_parent_tag = NULL; 2417 } 2418} 2419 2420static int 2421alc_shutdown(device_t dev) 2422{ 2423 2424 return (alc_suspend(dev)); 2425} 2426 2427/* 2428 * Note, this driver resets the link speed to 10/100Mbps by 2429 * restarting auto-negotiation in suspend/shutdown phase but we 2430 * don't know whether that auto-negotiation would succeed or not 2431 * as driver has no control after powering off/suspend operation. 2432 * If the renegotiation fail WOL may not work. Running at 1Gbps 2433 * will draw more power than 375mA at 3.3V which is specified in 2434 * PCI specification and that would result in complete 2435 * shutdowning power to ethernet controller. 2436 * 2437 * TODO 2438 * Save current negotiated media speed/duplex/flow-control to 2439 * softc and restore the same link again after resuming. PHY 2440 * handling such as power down/resetting to 100Mbps may be better 2441 * handled in suspend method in phy driver. 2442 */ 2443static void 2444alc_setlinkspeed(struct alc_softc *sc) 2445{ 2446 struct mii_data *mii; 2447 int aneg, i; 2448 2449 mii = device_get_softc(sc->alc_miibus); 2450 mii_pollstat(mii); 2451 aneg = 0; 2452 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2453 (IFM_ACTIVE | IFM_AVALID)) { 2454 switch IFM_SUBTYPE(mii->mii_media_active) { 2455 case IFM_10_T: 2456 case IFM_100_TX: 2457 return; 2458 case IFM_1000_T: 2459 aneg++; 2460 break; 2461 default: 2462 break; 2463 } 2464 } 2465 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2466 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2467 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2468 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2469 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2470 DELAY(1000); 2471 if (aneg != 0) { 2472 /* 2473 * Poll link state until alc(4) get a 10/100Mbps link. 2474 */ 2475 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2476 mii_pollstat(mii); 2477 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2478 == (IFM_ACTIVE | IFM_AVALID)) { 2479 switch (IFM_SUBTYPE( 2480 mii->mii_media_active)) { 2481 case IFM_10_T: 2482 case IFM_100_TX: 2483 alc_mac_config(sc); 2484 return; 2485 default: 2486 break; 2487 } 2488 } 2489 ALC_UNLOCK(sc); 2490 pause("alclnk", hz); 2491 ALC_LOCK(sc); 2492 } 2493 if (i == MII_ANEGTICKS_GIGE) 2494 device_printf(sc->alc_dev, 2495 "establishing a link failed, WOL may not work!"); 2496 } 2497 /* 2498 * No link, force MAC to have 100Mbps, full-duplex link. 2499 * This is the last resort and may/may not work. 2500 */ 2501 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2502 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2503 alc_mac_config(sc); 2504} 2505 2506static void 2507alc_setwol(struct alc_softc *sc) 2508{ 2509 2510 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2511 alc_setwol_816x(sc); 2512 else 2513 alc_setwol_813x(sc); 2514} 2515 2516static void 2517alc_setwol_813x(struct alc_softc *sc) 2518{ 2519 struct ifnet *ifp; 2520 uint32_t reg, pmcs; 2521 uint16_t pmstat; 2522 2523 ALC_LOCK_ASSERT(sc); 2524 2525 alc_disable_l0s_l1(sc); 2526 ifp = sc->alc_ifp; 2527 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2528 /* Disable WOL. */ 2529 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2530 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2531 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2532 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2533 /* Force PHY power down. */ 2534 alc_phy_down(sc); 2535 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2536 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2537 return; 2538 } 2539 2540 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2541 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2542 alc_setlinkspeed(sc); 2543 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2544 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2545 } 2546 2547 pmcs = 0; 2548 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2549 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2550 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2551 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2552 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2553 MAC_CFG_BCAST); 2554 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2555 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2556 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2557 reg |= MAC_CFG_RX_ENB; 2558 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2559 2560 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2561 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2562 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2563 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2564 /* WOL disabled, PHY power down. */ 2565 alc_phy_down(sc); 2566 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2567 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2568 } 2569 /* Request PME. */ 2570 pmstat = pci_read_config(sc->alc_dev, 2571 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2572 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2573 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2574 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2575 pci_write_config(sc->alc_dev, 2576 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2577} 2578 2579static void 2580alc_setwol_816x(struct alc_softc *sc) 2581{ 2582 struct ifnet *ifp; 2583 uint32_t gphy, mac, master, pmcs, reg; 2584 uint16_t pmstat; 2585 2586 ALC_LOCK_ASSERT(sc); 2587 2588 ifp = sc->alc_ifp; 2589 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2590 master &= ~MASTER_CLK_SEL_DIS; 2591 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2592 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2593 GPHY_CFG_PHY_PLL_ON); 2594 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2595 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2596 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2597 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2598 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2599 } else { 2600 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2601 gphy |= GPHY_CFG_EXT_RESET; 2602 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2603 alc_setlinkspeed(sc); 2604 } 2605 pmcs = 0; 2606 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2607 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2608 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2609 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2610 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2611 MAC_CFG_BCAST); 2612 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2613 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2614 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2615 mac |= MAC_CFG_RX_ENB; 2616 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2617 ANEG_S3DIG10_SL); 2618 } 2619 2620 /* Enable OSC. */ 2621 reg = CSR_READ_4(sc, ALC_MISC); 2622 reg &= ~MISC_INTNLOSC_OPEN; 2623 CSR_WRITE_4(sc, ALC_MISC, reg); 2624 reg |= MISC_INTNLOSC_OPEN; 2625 CSR_WRITE_4(sc, ALC_MISC, reg); 2626 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2627 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2628 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2629 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2630 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2631 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2632 2633 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2634 /* Request PME. */ 2635 pmstat = pci_read_config(sc->alc_dev, 2636 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2637 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2638 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2639 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2640 pci_write_config(sc->alc_dev, 2641 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2642 } 2643} 2644 2645static int 2646alc_suspend(device_t dev) 2647{ 2648 struct alc_softc *sc; 2649 2650 sc = device_get_softc(dev); 2651 2652 ALC_LOCK(sc); 2653 alc_stop(sc); 2654 alc_setwol(sc); 2655 ALC_UNLOCK(sc); 2656 2657 return (0); 2658} 2659 2660static int 2661alc_resume(device_t dev) 2662{ 2663 struct alc_softc *sc; 2664 struct ifnet *ifp; 2665 uint16_t pmstat; 2666 2667 sc = device_get_softc(dev); 2668 2669 ALC_LOCK(sc); 2670 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2671 /* Disable PME and clear PME status. */ 2672 pmstat = pci_read_config(sc->alc_dev, 2673 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2674 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2675 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2676 pci_write_config(sc->alc_dev, 2677 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2678 } 2679 } 2680 /* Reset PHY. */ 2681 alc_phy_reset(sc); 2682 ifp = sc->alc_ifp; 2683 if ((ifp->if_flags & IFF_UP) != 0) { 2684 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2685 alc_init_locked(sc); 2686 } 2687 ALC_UNLOCK(sc); 2688 2689 return (0); 2690} 2691 2692static int 2693alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2694{ 2695 struct alc_txdesc *txd, *txd_last; 2696 struct tx_desc *desc; 2697 struct mbuf *m; 2698 struct ip *ip; 2699 struct tcphdr *tcp; 2700 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2701 bus_dmamap_t map; 2702 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2703 int error, idx, nsegs, prod; 2704 2705 ALC_LOCK_ASSERT(sc); 2706 2707 M_ASSERTPKTHDR((*m_head)); 2708 2709 m = *m_head; 2710 ip = NULL; 2711 tcp = NULL; 2712 ip_off = poff = 0; 2713 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2714 /* 2715 * AR81[3567]x requires offset of TCP/UDP header in its 2716 * Tx descriptor to perform Tx checksum offloading. TSO 2717 * also requires TCP header offset and modification of 2718 * IP/TCP header. This kind of operation takes many CPU 2719 * cycles on FreeBSD so fast host CPU is required to get 2720 * smooth TSO performance. 2721 */ 2722 struct ether_header *eh; 2723 2724 if (M_WRITABLE(m) == 0) { 2725 /* Get a writable copy. */ 2726 m = m_dup(*m_head, M_NOWAIT); 2727 /* Release original mbufs. */ 2728 m_freem(*m_head); 2729 if (m == NULL) { 2730 *m_head = NULL; 2731 return (ENOBUFS); 2732 } 2733 *m_head = m; 2734 } 2735 2736 ip_off = sizeof(struct ether_header); 2737 m = m_pullup(m, ip_off); 2738 if (m == NULL) { 2739 *m_head = NULL; 2740 return (ENOBUFS); 2741 } 2742 eh = mtod(m, struct ether_header *); 2743 /* 2744 * Check if hardware VLAN insertion is off. 2745 * Additional check for LLC/SNAP frame? 2746 */ 2747 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2748 ip_off = sizeof(struct ether_vlan_header); 2749 m = m_pullup(m, ip_off); 2750 if (m == NULL) { 2751 *m_head = NULL; 2752 return (ENOBUFS); 2753 } 2754 } 2755 m = m_pullup(m, ip_off + sizeof(struct ip)); 2756 if (m == NULL) { 2757 *m_head = NULL; 2758 return (ENOBUFS); 2759 } 2760 ip = (struct ip *)(mtod(m, char *) + ip_off); 2761 poff = ip_off + (ip->ip_hl << 2); 2762 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2763 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2764 if (m == NULL) { 2765 *m_head = NULL; 2766 return (ENOBUFS); 2767 } 2768 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2769 m = m_pullup(m, poff + (tcp->th_off << 2)); 2770 if (m == NULL) { 2771 *m_head = NULL; 2772 return (ENOBUFS); 2773 } 2774 /* 2775 * Due to strict adherence of Microsoft NDIS 2776 * Large Send specification, hardware expects 2777 * a pseudo TCP checksum inserted by upper 2778 * stack. Unfortunately the pseudo TCP 2779 * checksum that NDIS refers to does not include 2780 * TCP payload length so driver should recompute 2781 * the pseudo checksum here. Hopefully this 2782 * wouldn't be much burden on modern CPUs. 2783 * 2784 * Reset IP checksum and recompute TCP pseudo 2785 * checksum as NDIS specification said. 2786 */ 2787 ip = (struct ip *)(mtod(m, char *) + ip_off); 2788 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2789 ip->ip_sum = 0; 2790 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2791 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2792 } 2793 *m_head = m; 2794 } 2795 2796 prod = sc->alc_cdata.alc_tx_prod; 2797 txd = &sc->alc_cdata.alc_txdesc[prod]; 2798 txd_last = txd; 2799 map = txd->tx_dmamap; 2800 2801 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2802 *m_head, txsegs, &nsegs, 0); 2803 if (error == EFBIG) { 2804 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2805 if (m == NULL) { 2806 m_freem(*m_head); 2807 *m_head = NULL; 2808 return (ENOMEM); 2809 } 2810 *m_head = m; 2811 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2812 *m_head, txsegs, &nsegs, 0); 2813 if (error != 0) { 2814 m_freem(*m_head); 2815 *m_head = NULL; 2816 return (error); 2817 } 2818 } else if (error != 0) 2819 return (error); 2820 if (nsegs == 0) { 2821 m_freem(*m_head); 2822 *m_head = NULL; 2823 return (EIO); 2824 } 2825 2826 /* Check descriptor overrun. */ 2827 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2828 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2829 return (ENOBUFS); 2830 } 2831 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2832 2833 m = *m_head; 2834 cflags = TD_ETHERNET; 2835 vtag = 0; 2836 desc = NULL; 2837 idx = 0; 2838 /* Configure VLAN hardware tag insertion. */ 2839 if ((m->m_flags & M_VLANTAG) != 0) { 2840 vtag = htons(m->m_pkthdr.ether_vtag); 2841 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2842 cflags |= TD_INS_VLAN_TAG; 2843 } 2844 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2845 /* Request TSO and set MSS. */ 2846 cflags |= TD_TSO | TD_TSO_DESCV1; 2847 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2848 TD_MSS_MASK; 2849 /* Set TCP header offset. */ 2850 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2851 TD_TCPHDR_OFFSET_MASK; 2852 /* 2853 * AR81[3567]x requires the first buffer should 2854 * only hold IP/TCP header data. Payload should 2855 * be handled in other descriptors. 2856 */ 2857 hdrlen = poff + (tcp->th_off << 2); 2858 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2859 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2860 desc->flags = htole32(cflags); 2861 desc->addr = htole64(txsegs[0].ds_addr); 2862 sc->alc_cdata.alc_tx_cnt++; 2863 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2864 if (m->m_len - hdrlen > 0) { 2865 /* Handle remaining payload of the first fragment. */ 2866 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2867 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2868 vtag)); 2869 desc->flags = htole32(cflags); 2870 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2871 sc->alc_cdata.alc_tx_cnt++; 2872 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2873 } 2874 /* Handle remaining fragments. */ 2875 idx = 1; 2876 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2877 /* Configure Tx checksum offload. */ 2878#ifdef ALC_USE_CUSTOM_CSUM 2879 cflags |= TD_CUSTOM_CSUM; 2880 /* Set checksum start offset. */ 2881 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2882 TD_PLOAD_OFFSET_MASK; 2883 /* Set checksum insertion position of TCP/UDP. */ 2884 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2885 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2886#else 2887 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2888 cflags |= TD_IPCSUM; 2889 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2890 cflags |= TD_TCPCSUM; 2891 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2892 cflags |= TD_UDPCSUM; 2893 /* Set TCP/UDP header offset. */ 2894 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2895 TD_L4HDR_OFFSET_MASK; 2896#endif 2897 } 2898 for (; idx < nsegs; idx++) { 2899 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2900 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2901 desc->flags = htole32(cflags); 2902 desc->addr = htole64(txsegs[idx].ds_addr); 2903 sc->alc_cdata.alc_tx_cnt++; 2904 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2905 } 2906 /* Update producer index. */ 2907 sc->alc_cdata.alc_tx_prod = prod; 2908 2909 /* Finally set EOP on the last descriptor. */ 2910 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2911 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2912 desc->flags |= htole32(TD_EOP); 2913 2914 /* Swap dmamap of the first and the last. */ 2915 txd = &sc->alc_cdata.alc_txdesc[prod]; 2916 map = txd_last->tx_dmamap; 2917 txd_last->tx_dmamap = txd->tx_dmamap; 2918 txd->tx_dmamap = map; 2919 txd->tx_m = m; 2920 2921 return (0); 2922} 2923 2924static void 2925alc_start(struct ifnet *ifp) 2926{ 2927 struct alc_softc *sc; 2928 2929 sc = ifp->if_softc; 2930 ALC_LOCK(sc); 2931 alc_start_locked(ifp); 2932 ALC_UNLOCK(sc); 2933} 2934 2935static void 2936alc_start_locked(struct ifnet *ifp) 2937{ 2938 struct alc_softc *sc; 2939 struct mbuf *m_head; 2940 int enq; 2941 2942 sc = ifp->if_softc; 2943 2944 ALC_LOCK_ASSERT(sc); 2945 2946 /* Reclaim transmitted frames. */ 2947 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2948 alc_txeof(sc); 2949 2950 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2951 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2952 return; 2953 2954 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2955 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2956 if (m_head == NULL) 2957 break; 2958 /* 2959 * Pack the data into the transmit ring. If we 2960 * don't have room, set the OACTIVE flag and wait 2961 * for the NIC to drain the ring. 2962 */ 2963 if (alc_encap(sc, &m_head)) { 2964 if (m_head == NULL) 2965 break; 2966 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2967 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2968 break; 2969 } 2970 2971 enq++; 2972 /* 2973 * If there's a BPF listener, bounce a copy of this frame 2974 * to him. 2975 */ 2976 ETHER_BPF_MTAP(ifp, m_head); 2977 } 2978 2979 if (enq > 0) { 2980 /* Sync descriptors. */ 2981 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2982 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2983 /* Kick. Assume we're using normal Tx priority queue. */ 2984 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2985 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2986 (uint16_t)sc->alc_cdata.alc_tx_prod); 2987 else 2988 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2989 (sc->alc_cdata.alc_tx_prod << 2990 MBOX_TD_PROD_LO_IDX_SHIFT) & 2991 MBOX_TD_PROD_LO_IDX_MASK); 2992 /* Set a timeout in case the chip goes out to lunch. */ 2993 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2994 } 2995} 2996 2997static void 2998alc_watchdog(struct alc_softc *sc) 2999{ 3000 struct ifnet *ifp; 3001 3002 ALC_LOCK_ASSERT(sc); 3003 3004 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3005 return; 3006 3007 ifp = sc->alc_ifp; 3008 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3009 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3010 ifp->if_oerrors++; 3011 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3012 alc_init_locked(sc); 3013 return; 3014 } 3015 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3016 ifp->if_oerrors++; 3017 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3018 alc_init_locked(sc); 3019 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3020 alc_start_locked(ifp); 3021} 3022 3023static int 3024alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3025{ 3026 struct alc_softc *sc; 3027 struct ifreq *ifr; 3028 struct mii_data *mii; 3029 int error, mask; 3030 3031 sc = ifp->if_softc; 3032 ifr = (struct ifreq *)data; 3033 error = 0; 3034 switch (cmd) { 3035 case SIOCSIFMTU: 3036 if (ifr->ifr_mtu < ETHERMIN || 3037 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3038 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3039 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3040 ifr->ifr_mtu > ETHERMTU)) 3041 error = EINVAL; 3042 else if (ifp->if_mtu != ifr->ifr_mtu) { 3043 ALC_LOCK(sc); 3044 ifp->if_mtu = ifr->ifr_mtu; 3045 /* AR81[3567]x has 13 bits MSS field. */ 3046 if (ifp->if_mtu > ALC_TSO_MTU && 3047 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3048 ifp->if_capenable &= ~IFCAP_TSO4; 3049 ifp->if_hwassist &= ~CSUM_TSO; 3050 VLAN_CAPABILITIES(ifp); 3051 } 3052 ALC_UNLOCK(sc); 3053 } 3054 break; 3055 case SIOCSIFFLAGS: 3056 ALC_LOCK(sc); 3057 if ((ifp->if_flags & IFF_UP) != 0) { 3058 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3059 ((ifp->if_flags ^ sc->alc_if_flags) & 3060 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3061 alc_rxfilter(sc); 3062 else 3063 alc_init_locked(sc); 3064 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3065 alc_stop(sc); 3066 sc->alc_if_flags = ifp->if_flags; 3067 ALC_UNLOCK(sc); 3068 break; 3069 case SIOCADDMULTI: 3070 case SIOCDELMULTI: 3071 ALC_LOCK(sc); 3072 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3073 alc_rxfilter(sc); 3074 ALC_UNLOCK(sc); 3075 break; 3076 case SIOCSIFMEDIA: 3077 case SIOCGIFMEDIA: 3078 mii = device_get_softc(sc->alc_miibus); 3079 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3080 break; 3081 case SIOCSIFCAP: 3082 ALC_LOCK(sc); 3083 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3084 if ((mask & IFCAP_TXCSUM) != 0 && 3085 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3086 ifp->if_capenable ^= IFCAP_TXCSUM; 3087 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3088 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3089 else 3090 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3091 } 3092 if ((mask & IFCAP_TSO4) != 0 && 3093 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3094 ifp->if_capenable ^= IFCAP_TSO4; 3095 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3096 /* AR81[3567]x has 13 bits MSS field. */ 3097 if (ifp->if_mtu > ALC_TSO_MTU) { 3098 ifp->if_capenable &= ~IFCAP_TSO4; 3099 ifp->if_hwassist &= ~CSUM_TSO; 3100 } else 3101 ifp->if_hwassist |= CSUM_TSO; 3102 } else 3103 ifp->if_hwassist &= ~CSUM_TSO; 3104 } 3105 if ((mask & IFCAP_WOL_MCAST) != 0 && 3106 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3107 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3108 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3109 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3110 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3111 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3112 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3113 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3114 alc_rxvlan(sc); 3115 } 3116 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3117 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3118 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3119 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3120 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3121 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3122 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3123 ifp->if_capenable &= 3124 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3125 ALC_UNLOCK(sc); 3126 VLAN_CAPABILITIES(ifp); 3127 break; 3128 default: 3129 error = ether_ioctl(ifp, cmd, data); 3130 break; 3131 } 3132 3133 return (error); 3134} 3135 3136static void 3137alc_mac_config(struct alc_softc *sc) 3138{ 3139 struct mii_data *mii; 3140 uint32_t reg; 3141 3142 ALC_LOCK_ASSERT(sc); 3143 3144 mii = device_get_softc(sc->alc_miibus); 3145 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3146 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3147 MAC_CFG_SPEED_MASK); 3148 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3149 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3150 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3151 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3152 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3153 /* Reprogram MAC with resolved speed/duplex. */ 3154 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3155 case IFM_10_T: 3156 case IFM_100_TX: 3157 reg |= MAC_CFG_SPEED_10_100; 3158 break; 3159 case IFM_1000_T: 3160 reg |= MAC_CFG_SPEED_1000; 3161 break; 3162 } 3163 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3164 reg |= MAC_CFG_FULL_DUPLEX; 3165 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3166 reg |= MAC_CFG_TX_FC; 3167 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3168 reg |= MAC_CFG_RX_FC; 3169 } 3170 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3171} 3172 3173static void 3174alc_stats_clear(struct alc_softc *sc) 3175{ 3176 struct smb sb, *smb; 3177 uint32_t *reg; 3178 int i; 3179 3180 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3181 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3182 sc->alc_cdata.alc_smb_map, 3183 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3184 smb = sc->alc_rdata.alc_smb; 3185 /* Update done, clear. */ 3186 smb->updated = 0; 3187 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3188 sc->alc_cdata.alc_smb_map, 3189 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3190 } else { 3191 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3192 reg++) { 3193 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3194 i += sizeof(uint32_t); 3195 } 3196 /* Read Tx statistics. */ 3197 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3198 reg++) { 3199 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3200 i += sizeof(uint32_t); 3201 } 3202 } 3203} 3204 3205static void 3206alc_stats_update(struct alc_softc *sc) 3207{ 3208 struct alc_hw_stats *stat; 3209 struct smb sb, *smb; 3210 struct ifnet *ifp; 3211 uint32_t *reg; 3212 int i; 3213 3214 ALC_LOCK_ASSERT(sc); 3215 3216 ifp = sc->alc_ifp; 3217 stat = &sc->alc_stats; 3218 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3219 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3220 sc->alc_cdata.alc_smb_map, 3221 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3222 smb = sc->alc_rdata.alc_smb; 3223 if (smb->updated == 0) 3224 return; 3225 } else { 3226 smb = &sb; 3227 /* Read Rx statistics. */ 3228 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3229 reg++) { 3230 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3231 i += sizeof(uint32_t); 3232 } 3233 /* Read Tx statistics. */ 3234 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3235 reg++) { 3236 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3237 i += sizeof(uint32_t); 3238 } 3239 } 3240 3241 /* Rx stats. */ 3242 stat->rx_frames += smb->rx_frames; 3243 stat->rx_bcast_frames += smb->rx_bcast_frames; 3244 stat->rx_mcast_frames += smb->rx_mcast_frames; 3245 stat->rx_pause_frames += smb->rx_pause_frames; 3246 stat->rx_control_frames += smb->rx_control_frames; 3247 stat->rx_crcerrs += smb->rx_crcerrs; 3248 stat->rx_lenerrs += smb->rx_lenerrs; 3249 stat->rx_bytes += smb->rx_bytes; 3250 stat->rx_runts += smb->rx_runts; 3251 stat->rx_fragments += smb->rx_fragments; 3252 stat->rx_pkts_64 += smb->rx_pkts_64; 3253 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3254 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3255 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3256 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3257 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3258 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3259 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3260 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3261 stat->rx_rrs_errs += smb->rx_rrs_errs; 3262 stat->rx_alignerrs += smb->rx_alignerrs; 3263 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3264 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3265 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3266 3267 /* Tx stats. */ 3268 stat->tx_frames += smb->tx_frames; 3269 stat->tx_bcast_frames += smb->tx_bcast_frames; 3270 stat->tx_mcast_frames += smb->tx_mcast_frames; 3271 stat->tx_pause_frames += smb->tx_pause_frames; 3272 stat->tx_excess_defer += smb->tx_excess_defer; 3273 stat->tx_control_frames += smb->tx_control_frames; 3274 stat->tx_deferred += smb->tx_deferred; 3275 stat->tx_bytes += smb->tx_bytes; 3276 stat->tx_pkts_64 += smb->tx_pkts_64; 3277 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3278 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3279 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3280 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3281 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3282 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3283 stat->tx_single_colls += smb->tx_single_colls; 3284 stat->tx_multi_colls += smb->tx_multi_colls; 3285 stat->tx_late_colls += smb->tx_late_colls; 3286 stat->tx_excess_colls += smb->tx_excess_colls; 3287 stat->tx_underrun += smb->tx_underrun; 3288 stat->tx_desc_underrun += smb->tx_desc_underrun; 3289 stat->tx_lenerrs += smb->tx_lenerrs; 3290 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3291 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3292 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3293 3294 /* Update counters in ifnet. */ 3295 ifp->if_opackets += smb->tx_frames; 3296 3297 ifp->if_collisions += smb->tx_single_colls + 3298 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3299 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 3300 3301 /* 3302 * XXX 3303 * tx_pkts_truncated counter looks suspicious. It constantly 3304 * increments with no sign of Tx errors. This may indicate 3305 * the counter name is not correct one so I've removed the 3306 * counter in output errors. 3307 */ 3308 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 3309 smb->tx_underrun + smb->tx_pkts_truncated; 3310 3311 ifp->if_ipackets += smb->rx_frames; 3312 3313 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 3314 smb->rx_runts + smb->rx_pkts_truncated + 3315 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3316 smb->rx_alignerrs; 3317 3318 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3319 /* Update done, clear. */ 3320 smb->updated = 0; 3321 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3322 sc->alc_cdata.alc_smb_map, 3323 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3324 } 3325} 3326 3327static int 3328alc_intr(void *arg) 3329{ 3330 struct alc_softc *sc; 3331 uint32_t status; 3332 3333 sc = (struct alc_softc *)arg; 3334 3335 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3336 if ((status & ALC_INTRS) == 0) 3337 return (FILTER_STRAY); 3338 /* Disable interrupts. */ 3339 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3340 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3341 3342 return (FILTER_HANDLED); 3343} 3344 3345static void 3346alc_int_task(void *arg, int pending) 3347{ 3348 struct alc_softc *sc; 3349 struct ifnet *ifp; 3350 uint32_t status; 3351 int more; 3352 3353 sc = (struct alc_softc *)arg; 3354 ifp = sc->alc_ifp; 3355 3356 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3357 ALC_LOCK(sc); 3358 if (sc->alc_morework != 0) { 3359 sc->alc_morework = 0; 3360 status |= INTR_RX_PKT; 3361 } 3362 if ((status & ALC_INTRS) == 0) 3363 goto done; 3364 3365 /* Acknowledge interrupts but still disable interrupts. */ 3366 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3367 3368 more = 0; 3369 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3370 if ((status & INTR_RX_PKT) != 0) { 3371 more = alc_rxintr(sc, sc->alc_process_limit); 3372 if (more == EAGAIN) 3373 sc->alc_morework = 1; 3374 else if (more == EIO) { 3375 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3376 alc_init_locked(sc); 3377 ALC_UNLOCK(sc); 3378 return; 3379 } 3380 } 3381 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3382 INTR_TXQ_TO_RST)) != 0) { 3383 if ((status & INTR_DMA_RD_TO_RST) != 0) 3384 device_printf(sc->alc_dev, 3385 "DMA read error! -- resetting\n"); 3386 if ((status & INTR_DMA_WR_TO_RST) != 0) 3387 device_printf(sc->alc_dev, 3388 "DMA write error! -- resetting\n"); 3389 if ((status & INTR_TXQ_TO_RST) != 0) 3390 device_printf(sc->alc_dev, 3391 "TxQ reset! -- resetting\n"); 3392 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3393 alc_init_locked(sc); 3394 ALC_UNLOCK(sc); 3395 return; 3396 } 3397 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3398 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3399 alc_start_locked(ifp); 3400 } 3401 3402 if (more == EAGAIN || 3403 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3404 ALC_UNLOCK(sc); 3405 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3406 return; 3407 } 3408 3409done: 3410 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3411 /* Re-enable interrupts if we're running. */ 3412 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3413 } 3414 ALC_UNLOCK(sc); 3415} 3416 3417static void 3418alc_txeof(struct alc_softc *sc) 3419{ 3420 struct ifnet *ifp; 3421 struct alc_txdesc *txd; 3422 uint32_t cons, prod; 3423 int prog; 3424 3425 ALC_LOCK_ASSERT(sc); 3426 3427 ifp = sc->alc_ifp; 3428 3429 if (sc->alc_cdata.alc_tx_cnt == 0) 3430 return; 3431 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3432 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3433 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3434 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3435 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3436 prod = sc->alc_rdata.alc_cmb->cons; 3437 } else { 3438 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3439 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3440 else { 3441 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3442 /* Assume we're using normal Tx priority queue. */ 3443 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3444 MBOX_TD_CONS_LO_IDX_SHIFT; 3445 } 3446 } 3447 cons = sc->alc_cdata.alc_tx_cons; 3448 /* 3449 * Go through our Tx list and free mbufs for those 3450 * frames which have been transmitted. 3451 */ 3452 for (prog = 0; cons != prod; prog++, 3453 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3454 if (sc->alc_cdata.alc_tx_cnt <= 0) 3455 break; 3456 prog++; 3457 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3458 sc->alc_cdata.alc_tx_cnt--; 3459 txd = &sc->alc_cdata.alc_txdesc[cons]; 3460 if (txd->tx_m != NULL) { 3461 /* Reclaim transmitted mbufs. */ 3462 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3463 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3464 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3465 txd->tx_dmamap); 3466 m_freem(txd->tx_m); 3467 txd->tx_m = NULL; 3468 } 3469 } 3470 3471 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3472 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3473 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3474 sc->alc_cdata.alc_tx_cons = cons; 3475 /* 3476 * Unarm watchdog timer only when there is no pending 3477 * frames in Tx queue. 3478 */ 3479 if (sc->alc_cdata.alc_tx_cnt == 0) 3480 sc->alc_watchdog_timer = 0; 3481} 3482 3483static int 3484alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3485{ 3486 struct mbuf *m; 3487 bus_dma_segment_t segs[1]; 3488 bus_dmamap_t map; 3489 int nsegs; 3490 3491 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3492 if (m == NULL) 3493 return (ENOBUFS); 3494 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3495#ifndef __NO_STRICT_ALIGNMENT 3496 m_adj(m, sizeof(uint64_t)); 3497#endif 3498 3499 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3500 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3501 m_freem(m); 3502 return (ENOBUFS); 3503 } 3504 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3505 3506 if (rxd->rx_m != NULL) { 3507 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3508 BUS_DMASYNC_POSTREAD); 3509 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3510 } 3511 map = rxd->rx_dmamap; 3512 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3513 sc->alc_cdata.alc_rx_sparemap = map; 3514 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3515 BUS_DMASYNC_PREREAD); 3516 rxd->rx_m = m; 3517 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3518 return (0); 3519} 3520 3521static int 3522alc_rxintr(struct alc_softc *sc, int count) 3523{ 3524 struct ifnet *ifp; 3525 struct rx_rdesc *rrd; 3526 uint32_t nsegs, status; 3527 int rr_cons, prog; 3528 3529 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3530 sc->alc_cdata.alc_rr_ring_map, 3531 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3532 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3533 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3534 rr_cons = sc->alc_cdata.alc_rr_cons; 3535 ifp = sc->alc_ifp; 3536 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3537 if (count-- <= 0) 3538 break; 3539 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3540 status = le32toh(rrd->status); 3541 if ((status & RRD_VALID) == 0) 3542 break; 3543 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3544 if (nsegs == 0) { 3545 /* This should not happen! */ 3546 device_printf(sc->alc_dev, 3547 "unexpected segment count -- resetting\n"); 3548 return (EIO); 3549 } 3550 alc_rxeof(sc, rrd); 3551 /* Clear Rx return status. */ 3552 rrd->status = 0; 3553 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3554 sc->alc_cdata.alc_rx_cons += nsegs; 3555 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3556 prog += nsegs; 3557 } 3558 3559 if (prog > 0) { 3560 /* Update the consumer index. */ 3561 sc->alc_cdata.alc_rr_cons = rr_cons; 3562 /* Sync Rx return descriptors. */ 3563 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3564 sc->alc_cdata.alc_rr_ring_map, 3565 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3566 /* 3567 * Sync updated Rx descriptors such that controller see 3568 * modified buffer addresses. 3569 */ 3570 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3571 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3572 /* 3573 * Let controller know availability of new Rx buffers. 3574 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3575 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3576 * only when Rx buffer pre-fetching is required. In 3577 * addition we already set ALC_RX_RD_FREE_THRESH to 3578 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3579 * it still seems that pre-fetching needs more 3580 * experimentation. 3581 */ 3582 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3583 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3584 (uint16_t)sc->alc_cdata.alc_rx_cons); 3585 else 3586 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3587 sc->alc_cdata.alc_rx_cons); 3588 } 3589 3590 return (count > 0 ? 0 : EAGAIN); 3591} 3592 3593#ifndef __NO_STRICT_ALIGNMENT 3594static struct mbuf * 3595alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3596{ 3597 struct mbuf *n; 3598 int i; 3599 uint16_t *src, *dst; 3600 3601 src = mtod(m, uint16_t *); 3602 dst = src - 3; 3603 3604 if (m->m_next == NULL) { 3605 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3606 *dst++ = *src++; 3607 m->m_data -= 6; 3608 return (m); 3609 } 3610 /* 3611 * Append a new mbuf to received mbuf chain and copy ethernet 3612 * header from the mbuf chain. This can save lots of CPU 3613 * cycles for jumbo frame. 3614 */ 3615 MGETHDR(n, M_NOWAIT, MT_DATA); 3616 if (n == NULL) { 3617 ifp->if_iqdrops++; 3618 m_freem(m); 3619 return (NULL); 3620 } 3621 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3622 m->m_data += ETHER_HDR_LEN; 3623 m->m_len -= ETHER_HDR_LEN; 3624 n->m_len = ETHER_HDR_LEN; 3625 M_MOVE_PKTHDR(n, m); 3626 n->m_next = m; 3627 return (n); 3628} 3629#endif 3630 3631/* Receive a frame. */ 3632static void 3633alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3634{ 3635 struct alc_rxdesc *rxd; 3636 struct ifnet *ifp; 3637 struct mbuf *mp, *m; 3638 uint32_t rdinfo, status, vtag; 3639 int count, nsegs, rx_cons; 3640 3641 ifp = sc->alc_ifp; 3642 status = le32toh(rrd->status); 3643 rdinfo = le32toh(rrd->rdinfo); 3644 rx_cons = RRD_RD_IDX(rdinfo); 3645 nsegs = RRD_RD_CNT(rdinfo); 3646 3647 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3648 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3649 /* 3650 * We want to pass the following frames to upper 3651 * layer regardless of error status of Rx return 3652 * ring. 3653 * 3654 * o IP/TCP/UDP checksum is bad. 3655 * o frame length and protocol specific length 3656 * does not match. 3657 * 3658 * Force network stack compute checksum for 3659 * errored frames. 3660 */ 3661 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3662 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3663 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3664 return; 3665 } 3666 3667 for (count = 0; count < nsegs; count++, 3668 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3669 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3670 mp = rxd->rx_m; 3671 /* Add a new receive buffer to the ring. */ 3672 if (alc_newbuf(sc, rxd) != 0) { 3673 ifp->if_iqdrops++; 3674 /* Reuse Rx buffers. */ 3675 if (sc->alc_cdata.alc_rxhead != NULL) 3676 m_freem(sc->alc_cdata.alc_rxhead); 3677 break; 3678 } 3679 3680 /* 3681 * Assume we've received a full sized frame. 3682 * Actual size is fixed when we encounter the end of 3683 * multi-segmented frame. 3684 */ 3685 mp->m_len = sc->alc_buf_size; 3686 3687 /* Chain received mbufs. */ 3688 if (sc->alc_cdata.alc_rxhead == NULL) { 3689 sc->alc_cdata.alc_rxhead = mp; 3690 sc->alc_cdata.alc_rxtail = mp; 3691 } else { 3692 mp->m_flags &= ~M_PKTHDR; 3693 sc->alc_cdata.alc_rxprev_tail = 3694 sc->alc_cdata.alc_rxtail; 3695 sc->alc_cdata.alc_rxtail->m_next = mp; 3696 sc->alc_cdata.alc_rxtail = mp; 3697 } 3698 3699 if (count == nsegs - 1) { 3700 /* Last desc. for this frame. */ 3701 m = sc->alc_cdata.alc_rxhead; 3702 m->m_flags |= M_PKTHDR; 3703 /* 3704 * It seems that L1C/L2C controller has no way 3705 * to tell hardware to strip CRC bytes. 3706 */ 3707 m->m_pkthdr.len = 3708 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3709 if (nsegs > 1) { 3710 /* Set last mbuf size. */ 3711 mp->m_len = sc->alc_cdata.alc_rxlen - 3712 (nsegs - 1) * sc->alc_buf_size; 3713 /* Remove the CRC bytes in chained mbufs. */ 3714 if (mp->m_len <= ETHER_CRC_LEN) { 3715 sc->alc_cdata.alc_rxtail = 3716 sc->alc_cdata.alc_rxprev_tail; 3717 sc->alc_cdata.alc_rxtail->m_len -= 3718 (ETHER_CRC_LEN - mp->m_len); 3719 sc->alc_cdata.alc_rxtail->m_next = NULL; 3720 m_freem(mp); 3721 } else { 3722 mp->m_len -= ETHER_CRC_LEN; 3723 } 3724 } else 3725 m->m_len = m->m_pkthdr.len; 3726 m->m_pkthdr.rcvif = ifp; 3727 /* 3728 * Due to hardware bugs, Rx checksum offloading 3729 * was intentionally disabled. 3730 */ 3731 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3732 (status & RRD_VLAN_TAG) != 0) { 3733 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3734 m->m_pkthdr.ether_vtag = ntohs(vtag); 3735 m->m_flags |= M_VLANTAG; 3736 } 3737#ifndef __NO_STRICT_ALIGNMENT 3738 m = alc_fixup_rx(ifp, m); 3739 if (m != NULL) 3740#endif 3741 { 3742 /* Pass it on. */ 3743 ALC_UNLOCK(sc); 3744 (*ifp->if_input)(ifp, m); 3745 ALC_LOCK(sc); 3746 } 3747 } 3748 } 3749 /* Reset mbuf chains. */ 3750 ALC_RXCHAIN_RESET(sc); 3751} 3752 3753static void 3754alc_tick(void *arg) 3755{ 3756 struct alc_softc *sc; 3757 struct mii_data *mii; 3758 3759 sc = (struct alc_softc *)arg; 3760 3761 ALC_LOCK_ASSERT(sc); 3762 3763 mii = device_get_softc(sc->alc_miibus); 3764 mii_tick(mii); 3765 alc_stats_update(sc); 3766 /* 3767 * alc(4) does not rely on Tx completion interrupts to reclaim 3768 * transferred buffers. Instead Tx completion interrupts are 3769 * used to hint for scheduling Tx task. So it's necessary to 3770 * release transmitted buffers by kicking Tx completion 3771 * handler. This limits the maximum reclamation delay to a hz. 3772 */ 3773 alc_txeof(sc); 3774 alc_watchdog(sc); 3775 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3776} 3777 3778static void 3779alc_osc_reset(struct alc_softc *sc) 3780{ 3781 uint32_t reg; 3782 3783 reg = CSR_READ_4(sc, ALC_MISC3); 3784 reg &= ~MISC3_25M_BY_SW; 3785 reg |= MISC3_25M_NOTO_INTNL; 3786 CSR_WRITE_4(sc, ALC_MISC3, reg); 3787 3788 reg = CSR_READ_4(sc, ALC_MISC); 3789 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3790 /* 3791 * Restore over-current protection default value. 3792 * This value could be reset by MAC reset. 3793 */ 3794 reg &= ~MISC_PSW_OCP_MASK; 3795 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3796 reg &= ~MISC_INTNLOSC_OPEN; 3797 CSR_WRITE_4(sc, ALC_MISC, reg); 3798 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3799 reg = CSR_READ_4(sc, ALC_MISC2); 3800 reg &= ~MISC2_CALB_START; 3801 CSR_WRITE_4(sc, ALC_MISC2, reg); 3802 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3803 3804 } else { 3805 reg &= ~MISC_INTNLOSC_OPEN; 3806 /* Disable isolate for revision A devices. */ 3807 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3808 reg &= ~MISC_ISO_ENB; 3809 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3810 CSR_WRITE_4(sc, ALC_MISC, reg); 3811 } 3812 3813 DELAY(20); 3814} 3815 3816static void 3817alc_reset(struct alc_softc *sc) 3818{ 3819 uint32_t pmcfg, reg; 3820 int i; 3821 3822 pmcfg = 0; 3823 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3824 /* Reset workaround. */ 3825 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3826 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3827 (sc->alc_rev & 0x01) != 0) { 3828 /* Disable L0s/L1s before reset. */ 3829 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3830 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3831 != 0) { 3832 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3833 PM_CFG_ASPM_L1_ENB); 3834 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3835 } 3836 } 3837 } 3838 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3839 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3840 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3841 3842 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3843 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3844 DELAY(10); 3845 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3846 break; 3847 } 3848 if (i == 0) 3849 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3850 } 3851 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3852 DELAY(10); 3853 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3854 break; 3855 } 3856 if (i == 0) 3857 device_printf(sc->alc_dev, "master reset timeout!\n"); 3858 3859 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3860 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3861 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3862 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3863 break; 3864 DELAY(10); 3865 } 3866 if (i == 0) 3867 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3868 3869 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3870 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3871 (sc->alc_rev & 0x01) != 0) { 3872 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3873 reg |= MASTER_CLK_SEL_DIS; 3874 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3875 /* Restore L0s/L1s config. */ 3876 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3877 != 0) 3878 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3879 } 3880 3881 alc_osc_reset(sc); 3882 reg = CSR_READ_4(sc, ALC_MISC3); 3883 reg &= ~MISC3_25M_BY_SW; 3884 reg |= MISC3_25M_NOTO_INTNL; 3885 CSR_WRITE_4(sc, ALC_MISC3, reg); 3886 reg = CSR_READ_4(sc, ALC_MISC); 3887 reg &= ~MISC_INTNLOSC_OPEN; 3888 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3889 reg &= ~MISC_ISO_ENB; 3890 CSR_WRITE_4(sc, ALC_MISC, reg); 3891 DELAY(20); 3892 } 3893 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3894 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3895 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3896 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3897 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3898 SERDES_PHY_CLK_SLOWDOWN); 3899} 3900 3901static void 3902alc_init(void *xsc) 3903{ 3904 struct alc_softc *sc; 3905 3906 sc = (struct alc_softc *)xsc; 3907 ALC_LOCK(sc); 3908 alc_init_locked(sc); 3909 ALC_UNLOCK(sc); 3910} 3911 3912static void 3913alc_init_locked(struct alc_softc *sc) 3914{ 3915 struct ifnet *ifp; 3916 struct mii_data *mii; 3917 uint8_t eaddr[ETHER_ADDR_LEN]; 3918 bus_addr_t paddr; 3919 uint32_t reg, rxf_hi, rxf_lo; 3920 3921 ALC_LOCK_ASSERT(sc); 3922 3923 ifp = sc->alc_ifp; 3924 mii = device_get_softc(sc->alc_miibus); 3925 3926 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3927 return; 3928 /* 3929 * Cancel any pending I/O. 3930 */ 3931 alc_stop(sc); 3932 /* 3933 * Reset the chip to a known state. 3934 */ 3935 alc_reset(sc); 3936 3937 /* Initialize Rx descriptors. */ 3938 if (alc_init_rx_ring(sc) != 0) { 3939 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3940 alc_stop(sc); 3941 return; 3942 } 3943 alc_init_rr_ring(sc); 3944 alc_init_tx_ring(sc); 3945 alc_init_cmb(sc); 3946 alc_init_smb(sc); 3947 3948 /* Enable all clocks. */ 3949 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3950 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3951 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3952 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3953 CLK_GATING_RXMAC_ENB); 3954 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3955 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3956 IDLE_DECISN_TIMER_DEFAULT_1MS); 3957 } else 3958 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3959 3960 /* Reprogram the station address. */ 3961 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3962 CSR_WRITE_4(sc, ALC_PAR0, 3963 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3964 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3965 /* 3966 * Clear WOL status and disable all WOL feature as WOL 3967 * would interfere Rx operation under normal environments. 3968 */ 3969 CSR_READ_4(sc, ALC_WOL_CFG); 3970 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3971 /* Set Tx descriptor base addresses. */ 3972 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3973 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3974 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3975 /* We don't use high priority ring. */ 3976 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3977 /* Set Tx descriptor counter. */ 3978 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3979 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3980 /* Set Rx descriptor base addresses. */ 3981 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3982 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3983 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3984 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3985 /* We use one Rx ring. */ 3986 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3987 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3988 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3989 } 3990 /* Set Rx descriptor counter. */ 3991 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3992 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3993 3994 /* 3995 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3996 * if it do not fit the buffer size. Rx return descriptor holds 3997 * a counter that indicates how many fragments were made by the 3998 * hardware. The buffer size should be multiple of 8 bytes. 3999 * Since hardware has limit on the size of buffer size, always 4000 * use the maximum value. 4001 * For strict-alignment architectures make sure to reduce buffer 4002 * size by 8 bytes to make room for alignment fixup. 4003 */ 4004#ifndef __NO_STRICT_ALIGNMENT 4005 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4006#else 4007 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4008#endif 4009 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4010 4011 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4012 /* Set Rx return descriptor base addresses. */ 4013 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4014 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4015 /* We use one Rx return ring. */ 4016 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4017 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4018 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4019 } 4020 /* Set Rx return descriptor counter. */ 4021 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4022 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4023 paddr = sc->alc_rdata.alc_cmb_paddr; 4024 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4025 paddr = sc->alc_rdata.alc_smb_paddr; 4026 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4027 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4028 4029 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4030 /* Reconfigure SRAM - Vendor magic. */ 4031 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4032 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4033 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4034 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4035 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4036 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4037 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4038 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4039 } 4040 4041 /* Tell hardware that we're ready to load DMA blocks. */ 4042 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4043 4044 /* Configure interrupt moderation timer. */ 4045 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4046 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4047 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4048 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4049 /* 4050 * We don't want to automatic interrupt clear as task queue 4051 * for the interrupt should know interrupt status. 4052 */ 4053 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4054 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4055 reg |= MASTER_SA_TIMER_ENB; 4056 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4057 reg |= MASTER_IM_RX_TIMER_ENB; 4058 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4059 ALC_USECS(sc->alc_int_tx_mod) != 0) 4060 reg |= MASTER_IM_TX_TIMER_ENB; 4061 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4062 /* 4063 * Disable interrupt re-trigger timer. We don't want automatic 4064 * re-triggering of un-ACKed interrupts. 4065 */ 4066 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4067 /* Configure CMB. */ 4068 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4069 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4070 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4071 ALC_USECS(sc->alc_int_tx_mod)); 4072 } else { 4073 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4074 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4075 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4076 } else 4077 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4078 } 4079 /* 4080 * Hardware can be configured to issue SMB interrupt based 4081 * on programmed interval. Since there is a callout that is 4082 * invoked for every hz in driver we use that instead of 4083 * relying on periodic SMB interrupt. 4084 */ 4085 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4086 /* Clear MAC statistics. */ 4087 alc_stats_clear(sc); 4088 4089 /* 4090 * Always use maximum frame size that controller can support. 4091 * Otherwise received frames that has larger frame length 4092 * than alc(4) MTU would be silently dropped in hardware. This 4093 * would make path-MTU discovery hard as sender wouldn't get 4094 * any responses from receiver. alc(4) supports 4095 * multi-fragmented frames on Rx path so it has no issue on 4096 * assembling fragmented frames. Using maximum frame size also 4097 * removes the need to reinitialize hardware when interface 4098 * MTU configuration was changed. 4099 * 4100 * Be conservative in what you do, be liberal in what you 4101 * accept from others - RFC 793. 4102 */ 4103 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4104 4105 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4106 /* Disable header split(?) */ 4107 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4108 4109 /* Configure IPG/IFG parameters. */ 4110 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4111 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4112 IPG_IFG_IPGT_MASK) | 4113 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4114 IPG_IFG_MIFG_MASK) | 4115 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4116 IPG_IFG_IPG1_MASK) | 4117 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4118 IPG_IFG_IPG2_MASK)); 4119 /* Set parameters for half-duplex media. */ 4120 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4121 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4122 HDPX_CFG_LCOL_MASK) | 4123 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4124 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4125 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4126 HDPX_CFG_ABEBT_MASK) | 4127 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4128 HDPX_CFG_JAMIPG_MASK)); 4129 } 4130 4131 /* 4132 * Set TSO/checksum offload threshold. For frames that is 4133 * larger than this threshold, hardware wouldn't do 4134 * TSO/checksum offloading. 4135 */ 4136 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4137 TSO_OFFLOAD_THRESH_MASK; 4138 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4139 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4140 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4141 /* Configure TxQ. */ 4142 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4143 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4144 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4145 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4146 reg >>= 1; 4147 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4148 TXQ_CFG_TD_BURST_MASK; 4149 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4150 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4151 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4152 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4153 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4154 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4155 HQTD_CFG_BURST_ENB); 4156 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4157 reg = WRR_PRI_RESTRICT_NONE; 4158 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4159 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4160 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4161 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4162 CSR_WRITE_4(sc, ALC_WRR, reg); 4163 } else { 4164 /* Configure Rx free descriptor pre-fetching. */ 4165 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4166 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4167 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4168 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4169 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4170 } 4171 4172 /* 4173 * Configure flow control parameters. 4174 * XON : 80% of Rx FIFO 4175 * XOFF : 30% of Rx FIFO 4176 */ 4177 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4178 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4179 reg &= SRAM_RX_FIFO_LEN_MASK; 4180 reg *= 8; 4181 if (reg > 8 * 1024) 4182 reg -= RX_FIFO_PAUSE_816X_RSVD; 4183 else 4184 reg -= RX_BUF_SIZE_MAX; 4185 reg /= 8; 4186 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4187 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4188 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4189 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4190 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4191 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4192 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4193 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4194 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4195 rxf_hi = (reg * 8) / 10; 4196 rxf_lo = (reg * 3) / 10; 4197 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4198 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4199 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4200 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4201 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4202 } 4203 4204 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4205 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4206 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4207 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4208 } 4209 4210 /* Configure RxQ. */ 4211 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4212 RXQ_CFG_RD_BURST_MASK; 4213 reg |= RXQ_CFG_RSS_MODE_DIS; 4214 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4215 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4216 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4217 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4218 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4219 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4220 } else { 4221 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4222 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4223 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4224 } 4225 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4226 4227 /* Configure DMA parameters. */ 4228 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4229 reg |= sc->alc_rcb; 4230 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4231 reg |= DMA_CFG_CMB_ENB; 4232 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4233 reg |= DMA_CFG_SMB_ENB; 4234 else 4235 reg |= DMA_CFG_SMB_DIS; 4236 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4237 DMA_CFG_RD_BURST_SHIFT; 4238 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4239 DMA_CFG_WR_BURST_SHIFT; 4240 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4241 DMA_CFG_RD_DELAY_CNT_MASK; 4242 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4243 DMA_CFG_WR_DELAY_CNT_MASK; 4244 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4245 switch (AR816X_REV(sc->alc_rev)) { 4246 case AR816X_REV_A0: 4247 case AR816X_REV_A1: 4248 reg |= DMA_CFG_RD_CHNL_SEL_2; 4249 break; 4250 case AR816X_REV_B0: 4251 /* FALLTHROUGH */ 4252 default: 4253 reg |= DMA_CFG_RD_CHNL_SEL_4; 4254 break; 4255 } 4256 } 4257 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4258 4259 /* 4260 * Configure Tx/Rx MACs. 4261 * - Auto-padding for short frames. 4262 * - Enable CRC generation. 4263 * Actual reconfiguration of MAC for resolved speed/duplex 4264 * is followed after detection of link establishment. 4265 * AR813x/AR815x always does checksum computation regardless 4266 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4267 * have bug in protocol field in Rx return structure so 4268 * these controllers can't handle fragmented frames. Disable 4269 * Rx checksum offloading until there is a newer controller 4270 * that has sane implementation. 4271 */ 4272 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4273 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4274 MAC_CFG_PREAMBLE_MASK); 4275 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4276 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4277 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4278 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4279 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4280 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4281 reg |= MAC_CFG_SPEED_10_100; 4282 else 4283 reg |= MAC_CFG_SPEED_1000; 4284 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4285 4286 /* Set up the receive filter. */ 4287 alc_rxfilter(sc); 4288 alc_rxvlan(sc); 4289 4290 /* Acknowledge all pending interrupts and clear it. */ 4291 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4292 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4293 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4294 4295 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4296 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4297 4298 sc->alc_flags &= ~ALC_FLAG_LINK; 4299 /* Switch to the current media. */ 4300 alc_mediachange_locked(sc); 4301 4302 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4303} 4304 4305static void 4306alc_stop(struct alc_softc *sc) 4307{ 4308 struct ifnet *ifp; 4309 struct alc_txdesc *txd; 4310 struct alc_rxdesc *rxd; 4311 uint32_t reg; 4312 int i; 4313 4314 ALC_LOCK_ASSERT(sc); 4315 /* 4316 * Mark the interface down and cancel the watchdog timer. 4317 */ 4318 ifp = sc->alc_ifp; 4319 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4320 sc->alc_flags &= ~ALC_FLAG_LINK; 4321 callout_stop(&sc->alc_tick_ch); 4322 sc->alc_watchdog_timer = 0; 4323 alc_stats_update(sc); 4324 /* Disable interrupts. */ 4325 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4326 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4327 /* Disable DMA. */ 4328 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4329 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4330 reg |= DMA_CFG_SMB_DIS; 4331 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4332 DELAY(1000); 4333 /* Stop Rx/Tx MACs. */ 4334 alc_stop_mac(sc); 4335 /* Disable interrupts which might be touched in taskq handler. */ 4336 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4337 /* Disable L0s/L1s */ 4338 alc_aspm(sc, 0, IFM_UNKNOWN); 4339 /* Reclaim Rx buffers that have been processed. */ 4340 if (sc->alc_cdata.alc_rxhead != NULL) 4341 m_freem(sc->alc_cdata.alc_rxhead); 4342 ALC_RXCHAIN_RESET(sc); 4343 /* 4344 * Free Tx/Rx mbufs still in the queues. 4345 */ 4346 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4347 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4348 if (rxd->rx_m != NULL) { 4349 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4350 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4351 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4352 rxd->rx_dmamap); 4353 m_freem(rxd->rx_m); 4354 rxd->rx_m = NULL; 4355 } 4356 } 4357 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4358 txd = &sc->alc_cdata.alc_txdesc[i]; 4359 if (txd->tx_m != NULL) { 4360 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4361 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4362 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4363 txd->tx_dmamap); 4364 m_freem(txd->tx_m); 4365 txd->tx_m = NULL; 4366 } 4367 } 4368} 4369 4370static void 4371alc_stop_mac(struct alc_softc *sc) 4372{ 4373 uint32_t reg; 4374 int i; 4375 4376 alc_stop_queue(sc); 4377 /* Disable Rx/Tx MAC. */ 4378 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4379 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4380 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4381 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4382 } 4383 for (i = ALC_TIMEOUT; i > 0; i--) { 4384 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4385 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4386 break; 4387 DELAY(10); 4388 } 4389 if (i == 0) 4390 device_printf(sc->alc_dev, 4391 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4392} 4393 4394static void 4395alc_start_queue(struct alc_softc *sc) 4396{ 4397 uint32_t qcfg[] = { 4398 0, 4399 RXQ_CFG_QUEUE0_ENB, 4400 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4401 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4402 RXQ_CFG_ENB 4403 }; 4404 uint32_t cfg; 4405 4406 ALC_LOCK_ASSERT(sc); 4407 4408 /* Enable RxQ. */ 4409 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4410 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4411 cfg &= ~RXQ_CFG_ENB; 4412 cfg |= qcfg[1]; 4413 } else 4414 cfg |= RXQ_CFG_QUEUE0_ENB; 4415 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4416 /* Enable TxQ. */ 4417 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4418 cfg |= TXQ_CFG_ENB; 4419 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4420} 4421 4422static void 4423alc_stop_queue(struct alc_softc *sc) 4424{ 4425 uint32_t reg; 4426 int i; 4427 4428 /* Disable RxQ. */ 4429 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4430 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4431 if ((reg & RXQ_CFG_ENB) != 0) { 4432 reg &= ~RXQ_CFG_ENB; 4433 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4434 } 4435 } else { 4436 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4437 reg &= ~RXQ_CFG_QUEUE0_ENB; 4438 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4439 } 4440 } 4441 /* Disable TxQ. */ 4442 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4443 if ((reg & TXQ_CFG_ENB) != 0) { 4444 reg &= ~TXQ_CFG_ENB; 4445 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4446 } 4447 DELAY(40); 4448 for (i = ALC_TIMEOUT; i > 0; i--) { 4449 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4450 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4451 break; 4452 DELAY(10); 4453 } 4454 if (i == 0) 4455 device_printf(sc->alc_dev, 4456 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4457} 4458 4459static void 4460alc_init_tx_ring(struct alc_softc *sc) 4461{ 4462 struct alc_ring_data *rd; 4463 struct alc_txdesc *txd; 4464 int i; 4465 4466 ALC_LOCK_ASSERT(sc); 4467 4468 sc->alc_cdata.alc_tx_prod = 0; 4469 sc->alc_cdata.alc_tx_cons = 0; 4470 sc->alc_cdata.alc_tx_cnt = 0; 4471 4472 rd = &sc->alc_rdata; 4473 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4474 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4475 txd = &sc->alc_cdata.alc_txdesc[i]; 4476 txd->tx_m = NULL; 4477 } 4478 4479 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4480 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4481} 4482 4483static int 4484alc_init_rx_ring(struct alc_softc *sc) 4485{ 4486 struct alc_ring_data *rd; 4487 struct alc_rxdesc *rxd; 4488 int i; 4489 4490 ALC_LOCK_ASSERT(sc); 4491 4492 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4493 sc->alc_morework = 0; 4494 rd = &sc->alc_rdata; 4495 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4496 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4497 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4498 rxd->rx_m = NULL; 4499 rxd->rx_desc = &rd->alc_rx_ring[i]; 4500 if (alc_newbuf(sc, rxd) != 0) 4501 return (ENOBUFS); 4502 } 4503 4504 /* 4505 * Since controller does not update Rx descriptors, driver 4506 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4507 * is enough to ensure coherence. 4508 */ 4509 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4510 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4511 /* Let controller know availability of new Rx buffers. */ 4512 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4513 4514 return (0); 4515} 4516 4517static void 4518alc_init_rr_ring(struct alc_softc *sc) 4519{ 4520 struct alc_ring_data *rd; 4521 4522 ALC_LOCK_ASSERT(sc); 4523 4524 sc->alc_cdata.alc_rr_cons = 0; 4525 ALC_RXCHAIN_RESET(sc); 4526 4527 rd = &sc->alc_rdata; 4528 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4529 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4530 sc->alc_cdata.alc_rr_ring_map, 4531 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4532} 4533 4534static void 4535alc_init_cmb(struct alc_softc *sc) 4536{ 4537 struct alc_ring_data *rd; 4538 4539 ALC_LOCK_ASSERT(sc); 4540 4541 rd = &sc->alc_rdata; 4542 bzero(rd->alc_cmb, ALC_CMB_SZ); 4543 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4544 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4545} 4546 4547static void 4548alc_init_smb(struct alc_softc *sc) 4549{ 4550 struct alc_ring_data *rd; 4551 4552 ALC_LOCK_ASSERT(sc); 4553 4554 rd = &sc->alc_rdata; 4555 bzero(rd->alc_smb, ALC_SMB_SZ); 4556 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4558} 4559 4560static void 4561alc_rxvlan(struct alc_softc *sc) 4562{ 4563 struct ifnet *ifp; 4564 uint32_t reg; 4565 4566 ALC_LOCK_ASSERT(sc); 4567 4568 ifp = sc->alc_ifp; 4569 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4570 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4571 reg |= MAC_CFG_VLAN_TAG_STRIP; 4572 else 4573 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4574 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4575} 4576 4577static void 4578alc_rxfilter(struct alc_softc *sc) 4579{ 4580 struct ifnet *ifp; 4581 struct ifmultiaddr *ifma; 4582 uint32_t crc; 4583 uint32_t mchash[2]; 4584 uint32_t rxcfg; 4585 4586 ALC_LOCK_ASSERT(sc); 4587 4588 ifp = sc->alc_ifp; 4589 4590 bzero(mchash, sizeof(mchash)); 4591 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4592 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4593 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4594 rxcfg |= MAC_CFG_BCAST; 4595 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4596 if ((ifp->if_flags & IFF_PROMISC) != 0) 4597 rxcfg |= MAC_CFG_PROMISC; 4598 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4599 rxcfg |= MAC_CFG_ALLMULTI; 4600 mchash[0] = 0xFFFFFFFF; 4601 mchash[1] = 0xFFFFFFFF; 4602 goto chipit; 4603 } 4604 4605 if_maddr_rlock(ifp); 4606 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 4607 if (ifma->ifma_addr->sa_family != AF_LINK) 4608 continue; 4609 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 4610 ifma->ifma_addr), ETHER_ADDR_LEN); 4611 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4612 } 4613 if_maddr_runlock(ifp); 4614 4615chipit: 4616 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4617 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4618 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4619} 4620 4621static int 4622sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4623{ 4624 int error, value; 4625 4626 if (arg1 == NULL) 4627 return (EINVAL); 4628 value = *(int *)arg1; 4629 error = sysctl_handle_int(oidp, &value, 0, req); 4630 if (error || req->newptr == NULL) 4631 return (error); 4632 if (value < low || value > high) 4633 return (EINVAL); 4634 *(int *)arg1 = value; 4635 4636 return (0); 4637} 4638 4639static int 4640sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4641{ 4642 return (sysctl_int_range(oidp, arg1, arg2, req, 4643 ALC_PROC_MIN, ALC_PROC_MAX)); 4644} 4645 4646static int 4647sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4648{ 4649 4650 return (sysctl_int_range(oidp, arg1, arg2, req, 4651 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4652} 4653