1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pciercx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pciercx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCIERCX_DEFS_H__ 53#define __CVMX_PCIERCX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 61 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 62 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 63 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 64 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 65 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 66 cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", block_id); 67 return 0x0000000000000000ull; 68} 69#else 70#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull) 71#endif 72#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 73static inline uint64_t CVMX_PCIERCX_CFG001(unsigned long block_id) 74{ 75 if (!( 76 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 77 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 78 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 79 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 80 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 81 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 82 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 83 cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", block_id); 84 return 0x0000000000000004ull; 85} 86#else 87#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull) 88#endif 89#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 90static inline uint64_t CVMX_PCIERCX_CFG002(unsigned long block_id) 91{ 92 if (!( 93 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 94 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 95 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 96 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 97 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 98 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 99 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 100 cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", block_id); 101 return 0x0000000000000008ull; 102} 103#else 104#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull) 105#endif 106#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 107static inline uint64_t CVMX_PCIERCX_CFG003(unsigned long block_id) 108{ 109 if (!( 110 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 111 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 112 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 113 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 114 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 115 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 116 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 117 cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", block_id); 118 return 0x000000000000000Cull; 119} 120#else 121#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull) 122#endif 123#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124static inline uint64_t CVMX_PCIERCX_CFG004(unsigned long block_id) 125{ 126 if (!( 127 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 128 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 129 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 130 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 131 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 132 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 133 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 134 cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", block_id); 135 return 0x0000000000000010ull; 136} 137#else 138#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull) 139#endif 140#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 141static inline uint64_t CVMX_PCIERCX_CFG005(unsigned long block_id) 142{ 143 if (!( 144 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 145 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 146 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 148 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 149 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 150 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 151 cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", block_id); 152 return 0x0000000000000014ull; 153} 154#else 155#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull) 156#endif 157#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 158static inline uint64_t CVMX_PCIERCX_CFG006(unsigned long block_id) 159{ 160 if (!( 161 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 162 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 163 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 164 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 165 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 166 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 167 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 168 cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", block_id); 169 return 0x0000000000000018ull; 170} 171#else 172#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull) 173#endif 174#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175static inline uint64_t CVMX_PCIERCX_CFG007(unsigned long block_id) 176{ 177 if (!( 178 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 179 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 180 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 181 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 182 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 183 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 184 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 185 cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", block_id); 186 return 0x000000000000001Cull; 187} 188#else 189#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull) 190#endif 191#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192static inline uint64_t CVMX_PCIERCX_CFG008(unsigned long block_id) 193{ 194 if (!( 195 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 196 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 197 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 198 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 199 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 200 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 201 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 202 cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", block_id); 203 return 0x0000000000000020ull; 204} 205#else 206#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull) 207#endif 208#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 209static inline uint64_t CVMX_PCIERCX_CFG009(unsigned long block_id) 210{ 211 if (!( 212 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 214 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 215 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 216 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 217 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 218 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 219 cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", block_id); 220 return 0x0000000000000024ull; 221} 222#else 223#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull) 224#endif 225#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 226static inline uint64_t CVMX_PCIERCX_CFG010(unsigned long block_id) 227{ 228 if (!( 229 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 230 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 231 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 232 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 233 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 234 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 235 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 236 cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", block_id); 237 return 0x0000000000000028ull; 238} 239#else 240#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_PCIERCX_CFG011(unsigned long block_id) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 247 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 248 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 249 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 250 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 251 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 252 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 253 cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", block_id); 254 return 0x000000000000002Cull; 255} 256#else 257#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull) 258#endif 259#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260static inline uint64_t CVMX_PCIERCX_CFG012(unsigned long block_id) 261{ 262 if (!( 263 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 264 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 265 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 266 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 267 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 268 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 269 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 270 cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", block_id); 271 return 0x0000000000000030ull; 272} 273#else 274#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull) 275#endif 276#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277static inline uint64_t CVMX_PCIERCX_CFG013(unsigned long block_id) 278{ 279 if (!( 280 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 281 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 282 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 283 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 284 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 285 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 286 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 287 cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", block_id); 288 return 0x0000000000000034ull; 289} 290#else 291#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull) 292#endif 293#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 294static inline uint64_t CVMX_PCIERCX_CFG014(unsigned long block_id) 295{ 296 if (!( 297 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 298 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 299 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 300 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 301 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 302 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 303 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 304 cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", block_id); 305 return 0x0000000000000038ull; 306} 307#else 308#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull) 309#endif 310#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311static inline uint64_t CVMX_PCIERCX_CFG015(unsigned long block_id) 312{ 313 if (!( 314 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 315 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 316 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 317 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 318 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 319 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 320 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 321 cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", block_id); 322 return 0x000000000000003Cull; 323} 324#else 325#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull) 326#endif 327#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 328static inline uint64_t CVMX_PCIERCX_CFG016(unsigned long block_id) 329{ 330 if (!( 331 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 332 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 333 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 335 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 336 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 337 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 338 cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", block_id); 339 return 0x0000000000000040ull; 340} 341#else 342#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull) 343#endif 344#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 345static inline uint64_t CVMX_PCIERCX_CFG017(unsigned long block_id) 346{ 347 if (!( 348 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 349 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 350 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 351 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 352 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 353 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 354 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 355 cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", block_id); 356 return 0x0000000000000044ull; 357} 358#else 359#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull) 360#endif 361#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 362static inline uint64_t CVMX_PCIERCX_CFG020(unsigned long block_id) 363{ 364 if (!( 365 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 366 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 367 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 368 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 369 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 370 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 371 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 372 cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", block_id); 373 return 0x0000000000000050ull; 374} 375#else 376#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull) 377#endif 378#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379static inline uint64_t CVMX_PCIERCX_CFG021(unsigned long block_id) 380{ 381 if (!( 382 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 383 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 384 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 385 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 386 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 387 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 388 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 389 cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", block_id); 390 return 0x0000000000000054ull; 391} 392#else 393#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull) 394#endif 395#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 396static inline uint64_t CVMX_PCIERCX_CFG022(unsigned long block_id) 397{ 398 if (!( 399 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 400 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 401 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 402 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 403 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 404 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 405 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 406 cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", block_id); 407 return 0x0000000000000058ull; 408} 409#else 410#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull) 411#endif 412#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 413static inline uint64_t CVMX_PCIERCX_CFG023(unsigned long block_id) 414{ 415 if (!( 416 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 417 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 418 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 419 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 420 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 421 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 422 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 423 cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", block_id); 424 return 0x000000000000005Cull; 425} 426#else 427#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430static inline uint64_t CVMX_PCIERCX_CFG028(unsigned long block_id) 431{ 432 if (!( 433 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 434 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 435 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 436 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 437 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 438 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 439 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 440 cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", block_id); 441 return 0x0000000000000070ull; 442} 443#else 444#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull) 445#endif 446#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 447static inline uint64_t CVMX_PCIERCX_CFG029(unsigned long block_id) 448{ 449 if (!( 450 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 451 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 452 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 453 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 454 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 455 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 456 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 457 cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", block_id); 458 return 0x0000000000000074ull; 459} 460#else 461#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull) 462#endif 463#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 464static inline uint64_t CVMX_PCIERCX_CFG030(unsigned long block_id) 465{ 466 if (!( 467 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 468 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 469 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 470 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 471 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 472 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 473 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 474 cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", block_id); 475 return 0x0000000000000078ull; 476} 477#else 478#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull) 479#endif 480#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 481static inline uint64_t CVMX_PCIERCX_CFG031(unsigned long block_id) 482{ 483 if (!( 484 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 485 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 486 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 487 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 488 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 489 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 490 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 491 cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", block_id); 492 return 0x000000000000007Cull; 493} 494#else 495#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull) 496#endif 497#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498static inline uint64_t CVMX_PCIERCX_CFG032(unsigned long block_id) 499{ 500 if (!( 501 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 502 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 503 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 504 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 505 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 506 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 507 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 508 cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", block_id); 509 return 0x0000000000000080ull; 510} 511#else 512#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull) 513#endif 514#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 515static inline uint64_t CVMX_PCIERCX_CFG033(unsigned long block_id) 516{ 517 if (!( 518 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 519 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 520 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 521 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 522 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 523 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 524 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 525 cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", block_id); 526 return 0x0000000000000084ull; 527} 528#else 529#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull) 530#endif 531#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 532static inline uint64_t CVMX_PCIERCX_CFG034(unsigned long block_id) 533{ 534 if (!( 535 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 536 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 537 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 538 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 539 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 540 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 541 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 542 cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", block_id); 543 return 0x0000000000000088ull; 544} 545#else 546#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull) 547#endif 548#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 549static inline uint64_t CVMX_PCIERCX_CFG035(unsigned long block_id) 550{ 551 if (!( 552 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 553 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 554 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 555 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 556 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 557 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 558 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 559 cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", block_id); 560 return 0x000000000000008Cull; 561} 562#else 563#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull) 564#endif 565#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566static inline uint64_t CVMX_PCIERCX_CFG036(unsigned long block_id) 567{ 568 if (!( 569 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 570 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 571 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 572 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 573 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 574 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 575 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 576 cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", block_id); 577 return 0x0000000000000090ull; 578} 579#else 580#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull) 581#endif 582#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 583static inline uint64_t CVMX_PCIERCX_CFG037(unsigned long block_id) 584{ 585 if (!( 586 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 587 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 588 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 589 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 590 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 591 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 592 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 593 cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", block_id); 594 return 0x0000000000000094ull; 595} 596#else 597#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull) 598#endif 599#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 600static inline uint64_t CVMX_PCIERCX_CFG038(unsigned long block_id) 601{ 602 if (!( 603 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 604 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 605 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 606 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 607 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 608 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 609 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 610 cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", block_id); 611 return 0x0000000000000098ull; 612} 613#else 614#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull) 615#endif 616#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617static inline uint64_t CVMX_PCIERCX_CFG039(unsigned long block_id) 618{ 619 if (!( 620 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 621 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 622 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 623 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 624 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 625 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 626 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 627 cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", block_id); 628 return 0x000000000000009Cull; 629} 630#else 631#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull) 632#endif 633#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 634static inline uint64_t CVMX_PCIERCX_CFG040(unsigned long block_id) 635{ 636 if (!( 637 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 638 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 639 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 640 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 641 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 642 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 643 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 644 cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", block_id); 645 return 0x00000000000000A0ull; 646} 647#else 648#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull) 649#endif 650#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 651static inline uint64_t CVMX_PCIERCX_CFG041(unsigned long block_id) 652{ 653 if (!( 654 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 655 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 656 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 657 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 658 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 659 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 660 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 661 cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", block_id); 662 return 0x00000000000000A4ull; 663} 664#else 665#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull) 666#endif 667#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 668static inline uint64_t CVMX_PCIERCX_CFG042(unsigned long block_id) 669{ 670 if (!( 671 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 672 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 673 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 674 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 675 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 676 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 677 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 678 cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", block_id); 679 return 0x00000000000000A8ull; 680} 681#else 682#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull) 683#endif 684#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 685static inline uint64_t CVMX_PCIERCX_CFG064(unsigned long block_id) 686{ 687 if (!( 688 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 689 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 690 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 691 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 692 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 693 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 694 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 695 cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", block_id); 696 return 0x0000000000000100ull; 697} 698#else 699#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull) 700#endif 701#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 702static inline uint64_t CVMX_PCIERCX_CFG065(unsigned long block_id) 703{ 704 if (!( 705 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 706 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 707 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 708 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 709 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 710 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 711 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 712 cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", block_id); 713 return 0x0000000000000104ull; 714} 715#else 716#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull) 717#endif 718#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 719static inline uint64_t CVMX_PCIERCX_CFG066(unsigned long block_id) 720{ 721 if (!( 722 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 723 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 724 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 725 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 726 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 727 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 728 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 729 cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", block_id); 730 return 0x0000000000000108ull; 731} 732#else 733#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull) 734#endif 735#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 736static inline uint64_t CVMX_PCIERCX_CFG067(unsigned long block_id) 737{ 738 if (!( 739 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 740 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 741 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 742 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 743 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 744 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 745 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 746 cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", block_id); 747 return 0x000000000000010Cull; 748} 749#else 750#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull) 751#endif 752#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 753static inline uint64_t CVMX_PCIERCX_CFG068(unsigned long block_id) 754{ 755 if (!( 756 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 757 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 758 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 759 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 760 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 761 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 762 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 763 cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", block_id); 764 return 0x0000000000000110ull; 765} 766#else 767#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull) 768#endif 769#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 770static inline uint64_t CVMX_PCIERCX_CFG069(unsigned long block_id) 771{ 772 if (!( 773 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 774 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 775 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 776 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 777 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 778 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 779 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 780 cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", block_id); 781 return 0x0000000000000114ull; 782} 783#else 784#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull) 785#endif 786#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 787static inline uint64_t CVMX_PCIERCX_CFG070(unsigned long block_id) 788{ 789 if (!( 790 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 791 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 792 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 793 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 794 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 795 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 796 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 797 cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", block_id); 798 return 0x0000000000000118ull; 799} 800#else 801#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull) 802#endif 803#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 804static inline uint64_t CVMX_PCIERCX_CFG071(unsigned long block_id) 805{ 806 if (!( 807 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 808 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 809 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 810 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 811 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 812 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 813 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 814 cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", block_id); 815 return 0x000000000000011Cull; 816} 817#else 818#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull) 819#endif 820#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 821static inline uint64_t CVMX_PCIERCX_CFG072(unsigned long block_id) 822{ 823 if (!( 824 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 825 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 826 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 827 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 828 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 829 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 830 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 831 cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", block_id); 832 return 0x0000000000000120ull; 833} 834#else 835#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull) 836#endif 837#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 838static inline uint64_t CVMX_PCIERCX_CFG073(unsigned long block_id) 839{ 840 if (!( 841 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 842 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 843 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 844 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 845 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 846 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 847 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 848 cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", block_id); 849 return 0x0000000000000124ull; 850} 851#else 852#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull) 853#endif 854#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 855static inline uint64_t CVMX_PCIERCX_CFG074(unsigned long block_id) 856{ 857 if (!( 858 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 859 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 860 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 861 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 862 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 863 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 864 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 865 cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", block_id); 866 return 0x0000000000000128ull; 867} 868#else 869#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull) 870#endif 871#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 872static inline uint64_t CVMX_PCIERCX_CFG075(unsigned long block_id) 873{ 874 if (!( 875 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 876 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 877 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 878 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 879 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 880 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 881 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 882 cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", block_id); 883 return 0x000000000000012Cull; 884} 885#else 886#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull) 887#endif 888#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 889static inline uint64_t CVMX_PCIERCX_CFG076(unsigned long block_id) 890{ 891 if (!( 892 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 893 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 894 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 895 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 896 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 897 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 898 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 899 cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", block_id); 900 return 0x0000000000000130ull; 901} 902#else 903#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull) 904#endif 905#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 906static inline uint64_t CVMX_PCIERCX_CFG077(unsigned long block_id) 907{ 908 if (!( 909 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 910 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 911 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 912 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 913 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 914 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 915 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 916 cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", block_id); 917 return 0x0000000000000134ull; 918} 919#else 920#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull) 921#endif 922#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 923static inline uint64_t CVMX_PCIERCX_CFG448(unsigned long block_id) 924{ 925 if (!( 926 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 927 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 928 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 929 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 930 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 931 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 932 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 933 cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", block_id); 934 return 0x0000000000000700ull; 935} 936#else 937#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull) 938#endif 939#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 940static inline uint64_t CVMX_PCIERCX_CFG449(unsigned long block_id) 941{ 942 if (!( 943 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 944 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 945 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 946 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 947 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 948 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 949 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 950 cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", block_id); 951 return 0x0000000000000704ull; 952} 953#else 954#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull) 955#endif 956#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 957static inline uint64_t CVMX_PCIERCX_CFG450(unsigned long block_id) 958{ 959 if (!( 960 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 961 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 962 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 963 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 964 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 965 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 966 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 967 cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", block_id); 968 return 0x0000000000000708ull; 969} 970#else 971#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull) 972#endif 973#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 974static inline uint64_t CVMX_PCIERCX_CFG451(unsigned long block_id) 975{ 976 if (!( 977 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 978 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 979 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 980 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 981 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 982 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 983 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 984 cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", block_id); 985 return 0x000000000000070Cull; 986} 987#else 988#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull) 989#endif 990#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 991static inline uint64_t CVMX_PCIERCX_CFG452(unsigned long block_id) 992{ 993 if (!( 994 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 995 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 996 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 997 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 998 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 999 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1000 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1001 cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", block_id); 1002 return 0x0000000000000710ull; 1003} 1004#else 1005#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull) 1006#endif 1007#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1008static inline uint64_t CVMX_PCIERCX_CFG453(unsigned long block_id) 1009{ 1010 if (!( 1011 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1012 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1013 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1014 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1015 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1016 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1017 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1018 cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", block_id); 1019 return 0x0000000000000714ull; 1020} 1021#else 1022#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull) 1023#endif 1024#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1025static inline uint64_t CVMX_PCIERCX_CFG454(unsigned long block_id) 1026{ 1027 if (!( 1028 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1029 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1030 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1031 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1032 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1033 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1034 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1035 cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", block_id); 1036 return 0x0000000000000718ull; 1037} 1038#else 1039#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull) 1040#endif 1041#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1042static inline uint64_t CVMX_PCIERCX_CFG455(unsigned long block_id) 1043{ 1044 if (!( 1045 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1046 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1047 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1048 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1049 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1050 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1051 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1052 cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", block_id); 1053 return 0x000000000000071Cull; 1054} 1055#else 1056#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull) 1057#endif 1058#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1059static inline uint64_t CVMX_PCIERCX_CFG456(unsigned long block_id) 1060{ 1061 if (!( 1062 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1063 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1064 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1065 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1066 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1067 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1068 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1069 cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", block_id); 1070 return 0x0000000000000720ull; 1071} 1072#else 1073#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull) 1074#endif 1075#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1076static inline uint64_t CVMX_PCIERCX_CFG458(unsigned long block_id) 1077{ 1078 if (!( 1079 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1080 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1081 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1082 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1083 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1084 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1085 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1086 cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", block_id); 1087 return 0x0000000000000728ull; 1088} 1089#else 1090#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull) 1091#endif 1092#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1093static inline uint64_t CVMX_PCIERCX_CFG459(unsigned long block_id) 1094{ 1095 if (!( 1096 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1097 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1098 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1099 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1100 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1101 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1102 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1103 cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", block_id); 1104 return 0x000000000000072Cull; 1105} 1106#else 1107#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull) 1108#endif 1109#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1110static inline uint64_t CVMX_PCIERCX_CFG460(unsigned long block_id) 1111{ 1112 if (!( 1113 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1114 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1115 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1116 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1117 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1118 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1119 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1120 cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", block_id); 1121 return 0x0000000000000730ull; 1122} 1123#else 1124#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull) 1125#endif 1126#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1127static inline uint64_t CVMX_PCIERCX_CFG461(unsigned long block_id) 1128{ 1129 if (!( 1130 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1131 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1132 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1133 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1134 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1135 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1136 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1137 cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", block_id); 1138 return 0x0000000000000734ull; 1139} 1140#else 1141#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull) 1142#endif 1143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1144static inline uint64_t CVMX_PCIERCX_CFG462(unsigned long block_id) 1145{ 1146 if (!( 1147 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1148 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1149 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1150 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1151 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1152 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1153 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1154 cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", block_id); 1155 return 0x0000000000000738ull; 1156} 1157#else 1158#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull) 1159#endif 1160#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1161static inline uint64_t CVMX_PCIERCX_CFG463(unsigned long block_id) 1162{ 1163 if (!( 1164 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1165 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1166 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1167 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1168 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1169 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1170 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1171 cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", block_id); 1172 return 0x000000000000073Cull; 1173} 1174#else 1175#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull) 1176#endif 1177#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1178static inline uint64_t CVMX_PCIERCX_CFG464(unsigned long block_id) 1179{ 1180 if (!( 1181 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1182 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1183 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1184 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1185 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1186 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1187 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1188 cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", block_id); 1189 return 0x0000000000000740ull; 1190} 1191#else 1192#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull) 1193#endif 1194#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1195static inline uint64_t CVMX_PCIERCX_CFG465(unsigned long block_id) 1196{ 1197 if (!( 1198 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1199 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1200 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1201 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1202 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1203 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1204 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1205 cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", block_id); 1206 return 0x0000000000000744ull; 1207} 1208#else 1209#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull) 1210#endif 1211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1212static inline uint64_t CVMX_PCIERCX_CFG466(unsigned long block_id) 1213{ 1214 if (!( 1215 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1216 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1217 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1218 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1219 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1220 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1221 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1222 cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", block_id); 1223 return 0x0000000000000748ull; 1224} 1225#else 1226#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull) 1227#endif 1228#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1229static inline uint64_t CVMX_PCIERCX_CFG467(unsigned long block_id) 1230{ 1231 if (!( 1232 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1233 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1234 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1235 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1236 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1237 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1238 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1239 cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", block_id); 1240 return 0x000000000000074Cull; 1241} 1242#else 1243#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull) 1244#endif 1245#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1246static inline uint64_t CVMX_PCIERCX_CFG468(unsigned long block_id) 1247{ 1248 if (!( 1249 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1250 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1251 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1252 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1253 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1254 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1255 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1256 cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", block_id); 1257 return 0x0000000000000750ull; 1258} 1259#else 1260#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull) 1261#endif 1262#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1263static inline uint64_t CVMX_PCIERCX_CFG490(unsigned long block_id) 1264{ 1265 if (!( 1266 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1267 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1268 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1269 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1270 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1271 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1272 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1273 cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", block_id); 1274 return 0x00000000000007A8ull; 1275} 1276#else 1277#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull) 1278#endif 1279#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1280static inline uint64_t CVMX_PCIERCX_CFG491(unsigned long block_id) 1281{ 1282 if (!( 1283 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1284 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1285 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1286 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1287 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1288 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1289 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1290 cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", block_id); 1291 return 0x00000000000007ACull; 1292} 1293#else 1294#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull) 1295#endif 1296#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1297static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long block_id) 1298{ 1299 if (!( 1300 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1301 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1302 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1303 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1304 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1305 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1306 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1307 cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", block_id); 1308 return 0x00000000000007B0ull; 1309} 1310#else 1311#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull) 1312#endif 1313#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1314static inline uint64_t CVMX_PCIERCX_CFG515(unsigned long block_id) 1315{ 1316 if (!( 1317 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1318 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1319 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1320 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1321 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1322 cvmx_warn("CVMX_PCIERCX_CFG515(%lu) is invalid on this chip\n", block_id); 1323 return 0x000000000000080Cull; 1324} 1325#else 1326#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull) 1327#endif 1328#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1329static inline uint64_t CVMX_PCIERCX_CFG516(unsigned long block_id) 1330{ 1331 if (!( 1332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1334 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1335 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1336 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1337 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1338 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1339 cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", block_id); 1340 return 0x0000000000000810ull; 1341} 1342#else 1343#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull) 1344#endif 1345#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1346static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long block_id) 1347{ 1348 if (!( 1349 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1350 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1351 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1352 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1353 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1354 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1355 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1356 cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", block_id); 1357 return 0x0000000000000814ull; 1358} 1359#else 1360#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull) 1361#endif 1362 1363/** 1364 * cvmx_pcierc#_cfg000 1365 * 1366 * PCIE_CFG000 = First 32-bits of PCIE type 1 config space (Device ID and Vendor ID Register) 1367 * 1368 */ 1369union cvmx_pciercx_cfg000 { 1370 uint32_t u32; 1371 struct cvmx_pciercx_cfg000_s { 1372#ifdef __BIG_ENDIAN_BITFIELD 1373 uint32_t devid : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR 1374 However, the application must not change this field. */ 1375 uint32_t vendid : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR 1376 However, the application must not change this field. */ 1377#else 1378 uint32_t vendid : 16; 1379 uint32_t devid : 16; 1380#endif 1381 } s; 1382 struct cvmx_pciercx_cfg000_s cn52xx; 1383 struct cvmx_pciercx_cfg000_s cn52xxp1; 1384 struct cvmx_pciercx_cfg000_s cn56xx; 1385 struct cvmx_pciercx_cfg000_s cn56xxp1; 1386 struct cvmx_pciercx_cfg000_s cn61xx; 1387 struct cvmx_pciercx_cfg000_s cn63xx; 1388 struct cvmx_pciercx_cfg000_s cn63xxp1; 1389 struct cvmx_pciercx_cfg000_s cn66xx; 1390 struct cvmx_pciercx_cfg000_s cn68xx; 1391 struct cvmx_pciercx_cfg000_s cn68xxp1; 1392 struct cvmx_pciercx_cfg000_s cnf71xx; 1393}; 1394typedef union cvmx_pciercx_cfg000 cvmx_pciercx_cfg000_t; 1395 1396/** 1397 * cvmx_pcierc#_cfg001 1398 * 1399 * PCIE_CFG001 = Second 32-bits of PCIE type 1 config space (Command/Status Register) 1400 * 1401 */ 1402union cvmx_pciercx_cfg001 { 1403 uint32_t u32; 1404 struct cvmx_pciercx_cfg001_s { 1405#ifdef __BIG_ENDIAN_BITFIELD 1406 uint32_t dpe : 1; /**< Detected Parity Error */ 1407 uint32_t sse : 1; /**< Signaled System Error */ 1408 uint32_t rma : 1; /**< Received Master Abort */ 1409 uint32_t rta : 1; /**< Received Target Abort */ 1410 uint32_t sta : 1; /**< Signaled Target Abort */ 1411 uint32_t devt : 2; /**< DEVSEL Timing 1412 Not applicable for PCI Express. Hardwired to 0. */ 1413 uint32_t mdpe : 1; /**< Master Data Parity Error */ 1414 uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1415 Not applicable for PCI Express. Hardwired to 0. */ 1416 uint32_t reserved_22_22 : 1; 1417 uint32_t m66 : 1; /**< 66 MHz Capable 1418 Not applicable for PCI Express. Hardwired to 0. */ 1419 uint32_t cl : 1; /**< Capabilities List 1420 Indicates presence of an extended capability item. 1421 Hardwired to 1. */ 1422 uint32_t i_stat : 1; /**< INTx Status */ 1423 uint32_t reserved_11_18 : 8; 1424 uint32_t i_dis : 1; /**< INTx Assertion Disable */ 1425 uint32_t fbbe : 1; /**< Fast Back-to-Back Enable 1426 Not applicable for PCI Express. Must be hardwired to 0. */ 1427 uint32_t see : 1; /**< SERR# Enable */ 1428 uint32_t ids_wcc : 1; /**< IDSEL Stepping/Wait Cycle Control 1429 Not applicable for PCI Express. Must be hardwired to 0 */ 1430 uint32_t per : 1; /**< Parity Error Response */ 1431 uint32_t vps : 1; /**< VGA Palette Snoop 1432 Not applicable for PCI Express. Must be hardwired to 0. */ 1433 uint32_t mwice : 1; /**< Memory Write and Invalidate 1434 Not applicable for PCI Express. Must be hardwired to 0. */ 1435 uint32_t scse : 1; /**< Special Cycle Enable 1436 Not applicable for PCI Express. Must be hardwired to 0. */ 1437 uint32_t me : 1; /**< Bus Master Enable */ 1438 uint32_t msae : 1; /**< Memory Space Enable */ 1439 uint32_t isae : 1; /**< I/O Space Enable */ 1440#else 1441 uint32_t isae : 1; 1442 uint32_t msae : 1; 1443 uint32_t me : 1; 1444 uint32_t scse : 1; 1445 uint32_t mwice : 1; 1446 uint32_t vps : 1; 1447 uint32_t per : 1; 1448 uint32_t ids_wcc : 1; 1449 uint32_t see : 1; 1450 uint32_t fbbe : 1; 1451 uint32_t i_dis : 1; 1452 uint32_t reserved_11_18 : 8; 1453 uint32_t i_stat : 1; 1454 uint32_t cl : 1; 1455 uint32_t m66 : 1; 1456 uint32_t reserved_22_22 : 1; 1457 uint32_t fbb : 1; 1458 uint32_t mdpe : 1; 1459 uint32_t devt : 2; 1460 uint32_t sta : 1; 1461 uint32_t rta : 1; 1462 uint32_t rma : 1; 1463 uint32_t sse : 1; 1464 uint32_t dpe : 1; 1465#endif 1466 } s; 1467 struct cvmx_pciercx_cfg001_s cn52xx; 1468 struct cvmx_pciercx_cfg001_s cn52xxp1; 1469 struct cvmx_pciercx_cfg001_s cn56xx; 1470 struct cvmx_pciercx_cfg001_s cn56xxp1; 1471 struct cvmx_pciercx_cfg001_s cn61xx; 1472 struct cvmx_pciercx_cfg001_s cn63xx; 1473 struct cvmx_pciercx_cfg001_s cn63xxp1; 1474 struct cvmx_pciercx_cfg001_s cn66xx; 1475 struct cvmx_pciercx_cfg001_s cn68xx; 1476 struct cvmx_pciercx_cfg001_s cn68xxp1; 1477 struct cvmx_pciercx_cfg001_s cnf71xx; 1478}; 1479typedef union cvmx_pciercx_cfg001 cvmx_pciercx_cfg001_t; 1480 1481/** 1482 * cvmx_pcierc#_cfg002 1483 * 1484 * PCIE_CFG002 = Third 32-bits of PCIE type 1 config space (Revision ID/Class Code Register) 1485 * 1486 */ 1487union cvmx_pciercx_cfg002 { 1488 uint32_t u32; 1489 struct cvmx_pciercx_cfg002_s { 1490#ifdef __BIG_ENDIAN_BITFIELD 1491 uint32_t bcc : 8; /**< Base Class Code, writable through PEM(0..1)_CFG_WR 1492 However, the application must not change this field. */ 1493 uint32_t sc : 8; /**< Subclass Code, writable through PEM(0..1)_CFG_WR 1494 However, the application must not change this field. */ 1495 uint32_t pi : 8; /**< Programming Interface, writable through PEM(0..1)_CFG_WR 1496 However, the application must not change this field. */ 1497 uint32_t rid : 8; /**< Revision ID, writable through PEM(0..1)_CFG_WR 1498 However, the application must not change this field. */ 1499#else 1500 uint32_t rid : 8; 1501 uint32_t pi : 8; 1502 uint32_t sc : 8; 1503 uint32_t bcc : 8; 1504#endif 1505 } s; 1506 struct cvmx_pciercx_cfg002_s cn52xx; 1507 struct cvmx_pciercx_cfg002_s cn52xxp1; 1508 struct cvmx_pciercx_cfg002_s cn56xx; 1509 struct cvmx_pciercx_cfg002_s cn56xxp1; 1510 struct cvmx_pciercx_cfg002_s cn61xx; 1511 struct cvmx_pciercx_cfg002_s cn63xx; 1512 struct cvmx_pciercx_cfg002_s cn63xxp1; 1513 struct cvmx_pciercx_cfg002_s cn66xx; 1514 struct cvmx_pciercx_cfg002_s cn68xx; 1515 struct cvmx_pciercx_cfg002_s cn68xxp1; 1516 struct cvmx_pciercx_cfg002_s cnf71xx; 1517}; 1518typedef union cvmx_pciercx_cfg002 cvmx_pciercx_cfg002_t; 1519 1520/** 1521 * cvmx_pcierc#_cfg003 1522 * 1523 * PCIE_CFG003 = Fourth 32-bits of PCIE type 1 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register) 1524 * 1525 */ 1526union cvmx_pciercx_cfg003 { 1527 uint32_t u32; 1528 struct cvmx_pciercx_cfg003_s { 1529#ifdef __BIG_ENDIAN_BITFIELD 1530 uint32_t bist : 8; /**< The BIST register functions are not supported. 1531 All 8 bits of the BIST register are hardwired to 0. */ 1532 uint32_t mfd : 1; /**< Multi Function Device 1533 The Multi Function Device bit is writable through PEM(0..1)_CFG_WR. 1534 However, this is a single function device. Therefore, the 1535 application must not write a 1 to this bit. */ 1536 uint32_t chf : 7; /**< Configuration Header Format 1537 Hardwired to 1. */ 1538 uint32_t lt : 8; /**< Master Latency Timer 1539 Not applicable for PCI Express, hardwired to 0. */ 1540 uint32_t cls : 8; /**< Cache Line Size 1541 The Cache Line Size register is RW for legacy compatibility 1542 purposes and is not applicable to PCI Express device 1543 functionality. */ 1544#else 1545 uint32_t cls : 8; 1546 uint32_t lt : 8; 1547 uint32_t chf : 7; 1548 uint32_t mfd : 1; 1549 uint32_t bist : 8; 1550#endif 1551 } s; 1552 struct cvmx_pciercx_cfg003_s cn52xx; 1553 struct cvmx_pciercx_cfg003_s cn52xxp1; 1554 struct cvmx_pciercx_cfg003_s cn56xx; 1555 struct cvmx_pciercx_cfg003_s cn56xxp1; 1556 struct cvmx_pciercx_cfg003_s cn61xx; 1557 struct cvmx_pciercx_cfg003_s cn63xx; 1558 struct cvmx_pciercx_cfg003_s cn63xxp1; 1559 struct cvmx_pciercx_cfg003_s cn66xx; 1560 struct cvmx_pciercx_cfg003_s cn68xx; 1561 struct cvmx_pciercx_cfg003_s cn68xxp1; 1562 struct cvmx_pciercx_cfg003_s cnf71xx; 1563}; 1564typedef union cvmx_pciercx_cfg003 cvmx_pciercx_cfg003_t; 1565 1566/** 1567 * cvmx_pcierc#_cfg004 1568 * 1569 * PCIE_CFG004 = Fifth 32-bits of PCIE type 1 config space (Base Address Register 0 - Low) 1570 * 1571 */ 1572union cvmx_pciercx_cfg004 { 1573 uint32_t u32; 1574 struct cvmx_pciercx_cfg004_s { 1575#ifdef __BIG_ENDIAN_BITFIELD 1576 uint32_t reserved_0_31 : 32; 1577#else 1578 uint32_t reserved_0_31 : 32; 1579#endif 1580 } s; 1581 struct cvmx_pciercx_cfg004_s cn52xx; 1582 struct cvmx_pciercx_cfg004_s cn52xxp1; 1583 struct cvmx_pciercx_cfg004_s cn56xx; 1584 struct cvmx_pciercx_cfg004_s cn56xxp1; 1585 struct cvmx_pciercx_cfg004_s cn61xx; 1586 struct cvmx_pciercx_cfg004_s cn63xx; 1587 struct cvmx_pciercx_cfg004_s cn63xxp1; 1588 struct cvmx_pciercx_cfg004_s cn66xx; 1589 struct cvmx_pciercx_cfg004_s cn68xx; 1590 struct cvmx_pciercx_cfg004_s cn68xxp1; 1591 struct cvmx_pciercx_cfg004_s cnf71xx; 1592}; 1593typedef union cvmx_pciercx_cfg004 cvmx_pciercx_cfg004_t; 1594 1595/** 1596 * cvmx_pcierc#_cfg005 1597 * 1598 * PCIE_CFG005 = Sixth 32-bits of PCIE type 1 config space (Base Address Register 0 - High) 1599 * 1600 */ 1601union cvmx_pciercx_cfg005 { 1602 uint32_t u32; 1603 struct cvmx_pciercx_cfg005_s { 1604#ifdef __BIG_ENDIAN_BITFIELD 1605 uint32_t reserved_0_31 : 32; 1606#else 1607 uint32_t reserved_0_31 : 32; 1608#endif 1609 } s; 1610 struct cvmx_pciercx_cfg005_s cn52xx; 1611 struct cvmx_pciercx_cfg005_s cn52xxp1; 1612 struct cvmx_pciercx_cfg005_s cn56xx; 1613 struct cvmx_pciercx_cfg005_s cn56xxp1; 1614 struct cvmx_pciercx_cfg005_s cn61xx; 1615 struct cvmx_pciercx_cfg005_s cn63xx; 1616 struct cvmx_pciercx_cfg005_s cn63xxp1; 1617 struct cvmx_pciercx_cfg005_s cn66xx; 1618 struct cvmx_pciercx_cfg005_s cn68xx; 1619 struct cvmx_pciercx_cfg005_s cn68xxp1; 1620 struct cvmx_pciercx_cfg005_s cnf71xx; 1621}; 1622typedef union cvmx_pciercx_cfg005 cvmx_pciercx_cfg005_t; 1623 1624/** 1625 * cvmx_pcierc#_cfg006 1626 * 1627 * PCIE_CFG006 = Seventh 32-bits of PCIE type 1 config space (Bus Number Registers) 1628 * 1629 */ 1630union cvmx_pciercx_cfg006 { 1631 uint32_t u32; 1632 struct cvmx_pciercx_cfg006_s { 1633#ifdef __BIG_ENDIAN_BITFIELD 1634 uint32_t slt : 8; /**< Secondary Latency Timer 1635 Not applicable to PCI Express, hardwired to 0x00. */ 1636 uint32_t subbnum : 8; /**< Subordinate Bus Number */ 1637 uint32_t sbnum : 8; /**< Secondary Bus Number */ 1638 uint32_t pbnum : 8; /**< Primary Bus Number */ 1639#else 1640 uint32_t pbnum : 8; 1641 uint32_t sbnum : 8; 1642 uint32_t subbnum : 8; 1643 uint32_t slt : 8; 1644#endif 1645 } s; 1646 struct cvmx_pciercx_cfg006_s cn52xx; 1647 struct cvmx_pciercx_cfg006_s cn52xxp1; 1648 struct cvmx_pciercx_cfg006_s cn56xx; 1649 struct cvmx_pciercx_cfg006_s cn56xxp1; 1650 struct cvmx_pciercx_cfg006_s cn61xx; 1651 struct cvmx_pciercx_cfg006_s cn63xx; 1652 struct cvmx_pciercx_cfg006_s cn63xxp1; 1653 struct cvmx_pciercx_cfg006_s cn66xx; 1654 struct cvmx_pciercx_cfg006_s cn68xx; 1655 struct cvmx_pciercx_cfg006_s cn68xxp1; 1656 struct cvmx_pciercx_cfg006_s cnf71xx; 1657}; 1658typedef union cvmx_pciercx_cfg006 cvmx_pciercx_cfg006_t; 1659 1660/** 1661 * cvmx_pcierc#_cfg007 1662 * 1663 * PCIE_CFG007 = Eighth 32-bits of PCIE type 1 config space (IO Base and IO Limit/Secondary Status Register) 1664 * 1665 */ 1666union cvmx_pciercx_cfg007 { 1667 uint32_t u32; 1668 struct cvmx_pciercx_cfg007_s { 1669#ifdef __BIG_ENDIAN_BITFIELD 1670 uint32_t dpe : 1; /**< Detected Parity Error */ 1671 uint32_t sse : 1; /**< Signaled System Error */ 1672 uint32_t rma : 1; /**< Received Master Abort */ 1673 uint32_t rta : 1; /**< Received Target Abort */ 1674 uint32_t sta : 1; /**< Signaled Target Abort */ 1675 uint32_t devt : 2; /**< DEVSEL Timing 1676 Not applicable for PCI Express. Hardwired to 0. */ 1677 uint32_t mdpe : 1; /**< Master Data Parity Error */ 1678 uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1679 Not applicable for PCI Express. Hardwired to 0. */ 1680 uint32_t reserved_22_22 : 1; 1681 uint32_t m66 : 1; /**< 66 MHz Capable 1682 Not applicable for PCI Express. Hardwired to 0. */ 1683 uint32_t reserved_16_20 : 5; 1684 uint32_t lio_limi : 4; /**< I/O Space Limit */ 1685 uint32_t reserved_9_11 : 3; 1686 uint32_t io32b : 1; /**< 32-Bit I/O Space */ 1687 uint32_t lio_base : 4; /**< I/O Space Base */ 1688 uint32_t reserved_1_3 : 3; 1689 uint32_t io32a : 1; /**< 32-Bit I/O Space 1690 o 0 = 16-bit I/O addressing 1691 o 1 = 32-bit I/O addressing 1692 This bit is writable through PEM(0..1)_CFG_WR. 1693 When the application 1694 writes to this bit through PEM(0..1)_CFG_WR, 1695 the same value is written 1696 to bit 8 of this register. */ 1697#else 1698 uint32_t io32a : 1; 1699 uint32_t reserved_1_3 : 3; 1700 uint32_t lio_base : 4; 1701 uint32_t io32b : 1; 1702 uint32_t reserved_9_11 : 3; 1703 uint32_t lio_limi : 4; 1704 uint32_t reserved_16_20 : 5; 1705 uint32_t m66 : 1; 1706 uint32_t reserved_22_22 : 1; 1707 uint32_t fbb : 1; 1708 uint32_t mdpe : 1; 1709 uint32_t devt : 2; 1710 uint32_t sta : 1; 1711 uint32_t rta : 1; 1712 uint32_t rma : 1; 1713 uint32_t sse : 1; 1714 uint32_t dpe : 1; 1715#endif 1716 } s; 1717 struct cvmx_pciercx_cfg007_s cn52xx; 1718 struct cvmx_pciercx_cfg007_s cn52xxp1; 1719 struct cvmx_pciercx_cfg007_s cn56xx; 1720 struct cvmx_pciercx_cfg007_s cn56xxp1; 1721 struct cvmx_pciercx_cfg007_s cn61xx; 1722 struct cvmx_pciercx_cfg007_s cn63xx; 1723 struct cvmx_pciercx_cfg007_s cn63xxp1; 1724 struct cvmx_pciercx_cfg007_s cn66xx; 1725 struct cvmx_pciercx_cfg007_s cn68xx; 1726 struct cvmx_pciercx_cfg007_s cn68xxp1; 1727 struct cvmx_pciercx_cfg007_s cnf71xx; 1728}; 1729typedef union cvmx_pciercx_cfg007 cvmx_pciercx_cfg007_t; 1730 1731/** 1732 * cvmx_pcierc#_cfg008 1733 * 1734 * PCIE_CFG008 = Ninth 32-bits of PCIE type 1 config space (Memory Base and Memory Limit Register) 1735 * 1736 */ 1737union cvmx_pciercx_cfg008 { 1738 uint32_t u32; 1739 struct cvmx_pciercx_cfg008_s { 1740#ifdef __BIG_ENDIAN_BITFIELD 1741 uint32_t ml_addr : 12; /**< Memory Limit Address */ 1742 uint32_t reserved_16_19 : 4; 1743 uint32_t mb_addr : 12; /**< Memory Base Address */ 1744 uint32_t reserved_0_3 : 4; 1745#else 1746 uint32_t reserved_0_3 : 4; 1747 uint32_t mb_addr : 12; 1748 uint32_t reserved_16_19 : 4; 1749 uint32_t ml_addr : 12; 1750#endif 1751 } s; 1752 struct cvmx_pciercx_cfg008_s cn52xx; 1753 struct cvmx_pciercx_cfg008_s cn52xxp1; 1754 struct cvmx_pciercx_cfg008_s cn56xx; 1755 struct cvmx_pciercx_cfg008_s cn56xxp1; 1756 struct cvmx_pciercx_cfg008_s cn61xx; 1757 struct cvmx_pciercx_cfg008_s cn63xx; 1758 struct cvmx_pciercx_cfg008_s cn63xxp1; 1759 struct cvmx_pciercx_cfg008_s cn66xx; 1760 struct cvmx_pciercx_cfg008_s cn68xx; 1761 struct cvmx_pciercx_cfg008_s cn68xxp1; 1762 struct cvmx_pciercx_cfg008_s cnf71xx; 1763}; 1764typedef union cvmx_pciercx_cfg008 cvmx_pciercx_cfg008_t; 1765 1766/** 1767 * cvmx_pcierc#_cfg009 1768 * 1769 * PCIE_CFG009 = Tenth 32-bits of PCIE type 1 config space (Prefetchable Memory Base and Limit Register) 1770 * 1771 */ 1772union cvmx_pciercx_cfg009 { 1773 uint32_t u32; 1774 struct cvmx_pciercx_cfg009_s { 1775#ifdef __BIG_ENDIAN_BITFIELD 1776 uint32_t lmem_limit : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory End Address */ 1777 uint32_t reserved_17_19 : 3; 1778 uint32_t mem64b : 1; /**< 64-Bit Memory Addressing 1779 o 0 = 32-bit memory addressing 1780 o 1 = 64-bit memory addressing */ 1781 uint32_t lmem_base : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory Start Address */ 1782 uint32_t reserved_1_3 : 3; 1783 uint32_t mem64a : 1; /**< 64-Bit Memory Addressing 1784 o 0 = 32-bit memory addressing 1785 o 1 = 64-bit memory addressing 1786 This bit is writable through PEM(0..1)_CFG_WR. 1787 When the application 1788 writes to this bit through PEM(0..1)_CFG_WR, 1789 the same value is written 1790 to bit 16 of this register. */ 1791#else 1792 uint32_t mem64a : 1; 1793 uint32_t reserved_1_3 : 3; 1794 uint32_t lmem_base : 12; 1795 uint32_t mem64b : 1; 1796 uint32_t reserved_17_19 : 3; 1797 uint32_t lmem_limit : 12; 1798#endif 1799 } s; 1800 struct cvmx_pciercx_cfg009_s cn52xx; 1801 struct cvmx_pciercx_cfg009_s cn52xxp1; 1802 struct cvmx_pciercx_cfg009_s cn56xx; 1803 struct cvmx_pciercx_cfg009_s cn56xxp1; 1804 struct cvmx_pciercx_cfg009_s cn61xx; 1805 struct cvmx_pciercx_cfg009_s cn63xx; 1806 struct cvmx_pciercx_cfg009_s cn63xxp1; 1807 struct cvmx_pciercx_cfg009_s cn66xx; 1808 struct cvmx_pciercx_cfg009_s cn68xx; 1809 struct cvmx_pciercx_cfg009_s cn68xxp1; 1810 struct cvmx_pciercx_cfg009_s cnf71xx; 1811}; 1812typedef union cvmx_pciercx_cfg009 cvmx_pciercx_cfg009_t; 1813 1814/** 1815 * cvmx_pcierc#_cfg010 1816 * 1817 * PCIE_CFG010 = Eleventh 32-bits of PCIE type 1 config space (Prefetchable Base Upper 32 Bits Register) 1818 * 1819 */ 1820union cvmx_pciercx_cfg010 { 1821 uint32_t u32; 1822 struct cvmx_pciercx_cfg010_s { 1823#ifdef __BIG_ENDIAN_BITFIELD 1824 uint32_t umem_base : 32; /**< Upper 32 Bits of Base Address of Prefetchable Memory Space 1825 Used only when 64-bit prefetchable memory addressing is 1826 enabled. */ 1827#else 1828 uint32_t umem_base : 32; 1829#endif 1830 } s; 1831 struct cvmx_pciercx_cfg010_s cn52xx; 1832 struct cvmx_pciercx_cfg010_s cn52xxp1; 1833 struct cvmx_pciercx_cfg010_s cn56xx; 1834 struct cvmx_pciercx_cfg010_s cn56xxp1; 1835 struct cvmx_pciercx_cfg010_s cn61xx; 1836 struct cvmx_pciercx_cfg010_s cn63xx; 1837 struct cvmx_pciercx_cfg010_s cn63xxp1; 1838 struct cvmx_pciercx_cfg010_s cn66xx; 1839 struct cvmx_pciercx_cfg010_s cn68xx; 1840 struct cvmx_pciercx_cfg010_s cn68xxp1; 1841 struct cvmx_pciercx_cfg010_s cnf71xx; 1842}; 1843typedef union cvmx_pciercx_cfg010 cvmx_pciercx_cfg010_t; 1844 1845/** 1846 * cvmx_pcierc#_cfg011 1847 * 1848 * PCIE_CFG011 = Twelfth 32-bits of PCIE type 1 config space (Prefetchable Limit Upper 32 Bits Register) 1849 * 1850 */ 1851union cvmx_pciercx_cfg011 { 1852 uint32_t u32; 1853 struct cvmx_pciercx_cfg011_s { 1854#ifdef __BIG_ENDIAN_BITFIELD 1855 uint32_t umem_limit : 32; /**< Upper 32 Bits of Limit Address of Prefetchable Memory Space 1856 Used only when 64-bit prefetchable memory addressing is 1857 enabled. */ 1858#else 1859 uint32_t umem_limit : 32; 1860#endif 1861 } s; 1862 struct cvmx_pciercx_cfg011_s cn52xx; 1863 struct cvmx_pciercx_cfg011_s cn52xxp1; 1864 struct cvmx_pciercx_cfg011_s cn56xx; 1865 struct cvmx_pciercx_cfg011_s cn56xxp1; 1866 struct cvmx_pciercx_cfg011_s cn61xx; 1867 struct cvmx_pciercx_cfg011_s cn63xx; 1868 struct cvmx_pciercx_cfg011_s cn63xxp1; 1869 struct cvmx_pciercx_cfg011_s cn66xx; 1870 struct cvmx_pciercx_cfg011_s cn68xx; 1871 struct cvmx_pciercx_cfg011_s cn68xxp1; 1872 struct cvmx_pciercx_cfg011_s cnf71xx; 1873}; 1874typedef union cvmx_pciercx_cfg011 cvmx_pciercx_cfg011_t; 1875 1876/** 1877 * cvmx_pcierc#_cfg012 1878 * 1879 * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 1 config space (IO Base and Limit Upper 16 Bits Register) 1880 * 1881 */ 1882union cvmx_pciercx_cfg012 { 1883 uint32_t u32; 1884 struct cvmx_pciercx_cfg012_s { 1885#ifdef __BIG_ENDIAN_BITFIELD 1886 uint32_t uio_limit : 16; /**< Upper 16 Bits of I/O Limit (if 32-bit I/O decoding is supported 1887 for devices on the secondary side) */ 1888 uint32_t uio_base : 16; /**< Upper 16 Bits of I/O Base (if 32-bit I/O decoding is supported 1889 for devices on the secondary side) */ 1890#else 1891 uint32_t uio_base : 16; 1892 uint32_t uio_limit : 16; 1893#endif 1894 } s; 1895 struct cvmx_pciercx_cfg012_s cn52xx; 1896 struct cvmx_pciercx_cfg012_s cn52xxp1; 1897 struct cvmx_pciercx_cfg012_s cn56xx; 1898 struct cvmx_pciercx_cfg012_s cn56xxp1; 1899 struct cvmx_pciercx_cfg012_s cn61xx; 1900 struct cvmx_pciercx_cfg012_s cn63xx; 1901 struct cvmx_pciercx_cfg012_s cn63xxp1; 1902 struct cvmx_pciercx_cfg012_s cn66xx; 1903 struct cvmx_pciercx_cfg012_s cn68xx; 1904 struct cvmx_pciercx_cfg012_s cn68xxp1; 1905 struct cvmx_pciercx_cfg012_s cnf71xx; 1906}; 1907typedef union cvmx_pciercx_cfg012 cvmx_pciercx_cfg012_t; 1908 1909/** 1910 * cvmx_pcierc#_cfg013 1911 * 1912 * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 1 config space (Capability Pointer Register) 1913 * 1914 */ 1915union cvmx_pciercx_cfg013 { 1916 uint32_t u32; 1917 struct cvmx_pciercx_cfg013_s { 1918#ifdef __BIG_ENDIAN_BITFIELD 1919 uint32_t reserved_8_31 : 24; 1920 uint32_t cp : 8; /**< First Capability Pointer. 1921 Points to Power Management Capability structure by 1922 default, writable through PEM(0..1)_CFG_WR 1923 However, the application must not change this field. */ 1924#else 1925 uint32_t cp : 8; 1926 uint32_t reserved_8_31 : 24; 1927#endif 1928 } s; 1929 struct cvmx_pciercx_cfg013_s cn52xx; 1930 struct cvmx_pciercx_cfg013_s cn52xxp1; 1931 struct cvmx_pciercx_cfg013_s cn56xx; 1932 struct cvmx_pciercx_cfg013_s cn56xxp1; 1933 struct cvmx_pciercx_cfg013_s cn61xx; 1934 struct cvmx_pciercx_cfg013_s cn63xx; 1935 struct cvmx_pciercx_cfg013_s cn63xxp1; 1936 struct cvmx_pciercx_cfg013_s cn66xx; 1937 struct cvmx_pciercx_cfg013_s cn68xx; 1938 struct cvmx_pciercx_cfg013_s cn68xxp1; 1939 struct cvmx_pciercx_cfg013_s cnf71xx; 1940}; 1941typedef union cvmx_pciercx_cfg013 cvmx_pciercx_cfg013_t; 1942 1943/** 1944 * cvmx_pcierc#_cfg014 1945 * 1946 * PCIE_CFG014 = Fifteenth 32-bits of PCIE type 1 config space (Expansion ROM Base Address Register) 1947 * 1948 */ 1949union cvmx_pciercx_cfg014 { 1950 uint32_t u32; 1951 struct cvmx_pciercx_cfg014_s { 1952#ifdef __BIG_ENDIAN_BITFIELD 1953 uint32_t reserved_0_31 : 32; 1954#else 1955 uint32_t reserved_0_31 : 32; 1956#endif 1957 } s; 1958 struct cvmx_pciercx_cfg014_s cn52xx; 1959 struct cvmx_pciercx_cfg014_s cn52xxp1; 1960 struct cvmx_pciercx_cfg014_s cn56xx; 1961 struct cvmx_pciercx_cfg014_s cn56xxp1; 1962 struct cvmx_pciercx_cfg014_s cn61xx; 1963 struct cvmx_pciercx_cfg014_s cn63xx; 1964 struct cvmx_pciercx_cfg014_s cn63xxp1; 1965 struct cvmx_pciercx_cfg014_s cn66xx; 1966 struct cvmx_pciercx_cfg014_s cn68xx; 1967 struct cvmx_pciercx_cfg014_s cn68xxp1; 1968 struct cvmx_pciercx_cfg014_s cnf71xx; 1969}; 1970typedef union cvmx_pciercx_cfg014 cvmx_pciercx_cfg014_t; 1971 1972/** 1973 * cvmx_pcierc#_cfg015 1974 * 1975 * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 1 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register) 1976 * 1977 */ 1978union cvmx_pciercx_cfg015 { 1979 uint32_t u32; 1980 struct cvmx_pciercx_cfg015_s { 1981#ifdef __BIG_ENDIAN_BITFIELD 1982 uint32_t reserved_28_31 : 4; 1983 uint32_t dtsees : 1; /**< Discard Timer SERR Enable Status 1984 Not applicable to PCI Express, hardwired to 0. */ 1985 uint32_t dts : 1; /**< Discard Timer Status 1986 Not applicable to PCI Express, hardwired to 0. */ 1987 uint32_t sdt : 1; /**< Secondary Discard Timer 1988 Not applicable to PCI Express, hardwired to 0. */ 1989 uint32_t pdt : 1; /**< Primary Discard Timer 1990 Not applicable to PCI Express, hardwired to 0. */ 1991 uint32_t fbbe : 1; /**< Fast Back-to-Back Transactions Enable 1992 Not applicable to PCI Express, hardwired to 0. */ 1993 uint32_t sbrst : 1; /**< Secondary Bus Reset 1994 Hot reset. Causes TS1s with the hot reset bit to be sent to 1995 the link partner. When set, SW should wait 2ms before 1996 clearing. The link partner normally responds by sending TS1s 1997 with the hot reset bit set, which will cause a link 1998 down event - refer to "PCIe Link-Down Reset in RC Mode" 1999 section. */ 2000 uint32_t mam : 1; /**< Master Abort Mode 2001 Not applicable to PCI Express, hardwired to 0. */ 2002 uint32_t vga16d : 1; /**< VGA 16-Bit Decode */ 2003 uint32_t vgae : 1; /**< VGA Enable */ 2004 uint32_t isae : 1; /**< ISA Enable */ 2005 uint32_t see : 1; /**< SERR Enable */ 2006 uint32_t pere : 1; /**< Parity Error Response Enable */ 2007 uint32_t inta : 8; /**< Interrupt Pin 2008 Identifies the legacy interrupt Message that the device 2009 (or device function) uses. 2010 The Interrupt Pin register is writable through PEM(0..1)_CFG_WR. 2011 In a single-function configuration, only INTA is used. 2012 Therefore, the application must not change this field. */ 2013 uint32_t il : 8; /**< Interrupt Line */ 2014#else 2015 uint32_t il : 8; 2016 uint32_t inta : 8; 2017 uint32_t pere : 1; 2018 uint32_t see : 1; 2019 uint32_t isae : 1; 2020 uint32_t vgae : 1; 2021 uint32_t vga16d : 1; 2022 uint32_t mam : 1; 2023 uint32_t sbrst : 1; 2024 uint32_t fbbe : 1; 2025 uint32_t pdt : 1; 2026 uint32_t sdt : 1; 2027 uint32_t dts : 1; 2028 uint32_t dtsees : 1; 2029 uint32_t reserved_28_31 : 4; 2030#endif 2031 } s; 2032 struct cvmx_pciercx_cfg015_s cn52xx; 2033 struct cvmx_pciercx_cfg015_s cn52xxp1; 2034 struct cvmx_pciercx_cfg015_s cn56xx; 2035 struct cvmx_pciercx_cfg015_s cn56xxp1; 2036 struct cvmx_pciercx_cfg015_s cn61xx; 2037 struct cvmx_pciercx_cfg015_s cn63xx; 2038 struct cvmx_pciercx_cfg015_s cn63xxp1; 2039 struct cvmx_pciercx_cfg015_s cn66xx; 2040 struct cvmx_pciercx_cfg015_s cn68xx; 2041 struct cvmx_pciercx_cfg015_s cn68xxp1; 2042 struct cvmx_pciercx_cfg015_s cnf71xx; 2043}; 2044typedef union cvmx_pciercx_cfg015 cvmx_pciercx_cfg015_t; 2045 2046/** 2047 * cvmx_pcierc#_cfg016 2048 * 2049 * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 1 config space 2050 * (Power Management Capability ID/ 2051 * Power Management Next Item Pointer/ 2052 * Power Management Capabilities Register) 2053 */ 2054union cvmx_pciercx_cfg016 { 2055 uint32_t u32; 2056 struct cvmx_pciercx_cfg016_s { 2057#ifdef __BIG_ENDIAN_BITFIELD 2058 uint32_t pmes : 5; /**< PME_Support 2059 A value of 0 for any bit indicates that the 2060 device (or function) is not capable of generating PME Messages 2061 while in that power state: 2062 o Bit 11: If set, PME Messages can be generated from D0 2063 o Bit 12: If set, PME Messages can be generated from D1 2064 o Bit 13: If set, PME Messages can be generated from D2 2065 o Bit 14: If set, PME Messages can be generated from D3hot 2066 o Bit 15: If set, PME Messages can be generated from D3cold 2067 The PME_Support field is writable through PEM(0..1)_CFG_WR. 2068 However, the application must not change this field. */ 2069 uint32_t d2s : 1; /**< D2 Support, writable through PEM(0..1)_CFG_WR 2070 However, the application must not change this field. */ 2071 uint32_t d1s : 1; /**< D1 Support, writable through PEM(0..1)_CFG_WR 2072 However, the application must not change this field. */ 2073 uint32_t auxc : 3; /**< AUX Current, writable through PEM(0..1)_CFG_WR 2074 However, the application must not change this field. */ 2075 uint32_t dsi : 1; /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR 2076 However, the application must not change this field. */ 2077 uint32_t reserved_20_20 : 1; 2078 uint32_t pme_clock : 1; /**< PME Clock, hardwired to 0 */ 2079 uint32_t pmsv : 3; /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR 2080 However, the application must not change this field. */ 2081 uint32_t ncp : 8; /**< Next Capability Pointer 2082 Points to the MSI capabilities by default, writable 2083 through PEM(0..1)_CFG_WR. */ 2084 uint32_t pmcid : 8; /**< Power Management Capability ID */ 2085#else 2086 uint32_t pmcid : 8; 2087 uint32_t ncp : 8; 2088 uint32_t pmsv : 3; 2089 uint32_t pme_clock : 1; 2090 uint32_t reserved_20_20 : 1; 2091 uint32_t dsi : 1; 2092 uint32_t auxc : 3; 2093 uint32_t d1s : 1; 2094 uint32_t d2s : 1; 2095 uint32_t pmes : 5; 2096#endif 2097 } s; 2098 struct cvmx_pciercx_cfg016_s cn52xx; 2099 struct cvmx_pciercx_cfg016_s cn52xxp1; 2100 struct cvmx_pciercx_cfg016_s cn56xx; 2101 struct cvmx_pciercx_cfg016_s cn56xxp1; 2102 struct cvmx_pciercx_cfg016_s cn61xx; 2103 struct cvmx_pciercx_cfg016_s cn63xx; 2104 struct cvmx_pciercx_cfg016_s cn63xxp1; 2105 struct cvmx_pciercx_cfg016_s cn66xx; 2106 struct cvmx_pciercx_cfg016_s cn68xx; 2107 struct cvmx_pciercx_cfg016_s cn68xxp1; 2108 struct cvmx_pciercx_cfg016_s cnf71xx; 2109}; 2110typedef union cvmx_pciercx_cfg016 cvmx_pciercx_cfg016_t; 2111 2112/** 2113 * cvmx_pcierc#_cfg017 2114 * 2115 * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 1 config space (Power Management Control and Status Register) 2116 * 2117 */ 2118union cvmx_pciercx_cfg017 { 2119 uint32_t u32; 2120 struct cvmx_pciercx_cfg017_s { 2121#ifdef __BIG_ENDIAN_BITFIELD 2122 uint32_t pmdia : 8; /**< Data register for additional information (not supported) */ 2123 uint32_t bpccee : 1; /**< Bus Power/Clock Control Enable, hardwired to 0 */ 2124 uint32_t bd3h : 1; /**< B2/B3 Support, hardwired to 0 */ 2125 uint32_t reserved_16_21 : 6; 2126 uint32_t pmess : 1; /**< PME Status 2127 Indicates if a previously enabled PME event occurred or not. */ 2128 uint32_t pmedsia : 2; /**< Data Scale (not supported) */ 2129 uint32_t pmds : 4; /**< Data Select (not supported) */ 2130 uint32_t pmeens : 1; /**< PME Enable 2131 A value of 1 indicates that the device is enabled to 2132 generate PME. */ 2133 uint32_t reserved_4_7 : 4; 2134 uint32_t nsr : 1; /**< No Soft Reset, writable through PEM(0..1)_CFG_WR 2135 However, the application must not change this field. */ 2136 uint32_t reserved_2_2 : 1; 2137 uint32_t ps : 2; /**< Power State 2138 Controls the device power state: 2139 o 00b: D0 2140 o 01b: D1 2141 o 10b: D2 2142 o 11b: D3 2143 The written value is ignored if the specific state is 2144 not supported. */ 2145#else 2146 uint32_t ps : 2; 2147 uint32_t reserved_2_2 : 1; 2148 uint32_t nsr : 1; 2149 uint32_t reserved_4_7 : 4; 2150 uint32_t pmeens : 1; 2151 uint32_t pmds : 4; 2152 uint32_t pmedsia : 2; 2153 uint32_t pmess : 1; 2154 uint32_t reserved_16_21 : 6; 2155 uint32_t bd3h : 1; 2156 uint32_t bpccee : 1; 2157 uint32_t pmdia : 8; 2158#endif 2159 } s; 2160 struct cvmx_pciercx_cfg017_s cn52xx; 2161 struct cvmx_pciercx_cfg017_s cn52xxp1; 2162 struct cvmx_pciercx_cfg017_s cn56xx; 2163 struct cvmx_pciercx_cfg017_s cn56xxp1; 2164 struct cvmx_pciercx_cfg017_s cn61xx; 2165 struct cvmx_pciercx_cfg017_s cn63xx; 2166 struct cvmx_pciercx_cfg017_s cn63xxp1; 2167 struct cvmx_pciercx_cfg017_s cn66xx; 2168 struct cvmx_pciercx_cfg017_s cn68xx; 2169 struct cvmx_pciercx_cfg017_s cn68xxp1; 2170 struct cvmx_pciercx_cfg017_s cnf71xx; 2171}; 2172typedef union cvmx_pciercx_cfg017 cvmx_pciercx_cfg017_t; 2173 2174/** 2175 * cvmx_pcierc#_cfg020 2176 * 2177 * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 1 config space 2178 * (MSI Capability ID/ 2179 * MSI Next Item Pointer/ 2180 * MSI Control Register) 2181 */ 2182union cvmx_pciercx_cfg020 { 2183 uint32_t u32; 2184 struct cvmx_pciercx_cfg020_s { 2185#ifdef __BIG_ENDIAN_BITFIELD 2186 uint32_t reserved_25_31 : 7; 2187 uint32_t pvm : 1; /**< Per-vector masking capable */ 2188 uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR 2189 However, the application must not change this field. */ 2190 uint32_t mme : 3; /**< Multiple Message Enabled 2191 Indicates that multiple Message mode is enabled by system 2192 software. The number of Messages enabled must be less than 2193 or equal to the Multiple Message Capable value. */ 2194 uint32_t mmc : 3; /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR 2195 However, the application must not change this field. */ 2196 uint32_t msien : 1; /**< MSI Enabled 2197 When set, INTx must be disabled. 2198 This bit must never be set, as internal-MSI is not supported in 2199 RC mode. (Note that this has no effect on external MSI, which 2200 will be commonly used in RC mode.) */ 2201 uint32_t ncp : 8; /**< Next Capability Pointer 2202 Points to PCI Express Capabilities by default, 2203 writable through PEM(0..1)_CFG_WR. 2204 However, the application must not change this field. */ 2205 uint32_t msicid : 8; /**< MSI Capability ID */ 2206#else 2207 uint32_t msicid : 8; 2208 uint32_t ncp : 8; 2209 uint32_t msien : 1; 2210 uint32_t mmc : 3; 2211 uint32_t mme : 3; 2212 uint32_t m64 : 1; 2213 uint32_t pvm : 1; 2214 uint32_t reserved_25_31 : 7; 2215#endif 2216 } s; 2217 struct cvmx_pciercx_cfg020_cn52xx { 2218#ifdef __BIG_ENDIAN_BITFIELD 2219 uint32_t reserved_24_31 : 8; 2220 uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PESC(0..1)_CFG_WR 2221 However, the application must not change this field. */ 2222 uint32_t mme : 3; /**< Multiple Message Enabled 2223 Indicates that multiple Message mode is enabled by system 2224 software. The number of Messages enabled must be less than 2225 or equal to the Multiple Message Capable value. */ 2226 uint32_t mmc : 3; /**< Multiple Message Capable, writable through PESC(0..1)_CFG_WR 2227 However, the application must not change this field. */ 2228 uint32_t msien : 1; /**< MSI Enabled 2229 When set, INTx must be disabled. 2230 This bit must never be set, as internal-MSI is not supported in 2231 RC mode. (Note that this has no effect on external MSI, which 2232 will be commonly used in RC mode.) */ 2233 uint32_t ncp : 8; /**< Next Capability Pointer 2234 Points to PCI Express Capabilities by default, 2235 writable through PESC(0..1)_CFG_WR. 2236 However, the application must not change this field. */ 2237 uint32_t msicid : 8; /**< MSI Capability ID */ 2238#else 2239 uint32_t msicid : 8; 2240 uint32_t ncp : 8; 2241 uint32_t msien : 1; 2242 uint32_t mmc : 3; 2243 uint32_t mme : 3; 2244 uint32_t m64 : 1; 2245 uint32_t reserved_24_31 : 8; 2246#endif 2247 } cn52xx; 2248 struct cvmx_pciercx_cfg020_cn52xx cn52xxp1; 2249 struct cvmx_pciercx_cfg020_cn52xx cn56xx; 2250 struct cvmx_pciercx_cfg020_cn52xx cn56xxp1; 2251 struct cvmx_pciercx_cfg020_s cn61xx; 2252 struct cvmx_pciercx_cfg020_cn52xx cn63xx; 2253 struct cvmx_pciercx_cfg020_cn52xx cn63xxp1; 2254 struct cvmx_pciercx_cfg020_cn52xx cn66xx; 2255 struct cvmx_pciercx_cfg020_cn52xx cn68xx; 2256 struct cvmx_pciercx_cfg020_cn52xx cn68xxp1; 2257 struct cvmx_pciercx_cfg020_s cnf71xx; 2258}; 2259typedef union cvmx_pciercx_cfg020 cvmx_pciercx_cfg020_t; 2260 2261/** 2262 * cvmx_pcierc#_cfg021 2263 * 2264 * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 1 config space (MSI Lower 32 Bits Address Register) 2265 * 2266 */ 2267union cvmx_pciercx_cfg021 { 2268 uint32_t u32; 2269 struct cvmx_pciercx_cfg021_s { 2270#ifdef __BIG_ENDIAN_BITFIELD 2271 uint32_t lmsi : 30; /**< Lower 32-bit Address */ 2272 uint32_t reserved_0_1 : 2; 2273#else 2274 uint32_t reserved_0_1 : 2; 2275 uint32_t lmsi : 30; 2276#endif 2277 } s; 2278 struct cvmx_pciercx_cfg021_s cn52xx; 2279 struct cvmx_pciercx_cfg021_s cn52xxp1; 2280 struct cvmx_pciercx_cfg021_s cn56xx; 2281 struct cvmx_pciercx_cfg021_s cn56xxp1; 2282 struct cvmx_pciercx_cfg021_s cn61xx; 2283 struct cvmx_pciercx_cfg021_s cn63xx; 2284 struct cvmx_pciercx_cfg021_s cn63xxp1; 2285 struct cvmx_pciercx_cfg021_s cn66xx; 2286 struct cvmx_pciercx_cfg021_s cn68xx; 2287 struct cvmx_pciercx_cfg021_s cn68xxp1; 2288 struct cvmx_pciercx_cfg021_s cnf71xx; 2289}; 2290typedef union cvmx_pciercx_cfg021 cvmx_pciercx_cfg021_t; 2291 2292/** 2293 * cvmx_pcierc#_cfg022 2294 * 2295 * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 1 config space (MSI Upper 32 bits Address Register) 2296 * 2297 */ 2298union cvmx_pciercx_cfg022 { 2299 uint32_t u32; 2300 struct cvmx_pciercx_cfg022_s { 2301#ifdef __BIG_ENDIAN_BITFIELD 2302 uint32_t umsi : 32; /**< Upper 32-bit Address */ 2303#else 2304 uint32_t umsi : 32; 2305#endif 2306 } s; 2307 struct cvmx_pciercx_cfg022_s cn52xx; 2308 struct cvmx_pciercx_cfg022_s cn52xxp1; 2309 struct cvmx_pciercx_cfg022_s cn56xx; 2310 struct cvmx_pciercx_cfg022_s cn56xxp1; 2311 struct cvmx_pciercx_cfg022_s cn61xx; 2312 struct cvmx_pciercx_cfg022_s cn63xx; 2313 struct cvmx_pciercx_cfg022_s cn63xxp1; 2314 struct cvmx_pciercx_cfg022_s cn66xx; 2315 struct cvmx_pciercx_cfg022_s cn68xx; 2316 struct cvmx_pciercx_cfg022_s cn68xxp1; 2317 struct cvmx_pciercx_cfg022_s cnf71xx; 2318}; 2319typedef union cvmx_pciercx_cfg022 cvmx_pciercx_cfg022_t; 2320 2321/** 2322 * cvmx_pcierc#_cfg023 2323 * 2324 * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 1 config space (MSI Data Register) 2325 * 2326 */ 2327union cvmx_pciercx_cfg023 { 2328 uint32_t u32; 2329 struct cvmx_pciercx_cfg023_s { 2330#ifdef __BIG_ENDIAN_BITFIELD 2331 uint32_t reserved_16_31 : 16; 2332 uint32_t msimd : 16; /**< MSI Data 2333 Pattern assigned by system software, bits [4:0] are Or-ed with 2334 MSI_VECTOR to generate 32 MSI Messages per function. */ 2335#else 2336 uint32_t msimd : 16; 2337 uint32_t reserved_16_31 : 16; 2338#endif 2339 } s; 2340 struct cvmx_pciercx_cfg023_s cn52xx; 2341 struct cvmx_pciercx_cfg023_s cn52xxp1; 2342 struct cvmx_pciercx_cfg023_s cn56xx; 2343 struct cvmx_pciercx_cfg023_s cn56xxp1; 2344 struct cvmx_pciercx_cfg023_s cn61xx; 2345 struct cvmx_pciercx_cfg023_s cn63xx; 2346 struct cvmx_pciercx_cfg023_s cn63xxp1; 2347 struct cvmx_pciercx_cfg023_s cn66xx; 2348 struct cvmx_pciercx_cfg023_s cn68xx; 2349 struct cvmx_pciercx_cfg023_s cn68xxp1; 2350 struct cvmx_pciercx_cfg023_s cnf71xx; 2351}; 2352typedef union cvmx_pciercx_cfg023 cvmx_pciercx_cfg023_t; 2353 2354/** 2355 * cvmx_pcierc#_cfg028 2356 * 2357 * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 1 config space 2358 * (PCI Express Capabilities List Register/ 2359 * PCI Express Capabilities Register) 2360 */ 2361union cvmx_pciercx_cfg028 { 2362 uint32_t u32; 2363 struct cvmx_pciercx_cfg028_s { 2364#ifdef __BIG_ENDIAN_BITFIELD 2365 uint32_t reserved_30_31 : 2; 2366 uint32_t imn : 5; /**< Interrupt Message Number 2367 Updated by hardware, writable through PEM(0..1)_CFG_WR. 2368 However, the application must not change this field. */ 2369 uint32_t si : 1; /**< Slot Implemented 2370 This bit is writable through PEM(0..1)_CFG_WR. 2371 However, it must 0 for an 2372 Endpoint device. Therefore, the application must not write a 2373 1 to this bit. */ 2374 uint32_t dpt : 4; /**< Device Port Type */ 2375 uint32_t pciecv : 4; /**< PCI Express Capability Version */ 2376 uint32_t ncp : 8; /**< Next Capability Pointer 2377 writable through PEM(0..1)_CFG_WR. 2378 However, the application must not change this field. */ 2379 uint32_t pcieid : 8; /**< PCIE Capability ID */ 2380#else 2381 uint32_t pcieid : 8; 2382 uint32_t ncp : 8; 2383 uint32_t pciecv : 4; 2384 uint32_t dpt : 4; 2385 uint32_t si : 1; 2386 uint32_t imn : 5; 2387 uint32_t reserved_30_31 : 2; 2388#endif 2389 } s; 2390 struct cvmx_pciercx_cfg028_s cn52xx; 2391 struct cvmx_pciercx_cfg028_s cn52xxp1; 2392 struct cvmx_pciercx_cfg028_s cn56xx; 2393 struct cvmx_pciercx_cfg028_s cn56xxp1; 2394 struct cvmx_pciercx_cfg028_s cn61xx; 2395 struct cvmx_pciercx_cfg028_s cn63xx; 2396 struct cvmx_pciercx_cfg028_s cn63xxp1; 2397 struct cvmx_pciercx_cfg028_s cn66xx; 2398 struct cvmx_pciercx_cfg028_s cn68xx; 2399 struct cvmx_pciercx_cfg028_s cn68xxp1; 2400 struct cvmx_pciercx_cfg028_s cnf71xx; 2401}; 2402typedef union cvmx_pciercx_cfg028 cvmx_pciercx_cfg028_t; 2403 2404/** 2405 * cvmx_pcierc#_cfg029 2406 * 2407 * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 1 config space (Device Capabilities Register) 2408 * 2409 */ 2410union cvmx_pciercx_cfg029 { 2411 uint32_t u32; 2412 struct cvmx_pciercx_cfg029_s { 2413#ifdef __BIG_ENDIAN_BITFIELD 2414 uint32_t reserved_28_31 : 4; 2415 uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2416 Not applicable for RC port, upstream port only. */ 2417 uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2418 Not applicable for RC port, upstream port only. */ 2419 uint32_t reserved_16_17 : 2; 2420 uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2421 However, the application must not change this field. */ 2422 uint32_t reserved_12_14 : 3; 2423 uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2424 Must be 0x0 for non-endpoint devices. */ 2425 uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2426 Must be 0x0 for non-endpoint devices. */ 2427 uint32_t etfs : 1; /**< Extended Tag Field Supported 2428 This bit is writable through PEM(0..1)_CFG_WR. 2429 However, the application 2430 must not write a 1 to this bit. */ 2431 uint32_t pfs : 2; /**< Phantom Function Supported 2432 This field is writable through PEM(0..1)_CFG_WR. 2433 However, Phantom 2434 Function is not supported. Therefore, the application must not 2435 write any value other than 0x0 to this field. */ 2436 uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2437 However, the application must not change this field. */ 2438#else 2439 uint32_t mpss : 3; 2440 uint32_t pfs : 2; 2441 uint32_t etfs : 1; 2442 uint32_t el0al : 3; 2443 uint32_t el1al : 3; 2444 uint32_t reserved_12_14 : 3; 2445 uint32_t rber : 1; 2446 uint32_t reserved_16_17 : 2; 2447 uint32_t csplv : 8; 2448 uint32_t cspls : 2; 2449 uint32_t reserved_28_31 : 4; 2450#endif 2451 } s; 2452 struct cvmx_pciercx_cfg029_s cn52xx; 2453 struct cvmx_pciercx_cfg029_s cn52xxp1; 2454 struct cvmx_pciercx_cfg029_s cn56xx; 2455 struct cvmx_pciercx_cfg029_s cn56xxp1; 2456 struct cvmx_pciercx_cfg029_s cn61xx; 2457 struct cvmx_pciercx_cfg029_s cn63xx; 2458 struct cvmx_pciercx_cfg029_s cn63xxp1; 2459 struct cvmx_pciercx_cfg029_s cn66xx; 2460 struct cvmx_pciercx_cfg029_s cn68xx; 2461 struct cvmx_pciercx_cfg029_s cn68xxp1; 2462 struct cvmx_pciercx_cfg029_s cnf71xx; 2463}; 2464typedef union cvmx_pciercx_cfg029 cvmx_pciercx_cfg029_t; 2465 2466/** 2467 * cvmx_pcierc#_cfg030 2468 * 2469 * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 1 config space 2470 * (Device Control Register/Device Status Register) 2471 */ 2472union cvmx_pciercx_cfg030 { 2473 uint32_t u32; 2474 struct cvmx_pciercx_cfg030_s { 2475#ifdef __BIG_ENDIAN_BITFIELD 2476 uint32_t reserved_22_31 : 10; 2477 uint32_t tp : 1; /**< Transaction Pending 2478 Hard-wired to 0. */ 2479 uint32_t ap_d : 1; /**< Aux Power Detected 2480 Set to 1 if Aux power detected. */ 2481 uint32_t ur_d : 1; /**< Unsupported Request Detected 2482 Errors are logged in this register regardless of whether 2483 error reporting is enabled in the Device Control register. 2484 UR_D occurs when we receive something we don't support. 2485 Unsupported requests are Nonfatal errors, so UR_D should 2486 cause NFE_D. Receiving a vendor defined message should 2487 cause an unsupported request. */ 2488 uint32_t fe_d : 1; /**< Fatal Error Detected 2489 Errors are logged in this register regardless of whether 2490 error reporting is enabled in the Device Control register. 2491 FE_D is set if receive any of the errors in PCIE_CFG066 that 2492 has a severity set to Fatal. Malformed TLP's generally fit 2493 into this category. */ 2494 uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2495 Errors are logged in this register regardless of whether 2496 error reporting is enabled in the Device Control register. 2497 NFE_D is set if we receive any of the errors in PCIE_CFG066 2498 that has a severity set to Nonfatal and does NOT meet Advisory 2499 Nonfatal criteria , which 2500 most poisoned TLP's should be. */ 2501 uint32_t ce_d : 1; /**< Correctable Error Detected 2502 Errors are logged in this register regardless of whether 2503 error reporting is enabled in the Device Control register. 2504 CE_D is set if we receive any of the errors in PCIE_CFG068 2505 for example a Replay Timer Timeout. Also, it can be set if 2506 we get any of the errors in PCIE_CFG066 that has a severity 2507 set to Nonfatal and meets the Advisory Nonfatal criteria, 2508 which most ECRC errors should be. */ 2509 uint32_t reserved_15_15 : 1; 2510 uint32_t mrrs : 3; /**< Max Read Request Size 2511 0 = 128B 2512 1 = 256B 2513 2 = 512B 2514 3 = 1024B 2515 4 = 2048B 2516 5 = 4096B 2517 Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and 2518 also must be set properly. 2519 SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must 2520 not exceed the desired max read request size. */ 2521 uint32_t ns_en : 1; /**< Enable No Snoop */ 2522 uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2523 uint32_t pf_en : 1; /**< Phantom Function Enable 2524 This bit should never be set - OCTEON requests never use 2525 phantom functions. */ 2526 uint32_t etf_en : 1; /**< Extended Tag Field Enable 2527 This bit should never be set - OCTEON requests never use 2528 extended tags. */ 2529 uint32_t mps : 3; /**< Max Payload Size 2530 Legal values: 2531 0 = 128B 2532 1 = 256B 2533 Larger sizes not supported. 2534 Note: Both PCI Express Ports must be set to the same value 2535 for Peer-to-Peer to function properly. 2536 Note: DPI_SLI_PRT#_CFG[MPS] must also be set to the same 2537 value for proper functionality. */ 2538 uint32_t ro_en : 1; /**< Enable Relaxed Ordering 2539 This bit is not used. */ 2540 uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2541 uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2542 uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2543 uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2544#else 2545 uint32_t ce_en : 1; 2546 uint32_t nfe_en : 1; 2547 uint32_t fe_en : 1; 2548 uint32_t ur_en : 1; 2549 uint32_t ro_en : 1; 2550 uint32_t mps : 3; 2551 uint32_t etf_en : 1; 2552 uint32_t pf_en : 1; 2553 uint32_t ap_en : 1; 2554 uint32_t ns_en : 1; 2555 uint32_t mrrs : 3; 2556 uint32_t reserved_15_15 : 1; 2557 uint32_t ce_d : 1; 2558 uint32_t nfe_d : 1; 2559 uint32_t fe_d : 1; 2560 uint32_t ur_d : 1; 2561 uint32_t ap_d : 1; 2562 uint32_t tp : 1; 2563 uint32_t reserved_22_31 : 10; 2564#endif 2565 } s; 2566 struct cvmx_pciercx_cfg030_s cn52xx; 2567 struct cvmx_pciercx_cfg030_s cn52xxp1; 2568 struct cvmx_pciercx_cfg030_s cn56xx; 2569 struct cvmx_pciercx_cfg030_s cn56xxp1; 2570 struct cvmx_pciercx_cfg030_s cn61xx; 2571 struct cvmx_pciercx_cfg030_s cn63xx; 2572 struct cvmx_pciercx_cfg030_s cn63xxp1; 2573 struct cvmx_pciercx_cfg030_s cn66xx; 2574 struct cvmx_pciercx_cfg030_s cn68xx; 2575 struct cvmx_pciercx_cfg030_s cn68xxp1; 2576 struct cvmx_pciercx_cfg030_s cnf71xx; 2577}; 2578typedef union cvmx_pciercx_cfg030 cvmx_pciercx_cfg030_t; 2579 2580/** 2581 * cvmx_pcierc#_cfg031 2582 * 2583 * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 1 config space 2584 * (Link Capabilities Register) 2585 */ 2586union cvmx_pciercx_cfg031 { 2587 uint32_t u32; 2588 struct cvmx_pciercx_cfg031_s { 2589#ifdef __BIG_ENDIAN_BITFIELD 2590 uint32_t pnum : 8; /**< Port Number 2591 writable through PEM(0..1)_CFG_WR, however the application 2592 must not change this field. */ 2593 uint32_t reserved_23_23 : 1; 2594 uint32_t aspm : 1; /**< ASPM Optionality Compliance */ 2595 uint32_t lbnc : 1; /**< Link Bandwidth Notification Capability 2596 Set to 1 for Root Complex devices. writable through PEM(0..1)_CFG_WR. 2597 However, the application must not change this field. */ 2598 uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable 2599 Set to 1 for Root Complex devices and 0 for Endpoint devices. */ 2600 uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2601 Not supported, hardwired to 0x0. */ 2602 uint32_t cpm : 1; /**< Clock Power Management 2603 The default value is the value you specify during hardware 2604 configuration, writable through PEM(0..1)_CFG_WR. 2605 However, the application must not change this field. */ 2606 uint32_t l1el : 3; /**< L1 Exit Latency 2607 The default value is the value you specify during hardware 2608 configuration, writable through PEM(0..1)_CFG_WR. 2609 However, the application must not change this field. */ 2610 uint32_t l0el : 3; /**< L0s Exit Latency 2611 The default value is the value you specify during hardware 2612 configuration, writable through PEM(0..1)_CFG_WR. 2613 However, the application must not change this field. */ 2614 uint32_t aslpms : 2; /**< Active State Link PM Support 2615 The default value is the value you specify during hardware 2616 configuration, writable through PEM(0..1)_CFG_WR. 2617 However, the application must not change this field. */ 2618 uint32_t mlw : 6; /**< Maximum Link Width 2619 The default value is the value you specify during hardware 2620 configuration (x1 or x2) writable through PEM(0..1)_CFG_WR. */ 2621 uint32_t mls : 4; /**< Maximum Link Speed 2622 The reset value of this field is controlled by a value sent from 2623 the lsb of the MIO_QLM#_SPD register. 2624 qlm#_spd[0] RST_VALUE NOTE 2625 1 0001b 2.5 GHz supported 2626 0 0010b 5.0 GHz and 2.5 GHz supported 2627 This field is writable through PEM(0..1)_CFG_WR. 2628 However, the application must not change this field. */ 2629#else 2630 uint32_t mls : 4; 2631 uint32_t mlw : 6; 2632 uint32_t aslpms : 2; 2633 uint32_t l0el : 3; 2634 uint32_t l1el : 3; 2635 uint32_t cpm : 1; 2636 uint32_t sderc : 1; 2637 uint32_t dllarc : 1; 2638 uint32_t lbnc : 1; 2639 uint32_t aspm : 1; 2640 uint32_t reserved_23_23 : 1; 2641 uint32_t pnum : 8; 2642#endif 2643 } s; 2644 struct cvmx_pciercx_cfg031_cn52xx { 2645#ifdef __BIG_ENDIAN_BITFIELD 2646 uint32_t pnum : 8; /**< Port Number, writable through PESC(0..1)_CFG_WR 2647 However, the application must not change this field. */ 2648 uint32_t reserved_22_23 : 2; 2649 uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */ 2650 uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable 2651 Set to 1 for Root Complex devices and 0 for Endpoint devices. */ 2652 uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2653 Not supported, hardwired to 0x0. */ 2654 uint32_t cpm : 1; /**< Clock Power Management 2655 The default value is the value you specify during hardware 2656 configuration, writable through PESC(0..1)_CFG_WR. 2657 However, the application must not change this field. */ 2658 uint32_t l1el : 3; /**< L1 Exit Latency 2659 The default value is the value you specify during hardware 2660 configuration, writable through PESC(0..1)_CFG_WR. 2661 However, the application must not change this field. */ 2662 uint32_t l0el : 3; /**< L0s Exit Latency 2663 The default value is the value you specify during hardware 2664 configuration, writable through PESC(0..1)_CFG_WR. 2665 However, the application must not change this field. */ 2666 uint32_t aslpms : 2; /**< Active State Link PM Support 2667 The default value is the value you specify during hardware 2668 configuration, writable through PESC(0..1)_CFG_WR. 2669 However, the application must not change this field. */ 2670 uint32_t mlw : 6; /**< Maximum Link Width 2671 The default value is the value you specify during hardware 2672 configuration (x1, x4, x8, or x16), writable through PESC(0..1)_CFG_WR. 2673 The SW needs to set this to 0x4 or 0x2 depending on the max 2674 number of lanes (QLM_CFG == 1 set to 0x4 else 0x2). */ 2675 uint32_t mls : 4; /**< Maximum Link Speed 2676 Default value is 0x1 for 2.5 Gbps Link. 2677 This field is writable through PESC(0..1)_CFG_WR. 2678 However, 0x1 is the 2679 only supported value. Therefore, the application must not write 2680 any value other than 0x1 to this field. */ 2681#else 2682 uint32_t mls : 4; 2683 uint32_t mlw : 6; 2684 uint32_t aslpms : 2; 2685 uint32_t l0el : 3; 2686 uint32_t l1el : 3; 2687 uint32_t cpm : 1; 2688 uint32_t sderc : 1; 2689 uint32_t dllarc : 1; 2690 uint32_t lbnc : 1; 2691 uint32_t reserved_22_23 : 2; 2692 uint32_t pnum : 8; 2693#endif 2694 } cn52xx; 2695 struct cvmx_pciercx_cfg031_cn52xx cn52xxp1; 2696 struct cvmx_pciercx_cfg031_cn52xx cn56xx; 2697 struct cvmx_pciercx_cfg031_cn52xx cn56xxp1; 2698 struct cvmx_pciercx_cfg031_s cn61xx; 2699 struct cvmx_pciercx_cfg031_cn52xx cn63xx; 2700 struct cvmx_pciercx_cfg031_cn52xx cn63xxp1; 2701 struct cvmx_pciercx_cfg031_s cn66xx; 2702 struct cvmx_pciercx_cfg031_s cn68xx; 2703 struct cvmx_pciercx_cfg031_cn52xx cn68xxp1; 2704 struct cvmx_pciercx_cfg031_s cnf71xx; 2705}; 2706typedef union cvmx_pciercx_cfg031 cvmx_pciercx_cfg031_t; 2707 2708/** 2709 * cvmx_pcierc#_cfg032 2710 * 2711 * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 1 config space 2712 * (Link Control Register/Link Status Register) 2713 */ 2714union cvmx_pciercx_cfg032 { 2715 uint32_t u32; 2716 struct cvmx_pciercx_cfg032_s { 2717#ifdef __BIG_ENDIAN_BITFIELD 2718 uint32_t lab : 1; /**< Link Autonomous Bandwidth Status 2719 this bit is set to indicate that hardware has autonomously 2720 changed Link speed or width, without the Port transitioning 2721 through DL_Down status, for reasons other than to attempt 2722 to correct unreliable Link operation. */ 2723 uint32_t lbm : 1; /**< Link Bandwidth Management Status 2724 This bit is set to indicate either of the following has 2725 occurred without the Port transitioning through DL_DOWN status 2726 o A link retraining has completed following a write of 1b to 2727 the Retrain Link bit 2728 o Hardware has changed the Link speed or width to attempt to 2729 correct unreliable Link operation, either through a LTSSM 2730 timeout of higher level process. This bit must be set if 2731 the Physical Layer reports a speed or width change was 2732 inititiated by the Downstream component tha was not 2733 indicated as an autonomous change */ 2734 uint32_t dlla : 1; /**< Data Link Layer Active */ 2735 uint32_t scc : 1; /**< Slot Clock Configuration 2736 Indicates that the component uses the same physical reference 2737 clock that the platform provides on the connector. The default 2738 value is the value you select during hardware configuration, 2739 writable through PEM(0..1)_CFG_WR. 2740 However, the application must not change this field. */ 2741 uint32_t lt : 1; /**< Link Training */ 2742 uint32_t reserved_26_26 : 1; 2743 uint32_t nlw : 6; /**< Negotiated Link Width 2744 Set automatically by hardware after Link initialization. 2745 Value is undefined when link is not up. */ 2746 uint32_t ls : 4; /**< Link Speed 2747 0001 == The negotiated Link speed: 2.5 Gbps 2748 0010 == The negotiated Link speed: 5.0 Gbps 2749 0100 == The negotiated Link speed: 8.0 Gbps (Not Supported) */ 2750 uint32_t reserved_12_15 : 4; 2751 uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable 2752 When set, enables the generation of an interrupt to indicate 2753 that the Link Autonomous Bandwidth Status bit has been set. */ 2754 uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable 2755 When set, enables the generation of an interrupt to indicate 2756 that the Link Bandwidth Management Status bit has been set. */ 2757 uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 2758 (Not Supported) */ 2759 uint32_t ecpm : 1; /**< Enable Clock Power Management 2760 Hardwired to 0 if Clock Power Management is disabled in 2761 the Link Capabilities register. */ 2762 uint32_t es : 1; /**< Extended Synch */ 2763 uint32_t ccc : 1; /**< Common Clock Configuration */ 2764 uint32_t rl : 1; /**< Retrain Link */ 2765 uint32_t ld : 1; /**< Link Disable */ 2766 uint32_t rcb : 1; /**< Read Completion Boundary (RCB), writable through PEM(0..1)_CFG_WR 2767 However, the application must not change this field 2768 because an RCB of 64 bytes is not supported. */ 2769 uint32_t reserved_2_2 : 1; 2770 uint32_t aslpc : 2; /**< Active State Link PM Control */ 2771#else 2772 uint32_t aslpc : 2; 2773 uint32_t reserved_2_2 : 1; 2774 uint32_t rcb : 1; 2775 uint32_t ld : 1; 2776 uint32_t rl : 1; 2777 uint32_t ccc : 1; 2778 uint32_t es : 1; 2779 uint32_t ecpm : 1; 2780 uint32_t hawd : 1; 2781 uint32_t lbm_int_enb : 1; 2782 uint32_t lab_int_enb : 1; 2783 uint32_t reserved_12_15 : 4; 2784 uint32_t ls : 4; 2785 uint32_t nlw : 6; 2786 uint32_t reserved_26_26 : 1; 2787 uint32_t lt : 1; 2788 uint32_t scc : 1; 2789 uint32_t dlla : 1; 2790 uint32_t lbm : 1; 2791 uint32_t lab : 1; 2792#endif 2793 } s; 2794 struct cvmx_pciercx_cfg032_s cn52xx; 2795 struct cvmx_pciercx_cfg032_s cn52xxp1; 2796 struct cvmx_pciercx_cfg032_s cn56xx; 2797 struct cvmx_pciercx_cfg032_s cn56xxp1; 2798 struct cvmx_pciercx_cfg032_s cn61xx; 2799 struct cvmx_pciercx_cfg032_s cn63xx; 2800 struct cvmx_pciercx_cfg032_s cn63xxp1; 2801 struct cvmx_pciercx_cfg032_s cn66xx; 2802 struct cvmx_pciercx_cfg032_s cn68xx; 2803 struct cvmx_pciercx_cfg032_s cn68xxp1; 2804 struct cvmx_pciercx_cfg032_s cnf71xx; 2805}; 2806typedef union cvmx_pciercx_cfg032 cvmx_pciercx_cfg032_t; 2807 2808/** 2809 * cvmx_pcierc#_cfg033 2810 * 2811 * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 1 config space 2812 * (Slot Capabilities Register) 2813 */ 2814union cvmx_pciercx_cfg033 { 2815 uint32_t u32; 2816 struct cvmx_pciercx_cfg033_s { 2817#ifdef __BIG_ENDIAN_BITFIELD 2818 uint32_t ps_num : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR 2819 However, the application must not change this field. */ 2820 uint32_t nccs : 1; /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR 2821 However, the application must not change this field. */ 2822 uint32_t emip : 1; /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR 2823 However, the application must not change this field. */ 2824 uint32_t sp_ls : 2; /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR. */ 2825 uint32_t sp_lv : 8; /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR. */ 2826 uint32_t hp_c : 1; /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR 2827 However, the application must not change this field. */ 2828 uint32_t hp_s : 1; /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR 2829 However, the application must not change this field. */ 2830 uint32_t pip : 1; /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR 2831 However, the application must not change this field. */ 2832 uint32_t aip : 1; /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR 2833 However, the application must not change this field. */ 2834 uint32_t mrlsp : 1; /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR 2835 However, the application must not change this field. */ 2836 uint32_t pcp : 1; /**< Power Controller Present, writable through PEM(0..1)_CFG_WR 2837 However, the application must not change this field. */ 2838 uint32_t abp : 1; /**< Attention Button Present, writable through PEM(0..1)_CFG_WR 2839 However, the application must not change this field. */ 2840#else 2841 uint32_t abp : 1; 2842 uint32_t pcp : 1; 2843 uint32_t mrlsp : 1; 2844 uint32_t aip : 1; 2845 uint32_t pip : 1; 2846 uint32_t hp_s : 1; 2847 uint32_t hp_c : 1; 2848 uint32_t sp_lv : 8; 2849 uint32_t sp_ls : 2; 2850 uint32_t emip : 1; 2851 uint32_t nccs : 1; 2852 uint32_t ps_num : 13; 2853#endif 2854 } s; 2855 struct cvmx_pciercx_cfg033_s cn52xx; 2856 struct cvmx_pciercx_cfg033_s cn52xxp1; 2857 struct cvmx_pciercx_cfg033_s cn56xx; 2858 struct cvmx_pciercx_cfg033_s cn56xxp1; 2859 struct cvmx_pciercx_cfg033_s cn61xx; 2860 struct cvmx_pciercx_cfg033_s cn63xx; 2861 struct cvmx_pciercx_cfg033_s cn63xxp1; 2862 struct cvmx_pciercx_cfg033_s cn66xx; 2863 struct cvmx_pciercx_cfg033_s cn68xx; 2864 struct cvmx_pciercx_cfg033_s cn68xxp1; 2865 struct cvmx_pciercx_cfg033_s cnf71xx; 2866}; 2867typedef union cvmx_pciercx_cfg033 cvmx_pciercx_cfg033_t; 2868 2869/** 2870 * cvmx_pcierc#_cfg034 2871 * 2872 * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 1 config space 2873 * (Slot Control Register/Slot Status Register) 2874 */ 2875union cvmx_pciercx_cfg034 { 2876 uint32_t u32; 2877 struct cvmx_pciercx_cfg034_s { 2878#ifdef __BIG_ENDIAN_BITFIELD 2879 uint32_t reserved_25_31 : 7; 2880 uint32_t dlls_c : 1; /**< Data Link Layer State Changed */ 2881 uint32_t emis : 1; /**< Electromechanical Interlock Status */ 2882 uint32_t pds : 1; /**< Presence Detect State */ 2883 uint32_t mrlss : 1; /**< MRL Sensor State */ 2884 uint32_t ccint_d : 1; /**< Command Completed */ 2885 uint32_t pd_c : 1; /**< Presence Detect Changed */ 2886 uint32_t mrls_c : 1; /**< MRL Sensor Changed */ 2887 uint32_t pf_d : 1; /**< Power Fault Detected */ 2888 uint32_t abp_d : 1; /**< Attention Button Pressed */ 2889 uint32_t reserved_13_15 : 3; 2890 uint32_t dlls_en : 1; /**< Data Link Layer State Changed Enable */ 2891 uint32_t emic : 1; /**< Electromechanical Interlock Control */ 2892 uint32_t pcc : 1; /**< Power Controller Control */ 2893 uint32_t pic : 2; /**< Power Indicator Control */ 2894 uint32_t aic : 2; /**< Attention Indicator Control */ 2895 uint32_t hpint_en : 1; /**< Hot-Plug Interrupt Enable */ 2896 uint32_t ccint_en : 1; /**< Command Completed Interrupt Enable */ 2897 uint32_t pd_en : 1; /**< Presence Detect Changed Enable */ 2898 uint32_t mrls_en : 1; /**< MRL Sensor Changed Enable */ 2899 uint32_t pf_en : 1; /**< Power Fault Detected Enable */ 2900 uint32_t abp_en : 1; /**< Attention Button Pressed Enable */ 2901#else 2902 uint32_t abp_en : 1; 2903 uint32_t pf_en : 1; 2904 uint32_t mrls_en : 1; 2905 uint32_t pd_en : 1; 2906 uint32_t ccint_en : 1; 2907 uint32_t hpint_en : 1; 2908 uint32_t aic : 2; 2909 uint32_t pic : 2; 2910 uint32_t pcc : 1; 2911 uint32_t emic : 1; 2912 uint32_t dlls_en : 1; 2913 uint32_t reserved_13_15 : 3; 2914 uint32_t abp_d : 1; 2915 uint32_t pf_d : 1; 2916 uint32_t mrls_c : 1; 2917 uint32_t pd_c : 1; 2918 uint32_t ccint_d : 1; 2919 uint32_t mrlss : 1; 2920 uint32_t pds : 1; 2921 uint32_t emis : 1; 2922 uint32_t dlls_c : 1; 2923 uint32_t reserved_25_31 : 7; 2924#endif 2925 } s; 2926 struct cvmx_pciercx_cfg034_s cn52xx; 2927 struct cvmx_pciercx_cfg034_s cn52xxp1; 2928 struct cvmx_pciercx_cfg034_s cn56xx; 2929 struct cvmx_pciercx_cfg034_s cn56xxp1; 2930 struct cvmx_pciercx_cfg034_s cn61xx; 2931 struct cvmx_pciercx_cfg034_s cn63xx; 2932 struct cvmx_pciercx_cfg034_s cn63xxp1; 2933 struct cvmx_pciercx_cfg034_s cn66xx; 2934 struct cvmx_pciercx_cfg034_s cn68xx; 2935 struct cvmx_pciercx_cfg034_s cn68xxp1; 2936 struct cvmx_pciercx_cfg034_s cnf71xx; 2937}; 2938typedef union cvmx_pciercx_cfg034 cvmx_pciercx_cfg034_t; 2939 2940/** 2941 * cvmx_pcierc#_cfg035 2942 * 2943 * PCIE_CFG035 = Thirty-sixth 32-bits of PCIE type 1 config space 2944 * (Root Control Register/Root Capabilities Register) 2945 */ 2946union cvmx_pciercx_cfg035 { 2947 uint32_t u32; 2948 struct cvmx_pciercx_cfg035_s { 2949#ifdef __BIG_ENDIAN_BITFIELD 2950 uint32_t reserved_17_31 : 15; 2951 uint32_t crssv : 1; /**< CRS Software Visibility 2952 Not supported, hardwired to 0x0. */ 2953 uint32_t reserved_5_15 : 11; 2954 uint32_t crssve : 1; /**< CRS Software Visibility Enable 2955 Not supported, hardwired to 0x0. */ 2956 uint32_t pmeie : 1; /**< PME Interrupt Enable */ 2957 uint32_t sefee : 1; /**< System Error on Fatal Error Enable */ 2958 uint32_t senfee : 1; /**< System Error on Non-fatal Error Enable */ 2959 uint32_t secee : 1; /**< System Error on Correctable Error Enable */ 2960#else 2961 uint32_t secee : 1; 2962 uint32_t senfee : 1; 2963 uint32_t sefee : 1; 2964 uint32_t pmeie : 1; 2965 uint32_t crssve : 1; 2966 uint32_t reserved_5_15 : 11; 2967 uint32_t crssv : 1; 2968 uint32_t reserved_17_31 : 15; 2969#endif 2970 } s; 2971 struct cvmx_pciercx_cfg035_s cn52xx; 2972 struct cvmx_pciercx_cfg035_s cn52xxp1; 2973 struct cvmx_pciercx_cfg035_s cn56xx; 2974 struct cvmx_pciercx_cfg035_s cn56xxp1; 2975 struct cvmx_pciercx_cfg035_s cn61xx; 2976 struct cvmx_pciercx_cfg035_s cn63xx; 2977 struct cvmx_pciercx_cfg035_s cn63xxp1; 2978 struct cvmx_pciercx_cfg035_s cn66xx; 2979 struct cvmx_pciercx_cfg035_s cn68xx; 2980 struct cvmx_pciercx_cfg035_s cn68xxp1; 2981 struct cvmx_pciercx_cfg035_s cnf71xx; 2982}; 2983typedef union cvmx_pciercx_cfg035 cvmx_pciercx_cfg035_t; 2984 2985/** 2986 * cvmx_pcierc#_cfg036 2987 * 2988 * PCIE_CFG036 = Thirty-seventh 32-bits of PCIE type 1 config space 2989 * (Root Status Register) 2990 */ 2991union cvmx_pciercx_cfg036 { 2992 uint32_t u32; 2993 struct cvmx_pciercx_cfg036_s { 2994#ifdef __BIG_ENDIAN_BITFIELD 2995 uint32_t reserved_18_31 : 14; 2996 uint32_t pme_pend : 1; /**< PME Pending */ 2997 uint32_t pme_stat : 1; /**< PME Status */ 2998 uint32_t pme_rid : 16; /**< PME Requester ID */ 2999#else 3000 uint32_t pme_rid : 16; 3001 uint32_t pme_stat : 1; 3002 uint32_t pme_pend : 1; 3003 uint32_t reserved_18_31 : 14; 3004#endif 3005 } s; 3006 struct cvmx_pciercx_cfg036_s cn52xx; 3007 struct cvmx_pciercx_cfg036_s cn52xxp1; 3008 struct cvmx_pciercx_cfg036_s cn56xx; 3009 struct cvmx_pciercx_cfg036_s cn56xxp1; 3010 struct cvmx_pciercx_cfg036_s cn61xx; 3011 struct cvmx_pciercx_cfg036_s cn63xx; 3012 struct cvmx_pciercx_cfg036_s cn63xxp1; 3013 struct cvmx_pciercx_cfg036_s cn66xx; 3014 struct cvmx_pciercx_cfg036_s cn68xx; 3015 struct cvmx_pciercx_cfg036_s cn68xxp1; 3016 struct cvmx_pciercx_cfg036_s cnf71xx; 3017}; 3018typedef union cvmx_pciercx_cfg036 cvmx_pciercx_cfg036_t; 3019 3020/** 3021 * cvmx_pcierc#_cfg037 3022 * 3023 * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 1 config space 3024 * (Device Capabilities 2 Register) 3025 */ 3026union cvmx_pciercx_cfg037 { 3027 uint32_t u32; 3028 struct cvmx_pciercx_cfg037_s { 3029#ifdef __BIG_ENDIAN_BITFIELD 3030 uint32_t reserved_20_31 : 12; 3031 uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported 3032 (Not Supported) */ 3033 uint32_t reserved_12_17 : 6; 3034 uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported 3035 (Not Supported) */ 3036 uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3037 When set, the routing element never carries out the passing 3038 permitted in the Relaxed Ordering Model. */ 3039 uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3040 (Not Supported) */ 3041 uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3042 (Not Supported) */ 3043 uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3044 (Not Supported) */ 3045 uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3046 (Not Supported) */ 3047 uint32_t reserved_5_5 : 1; 3048 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3049 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3050#else 3051 uint32_t ctrs : 4; 3052 uint32_t ctds : 1; 3053 uint32_t reserved_5_5 : 1; 3054 uint32_t atom_ops : 1; 3055 uint32_t atom32s : 1; 3056 uint32_t atom64s : 1; 3057 uint32_t atom128s : 1; 3058 uint32_t noroprpr : 1; 3059 uint32_t ltrs : 1; 3060 uint32_t reserved_12_17 : 6; 3061 uint32_t obffs : 2; 3062 uint32_t reserved_20_31 : 12; 3063#endif 3064 } s; 3065 struct cvmx_pciercx_cfg037_cn52xx { 3066#ifdef __BIG_ENDIAN_BITFIELD 3067 uint32_t reserved_5_31 : 27; 3068 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3069 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported 3070 Value of 0 indicates that Completion Timeout Programming 3071 is not supported 3072 Completion timeout is 16.7ms. */ 3073#else 3074 uint32_t ctrs : 4; 3075 uint32_t ctds : 1; 3076 uint32_t reserved_5_31 : 27; 3077#endif 3078 } cn52xx; 3079 struct cvmx_pciercx_cfg037_cn52xx cn52xxp1; 3080 struct cvmx_pciercx_cfg037_cn52xx cn56xx; 3081 struct cvmx_pciercx_cfg037_cn52xx cn56xxp1; 3082 struct cvmx_pciercx_cfg037_cn61xx { 3083#ifdef __BIG_ENDIAN_BITFIELD 3084 uint32_t reserved_14_31 : 18; 3085 uint32_t tph : 2; /**< TPH Completer Supported 3086 (Not Supported) */ 3087 uint32_t reserved_11_11 : 1; 3088 uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3089 When set, the routing element never carries out the passing 3090 permitted in the Relaxed Ordering Model. */ 3091 uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3092 (Not Supported) */ 3093 uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3094 (Not Supported) */ 3095 uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3096 (Not Supported) */ 3097 uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3098 (Not Supported) */ 3099 uint32_t ari_fw : 1; /**< ARI Forwarding Supported 3100 (Not Supported) */ 3101 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3102 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3103#else 3104 uint32_t ctrs : 4; 3105 uint32_t ctds : 1; 3106 uint32_t ari_fw : 1; 3107 uint32_t atom_ops : 1; 3108 uint32_t atom32s : 1; 3109 uint32_t atom64s : 1; 3110 uint32_t atom128s : 1; 3111 uint32_t noroprpr : 1; 3112 uint32_t reserved_11_11 : 1; 3113 uint32_t tph : 2; 3114 uint32_t reserved_14_31 : 18; 3115#endif 3116 } cn61xx; 3117 struct cvmx_pciercx_cfg037_cn52xx cn63xx; 3118 struct cvmx_pciercx_cfg037_cn52xx cn63xxp1; 3119 struct cvmx_pciercx_cfg037_cn66xx { 3120#ifdef __BIG_ENDIAN_BITFIELD 3121 uint32_t reserved_14_31 : 18; 3122 uint32_t tph : 2; /**< TPH Completer Supported 3123 (Not Supported) */ 3124 uint32_t reserved_11_11 : 1; 3125 uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3126 When set, the routing element never carries out the passing 3127 permitted in the Relaxed Ordering Model. */ 3128 uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3129 (Not Supported) */ 3130 uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3131 (Not Supported) */ 3132 uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3133 (Not Supported) */ 3134 uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3135 (Not Supported) */ 3136 uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3137 (Not Supported) */ 3138 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3139 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3140#else 3141 uint32_t ctrs : 4; 3142 uint32_t ctds : 1; 3143 uint32_t ari : 1; 3144 uint32_t atom_ops : 1; 3145 uint32_t atom32s : 1; 3146 uint32_t atom64s : 1; 3147 uint32_t atom128s : 1; 3148 uint32_t noroprpr : 1; 3149 uint32_t reserved_11_11 : 1; 3150 uint32_t tph : 2; 3151 uint32_t reserved_14_31 : 18; 3152#endif 3153 } cn66xx; 3154 struct cvmx_pciercx_cfg037_cn66xx cn68xx; 3155 struct cvmx_pciercx_cfg037_cn66xx cn68xxp1; 3156 struct cvmx_pciercx_cfg037_cnf71xx { 3157#ifdef __BIG_ENDIAN_BITFIELD 3158 uint32_t reserved_20_31 : 12; 3159 uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported 3160 (Not Supported) */ 3161 uint32_t reserved_14_17 : 4; 3162 uint32_t tphs : 2; /**< TPH Completer Supported 3163 (Not Supported) */ 3164 uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported 3165 (Not Supported) */ 3166 uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3167 When set, the routing element never carries out the passing 3168 permitted in the Relaxed Ordering Model. */ 3169 uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3170 (Not Supported) */ 3171 uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3172 (Not Supported) */ 3173 uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3174 (Not Supported) */ 3175 uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3176 (Not Supported) */ 3177 uint32_t ari_fw : 1; /**< ARI Forwarding Supported 3178 (Not Supported) */ 3179 uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3180 uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3181#else 3182 uint32_t ctrs : 4; 3183 uint32_t ctds : 1; 3184 uint32_t ari_fw : 1; 3185 uint32_t atom_ops : 1; 3186 uint32_t atom32s : 1; 3187 uint32_t atom64s : 1; 3188 uint32_t atom128s : 1; 3189 uint32_t noroprpr : 1; 3190 uint32_t ltrs : 1; 3191 uint32_t tphs : 2; 3192 uint32_t reserved_14_17 : 4; 3193 uint32_t obffs : 2; 3194 uint32_t reserved_20_31 : 12; 3195#endif 3196 } cnf71xx; 3197}; 3198typedef union cvmx_pciercx_cfg037 cvmx_pciercx_cfg037_t; 3199 3200/** 3201 * cvmx_pcierc#_cfg038 3202 * 3203 * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 1 config space 3204 * (Device Control 2 Register) 3205 */ 3206union cvmx_pciercx_cfg038 { 3207 uint32_t u32; 3208 struct cvmx_pciercx_cfg038_s { 3209#ifdef __BIG_ENDIAN_BITFIELD 3210 uint32_t reserved_15_31 : 17; 3211 uint32_t obffe : 2; /**< Optimized Buffer Flush Fill (OBFF) Enable 3212 (Not Supported) */ 3213 uint32_t reserved_11_12 : 2; 3214 uint32_t ltre : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Enable 3215 (Not Supported) */ 3216 uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable 3217 (Not Supported) */ 3218 uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable 3219 (Not Supported) */ 3220 uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking 3221 (Not Supported)m */ 3222 uint32_t atom_op : 1; /**< AtomicOp Requester Enable 3223 (Not Supported) */ 3224 uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3225 (Not Supported) */ 3226 uint32_t ctd : 1; /**< Completion Timeout Disable */ 3227 uint32_t ctv : 4; /**< Completion Timeout Value 3228 o 0000b Default range: 16 ms to 55 ms 3229 o 0001b 50 us to 100 us 3230 o 0010b 1 ms to 10 ms 3231 o 0101b 16 ms to 55 ms 3232 o 0110b 65 ms to 210 ms 3233 o 1001b 260 ms to 900 ms 3234 o 1010b 1 s to 3.5 s 3235 o 1101b 4 s to 13 s 3236 o 1110b 17 s to 64 s 3237 Values not defined are reserved */ 3238#else 3239 uint32_t ctv : 4; 3240 uint32_t ctd : 1; 3241 uint32_t ari : 1; 3242 uint32_t atom_op : 1; 3243 uint32_t atom_op_eb : 1; 3244 uint32_t id0_rq : 1; 3245 uint32_t id0_cp : 1; 3246 uint32_t ltre : 1; 3247 uint32_t reserved_11_12 : 2; 3248 uint32_t obffe : 2; 3249 uint32_t reserved_15_31 : 17; 3250#endif 3251 } s; 3252 struct cvmx_pciercx_cfg038_cn52xx { 3253#ifdef __BIG_ENDIAN_BITFIELD 3254 uint32_t reserved_5_31 : 27; 3255 uint32_t ctd : 1; /**< Completion Timeout Disable */ 3256 uint32_t ctv : 4; /**< Completion Timeout Value 3257 Completion Timeout Programming is not supported 3258 Completion timeout is 16.7ms. */ 3259#else 3260 uint32_t ctv : 4; 3261 uint32_t ctd : 1; 3262 uint32_t reserved_5_31 : 27; 3263#endif 3264 } cn52xx; 3265 struct cvmx_pciercx_cfg038_cn52xx cn52xxp1; 3266 struct cvmx_pciercx_cfg038_cn52xx cn56xx; 3267 struct cvmx_pciercx_cfg038_cn52xx cn56xxp1; 3268 struct cvmx_pciercx_cfg038_cn61xx { 3269#ifdef __BIG_ENDIAN_BITFIELD 3270 uint32_t reserved_10_31 : 22; 3271 uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable 3272 (Not Supported) */ 3273 uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable 3274 (Not Supported) */ 3275 uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking 3276 (Not Supported)m */ 3277 uint32_t atom_op : 1; /**< AtomicOp Requester Enable 3278 (Not Supported) */ 3279 uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3280 (Not Supported) */ 3281 uint32_t ctd : 1; /**< Completion Timeout Disable */ 3282 uint32_t ctv : 4; /**< Completion Timeout Value 3283 o 0000b Default range: 16 ms to 55 ms 3284 o 0001b 50 us to 100 us 3285 o 0010b 1 ms to 10 ms 3286 o 0101b 16 ms to 55 ms 3287 o 0110b 65 ms to 210 ms 3288 o 1001b 260 ms to 900 ms 3289 o 1010b 1 s to 3.5 s 3290 o 1101b 4 s to 13 s 3291 o 1110b 17 s to 64 s 3292 Values not defined are reserved */ 3293#else 3294 uint32_t ctv : 4; 3295 uint32_t ctd : 1; 3296 uint32_t ari : 1; 3297 uint32_t atom_op : 1; 3298 uint32_t atom_op_eb : 1; 3299 uint32_t id0_rq : 1; 3300 uint32_t id0_cp : 1; 3301 uint32_t reserved_10_31 : 22; 3302#endif 3303 } cn61xx; 3304 struct cvmx_pciercx_cfg038_cn52xx cn63xx; 3305 struct cvmx_pciercx_cfg038_cn52xx cn63xxp1; 3306 struct cvmx_pciercx_cfg038_cn61xx cn66xx; 3307 struct cvmx_pciercx_cfg038_cn61xx cn68xx; 3308 struct cvmx_pciercx_cfg038_cn61xx cn68xxp1; 3309 struct cvmx_pciercx_cfg038_s cnf71xx; 3310}; 3311typedef union cvmx_pciercx_cfg038 cvmx_pciercx_cfg038_t; 3312 3313/** 3314 * cvmx_pcierc#_cfg039 3315 * 3316 * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 1 config space 3317 * (Link Capabilities 2 Register) 3318 */ 3319union cvmx_pciercx_cfg039 { 3320 uint32_t u32; 3321 struct cvmx_pciercx_cfg039_s { 3322#ifdef __BIG_ENDIAN_BITFIELD 3323 uint32_t reserved_9_31 : 23; 3324 uint32_t cls : 1; /**< Crosslink Supported */ 3325 uint32_t slsv : 7; /**< Supported Link Speeds Vector 3326 Indicates the supported Link speeds of the associated Port. 3327 For each bit, a value of 1b indicates that the cooresponding 3328 Link speed is supported; otherwise, the Link speed is not 3329 supported. 3330 Bit definitions are: 3331 Bit 1 2.5 GT/s 3332 Bit 2 5.0 GT/s 3333 Bit 3 8.0 GT/s (Not Supported) 3334 Bits 7:4 reserved 3335 The reset value of this field is controlled by a value sent from 3336 the lsb of the MIO_QLM#_SPD register 3337 qlm#_spd[0] RST_VALUE NOTE 3338 1 0001b 2.5 GHz supported 3339 0 0011b 5.0 GHz and 2.5 GHz supported */ 3340 uint32_t reserved_0_0 : 1; 3341#else 3342 uint32_t reserved_0_0 : 1; 3343 uint32_t slsv : 7; 3344 uint32_t cls : 1; 3345 uint32_t reserved_9_31 : 23; 3346#endif 3347 } s; 3348 struct cvmx_pciercx_cfg039_cn52xx { 3349#ifdef __BIG_ENDIAN_BITFIELD 3350 uint32_t reserved_0_31 : 32; 3351#else 3352 uint32_t reserved_0_31 : 32; 3353#endif 3354 } cn52xx; 3355 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; 3356 struct cvmx_pciercx_cfg039_cn52xx cn56xx; 3357 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1; 3358 struct cvmx_pciercx_cfg039_s cn61xx; 3359 struct cvmx_pciercx_cfg039_s cn63xx; 3360 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1; 3361 struct cvmx_pciercx_cfg039_s cn66xx; 3362 struct cvmx_pciercx_cfg039_s cn68xx; 3363 struct cvmx_pciercx_cfg039_s cn68xxp1; 3364 struct cvmx_pciercx_cfg039_s cnf71xx; 3365}; 3366typedef union cvmx_pciercx_cfg039 cvmx_pciercx_cfg039_t; 3367 3368/** 3369 * cvmx_pcierc#_cfg040 3370 * 3371 * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 1 config space 3372 * (Link Control 2 Register/Link Status 2 Register) 3373 */ 3374union cvmx_pciercx_cfg040 { 3375 uint32_t u32; 3376 struct cvmx_pciercx_cfg040_s { 3377#ifdef __BIG_ENDIAN_BITFIELD 3378 uint32_t reserved_17_31 : 15; 3379 uint32_t cdl : 1; /**< Current De-emphasis Level 3380 When the Link is operating at 5 GT/s speed, this bit 3381 reflects the level of de-emphasis. Encodings: 3382 1b: -3.5 dB 3383 0b: -6 dB 3384 Note: The value in this bit is undefined when the Link is 3385 operating at 2.5 GT/s speed */ 3386 uint32_t reserved_13_15 : 3; 3387 uint32_t cde : 1; /**< Compliance De-emphasis 3388 This bit sets the de-emphasis level in Polling. Compliance 3389 state if the entry occurred due to the Tx Compliance 3390 Receive bit being 1b. Encodings: 3391 1b: -3.5 dB 3392 0b: -6 dB 3393 Note: When the Link is operating at 2.5 GT/s, the setting 3394 of this bit has no effect. */ 3395 uint32_t csos : 1; /**< Compliance SOS 3396 When set to 1b, the LTSSM is required to send SKP 3397 Ordered Sets periodically in between the (modified) 3398 compliance patterns. 3399 Note: When the Link is operating at 2.5 GT/s, the setting 3400 of this bit has no effect. */ 3401 uint32_t emc : 1; /**< Enter Modified Compliance 3402 When this bit is set to 1b, the device transmits a modified 3403 compliance pattern if the LTSSM enters Polling. 3404 Compliance state. */ 3405 uint32_t tm : 3; /**< Transmit Margin 3406 This field controls the value of the non-de-emphasized 3407 voltage level at the Transmitter signals: 3408 - 000: 800-1200 mV for full swing 400-600 mV for half-swing 3409 - 001-010: values must be monotonic with a non-zero slope 3410 - 011: 200-400 mV for full-swing and 100-200 mV for halfswing 3411 - 100-111: reserved 3412 This field is reset to 000b on entry to the LTSSM Polling. 3413 Compliance substate. 3414 When operating in 5.0 GT/s mode with full swing, the 3415 de-emphasis ratio must be maintained within +/- 1 dB 3416 from the specification-defined operational value 3417 either -3.5 or -6 dB). */ 3418 uint32_t sde : 1; /**< Selectable De-emphasis 3419 When the Link is operating at 5.0 GT/s speed, selects the 3420 level of de-emphasis: 3421 - 1: -3.5 dB 3422 - 0: -6 dB 3423 When the Link is operating at 2.5 GT/s speed, the setting 3424 of this bit has no effect. */ 3425 uint32_t hasd : 1; /**< Hardware Autonomous Speed Disable 3426 When asserted, the 3427 application must disable hardware from changing the Link 3428 speed for device-specific reasons other than attempting to 3429 correct unreliable Link operation by reducing Link speed. 3430 Initial transition to the highest supported common link 3431 speed is not blocked by this signal. */ 3432 uint32_t ec : 1; /**< Enter Compliance 3433 Software is permitted to force a link to enter Compliance 3434 mode at the speed indicated in the Target Link Speed 3435 field by setting this bit to 1b in both components on a link 3436 and then initiating a hot reset on the link. */ 3437 uint32_t tls : 4; /**< Target Link Speed 3438 For Downstream ports, this field sets an upper limit on link 3439 operational speed by restricting the values advertised by 3440 the upstream component in its training sequences: 3441 - 0001: 2.5Gb/s Target Link Speed 3442 - 0010: 5Gb/s Target Link Speed 3443 - 0100: 8Gb/s Target Link Speed (Not Supported) 3444 All other encodings are reserved. 3445 If a value is written to this field that does not correspond to 3446 a speed included in the Supported Link Speeds field, the 3447 result is undefined. 3448 For both Upstream and Downstream ports, this field is 3449 used to set the target compliance mode speed when 3450 software is using the Enter Compliance bit to force a link 3451 into compliance mode. 3452 The reset value of this field is controlled by a value sent from 3453 the lsb of the MIO_QLM#_SPD register. 3454 qlm#_spd[0] RST_VALUE NOTE 3455 1 0001b 2.5 GHz supported 3456 0 0010b 5.0 GHz and 2.5 GHz supported */ 3457#else 3458 uint32_t tls : 4; 3459 uint32_t ec : 1; 3460 uint32_t hasd : 1; 3461 uint32_t sde : 1; 3462 uint32_t tm : 3; 3463 uint32_t emc : 1; 3464 uint32_t csos : 1; 3465 uint32_t cde : 1; 3466 uint32_t reserved_13_15 : 3; 3467 uint32_t cdl : 1; 3468 uint32_t reserved_17_31 : 15; 3469#endif 3470 } s; 3471 struct cvmx_pciercx_cfg040_cn52xx { 3472#ifdef __BIG_ENDIAN_BITFIELD 3473 uint32_t reserved_0_31 : 32; 3474#else 3475 uint32_t reserved_0_31 : 32; 3476#endif 3477 } cn52xx; 3478 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; 3479 struct cvmx_pciercx_cfg040_cn52xx cn56xx; 3480 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; 3481 struct cvmx_pciercx_cfg040_s cn61xx; 3482 struct cvmx_pciercx_cfg040_s cn63xx; 3483 struct cvmx_pciercx_cfg040_s cn63xxp1; 3484 struct cvmx_pciercx_cfg040_s cn66xx; 3485 struct cvmx_pciercx_cfg040_s cn68xx; 3486 struct cvmx_pciercx_cfg040_s cn68xxp1; 3487 struct cvmx_pciercx_cfg040_s cnf71xx; 3488}; 3489typedef union cvmx_pciercx_cfg040 cvmx_pciercx_cfg040_t; 3490 3491/** 3492 * cvmx_pcierc#_cfg041 3493 * 3494 * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 1 config space 3495 * (Slot Capabilities 2 Register) 3496 */ 3497union cvmx_pciercx_cfg041 { 3498 uint32_t u32; 3499 struct cvmx_pciercx_cfg041_s { 3500#ifdef __BIG_ENDIAN_BITFIELD 3501 uint32_t reserved_0_31 : 32; 3502#else 3503 uint32_t reserved_0_31 : 32; 3504#endif 3505 } s; 3506 struct cvmx_pciercx_cfg041_s cn52xx; 3507 struct cvmx_pciercx_cfg041_s cn52xxp1; 3508 struct cvmx_pciercx_cfg041_s cn56xx; 3509 struct cvmx_pciercx_cfg041_s cn56xxp1; 3510 struct cvmx_pciercx_cfg041_s cn61xx; 3511 struct cvmx_pciercx_cfg041_s cn63xx; 3512 struct cvmx_pciercx_cfg041_s cn63xxp1; 3513 struct cvmx_pciercx_cfg041_s cn66xx; 3514 struct cvmx_pciercx_cfg041_s cn68xx; 3515 struct cvmx_pciercx_cfg041_s cn68xxp1; 3516 struct cvmx_pciercx_cfg041_s cnf71xx; 3517}; 3518typedef union cvmx_pciercx_cfg041 cvmx_pciercx_cfg041_t; 3519 3520/** 3521 * cvmx_pcierc#_cfg042 3522 * 3523 * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 1 config space 3524 * (Slot Control 2 Register/Slot Status 2 Register) 3525 */ 3526union cvmx_pciercx_cfg042 { 3527 uint32_t u32; 3528 struct cvmx_pciercx_cfg042_s { 3529#ifdef __BIG_ENDIAN_BITFIELD 3530 uint32_t reserved_0_31 : 32; 3531#else 3532 uint32_t reserved_0_31 : 32; 3533#endif 3534 } s; 3535 struct cvmx_pciercx_cfg042_s cn52xx; 3536 struct cvmx_pciercx_cfg042_s cn52xxp1; 3537 struct cvmx_pciercx_cfg042_s cn56xx; 3538 struct cvmx_pciercx_cfg042_s cn56xxp1; 3539 struct cvmx_pciercx_cfg042_s cn61xx; 3540 struct cvmx_pciercx_cfg042_s cn63xx; 3541 struct cvmx_pciercx_cfg042_s cn63xxp1; 3542 struct cvmx_pciercx_cfg042_s cn66xx; 3543 struct cvmx_pciercx_cfg042_s cn68xx; 3544 struct cvmx_pciercx_cfg042_s cn68xxp1; 3545 struct cvmx_pciercx_cfg042_s cnf71xx; 3546}; 3547typedef union cvmx_pciercx_cfg042 cvmx_pciercx_cfg042_t; 3548 3549/** 3550 * cvmx_pcierc#_cfg064 3551 * 3552 * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 1 config space 3553 * (PCI Express Extended Capability Header) 3554 */ 3555union cvmx_pciercx_cfg064 { 3556 uint32_t u32; 3557 struct cvmx_pciercx_cfg064_s { 3558#ifdef __BIG_ENDIAN_BITFIELD 3559 uint32_t nco : 12; /**< Next Capability Offset */ 3560 uint32_t cv : 4; /**< Capability Version */ 3561 uint32_t pcieec : 16; /**< PCIE Express Extended Capability */ 3562#else 3563 uint32_t pcieec : 16; 3564 uint32_t cv : 4; 3565 uint32_t nco : 12; 3566#endif 3567 } s; 3568 struct cvmx_pciercx_cfg064_s cn52xx; 3569 struct cvmx_pciercx_cfg064_s cn52xxp1; 3570 struct cvmx_pciercx_cfg064_s cn56xx; 3571 struct cvmx_pciercx_cfg064_s cn56xxp1; 3572 struct cvmx_pciercx_cfg064_s cn61xx; 3573 struct cvmx_pciercx_cfg064_s cn63xx; 3574 struct cvmx_pciercx_cfg064_s cn63xxp1; 3575 struct cvmx_pciercx_cfg064_s cn66xx; 3576 struct cvmx_pciercx_cfg064_s cn68xx; 3577 struct cvmx_pciercx_cfg064_s cn68xxp1; 3578 struct cvmx_pciercx_cfg064_s cnf71xx; 3579}; 3580typedef union cvmx_pciercx_cfg064 cvmx_pciercx_cfg064_t; 3581 3582/** 3583 * cvmx_pcierc#_cfg065 3584 * 3585 * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 1 config space 3586 * (Uncorrectable Error Status Register) 3587 */ 3588union cvmx_pciercx_cfg065 { 3589 uint32_t u32; 3590 struct cvmx_pciercx_cfg065_s { 3591#ifdef __BIG_ENDIAN_BITFIELD 3592 uint32_t reserved_25_31 : 7; 3593 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 3594 uint32_t reserved_23_23 : 1; 3595 uint32_t ucies : 1; /**< Uncorrectable Internal Error Status */ 3596 uint32_t reserved_21_21 : 1; 3597 uint32_t ures : 1; /**< Unsupported Request Error Status */ 3598 uint32_t ecrces : 1; /**< ECRC Error Status */ 3599 uint32_t mtlps : 1; /**< Malformed TLP Status */ 3600 uint32_t ros : 1; /**< Receiver Overflow Status */ 3601 uint32_t ucs : 1; /**< Unexpected Completion Status */ 3602 uint32_t cas : 1; /**< Completer Abort Status */ 3603 uint32_t cts : 1; /**< Completion Timeout Status */ 3604 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3605 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3606 uint32_t reserved_6_11 : 6; 3607 uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3608 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3609 uint32_t reserved_0_3 : 4; 3610#else 3611 uint32_t reserved_0_3 : 4; 3612 uint32_t dlpes : 1; 3613 uint32_t sdes : 1; 3614 uint32_t reserved_6_11 : 6; 3615 uint32_t ptlps : 1; 3616 uint32_t fcpes : 1; 3617 uint32_t cts : 1; 3618 uint32_t cas : 1; 3619 uint32_t ucs : 1; 3620 uint32_t ros : 1; 3621 uint32_t mtlps : 1; 3622 uint32_t ecrces : 1; 3623 uint32_t ures : 1; 3624 uint32_t reserved_21_21 : 1; 3625 uint32_t ucies : 1; 3626 uint32_t reserved_23_23 : 1; 3627 uint32_t uatombs : 1; 3628 uint32_t reserved_25_31 : 7; 3629#endif 3630 } s; 3631 struct cvmx_pciercx_cfg065_cn52xx { 3632#ifdef __BIG_ENDIAN_BITFIELD 3633 uint32_t reserved_21_31 : 11; 3634 uint32_t ures : 1; /**< Unsupported Request Error Status */ 3635 uint32_t ecrces : 1; /**< ECRC Error Status */ 3636 uint32_t mtlps : 1; /**< Malformed TLP Status */ 3637 uint32_t ros : 1; /**< Receiver Overflow Status */ 3638 uint32_t ucs : 1; /**< Unexpected Completion Status */ 3639 uint32_t cas : 1; /**< Completer Abort Status */ 3640 uint32_t cts : 1; /**< Completion Timeout Status */ 3641 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3642 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3643 uint32_t reserved_6_11 : 6; 3644 uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3645 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3646 uint32_t reserved_0_3 : 4; 3647#else 3648 uint32_t reserved_0_3 : 4; 3649 uint32_t dlpes : 1; 3650 uint32_t sdes : 1; 3651 uint32_t reserved_6_11 : 6; 3652 uint32_t ptlps : 1; 3653 uint32_t fcpes : 1; 3654 uint32_t cts : 1; 3655 uint32_t cas : 1; 3656 uint32_t ucs : 1; 3657 uint32_t ros : 1; 3658 uint32_t mtlps : 1; 3659 uint32_t ecrces : 1; 3660 uint32_t ures : 1; 3661 uint32_t reserved_21_31 : 11; 3662#endif 3663 } cn52xx; 3664 struct cvmx_pciercx_cfg065_cn52xx cn52xxp1; 3665 struct cvmx_pciercx_cfg065_cn52xx cn56xx; 3666 struct cvmx_pciercx_cfg065_cn52xx cn56xxp1; 3667 struct cvmx_pciercx_cfg065_cn61xx { 3668#ifdef __BIG_ENDIAN_BITFIELD 3669 uint32_t reserved_25_31 : 7; 3670 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 3671 uint32_t reserved_21_23 : 3; 3672 uint32_t ures : 1; /**< Unsupported Request Error Status */ 3673 uint32_t ecrces : 1; /**< ECRC Error Status */ 3674 uint32_t mtlps : 1; /**< Malformed TLP Status */ 3675 uint32_t ros : 1; /**< Receiver Overflow Status */ 3676 uint32_t ucs : 1; /**< Unexpected Completion Status */ 3677 uint32_t cas : 1; /**< Completer Abort Status */ 3678 uint32_t cts : 1; /**< Completion Timeout Status */ 3679 uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3680 uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3681 uint32_t reserved_6_11 : 6; 3682 uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3683 uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3684 uint32_t reserved_0_3 : 4; 3685#else 3686 uint32_t reserved_0_3 : 4; 3687 uint32_t dlpes : 1; 3688 uint32_t sdes : 1; 3689 uint32_t reserved_6_11 : 6; 3690 uint32_t ptlps : 1; 3691 uint32_t fcpes : 1; 3692 uint32_t cts : 1; 3693 uint32_t cas : 1; 3694 uint32_t ucs : 1; 3695 uint32_t ros : 1; 3696 uint32_t mtlps : 1; 3697 uint32_t ecrces : 1; 3698 uint32_t ures : 1; 3699 uint32_t reserved_21_23 : 3; 3700 uint32_t uatombs : 1; 3701 uint32_t reserved_25_31 : 7; 3702#endif 3703 } cn61xx; 3704 struct cvmx_pciercx_cfg065_cn52xx cn63xx; 3705 struct cvmx_pciercx_cfg065_cn52xx cn63xxp1; 3706 struct cvmx_pciercx_cfg065_cn61xx cn66xx; 3707 struct cvmx_pciercx_cfg065_cn61xx cn68xx; 3708 struct cvmx_pciercx_cfg065_cn52xx cn68xxp1; 3709 struct cvmx_pciercx_cfg065_s cnf71xx; 3710}; 3711typedef union cvmx_pciercx_cfg065 cvmx_pciercx_cfg065_t; 3712 3713/** 3714 * cvmx_pcierc#_cfg066 3715 * 3716 * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 1 config space 3717 * (Uncorrectable Error Mask Register) 3718 */ 3719union cvmx_pciercx_cfg066 { 3720 uint32_t u32; 3721 struct cvmx_pciercx_cfg066_s { 3722#ifdef __BIG_ENDIAN_BITFIELD 3723 uint32_t reserved_25_31 : 7; 3724 uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 3725 uint32_t reserved_23_23 : 1; 3726 uint32_t uciem : 1; /**< Uncorrectable Internal Error Mask */ 3727 uint32_t reserved_21_21 : 1; 3728 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 3729 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 3730 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 3731 uint32_t rom : 1; /**< Receiver Overflow Mask */ 3732 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 3733 uint32_t cam : 1; /**< Completer Abort Mask */ 3734 uint32_t ctm : 1; /**< Completion Timeout Mask */ 3735 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 3736 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 3737 uint32_t reserved_6_11 : 6; 3738 uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 3739 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 3740 uint32_t reserved_0_3 : 4; 3741#else 3742 uint32_t reserved_0_3 : 4; 3743 uint32_t dlpem : 1; 3744 uint32_t sdem : 1; 3745 uint32_t reserved_6_11 : 6; 3746 uint32_t ptlpm : 1; 3747 uint32_t fcpem : 1; 3748 uint32_t ctm : 1; 3749 uint32_t cam : 1; 3750 uint32_t ucm : 1; 3751 uint32_t rom : 1; 3752 uint32_t mtlpm : 1; 3753 uint32_t ecrcem : 1; 3754 uint32_t urem : 1; 3755 uint32_t reserved_21_21 : 1; 3756 uint32_t uciem : 1; 3757 uint32_t reserved_23_23 : 1; 3758 uint32_t uatombm : 1; 3759 uint32_t reserved_25_31 : 7; 3760#endif 3761 } s; 3762 struct cvmx_pciercx_cfg066_cn52xx { 3763#ifdef __BIG_ENDIAN_BITFIELD 3764 uint32_t reserved_21_31 : 11; 3765 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 3766 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 3767 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 3768 uint32_t rom : 1; /**< Receiver Overflow Mask */ 3769 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 3770 uint32_t cam : 1; /**< Completer Abort Mask */ 3771 uint32_t ctm : 1; /**< Completion Timeout Mask */ 3772 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 3773 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 3774 uint32_t reserved_6_11 : 6; 3775 uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 3776 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 3777 uint32_t reserved_0_3 : 4; 3778#else 3779 uint32_t reserved_0_3 : 4; 3780 uint32_t dlpem : 1; 3781 uint32_t sdem : 1; 3782 uint32_t reserved_6_11 : 6; 3783 uint32_t ptlpm : 1; 3784 uint32_t fcpem : 1; 3785 uint32_t ctm : 1; 3786 uint32_t cam : 1; 3787 uint32_t ucm : 1; 3788 uint32_t rom : 1; 3789 uint32_t mtlpm : 1; 3790 uint32_t ecrcem : 1; 3791 uint32_t urem : 1; 3792 uint32_t reserved_21_31 : 11; 3793#endif 3794 } cn52xx; 3795 struct cvmx_pciercx_cfg066_cn52xx cn52xxp1; 3796 struct cvmx_pciercx_cfg066_cn52xx cn56xx; 3797 struct cvmx_pciercx_cfg066_cn52xx cn56xxp1; 3798 struct cvmx_pciercx_cfg066_cn61xx { 3799#ifdef __BIG_ENDIAN_BITFIELD 3800 uint32_t reserved_25_31 : 7; 3801 uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 3802 uint32_t reserved_21_23 : 3; 3803 uint32_t urem : 1; /**< Unsupported Request Error Mask */ 3804 uint32_t ecrcem : 1; /**< ECRC Error Mask */ 3805 uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 3806 uint32_t rom : 1; /**< Receiver Overflow Mask */ 3807 uint32_t ucm : 1; /**< Unexpected Completion Mask */ 3808 uint32_t cam : 1; /**< Completer Abort Mask */ 3809 uint32_t ctm : 1; /**< Completion Timeout Mask */ 3810 uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 3811 uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 3812 uint32_t reserved_6_11 : 6; 3813 uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 3814 uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 3815 uint32_t reserved_0_3 : 4; 3816#else 3817 uint32_t reserved_0_3 : 4; 3818 uint32_t dlpem : 1; 3819 uint32_t sdem : 1; 3820 uint32_t reserved_6_11 : 6; 3821 uint32_t ptlpm : 1; 3822 uint32_t fcpem : 1; 3823 uint32_t ctm : 1; 3824 uint32_t cam : 1; 3825 uint32_t ucm : 1; 3826 uint32_t rom : 1; 3827 uint32_t mtlpm : 1; 3828 uint32_t ecrcem : 1; 3829 uint32_t urem : 1; 3830 uint32_t reserved_21_23 : 3; 3831 uint32_t uatombm : 1; 3832 uint32_t reserved_25_31 : 7; 3833#endif 3834 } cn61xx; 3835 struct cvmx_pciercx_cfg066_cn52xx cn63xx; 3836 struct cvmx_pciercx_cfg066_cn52xx cn63xxp1; 3837 struct cvmx_pciercx_cfg066_cn61xx cn66xx; 3838 struct cvmx_pciercx_cfg066_cn61xx cn68xx; 3839 struct cvmx_pciercx_cfg066_cn52xx cn68xxp1; 3840 struct cvmx_pciercx_cfg066_s cnf71xx; 3841}; 3842typedef union cvmx_pciercx_cfg066 cvmx_pciercx_cfg066_t; 3843 3844/** 3845 * cvmx_pcierc#_cfg067 3846 * 3847 * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 1 config space 3848 * (Uncorrectable Error Severity Register) 3849 */ 3850union cvmx_pciercx_cfg067 { 3851 uint32_t u32; 3852 struct cvmx_pciercx_cfg067_s { 3853#ifdef __BIG_ENDIAN_BITFIELD 3854 uint32_t reserved_25_31 : 7; 3855 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 3856 uint32_t reserved_23_23 : 1; 3857 uint32_t ucies : 1; /**< Uncorrectable Internal Error Severity */ 3858 uint32_t reserved_21_21 : 1; 3859 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 3860 uint32_t ecrces : 1; /**< ECRC Error Severity */ 3861 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 3862 uint32_t ros : 1; /**< Receiver Overflow Severity */ 3863 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 3864 uint32_t cas : 1; /**< Completer Abort Severity */ 3865 uint32_t cts : 1; /**< Completion Timeout Severity */ 3866 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 3867 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 3868 uint32_t reserved_6_11 : 6; 3869 uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 3870 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 3871 uint32_t reserved_0_3 : 4; 3872#else 3873 uint32_t reserved_0_3 : 4; 3874 uint32_t dlpes : 1; 3875 uint32_t sdes : 1; 3876 uint32_t reserved_6_11 : 6; 3877 uint32_t ptlps : 1; 3878 uint32_t fcpes : 1; 3879 uint32_t cts : 1; 3880 uint32_t cas : 1; 3881 uint32_t ucs : 1; 3882 uint32_t ros : 1; 3883 uint32_t mtlps : 1; 3884 uint32_t ecrces : 1; 3885 uint32_t ures : 1; 3886 uint32_t reserved_21_21 : 1; 3887 uint32_t ucies : 1; 3888 uint32_t reserved_23_23 : 1; 3889 uint32_t uatombs : 1; 3890 uint32_t reserved_25_31 : 7; 3891#endif 3892 } s; 3893 struct cvmx_pciercx_cfg067_cn52xx { 3894#ifdef __BIG_ENDIAN_BITFIELD 3895 uint32_t reserved_21_31 : 11; 3896 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 3897 uint32_t ecrces : 1; /**< ECRC Error Severity */ 3898 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 3899 uint32_t ros : 1; /**< Receiver Overflow Severity */ 3900 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 3901 uint32_t cas : 1; /**< Completer Abort Severity */ 3902 uint32_t cts : 1; /**< Completion Timeout Severity */ 3903 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 3904 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 3905 uint32_t reserved_6_11 : 6; 3906 uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 3907 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 3908 uint32_t reserved_0_3 : 4; 3909#else 3910 uint32_t reserved_0_3 : 4; 3911 uint32_t dlpes : 1; 3912 uint32_t sdes : 1; 3913 uint32_t reserved_6_11 : 6; 3914 uint32_t ptlps : 1; 3915 uint32_t fcpes : 1; 3916 uint32_t cts : 1; 3917 uint32_t cas : 1; 3918 uint32_t ucs : 1; 3919 uint32_t ros : 1; 3920 uint32_t mtlps : 1; 3921 uint32_t ecrces : 1; 3922 uint32_t ures : 1; 3923 uint32_t reserved_21_31 : 11; 3924#endif 3925 } cn52xx; 3926 struct cvmx_pciercx_cfg067_cn52xx cn52xxp1; 3927 struct cvmx_pciercx_cfg067_cn52xx cn56xx; 3928 struct cvmx_pciercx_cfg067_cn52xx cn56xxp1; 3929 struct cvmx_pciercx_cfg067_cn61xx { 3930#ifdef __BIG_ENDIAN_BITFIELD 3931 uint32_t reserved_25_31 : 7; 3932 uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 3933 uint32_t reserved_21_23 : 3; 3934 uint32_t ures : 1; /**< Unsupported Request Error Severity */ 3935 uint32_t ecrces : 1; /**< ECRC Error Severity */ 3936 uint32_t mtlps : 1; /**< Malformed TLP Severity */ 3937 uint32_t ros : 1; /**< Receiver Overflow Severity */ 3938 uint32_t ucs : 1; /**< Unexpected Completion Severity */ 3939 uint32_t cas : 1; /**< Completer Abort Severity */ 3940 uint32_t cts : 1; /**< Completion Timeout Severity */ 3941 uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 3942 uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 3943 uint32_t reserved_6_11 : 6; 3944 uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 3945 uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 3946 uint32_t reserved_0_3 : 4; 3947#else 3948 uint32_t reserved_0_3 : 4; 3949 uint32_t dlpes : 1; 3950 uint32_t sdes : 1; 3951 uint32_t reserved_6_11 : 6; 3952 uint32_t ptlps : 1; 3953 uint32_t fcpes : 1; 3954 uint32_t cts : 1; 3955 uint32_t cas : 1; 3956 uint32_t ucs : 1; 3957 uint32_t ros : 1; 3958 uint32_t mtlps : 1; 3959 uint32_t ecrces : 1; 3960 uint32_t ures : 1; 3961 uint32_t reserved_21_23 : 3; 3962 uint32_t uatombs : 1; 3963 uint32_t reserved_25_31 : 7; 3964#endif 3965 } cn61xx; 3966 struct cvmx_pciercx_cfg067_cn52xx cn63xx; 3967 struct cvmx_pciercx_cfg067_cn52xx cn63xxp1; 3968 struct cvmx_pciercx_cfg067_cn61xx cn66xx; 3969 struct cvmx_pciercx_cfg067_cn61xx cn68xx; 3970 struct cvmx_pciercx_cfg067_cn52xx cn68xxp1; 3971 struct cvmx_pciercx_cfg067_s cnf71xx; 3972}; 3973typedef union cvmx_pciercx_cfg067 cvmx_pciercx_cfg067_t; 3974 3975/** 3976 * cvmx_pcierc#_cfg068 3977 * 3978 * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 1 config space 3979 * (Correctable Error Status Register) 3980 */ 3981union cvmx_pciercx_cfg068 { 3982 uint32_t u32; 3983 struct cvmx_pciercx_cfg068_s { 3984#ifdef __BIG_ENDIAN_BITFIELD 3985 uint32_t reserved_15_31 : 17; 3986 uint32_t cies : 1; /**< Corrected Internal Error Status */ 3987 uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 3988 uint32_t rtts : 1; /**< Replay Timer Timeout Status */ 3989 uint32_t reserved_9_11 : 3; 3990 uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 3991 uint32_t bdllps : 1; /**< Bad DLLP Status */ 3992 uint32_t btlps : 1; /**< Bad TLP Status */ 3993 uint32_t reserved_1_5 : 5; 3994 uint32_t res : 1; /**< Receiver Error Status */ 3995#else 3996 uint32_t res : 1; 3997 uint32_t reserved_1_5 : 5; 3998 uint32_t btlps : 1; 3999 uint32_t bdllps : 1; 4000 uint32_t rnrs : 1; 4001 uint32_t reserved_9_11 : 3; 4002 uint32_t rtts : 1; 4003 uint32_t anfes : 1; 4004 uint32_t cies : 1; 4005 uint32_t reserved_15_31 : 17; 4006#endif 4007 } s; 4008 struct cvmx_pciercx_cfg068_cn52xx { 4009#ifdef __BIG_ENDIAN_BITFIELD 4010 uint32_t reserved_14_31 : 18; 4011 uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 4012 uint32_t rtts : 1; /**< Replay Timer Timeout Status */ 4013 uint32_t reserved_9_11 : 3; 4014 uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 4015 uint32_t bdllps : 1; /**< Bad DLLP Status */ 4016 uint32_t btlps : 1; /**< Bad TLP Status */ 4017 uint32_t reserved_1_5 : 5; 4018 uint32_t res : 1; /**< Receiver Error Status */ 4019#else 4020 uint32_t res : 1; 4021 uint32_t reserved_1_5 : 5; 4022 uint32_t btlps : 1; 4023 uint32_t bdllps : 1; 4024 uint32_t rnrs : 1; 4025 uint32_t reserved_9_11 : 3; 4026 uint32_t rtts : 1; 4027 uint32_t anfes : 1; 4028 uint32_t reserved_14_31 : 18; 4029#endif 4030 } cn52xx; 4031 struct cvmx_pciercx_cfg068_cn52xx cn52xxp1; 4032 struct cvmx_pciercx_cfg068_cn52xx cn56xx; 4033 struct cvmx_pciercx_cfg068_cn52xx cn56xxp1; 4034 struct cvmx_pciercx_cfg068_cn52xx cn61xx; 4035 struct cvmx_pciercx_cfg068_cn52xx cn63xx; 4036 struct cvmx_pciercx_cfg068_cn52xx cn63xxp1; 4037 struct cvmx_pciercx_cfg068_cn52xx cn66xx; 4038 struct cvmx_pciercx_cfg068_cn52xx cn68xx; 4039 struct cvmx_pciercx_cfg068_cn52xx cn68xxp1; 4040 struct cvmx_pciercx_cfg068_s cnf71xx; 4041}; 4042typedef union cvmx_pciercx_cfg068 cvmx_pciercx_cfg068_t; 4043 4044/** 4045 * cvmx_pcierc#_cfg069 4046 * 4047 * PCIE_CFG069 = Seventieth 32-bits of PCIE type 1 config space 4048 * (Correctable Error Mask Register) 4049 */ 4050union cvmx_pciercx_cfg069 { 4051 uint32_t u32; 4052 struct cvmx_pciercx_cfg069_s { 4053#ifdef __BIG_ENDIAN_BITFIELD 4054 uint32_t reserved_15_31 : 17; 4055 uint32_t ciem : 1; /**< Corrected Internal Error Mask */ 4056 uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 4057 uint32_t rttm : 1; /**< Replay Timer Timeout Mask */ 4058 uint32_t reserved_9_11 : 3; 4059 uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 4060 uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 4061 uint32_t btlpm : 1; /**< Bad TLP Mask */ 4062 uint32_t reserved_1_5 : 5; 4063 uint32_t rem : 1; /**< Receiver Error Mask */ 4064#else 4065 uint32_t rem : 1; 4066 uint32_t reserved_1_5 : 5; 4067 uint32_t btlpm : 1; 4068 uint32_t bdllpm : 1; 4069 uint32_t rnrm : 1; 4070 uint32_t reserved_9_11 : 3; 4071 uint32_t rttm : 1; 4072 uint32_t anfem : 1; 4073 uint32_t ciem : 1; 4074 uint32_t reserved_15_31 : 17; 4075#endif 4076 } s; 4077 struct cvmx_pciercx_cfg069_cn52xx { 4078#ifdef __BIG_ENDIAN_BITFIELD 4079 uint32_t reserved_14_31 : 18; 4080 uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 4081 uint32_t rttm : 1; /**< Replay Timer Timeout Mask */ 4082 uint32_t reserved_9_11 : 3; 4083 uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 4084 uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 4085 uint32_t btlpm : 1; /**< Bad TLP Mask */ 4086 uint32_t reserved_1_5 : 5; 4087 uint32_t rem : 1; /**< Receiver Error Mask */ 4088#else 4089 uint32_t rem : 1; 4090 uint32_t reserved_1_5 : 5; 4091 uint32_t btlpm : 1; 4092 uint32_t bdllpm : 1; 4093 uint32_t rnrm : 1; 4094 uint32_t reserved_9_11 : 3; 4095 uint32_t rttm : 1; 4096 uint32_t anfem : 1; 4097 uint32_t reserved_14_31 : 18; 4098#endif 4099 } cn52xx; 4100 struct cvmx_pciercx_cfg069_cn52xx cn52xxp1; 4101 struct cvmx_pciercx_cfg069_cn52xx cn56xx; 4102 struct cvmx_pciercx_cfg069_cn52xx cn56xxp1; 4103 struct cvmx_pciercx_cfg069_cn52xx cn61xx; 4104 struct cvmx_pciercx_cfg069_cn52xx cn63xx; 4105 struct cvmx_pciercx_cfg069_cn52xx cn63xxp1; 4106 struct cvmx_pciercx_cfg069_cn52xx cn66xx; 4107 struct cvmx_pciercx_cfg069_cn52xx cn68xx; 4108 struct cvmx_pciercx_cfg069_cn52xx cn68xxp1; 4109 struct cvmx_pciercx_cfg069_s cnf71xx; 4110}; 4111typedef union cvmx_pciercx_cfg069 cvmx_pciercx_cfg069_t; 4112 4113/** 4114 * cvmx_pcierc#_cfg070 4115 * 4116 * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 1 config space 4117 * (Advanced Capabilities and Control Register) 4118 */ 4119union cvmx_pciercx_cfg070 { 4120 uint32_t u32; 4121 struct cvmx_pciercx_cfg070_s { 4122#ifdef __BIG_ENDIAN_BITFIELD 4123 uint32_t reserved_9_31 : 23; 4124 uint32_t ce : 1; /**< ECRC Check Enable */ 4125 uint32_t cc : 1; /**< ECRC Check Capable */ 4126 uint32_t ge : 1; /**< ECRC Generation Enable */ 4127 uint32_t gc : 1; /**< ECRC Generation Capability */ 4128 uint32_t fep : 5; /**< First Error Pointer */ 4129#else 4130 uint32_t fep : 5; 4131 uint32_t gc : 1; 4132 uint32_t ge : 1; 4133 uint32_t cc : 1; 4134 uint32_t ce : 1; 4135 uint32_t reserved_9_31 : 23; 4136#endif 4137 } s; 4138 struct cvmx_pciercx_cfg070_s cn52xx; 4139 struct cvmx_pciercx_cfg070_s cn52xxp1; 4140 struct cvmx_pciercx_cfg070_s cn56xx; 4141 struct cvmx_pciercx_cfg070_s cn56xxp1; 4142 struct cvmx_pciercx_cfg070_s cn61xx; 4143 struct cvmx_pciercx_cfg070_s cn63xx; 4144 struct cvmx_pciercx_cfg070_s cn63xxp1; 4145 struct cvmx_pciercx_cfg070_s cn66xx; 4146 struct cvmx_pciercx_cfg070_s cn68xx; 4147 struct cvmx_pciercx_cfg070_s cn68xxp1; 4148 struct cvmx_pciercx_cfg070_s cnf71xx; 4149}; 4150typedef union cvmx_pciercx_cfg070 cvmx_pciercx_cfg070_t; 4151 4152/** 4153 * cvmx_pcierc#_cfg071 4154 * 4155 * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 1 config space 4156 * (Header Log Register 1) 4157 * 4158 * The Header Log registers collect the header for the TLP corresponding to a detected error. 4159 */ 4160union cvmx_pciercx_cfg071 { 4161 uint32_t u32; 4162 struct cvmx_pciercx_cfg071_s { 4163#ifdef __BIG_ENDIAN_BITFIELD 4164 uint32_t dword1 : 32; /**< Header Log Register (first DWORD) */ 4165#else 4166 uint32_t dword1 : 32; 4167#endif 4168 } s; 4169 struct cvmx_pciercx_cfg071_s cn52xx; 4170 struct cvmx_pciercx_cfg071_s cn52xxp1; 4171 struct cvmx_pciercx_cfg071_s cn56xx; 4172 struct cvmx_pciercx_cfg071_s cn56xxp1; 4173 struct cvmx_pciercx_cfg071_s cn61xx; 4174 struct cvmx_pciercx_cfg071_s cn63xx; 4175 struct cvmx_pciercx_cfg071_s cn63xxp1; 4176 struct cvmx_pciercx_cfg071_s cn66xx; 4177 struct cvmx_pciercx_cfg071_s cn68xx; 4178 struct cvmx_pciercx_cfg071_s cn68xxp1; 4179 struct cvmx_pciercx_cfg071_s cnf71xx; 4180}; 4181typedef union cvmx_pciercx_cfg071 cvmx_pciercx_cfg071_t; 4182 4183/** 4184 * cvmx_pcierc#_cfg072 4185 * 4186 * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 1 config space 4187 * (Header Log Register 2) 4188 * 4189 * The Header Log registers collect the header for the TLP corresponding to a detected error. 4190 */ 4191union cvmx_pciercx_cfg072 { 4192 uint32_t u32; 4193 struct cvmx_pciercx_cfg072_s { 4194#ifdef __BIG_ENDIAN_BITFIELD 4195 uint32_t dword2 : 32; /**< Header Log Register (second DWORD) */ 4196#else 4197 uint32_t dword2 : 32; 4198#endif 4199 } s; 4200 struct cvmx_pciercx_cfg072_s cn52xx; 4201 struct cvmx_pciercx_cfg072_s cn52xxp1; 4202 struct cvmx_pciercx_cfg072_s cn56xx; 4203 struct cvmx_pciercx_cfg072_s cn56xxp1; 4204 struct cvmx_pciercx_cfg072_s cn61xx; 4205 struct cvmx_pciercx_cfg072_s cn63xx; 4206 struct cvmx_pciercx_cfg072_s cn63xxp1; 4207 struct cvmx_pciercx_cfg072_s cn66xx; 4208 struct cvmx_pciercx_cfg072_s cn68xx; 4209 struct cvmx_pciercx_cfg072_s cn68xxp1; 4210 struct cvmx_pciercx_cfg072_s cnf71xx; 4211}; 4212typedef union cvmx_pciercx_cfg072 cvmx_pciercx_cfg072_t; 4213 4214/** 4215 * cvmx_pcierc#_cfg073 4216 * 4217 * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 1 config space 4218 * (Header Log Register 3) 4219 * 4220 * The Header Log registers collect the header for the TLP corresponding to a detected error. 4221 */ 4222union cvmx_pciercx_cfg073 { 4223 uint32_t u32; 4224 struct cvmx_pciercx_cfg073_s { 4225#ifdef __BIG_ENDIAN_BITFIELD 4226 uint32_t dword3 : 32; /**< Header Log Register (third DWORD) */ 4227#else 4228 uint32_t dword3 : 32; 4229#endif 4230 } s; 4231 struct cvmx_pciercx_cfg073_s cn52xx; 4232 struct cvmx_pciercx_cfg073_s cn52xxp1; 4233 struct cvmx_pciercx_cfg073_s cn56xx; 4234 struct cvmx_pciercx_cfg073_s cn56xxp1; 4235 struct cvmx_pciercx_cfg073_s cn61xx; 4236 struct cvmx_pciercx_cfg073_s cn63xx; 4237 struct cvmx_pciercx_cfg073_s cn63xxp1; 4238 struct cvmx_pciercx_cfg073_s cn66xx; 4239 struct cvmx_pciercx_cfg073_s cn68xx; 4240 struct cvmx_pciercx_cfg073_s cn68xxp1; 4241 struct cvmx_pciercx_cfg073_s cnf71xx; 4242}; 4243typedef union cvmx_pciercx_cfg073 cvmx_pciercx_cfg073_t; 4244 4245/** 4246 * cvmx_pcierc#_cfg074 4247 * 4248 * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 1 config space 4249 * (Header Log Register 4) 4250 * 4251 * The Header Log registers collect the header for the TLP corresponding to a detected error. 4252 */ 4253union cvmx_pciercx_cfg074 { 4254 uint32_t u32; 4255 struct cvmx_pciercx_cfg074_s { 4256#ifdef __BIG_ENDIAN_BITFIELD 4257 uint32_t dword4 : 32; /**< Header Log Register (fourth DWORD) */ 4258#else 4259 uint32_t dword4 : 32; 4260#endif 4261 } s; 4262 struct cvmx_pciercx_cfg074_s cn52xx; 4263 struct cvmx_pciercx_cfg074_s cn52xxp1; 4264 struct cvmx_pciercx_cfg074_s cn56xx; 4265 struct cvmx_pciercx_cfg074_s cn56xxp1; 4266 struct cvmx_pciercx_cfg074_s cn61xx; 4267 struct cvmx_pciercx_cfg074_s cn63xx; 4268 struct cvmx_pciercx_cfg074_s cn63xxp1; 4269 struct cvmx_pciercx_cfg074_s cn66xx; 4270 struct cvmx_pciercx_cfg074_s cn68xx; 4271 struct cvmx_pciercx_cfg074_s cn68xxp1; 4272 struct cvmx_pciercx_cfg074_s cnf71xx; 4273}; 4274typedef union cvmx_pciercx_cfg074 cvmx_pciercx_cfg074_t; 4275 4276/** 4277 * cvmx_pcierc#_cfg075 4278 * 4279 * PCIE_CFG075 = Seventy-sixth 32-bits of PCIE type 1 config space 4280 * (Root Error Command Register) 4281 */ 4282union cvmx_pciercx_cfg075 { 4283 uint32_t u32; 4284 struct cvmx_pciercx_cfg075_s { 4285#ifdef __BIG_ENDIAN_BITFIELD 4286 uint32_t reserved_3_31 : 29; 4287 uint32_t fere : 1; /**< Fatal Error Reporting Enable */ 4288 uint32_t nfere : 1; /**< Non-Fatal Error Reporting Enable */ 4289 uint32_t cere : 1; /**< Correctable Error Reporting Enable */ 4290#else 4291 uint32_t cere : 1; 4292 uint32_t nfere : 1; 4293 uint32_t fere : 1; 4294 uint32_t reserved_3_31 : 29; 4295#endif 4296 } s; 4297 struct cvmx_pciercx_cfg075_s cn52xx; 4298 struct cvmx_pciercx_cfg075_s cn52xxp1; 4299 struct cvmx_pciercx_cfg075_s cn56xx; 4300 struct cvmx_pciercx_cfg075_s cn56xxp1; 4301 struct cvmx_pciercx_cfg075_s cn61xx; 4302 struct cvmx_pciercx_cfg075_s cn63xx; 4303 struct cvmx_pciercx_cfg075_s cn63xxp1; 4304 struct cvmx_pciercx_cfg075_s cn66xx; 4305 struct cvmx_pciercx_cfg075_s cn68xx; 4306 struct cvmx_pciercx_cfg075_s cn68xxp1; 4307 struct cvmx_pciercx_cfg075_s cnf71xx; 4308}; 4309typedef union cvmx_pciercx_cfg075 cvmx_pciercx_cfg075_t; 4310 4311/** 4312 * cvmx_pcierc#_cfg076 4313 * 4314 * PCIE_CFG076 = Seventy-seventh 32-bits of PCIE type 1 config space 4315 * (Root Error Status Register) 4316 */ 4317union cvmx_pciercx_cfg076 { 4318 uint32_t u32; 4319 struct cvmx_pciercx_cfg076_s { 4320#ifdef __BIG_ENDIAN_BITFIELD 4321 uint32_t aeimn : 5; /**< Advanced Error Interrupt Message Number, 4322 writable through PEM(0..1)_CFG_WR */ 4323 uint32_t reserved_7_26 : 20; 4324 uint32_t femr : 1; /**< Fatal Error Messages Received */ 4325 uint32_t nfemr : 1; /**< Non-Fatal Error Messages Received */ 4326 uint32_t fuf : 1; /**< First Uncorrectable Fatal */ 4327 uint32_t multi_efnfr : 1; /**< Multiple ERR_FATAL/NONFATAL Received */ 4328 uint32_t efnfr : 1; /**< ERR_FATAL/NONFATAL Received */ 4329 uint32_t multi_ecr : 1; /**< Multiple ERR_COR Received */ 4330 uint32_t ecr : 1; /**< ERR_COR Received */ 4331#else 4332 uint32_t ecr : 1; 4333 uint32_t multi_ecr : 1; 4334 uint32_t efnfr : 1; 4335 uint32_t multi_efnfr : 1; 4336 uint32_t fuf : 1; 4337 uint32_t nfemr : 1; 4338 uint32_t femr : 1; 4339 uint32_t reserved_7_26 : 20; 4340 uint32_t aeimn : 5; 4341#endif 4342 } s; 4343 struct cvmx_pciercx_cfg076_s cn52xx; 4344 struct cvmx_pciercx_cfg076_s cn52xxp1; 4345 struct cvmx_pciercx_cfg076_s cn56xx; 4346 struct cvmx_pciercx_cfg076_s cn56xxp1; 4347 struct cvmx_pciercx_cfg076_s cn61xx; 4348 struct cvmx_pciercx_cfg076_s cn63xx; 4349 struct cvmx_pciercx_cfg076_s cn63xxp1; 4350 struct cvmx_pciercx_cfg076_s cn66xx; 4351 struct cvmx_pciercx_cfg076_s cn68xx; 4352 struct cvmx_pciercx_cfg076_s cn68xxp1; 4353 struct cvmx_pciercx_cfg076_s cnf71xx; 4354}; 4355typedef union cvmx_pciercx_cfg076 cvmx_pciercx_cfg076_t; 4356 4357/** 4358 * cvmx_pcierc#_cfg077 4359 * 4360 * PCIE_CFG077 = Seventy-eighth 32-bits of PCIE type 1 config space 4361 * (Error Source Identification Register) 4362 */ 4363union cvmx_pciercx_cfg077 { 4364 uint32_t u32; 4365 struct cvmx_pciercx_cfg077_s { 4366#ifdef __BIG_ENDIAN_BITFIELD 4367 uint32_t efnfsi : 16; /**< ERR_FATAL/NONFATAL Source Identification */ 4368 uint32_t ecsi : 16; /**< ERR_COR Source Identification */ 4369#else 4370 uint32_t ecsi : 16; 4371 uint32_t efnfsi : 16; 4372#endif 4373 } s; 4374 struct cvmx_pciercx_cfg077_s cn52xx; 4375 struct cvmx_pciercx_cfg077_s cn52xxp1; 4376 struct cvmx_pciercx_cfg077_s cn56xx; 4377 struct cvmx_pciercx_cfg077_s cn56xxp1; 4378 struct cvmx_pciercx_cfg077_s cn61xx; 4379 struct cvmx_pciercx_cfg077_s cn63xx; 4380 struct cvmx_pciercx_cfg077_s cn63xxp1; 4381 struct cvmx_pciercx_cfg077_s cn66xx; 4382 struct cvmx_pciercx_cfg077_s cn68xx; 4383 struct cvmx_pciercx_cfg077_s cn68xxp1; 4384 struct cvmx_pciercx_cfg077_s cnf71xx; 4385}; 4386typedef union cvmx_pciercx_cfg077 cvmx_pciercx_cfg077_t; 4387 4388/** 4389 * cvmx_pcierc#_cfg448 4390 * 4391 * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 1 config space 4392 * (Ack Latency Timer and Replay Timer Register) 4393 */ 4394union cvmx_pciercx_cfg448 { 4395 uint32_t u32; 4396 struct cvmx_pciercx_cfg448_s { 4397#ifdef __BIG_ENDIAN_BITFIELD 4398 uint32_t rtl : 16; /**< Replay Time Limit 4399 The replay timer expires when it reaches this limit. The PCI 4400 Express bus initiates a replay upon reception of a Nak or when 4401 the replay timer expires. 4402 This value will be set correctly by the hardware out of reset 4403 or when the negotiated Link-Width or Payload-Size changes. If 4404 the user changes this value through a CSR write or by an 4405 EEPROM load then they should refer to the PCIe Specification 4406 for the correct value. */ 4407 uint32_t rtltl : 16; /**< Round Trip Latency Time Limit 4408 The Ack/Nak latency timer expires when it reaches this limit. 4409 This value will be set correctly by the hardware out of reset 4410 or when the negotiated Link-Width or Payload-Size changes. If 4411 the user changes this value through a CSR write or by an 4412 EEPROM load then they should refer to the PCIe Specification 4413 for the correct value. */ 4414#else 4415 uint32_t rtltl : 16; 4416 uint32_t rtl : 16; 4417#endif 4418 } s; 4419 struct cvmx_pciercx_cfg448_s cn52xx; 4420 struct cvmx_pciercx_cfg448_s cn52xxp1; 4421 struct cvmx_pciercx_cfg448_s cn56xx; 4422 struct cvmx_pciercx_cfg448_s cn56xxp1; 4423 struct cvmx_pciercx_cfg448_s cn61xx; 4424 struct cvmx_pciercx_cfg448_s cn63xx; 4425 struct cvmx_pciercx_cfg448_s cn63xxp1; 4426 struct cvmx_pciercx_cfg448_s cn66xx; 4427 struct cvmx_pciercx_cfg448_s cn68xx; 4428 struct cvmx_pciercx_cfg448_s cn68xxp1; 4429 struct cvmx_pciercx_cfg448_s cnf71xx; 4430}; 4431typedef union cvmx_pciercx_cfg448 cvmx_pciercx_cfg448_t; 4432 4433/** 4434 * cvmx_pcierc#_cfg449 4435 * 4436 * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 1 config space 4437 * (Other Message Register) 4438 */ 4439union cvmx_pciercx_cfg449 { 4440 uint32_t u32; 4441 struct cvmx_pciercx_cfg449_s { 4442#ifdef __BIG_ENDIAN_BITFIELD 4443 uint32_t omr : 32; /**< Other Message Register 4444 This register can be used for either of the following purposes: 4445 o To send a specific PCI Express Message, the application 4446 writes the payload of the Message into this register, then 4447 sets bit 0 of the Port Link Control Register to send the 4448 Message. 4449 o To store a corruption pattern for corrupting the LCRC on all 4450 TLPs, the application places a 32-bit corruption pattern into 4451 this register and enables this function by setting bit 25 of 4452 the Port Link Control Register. When enabled, the transmit 4453 LCRC result is XOR'd with this pattern before inserting 4454 it into the packet. */ 4455#else 4456 uint32_t omr : 32; 4457#endif 4458 } s; 4459 struct cvmx_pciercx_cfg449_s cn52xx; 4460 struct cvmx_pciercx_cfg449_s cn52xxp1; 4461 struct cvmx_pciercx_cfg449_s cn56xx; 4462 struct cvmx_pciercx_cfg449_s cn56xxp1; 4463 struct cvmx_pciercx_cfg449_s cn61xx; 4464 struct cvmx_pciercx_cfg449_s cn63xx; 4465 struct cvmx_pciercx_cfg449_s cn63xxp1; 4466 struct cvmx_pciercx_cfg449_s cn66xx; 4467 struct cvmx_pciercx_cfg449_s cn68xx; 4468 struct cvmx_pciercx_cfg449_s cn68xxp1; 4469 struct cvmx_pciercx_cfg449_s cnf71xx; 4470}; 4471typedef union cvmx_pciercx_cfg449 cvmx_pciercx_cfg449_t; 4472 4473/** 4474 * cvmx_pcierc#_cfg450 4475 * 4476 * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 1 config space 4477 * (Port Force Link Register) 4478 */ 4479union cvmx_pciercx_cfg450 { 4480 uint32_t u32; 4481 struct cvmx_pciercx_cfg450_s { 4482#ifdef __BIG_ENDIAN_BITFIELD 4483 uint32_t lpec : 8; /**< Low Power Entrance Count 4484 The Power Management state will wait for this many clock cycles 4485 for the associated completion of a CfgWr to PCIE_CFG017 register 4486 Power State (PS) field register to go low-power. This register 4487 is intended for applications that do not let the PCI Express 4488 bus handle a completion for configuration request to the 4489 Power Management Control and Status (PCIE_CFG017) register. */ 4490 uint32_t reserved_22_23 : 2; 4491 uint32_t link_state : 6; /**< Link State 4492 The Link state that the PCI Express Bus will be forced to 4493 when bit 15 (Force Link) is set. 4494 State encoding: 4495 o DETECT_QUIET 00h 4496 o DETECT_ACT 01h 4497 o POLL_ACTIVE 02h 4498 o POLL_COMPLIANCE 03h 4499 o POLL_CONFIG 04h 4500 o PRE_DETECT_QUIET 05h 4501 o DETECT_WAIT 06h 4502 o CFG_LINKWD_START 07h 4503 o CFG_LINKWD_ACEPT 08h 4504 o CFG_LANENUM_WAIT 09h 4505 o CFG_LANENUM_ACEPT 0Ah 4506 o CFG_COMPLETE 0Bh 4507 o CFG_IDLE 0Ch 4508 o RCVRY_LOCK 0Dh 4509 o RCVRY_SPEED 0Eh 4510 o RCVRY_RCVRCFG 0Fh 4511 o RCVRY_IDLE 10h 4512 o L0 11h 4513 o L0S 12h 4514 o L123_SEND_EIDLE 13h 4515 o L1_IDLE 14h 4516 o L2_IDLE 15h 4517 o L2_WAKE 16h 4518 o DISABLED_ENTRY 17h 4519 o DISABLED_IDLE 18h 4520 o DISABLED 19h 4521 o LPBK_ENTRY 1Ah 4522 o LPBK_ACTIVE 1Bh 4523 o LPBK_EXIT 1Ch 4524 o LPBK_EXIT_TIMEOUT 1Dh 4525 o HOT_RESET_ENTRY 1Eh 4526 o HOT_RESET 1Fh */ 4527 uint32_t force_link : 1; /**< Force Link 4528 Forces the Link to the state specified by the Link State field. 4529 The Force Link pulse will trigger Link re-negotiation. 4530 * As the The Force Link is a pulse, writing a 1 to it does 4531 trigger the forced link state event, even thought reading it 4532 always returns a 0. */ 4533 uint32_t reserved_8_14 : 7; 4534 uint32_t link_num : 8; /**< Link Number */ 4535#else 4536 uint32_t link_num : 8; 4537 uint32_t reserved_8_14 : 7; 4538 uint32_t force_link : 1; 4539 uint32_t link_state : 6; 4540 uint32_t reserved_22_23 : 2; 4541 uint32_t lpec : 8; 4542#endif 4543 } s; 4544 struct cvmx_pciercx_cfg450_s cn52xx; 4545 struct cvmx_pciercx_cfg450_s cn52xxp1; 4546 struct cvmx_pciercx_cfg450_s cn56xx; 4547 struct cvmx_pciercx_cfg450_s cn56xxp1; 4548 struct cvmx_pciercx_cfg450_s cn61xx; 4549 struct cvmx_pciercx_cfg450_s cn63xx; 4550 struct cvmx_pciercx_cfg450_s cn63xxp1; 4551 struct cvmx_pciercx_cfg450_s cn66xx; 4552 struct cvmx_pciercx_cfg450_s cn68xx; 4553 struct cvmx_pciercx_cfg450_s cn68xxp1; 4554 struct cvmx_pciercx_cfg450_s cnf71xx; 4555}; 4556typedef union cvmx_pciercx_cfg450 cvmx_pciercx_cfg450_t; 4557 4558/** 4559 * cvmx_pcierc#_cfg451 4560 * 4561 * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 1 config space 4562 * (Ack Frequency Register) 4563 */ 4564union cvmx_pciercx_cfg451 { 4565 uint32_t u32; 4566 struct cvmx_pciercx_cfg451_s { 4567#ifdef __BIG_ENDIAN_BITFIELD 4568 uint32_t reserved_31_31 : 1; 4569 uint32_t easpml1 : 1; /**< Enter ASPM L1 without receive in L0s 4570 Allow core to enter ASPM L1 even when link partner did 4571 not go to L0s (receive is not in L0s). 4572 When not set, core goes to ASPM L1 only after idle period 4573 during which both receive and transmit are in L0s. */ 4574 uint32_t l1el : 3; /**< L1 Entrance Latency 4575 Values correspond to: 4576 o 000: 1 ms 4577 o 001: 2 ms 4578 o 010: 4 ms 4579 o 011: 8 ms 4580 o 100: 16 ms 4581 o 101: 32 ms 4582 o 110 or 111: 64 ms */ 4583 uint32_t l0el : 3; /**< L0s Entrance Latency 4584 Values correspond to: 4585 o 000: 1 ms 4586 o 001: 2 ms 4587 o 010: 3 ms 4588 o 011: 4 ms 4589 o 100: 5 ms 4590 o 101: 6 ms 4591 o 110 or 111: 7 ms */ 4592 uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 4593 The number of Fast Training Sequence ordered sets to be 4594 transmitted when transitioning from L0s to L0. The maximum 4595 number of FTS ordered-sets that a component can request is 255. 4596 Note: The core does not support a value of zero; a value of 4597 zero can cause the LTSSM to go into the recovery state 4598 when exiting from L0s. */ 4599 uint32_t n_fts : 8; /**< N_FTS 4600 The number of Fast Training Sequence ordered sets to be 4601 transmitted when transitioning from L0s to L0. The maximum 4602 number of FTS ordered-sets that a component can request is 255. 4603 Note: The core does not support a value of zero; a value of 4604 zero can cause the LTSSM to go into the recovery state 4605 when exiting from L0s. */ 4606 uint32_t ack_freq : 8; /**< Ack Frequency 4607 The number of pending Ack's specified here (up to 255) before 4608 sending an Ack. */ 4609#else 4610 uint32_t ack_freq : 8; 4611 uint32_t n_fts : 8; 4612 uint32_t n_fts_cc : 8; 4613 uint32_t l0el : 3; 4614 uint32_t l1el : 3; 4615 uint32_t easpml1 : 1; 4616 uint32_t reserved_31_31 : 1; 4617#endif 4618 } s; 4619 struct cvmx_pciercx_cfg451_cn52xx { 4620#ifdef __BIG_ENDIAN_BITFIELD 4621 uint32_t reserved_30_31 : 2; 4622 uint32_t l1el : 3; /**< L1 Entrance Latency 4623 Values correspond to: 4624 o 000: 1 ms 4625 o 001: 2 ms 4626 o 010: 4 ms 4627 o 011: 8 ms 4628 o 100: 16 ms 4629 o 101: 32 ms 4630 o 110 or 111: 64 ms */ 4631 uint32_t l0el : 3; /**< L0s Entrance Latency 4632 Values correspond to: 4633 o 000: 1 ms 4634 o 001: 2 ms 4635 o 010: 3 ms 4636 o 011: 4 ms 4637 o 100: 5 ms 4638 o 101: 6 ms 4639 o 110 or 111: 7 ms */ 4640 uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 4641 The number of Fast Training Sequence ordered sets to be 4642 transmitted when transitioning from L0s to L0. The maximum 4643 number of FTS ordered-sets that a component can request is 255. 4644 Note: The core does not support a value of zero; a value of 4645 zero can cause the LTSSM to go into the recovery state 4646 when exiting from L0s. */ 4647 uint32_t n_fts : 8; /**< N_FTS 4648 The number of Fast Training Sequence ordered sets to be 4649 transmitted when transitioning from L0s to L0. The maximum 4650 number of FTS ordered-sets that a component can request is 255. 4651 Note: The core does not support a value of zero; a value of 4652 zero can cause the LTSSM to go into the recovery state 4653 when exiting from L0s. */ 4654 uint32_t ack_freq : 8; /**< Ack Frequency 4655 The number of pending Ack's specified here (up to 255) before 4656 sending an Ack. */ 4657#else 4658 uint32_t ack_freq : 8; 4659 uint32_t n_fts : 8; 4660 uint32_t n_fts_cc : 8; 4661 uint32_t l0el : 3; 4662 uint32_t l1el : 3; 4663 uint32_t reserved_30_31 : 2; 4664#endif 4665 } cn52xx; 4666 struct cvmx_pciercx_cfg451_cn52xx cn52xxp1; 4667 struct cvmx_pciercx_cfg451_cn52xx cn56xx; 4668 struct cvmx_pciercx_cfg451_cn52xx cn56xxp1; 4669 struct cvmx_pciercx_cfg451_s cn61xx; 4670 struct cvmx_pciercx_cfg451_cn52xx cn63xx; 4671 struct cvmx_pciercx_cfg451_cn52xx cn63xxp1; 4672 struct cvmx_pciercx_cfg451_s cn66xx; 4673 struct cvmx_pciercx_cfg451_s cn68xx; 4674 struct cvmx_pciercx_cfg451_s cn68xxp1; 4675 struct cvmx_pciercx_cfg451_s cnf71xx; 4676}; 4677typedef union cvmx_pciercx_cfg451 cvmx_pciercx_cfg451_t; 4678 4679/** 4680 * cvmx_pcierc#_cfg452 4681 * 4682 * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 1 config space 4683 * (Port Link Control Register) 4684 */ 4685union cvmx_pciercx_cfg452 { 4686 uint32_t u32; 4687 struct cvmx_pciercx_cfg452_s { 4688#ifdef __BIG_ENDIAN_BITFIELD 4689 uint32_t reserved_26_31 : 6; 4690 uint32_t eccrc : 1; /**< Enable Corrupted CRC 4691 Causes corrupt LCRC for TLPs when set, 4692 using the pattern contained in the Other Message register. 4693 This is a test feature, not to be used in normal operation. */ 4694 uint32_t reserved_22_24 : 3; 4695 uint32_t lme : 6; /**< Link Mode Enable 4696 o 000001: x1 4697 o 000011: x2 4698 o 000111: x4 (not supported) 4699 o 001111: x8 (not supported) 4700 o 011111: x16 (not supported) 4701 o 111111: x32 (not supported) 4702 This field indicates the MAXIMUM number of lanes supported 4703 by the PCIe port. The value can be set less than 0x3 4704 to limit the number of lanes the PCIe will attempt to use. 4705 The programming of this field needs to be done by SW BEFORE 4706 enabling the link. See also MLW. 4707 (Note: The value of this field does NOT indicate the number 4708 of lanes in use by the PCIe. LME sets the max number of lanes 4709 in the PCIe core that COULD be used. As per the PCIe specs, 4710 the PCIe core can negotiate a smaller link width, so 4711 x1 is also supported when LME=0x3, for example.) */ 4712 uint32_t reserved_8_15 : 8; 4713 uint32_t flm : 1; /**< Fast Link Mode 4714 Sets all internal timers to fast mode for simulation purposes. */ 4715 uint32_t reserved_6_6 : 1; 4716 uint32_t dllle : 1; /**< DLL Link Enable 4717 Enables Link initialization. If DLL Link Enable = 0, the PCI 4718 Express bus does not transmit InitFC DLLPs and does not 4719 establish a Link. */ 4720 uint32_t reserved_4_4 : 1; 4721 uint32_t ra : 1; /**< Reset Assert 4722 Triggers a recovery and forces the LTSSM to the Hot Reset 4723 state (downstream port only). */ 4724 uint32_t le : 1; /**< Loopback Enable 4725 Initiate loopback mode as a master. On a 0->1 transition, 4726 the PCIe core sends TS ordered sets with the loopback bit set 4727 to cause the link partner to enter into loopback mode as a 4728 slave. Normal transmission is not possible when LE=1. To exit 4729 loopback mode, take the link through a reset sequence. */ 4730 uint32_t sd : 1; /**< Scramble Disable 4731 Turns off data scrambling. */ 4732 uint32_t omr : 1; /**< Other Message Request 4733 When software writes a `1' to this bit, the PCI Express bus 4734 transmits the Message contained in the Other Message register. */ 4735#else 4736 uint32_t omr : 1; 4737 uint32_t sd : 1; 4738 uint32_t le : 1; 4739 uint32_t ra : 1; 4740 uint32_t reserved_4_4 : 1; 4741 uint32_t dllle : 1; 4742 uint32_t reserved_6_6 : 1; 4743 uint32_t flm : 1; 4744 uint32_t reserved_8_15 : 8; 4745 uint32_t lme : 6; 4746 uint32_t reserved_22_24 : 3; 4747 uint32_t eccrc : 1; 4748 uint32_t reserved_26_31 : 6; 4749#endif 4750 } s; 4751 struct cvmx_pciercx_cfg452_s cn52xx; 4752 struct cvmx_pciercx_cfg452_s cn52xxp1; 4753 struct cvmx_pciercx_cfg452_s cn56xx; 4754 struct cvmx_pciercx_cfg452_s cn56xxp1; 4755 struct cvmx_pciercx_cfg452_cn61xx { 4756#ifdef __BIG_ENDIAN_BITFIELD 4757 uint32_t reserved_22_31 : 10; 4758 uint32_t lme : 6; /**< Link Mode Enable 4759 o 000001: x1 4760 o 000011: x2 4761 o 000111: x4 4762 o 001111: x8 (not supported) 4763 o 011111: x16 (not supported) 4764 o 111111: x32 (not supported) 4765 This field indicates the MAXIMUM number of lanes supported 4766 by the PCIe port. The value can be set less than 0x7 4767 to limit the number of lanes the PCIe will attempt to use. 4768 The programming of this field needs to be done by SW BEFORE 4769 enabling the link. See also MLW. 4770 (Note: The value of this field does NOT indicate the number 4771 of lanes in use by the PCIe. LME sets the max number of lanes 4772 in the PCIe core that COULD be used. As per the PCIe specs, 4773 the PCIe core can negotiate a smaller link width, so all 4774 of x4, x2, and x1 are supported when LME=0x7, 4775 for example.) */ 4776 uint32_t reserved_8_15 : 8; 4777 uint32_t flm : 1; /**< Fast Link Mode 4778 Sets all internal timers to fast mode for simulation purposes. */ 4779 uint32_t reserved_6_6 : 1; 4780 uint32_t dllle : 1; /**< DLL Link Enable 4781 Enables Link initialization. If DLL Link Enable = 0, the PCI 4782 Express bus does not transmit InitFC DLLPs and does not 4783 establish a Link. */ 4784 uint32_t reserved_4_4 : 1; 4785 uint32_t ra : 1; /**< Reset Assert 4786 Triggers a recovery and forces the LTSSM to the Hot Reset 4787 state (downstream port only). */ 4788 uint32_t le : 1; /**< Loopback Enable 4789 Initiate loopback mode as a master. On a 0->1 transition, 4790 the PCIe core sends TS ordered sets with the loopback bit set 4791 to cause the link partner to enter into loopback mode as a 4792 slave. Normal transmission is not possible when LE=1. To exit 4793 loopback mode, take the link through a reset sequence. */ 4794 uint32_t sd : 1; /**< Scramble Disable 4795 Turns off data scrambling. */ 4796 uint32_t omr : 1; /**< Other Message Request 4797 When software writes a `1' to this bit, the PCI Express bus 4798 transmits the Message contained in the Other Message register. */ 4799#else 4800 uint32_t omr : 1; 4801 uint32_t sd : 1; 4802 uint32_t le : 1; 4803 uint32_t ra : 1; 4804 uint32_t reserved_4_4 : 1; 4805 uint32_t dllle : 1; 4806 uint32_t reserved_6_6 : 1; 4807 uint32_t flm : 1; 4808 uint32_t reserved_8_15 : 8; 4809 uint32_t lme : 6; 4810 uint32_t reserved_22_31 : 10; 4811#endif 4812 } cn61xx; 4813 struct cvmx_pciercx_cfg452_s cn63xx; 4814 struct cvmx_pciercx_cfg452_s cn63xxp1; 4815 struct cvmx_pciercx_cfg452_cn61xx cn66xx; 4816 struct cvmx_pciercx_cfg452_cn61xx cn68xx; 4817 struct cvmx_pciercx_cfg452_cn61xx cn68xxp1; 4818 struct cvmx_pciercx_cfg452_cn61xx cnf71xx; 4819}; 4820typedef union cvmx_pciercx_cfg452 cvmx_pciercx_cfg452_t; 4821 4822/** 4823 * cvmx_pcierc#_cfg453 4824 * 4825 * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 1 config space 4826 * (Lane Skew Register) 4827 */ 4828union cvmx_pciercx_cfg453 { 4829 uint32_t u32; 4830 struct cvmx_pciercx_cfg453_s { 4831#ifdef __BIG_ENDIAN_BITFIELD 4832 uint32_t dlld : 1; /**< Disable Lane-to-Lane Deskew 4833 Disables the internal Lane-to-Lane deskew logic. */ 4834 uint32_t reserved_26_30 : 5; 4835 uint32_t ack_nak : 1; /**< Ack/Nak Disable 4836 Prevents the PCI Express bus from sending Ack and Nak DLLPs. */ 4837 uint32_t fcd : 1; /**< Flow Control Disable 4838 Prevents the PCI Express bus from sending FC DLLPs. */ 4839 uint32_t ilst : 24; /**< Insert Lane Skew for Transmit (not supported for x16) 4840 Causes skew between lanes for test purposes. There are three 4841 bits per Lane. The value is in units of one symbol time. For 4842 example, the value 010b for a Lane forces a skew of two symbol 4843 times for that Lane. The maximum skew value for any Lane is 5 4844 symbol times. */ 4845#else 4846 uint32_t ilst : 24; 4847 uint32_t fcd : 1; 4848 uint32_t ack_nak : 1; 4849 uint32_t reserved_26_30 : 5; 4850 uint32_t dlld : 1; 4851#endif 4852 } s; 4853 struct cvmx_pciercx_cfg453_s cn52xx; 4854 struct cvmx_pciercx_cfg453_s cn52xxp1; 4855 struct cvmx_pciercx_cfg453_s cn56xx; 4856 struct cvmx_pciercx_cfg453_s cn56xxp1; 4857 struct cvmx_pciercx_cfg453_s cn61xx; 4858 struct cvmx_pciercx_cfg453_s cn63xx; 4859 struct cvmx_pciercx_cfg453_s cn63xxp1; 4860 struct cvmx_pciercx_cfg453_s cn66xx; 4861 struct cvmx_pciercx_cfg453_s cn68xx; 4862 struct cvmx_pciercx_cfg453_s cn68xxp1; 4863 struct cvmx_pciercx_cfg453_s cnf71xx; 4864}; 4865typedef union cvmx_pciercx_cfg453 cvmx_pciercx_cfg453_t; 4866 4867/** 4868 * cvmx_pcierc#_cfg454 4869 * 4870 * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 1 config space 4871 * (Symbol Number Register) 4872 */ 4873union cvmx_pciercx_cfg454 { 4874 uint32_t u32; 4875 struct cvmx_pciercx_cfg454_s { 4876#ifdef __BIG_ENDIAN_BITFIELD 4877 uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1) 4878 Configuration Requests targeted at function numbers above this 4879 value will be returned with unsupported request */ 4880 uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 4881 Increases the timer value for the Flow Control watchdog timer, 4882 in increments of 16 clock cycles. */ 4883 uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 4884 Increases the timer value for the Ack/Nak latency timer, in 4885 increments of 64 clock cycles. */ 4886 uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 4887 Increases the timer value for the replay timer, in increments 4888 of 64 clock cycles. */ 4889 uint32_t reserved_11_13 : 3; 4890 uint32_t nskps : 3; /**< Number of SKP Symbols */ 4891 uint32_t reserved_0_7 : 8; 4892#else 4893 uint32_t reserved_0_7 : 8; 4894 uint32_t nskps : 3; 4895 uint32_t reserved_11_13 : 3; 4896 uint32_t tmrt : 5; 4897 uint32_t tmanlt : 5; 4898 uint32_t tmfcwt : 5; 4899 uint32_t cx_nfunc : 3; 4900#endif 4901 } s; 4902 struct cvmx_pciercx_cfg454_cn52xx { 4903#ifdef __BIG_ENDIAN_BITFIELD 4904 uint32_t reserved_29_31 : 3; 4905 uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 4906 Increases the timer value for the Flow Control watchdog timer, 4907 in increments of 16 clock cycles. */ 4908 uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 4909 Increases the timer value for the Ack/Nak latency timer, in 4910 increments of 64 clock cycles. */ 4911 uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 4912 Increases the timer value for the replay timer, in increments 4913 of 64 clock cycles. */ 4914 uint32_t reserved_11_13 : 3; 4915 uint32_t nskps : 3; /**< Number of SKP Symbols */ 4916 uint32_t reserved_4_7 : 4; 4917 uint32_t ntss : 4; /**< Number of TS Symbols 4918 Sets the number of TS identifier symbols that are sent in TS1 4919 and TS2 ordered sets. */ 4920#else 4921 uint32_t ntss : 4; 4922 uint32_t reserved_4_7 : 4; 4923 uint32_t nskps : 3; 4924 uint32_t reserved_11_13 : 3; 4925 uint32_t tmrt : 5; 4926 uint32_t tmanlt : 5; 4927 uint32_t tmfcwt : 5; 4928 uint32_t reserved_29_31 : 3; 4929#endif 4930 } cn52xx; 4931 struct cvmx_pciercx_cfg454_cn52xx cn52xxp1; 4932 struct cvmx_pciercx_cfg454_cn52xx cn56xx; 4933 struct cvmx_pciercx_cfg454_cn52xx cn56xxp1; 4934 struct cvmx_pciercx_cfg454_cn61xx { 4935#ifdef __BIG_ENDIAN_BITFIELD 4936 uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1) 4937 Configuration Requests targeted at function numbers above this 4938 value will be returned with unsupported request */ 4939 uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 4940 Increases the timer value for the Flow Control watchdog timer, 4941 in increments of 16 clock cycles. */ 4942 uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 4943 Increases the timer value for the Ack/Nak latency timer, in 4944 increments of 64 clock cycles. */ 4945 uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 4946 Increases the timer value for the replay timer, in increments 4947 of 64 clock cycles. */ 4948 uint32_t reserved_8_13 : 6; 4949 uint32_t mfuncn : 8; /**< Max Number of Functions Supported */ 4950#else 4951 uint32_t mfuncn : 8; 4952 uint32_t reserved_8_13 : 6; 4953 uint32_t tmrt : 5; 4954 uint32_t tmanlt : 5; 4955 uint32_t tmfcwt : 5; 4956 uint32_t cx_nfunc : 3; 4957#endif 4958 } cn61xx; 4959 struct cvmx_pciercx_cfg454_cn52xx cn63xx; 4960 struct cvmx_pciercx_cfg454_cn52xx cn63xxp1; 4961 struct cvmx_pciercx_cfg454_cn61xx cn66xx; 4962 struct cvmx_pciercx_cfg454_cn61xx cn68xx; 4963 struct cvmx_pciercx_cfg454_cn52xx cn68xxp1; 4964 struct cvmx_pciercx_cfg454_cn61xx cnf71xx; 4965}; 4966typedef union cvmx_pciercx_cfg454 cvmx_pciercx_cfg454_t; 4967 4968/** 4969 * cvmx_pcierc#_cfg455 4970 * 4971 * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 1 config space 4972 * (Symbol Timer Register/Filter Mask Register 1) 4973 */ 4974union cvmx_pciercx_cfg455 { 4975 uint32_t u32; 4976 struct cvmx_pciercx_cfg455_s { 4977#ifdef __BIG_ENDIAN_BITFIELD 4978 uint32_t m_cfg0_filt : 1; /**< Mask filtering of received Configuration Requests (RC mode only) */ 4979 uint32_t m_io_filt : 1; /**< Mask filtering of received I/O Requests (RC mode only) */ 4980 uint32_t msg_ctrl : 1; /**< Message Control 4981 The application must not change this field. */ 4982 uint32_t m_cpl_ecrc_filt : 1; /**< Mask ECRC error filtering for Completions */ 4983 uint32_t m_ecrc_filt : 1; /**< Mask ECRC error filtering */ 4984 uint32_t m_cpl_len_err : 1; /**< Mask Length mismatch error for received Completions */ 4985 uint32_t m_cpl_attr_err : 1; /**< Mask Attributes mismatch error for received Completions */ 4986 uint32_t m_cpl_tc_err : 1; /**< Mask Traffic Class mismatch error for received Completions */ 4987 uint32_t m_cpl_fun_err : 1; /**< Mask function mismatch error for received Completions */ 4988 uint32_t m_cpl_rid_err : 1; /**< Mask Requester ID mismatch error for received Completions */ 4989 uint32_t m_cpl_tag_err : 1; /**< Mask Tag error rules for received Completions */ 4990 uint32_t m_lk_filt : 1; /**< Mask Locked Request filtering */ 4991 uint32_t m_cfg1_filt : 1; /**< Mask Type 1 Configuration Request filtering */ 4992 uint32_t m_bar_match : 1; /**< Mask BAR match filtering */ 4993 uint32_t m_pois_filt : 1; /**< Mask poisoned TLP filtering */ 4994 uint32_t m_fun : 1; /**< Mask function */ 4995 uint32_t dfcwt : 1; /**< Disable FC Watchdog Timer */ 4996 uint32_t reserved_11_14 : 4; 4997 uint32_t skpiv : 11; /**< SKP Interval Value */ 4998#else 4999 uint32_t skpiv : 11; 5000 uint32_t reserved_11_14 : 4; 5001 uint32_t dfcwt : 1; 5002 uint32_t m_fun : 1; 5003 uint32_t m_pois_filt : 1; 5004 uint32_t m_bar_match : 1; 5005 uint32_t m_cfg1_filt : 1; 5006 uint32_t m_lk_filt : 1; 5007 uint32_t m_cpl_tag_err : 1; 5008 uint32_t m_cpl_rid_err : 1; 5009 uint32_t m_cpl_fun_err : 1; 5010 uint32_t m_cpl_tc_err : 1; 5011 uint32_t m_cpl_attr_err : 1; 5012 uint32_t m_cpl_len_err : 1; 5013 uint32_t m_ecrc_filt : 1; 5014 uint32_t m_cpl_ecrc_filt : 1; 5015 uint32_t msg_ctrl : 1; 5016 uint32_t m_io_filt : 1; 5017 uint32_t m_cfg0_filt : 1; 5018#endif 5019 } s; 5020 struct cvmx_pciercx_cfg455_s cn52xx; 5021 struct cvmx_pciercx_cfg455_s cn52xxp1; 5022 struct cvmx_pciercx_cfg455_s cn56xx; 5023 struct cvmx_pciercx_cfg455_s cn56xxp1; 5024 struct cvmx_pciercx_cfg455_s cn61xx; 5025 struct cvmx_pciercx_cfg455_s cn63xx; 5026 struct cvmx_pciercx_cfg455_s cn63xxp1; 5027 struct cvmx_pciercx_cfg455_s cn66xx; 5028 struct cvmx_pciercx_cfg455_s cn68xx; 5029 struct cvmx_pciercx_cfg455_s cn68xxp1; 5030 struct cvmx_pciercx_cfg455_s cnf71xx; 5031}; 5032typedef union cvmx_pciercx_cfg455 cvmx_pciercx_cfg455_t; 5033 5034/** 5035 * cvmx_pcierc#_cfg456 5036 * 5037 * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 1 config space 5038 * (Filter Mask Register 2) 5039 */ 5040union cvmx_pciercx_cfg456 { 5041 uint32_t u32; 5042 struct cvmx_pciercx_cfg456_s { 5043#ifdef __BIG_ENDIAN_BITFIELD 5044 uint32_t reserved_4_31 : 28; 5045 uint32_t m_handle_flush : 1; /**< Mask Core Filter to handle flush request */ 5046 uint32_t m_dabort_4ucpl : 1; /**< Mask DLLP abort for unexpected CPL */ 5047 uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 5048 uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 5049#else 5050 uint32_t m_vend0_drp : 1; 5051 uint32_t m_vend1_drp : 1; 5052 uint32_t m_dabort_4ucpl : 1; 5053 uint32_t m_handle_flush : 1; 5054 uint32_t reserved_4_31 : 28; 5055#endif 5056 } s; 5057 struct cvmx_pciercx_cfg456_cn52xx { 5058#ifdef __BIG_ENDIAN_BITFIELD 5059 uint32_t reserved_2_31 : 30; 5060 uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 5061 uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 5062#else 5063 uint32_t m_vend0_drp : 1; 5064 uint32_t m_vend1_drp : 1; 5065 uint32_t reserved_2_31 : 30; 5066#endif 5067 } cn52xx; 5068 struct cvmx_pciercx_cfg456_cn52xx cn52xxp1; 5069 struct cvmx_pciercx_cfg456_cn52xx cn56xx; 5070 struct cvmx_pciercx_cfg456_cn52xx cn56xxp1; 5071 struct cvmx_pciercx_cfg456_s cn61xx; 5072 struct cvmx_pciercx_cfg456_cn52xx cn63xx; 5073 struct cvmx_pciercx_cfg456_cn52xx cn63xxp1; 5074 struct cvmx_pciercx_cfg456_s cn66xx; 5075 struct cvmx_pciercx_cfg456_s cn68xx; 5076 struct cvmx_pciercx_cfg456_cn52xx cn68xxp1; 5077 struct cvmx_pciercx_cfg456_s cnf71xx; 5078}; 5079typedef union cvmx_pciercx_cfg456 cvmx_pciercx_cfg456_t; 5080 5081/** 5082 * cvmx_pcierc#_cfg458 5083 * 5084 * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 1 config space 5085 * (Debug Register 0) 5086 */ 5087union cvmx_pciercx_cfg458 { 5088 uint32_t u32; 5089 struct cvmx_pciercx_cfg458_s { 5090#ifdef __BIG_ENDIAN_BITFIELD 5091 uint32_t dbg_info_l32 : 32; /**< The value on cxpl_debug_info[31:0]. */ 5092#else 5093 uint32_t dbg_info_l32 : 32; 5094#endif 5095 } s; 5096 struct cvmx_pciercx_cfg458_s cn52xx; 5097 struct cvmx_pciercx_cfg458_s cn52xxp1; 5098 struct cvmx_pciercx_cfg458_s cn56xx; 5099 struct cvmx_pciercx_cfg458_s cn56xxp1; 5100 struct cvmx_pciercx_cfg458_s cn61xx; 5101 struct cvmx_pciercx_cfg458_s cn63xx; 5102 struct cvmx_pciercx_cfg458_s cn63xxp1; 5103 struct cvmx_pciercx_cfg458_s cn66xx; 5104 struct cvmx_pciercx_cfg458_s cn68xx; 5105 struct cvmx_pciercx_cfg458_s cn68xxp1; 5106 struct cvmx_pciercx_cfg458_s cnf71xx; 5107}; 5108typedef union cvmx_pciercx_cfg458 cvmx_pciercx_cfg458_t; 5109 5110/** 5111 * cvmx_pcierc#_cfg459 5112 * 5113 * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 1 config space 5114 * (Debug Register 1) 5115 */ 5116union cvmx_pciercx_cfg459 { 5117 uint32_t u32; 5118 struct cvmx_pciercx_cfg459_s { 5119#ifdef __BIG_ENDIAN_BITFIELD 5120 uint32_t dbg_info_u32 : 32; /**< The value on cxpl_debug_info[63:32]. */ 5121#else 5122 uint32_t dbg_info_u32 : 32; 5123#endif 5124 } s; 5125 struct cvmx_pciercx_cfg459_s cn52xx; 5126 struct cvmx_pciercx_cfg459_s cn52xxp1; 5127 struct cvmx_pciercx_cfg459_s cn56xx; 5128 struct cvmx_pciercx_cfg459_s cn56xxp1; 5129 struct cvmx_pciercx_cfg459_s cn61xx; 5130 struct cvmx_pciercx_cfg459_s cn63xx; 5131 struct cvmx_pciercx_cfg459_s cn63xxp1; 5132 struct cvmx_pciercx_cfg459_s cn66xx; 5133 struct cvmx_pciercx_cfg459_s cn68xx; 5134 struct cvmx_pciercx_cfg459_s cn68xxp1; 5135 struct cvmx_pciercx_cfg459_s cnf71xx; 5136}; 5137typedef union cvmx_pciercx_cfg459 cvmx_pciercx_cfg459_t; 5138 5139/** 5140 * cvmx_pcierc#_cfg460 5141 * 5142 * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 1 config space 5143 * (Transmit Posted FC Credit Status) 5144 */ 5145union cvmx_pciercx_cfg460 { 5146 uint32_t u32; 5147 struct cvmx_pciercx_cfg460_s { 5148#ifdef __BIG_ENDIAN_BITFIELD 5149 uint32_t reserved_20_31 : 12; 5150 uint32_t tphfcc : 8; /**< Transmit Posted Header FC Credits 5151 The Posted Header credits advertised by the receiver at the 5152 other end of the Link, updated with each UpdateFC DLLP. */ 5153 uint32_t tpdfcc : 12; /**< Transmit Posted Data FC Credits 5154 The Posted Data credits advertised by the receiver at the other 5155 end of the Link, updated with each UpdateFC DLLP. */ 5156#else 5157 uint32_t tpdfcc : 12; 5158 uint32_t tphfcc : 8; 5159 uint32_t reserved_20_31 : 12; 5160#endif 5161 } s; 5162 struct cvmx_pciercx_cfg460_s cn52xx; 5163 struct cvmx_pciercx_cfg460_s cn52xxp1; 5164 struct cvmx_pciercx_cfg460_s cn56xx; 5165 struct cvmx_pciercx_cfg460_s cn56xxp1; 5166 struct cvmx_pciercx_cfg460_s cn61xx; 5167 struct cvmx_pciercx_cfg460_s cn63xx; 5168 struct cvmx_pciercx_cfg460_s cn63xxp1; 5169 struct cvmx_pciercx_cfg460_s cn66xx; 5170 struct cvmx_pciercx_cfg460_s cn68xx; 5171 struct cvmx_pciercx_cfg460_s cn68xxp1; 5172 struct cvmx_pciercx_cfg460_s cnf71xx; 5173}; 5174typedef union cvmx_pciercx_cfg460 cvmx_pciercx_cfg460_t; 5175 5176/** 5177 * cvmx_pcierc#_cfg461 5178 * 5179 * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 1 config space 5180 * (Transmit Non-Posted FC Credit Status) 5181 */ 5182union cvmx_pciercx_cfg461 { 5183 uint32_t u32; 5184 struct cvmx_pciercx_cfg461_s { 5185#ifdef __BIG_ENDIAN_BITFIELD 5186 uint32_t reserved_20_31 : 12; 5187 uint32_t tchfcc : 8; /**< Transmit Non-Posted Header FC Credits 5188 The Non-Posted Header credits advertised by the receiver at the 5189 other end of the Link, updated with each UpdateFC DLLP. */ 5190 uint32_t tcdfcc : 12; /**< Transmit Non-Posted Data FC Credits 5191 The Non-Posted Data credits advertised by the receiver at the 5192 other end of the Link, updated with each UpdateFC DLLP. */ 5193#else 5194 uint32_t tcdfcc : 12; 5195 uint32_t tchfcc : 8; 5196 uint32_t reserved_20_31 : 12; 5197#endif 5198 } s; 5199 struct cvmx_pciercx_cfg461_s cn52xx; 5200 struct cvmx_pciercx_cfg461_s cn52xxp1; 5201 struct cvmx_pciercx_cfg461_s cn56xx; 5202 struct cvmx_pciercx_cfg461_s cn56xxp1; 5203 struct cvmx_pciercx_cfg461_s cn61xx; 5204 struct cvmx_pciercx_cfg461_s cn63xx; 5205 struct cvmx_pciercx_cfg461_s cn63xxp1; 5206 struct cvmx_pciercx_cfg461_s cn66xx; 5207 struct cvmx_pciercx_cfg461_s cn68xx; 5208 struct cvmx_pciercx_cfg461_s cn68xxp1; 5209 struct cvmx_pciercx_cfg461_s cnf71xx; 5210}; 5211typedef union cvmx_pciercx_cfg461 cvmx_pciercx_cfg461_t; 5212 5213/** 5214 * cvmx_pcierc#_cfg462 5215 * 5216 * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 1 config space 5217 * (Transmit Completion FC Credit Status ) 5218 */ 5219union cvmx_pciercx_cfg462 { 5220 uint32_t u32; 5221 struct cvmx_pciercx_cfg462_s { 5222#ifdef __BIG_ENDIAN_BITFIELD 5223 uint32_t reserved_20_31 : 12; 5224 uint32_t tchfcc : 8; /**< Transmit Completion Header FC Credits 5225 The Completion Header credits advertised by the receiver at the 5226 other end of the Link, updated with each UpdateFC DLLP. */ 5227 uint32_t tcdfcc : 12; /**< Transmit Completion Data FC Credits 5228 The Completion Data credits advertised by the receiver at the 5229 other end of the Link, updated with each UpdateFC DLLP. */ 5230#else 5231 uint32_t tcdfcc : 12; 5232 uint32_t tchfcc : 8; 5233 uint32_t reserved_20_31 : 12; 5234#endif 5235 } s; 5236 struct cvmx_pciercx_cfg462_s cn52xx; 5237 struct cvmx_pciercx_cfg462_s cn52xxp1; 5238 struct cvmx_pciercx_cfg462_s cn56xx; 5239 struct cvmx_pciercx_cfg462_s cn56xxp1; 5240 struct cvmx_pciercx_cfg462_s cn61xx; 5241 struct cvmx_pciercx_cfg462_s cn63xx; 5242 struct cvmx_pciercx_cfg462_s cn63xxp1; 5243 struct cvmx_pciercx_cfg462_s cn66xx; 5244 struct cvmx_pciercx_cfg462_s cn68xx; 5245 struct cvmx_pciercx_cfg462_s cn68xxp1; 5246 struct cvmx_pciercx_cfg462_s cnf71xx; 5247}; 5248typedef union cvmx_pciercx_cfg462 cvmx_pciercx_cfg462_t; 5249 5250/** 5251 * cvmx_pcierc#_cfg463 5252 * 5253 * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 1 config space 5254 * (Queue Status) 5255 */ 5256union cvmx_pciercx_cfg463 { 5257 uint32_t u32; 5258 struct cvmx_pciercx_cfg463_s { 5259#ifdef __BIG_ENDIAN_BITFIELD 5260 uint32_t reserved_3_31 : 29; 5261 uint32_t rqne : 1; /**< Received Queue Not Empty 5262 Indicates there is data in one or more of the receive buffers. */ 5263 uint32_t trbne : 1; /**< Transmit Retry Buffer Not Empty 5264 Indicates that there is data in the transmit retry buffer. */ 5265 uint32_t rtlpfccnr : 1; /**< Received TLP FC Credits Not Returned 5266 Indicates that the PCI Express bus has sent a TLP but has not 5267 yet received an UpdateFC DLLP indicating that the credits for 5268 that TLP have been restored by the receiver at the other end of 5269 the Link. */ 5270#else 5271 uint32_t rtlpfccnr : 1; 5272 uint32_t trbne : 1; 5273 uint32_t rqne : 1; 5274 uint32_t reserved_3_31 : 29; 5275#endif 5276 } s; 5277 struct cvmx_pciercx_cfg463_s cn52xx; 5278 struct cvmx_pciercx_cfg463_s cn52xxp1; 5279 struct cvmx_pciercx_cfg463_s cn56xx; 5280 struct cvmx_pciercx_cfg463_s cn56xxp1; 5281 struct cvmx_pciercx_cfg463_s cn61xx; 5282 struct cvmx_pciercx_cfg463_s cn63xx; 5283 struct cvmx_pciercx_cfg463_s cn63xxp1; 5284 struct cvmx_pciercx_cfg463_s cn66xx; 5285 struct cvmx_pciercx_cfg463_s cn68xx; 5286 struct cvmx_pciercx_cfg463_s cn68xxp1; 5287 struct cvmx_pciercx_cfg463_s cnf71xx; 5288}; 5289typedef union cvmx_pciercx_cfg463 cvmx_pciercx_cfg463_t; 5290 5291/** 5292 * cvmx_pcierc#_cfg464 5293 * 5294 * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 1 config space 5295 * (VC Transmit Arbitration Register 1) 5296 */ 5297union cvmx_pciercx_cfg464 { 5298 uint32_t u32; 5299 struct cvmx_pciercx_cfg464_s { 5300#ifdef __BIG_ENDIAN_BITFIELD 5301 uint32_t wrr_vc3 : 8; /**< WRR Weight for VC3 */ 5302 uint32_t wrr_vc2 : 8; /**< WRR Weight for VC2 */ 5303 uint32_t wrr_vc1 : 8; /**< WRR Weight for VC1 */ 5304 uint32_t wrr_vc0 : 8; /**< WRR Weight for VC0 */ 5305#else 5306 uint32_t wrr_vc0 : 8; 5307 uint32_t wrr_vc1 : 8; 5308 uint32_t wrr_vc2 : 8; 5309 uint32_t wrr_vc3 : 8; 5310#endif 5311 } s; 5312 struct cvmx_pciercx_cfg464_s cn52xx; 5313 struct cvmx_pciercx_cfg464_s cn52xxp1; 5314 struct cvmx_pciercx_cfg464_s cn56xx; 5315 struct cvmx_pciercx_cfg464_s cn56xxp1; 5316 struct cvmx_pciercx_cfg464_s cn61xx; 5317 struct cvmx_pciercx_cfg464_s cn63xx; 5318 struct cvmx_pciercx_cfg464_s cn63xxp1; 5319 struct cvmx_pciercx_cfg464_s cn66xx; 5320 struct cvmx_pciercx_cfg464_s cn68xx; 5321 struct cvmx_pciercx_cfg464_s cn68xxp1; 5322 struct cvmx_pciercx_cfg464_s cnf71xx; 5323}; 5324typedef union cvmx_pciercx_cfg464 cvmx_pciercx_cfg464_t; 5325 5326/** 5327 * cvmx_pcierc#_cfg465 5328 * 5329 * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of config space 5330 * (VC Transmit Arbitration Register 2) 5331 */ 5332union cvmx_pciercx_cfg465 { 5333 uint32_t u32; 5334 struct cvmx_pciercx_cfg465_s { 5335#ifdef __BIG_ENDIAN_BITFIELD 5336 uint32_t wrr_vc7 : 8; /**< WRR Weight for VC7 */ 5337 uint32_t wrr_vc6 : 8; /**< WRR Weight for VC6 */ 5338 uint32_t wrr_vc5 : 8; /**< WRR Weight for VC5 */ 5339 uint32_t wrr_vc4 : 8; /**< WRR Weight for VC4 */ 5340#else 5341 uint32_t wrr_vc4 : 8; 5342 uint32_t wrr_vc5 : 8; 5343 uint32_t wrr_vc6 : 8; 5344 uint32_t wrr_vc7 : 8; 5345#endif 5346 } s; 5347 struct cvmx_pciercx_cfg465_s cn52xx; 5348 struct cvmx_pciercx_cfg465_s cn52xxp1; 5349 struct cvmx_pciercx_cfg465_s cn56xx; 5350 struct cvmx_pciercx_cfg465_s cn56xxp1; 5351 struct cvmx_pciercx_cfg465_s cn61xx; 5352 struct cvmx_pciercx_cfg465_s cn63xx; 5353 struct cvmx_pciercx_cfg465_s cn63xxp1; 5354 struct cvmx_pciercx_cfg465_s cn66xx; 5355 struct cvmx_pciercx_cfg465_s cn68xx; 5356 struct cvmx_pciercx_cfg465_s cn68xxp1; 5357 struct cvmx_pciercx_cfg465_s cnf71xx; 5358}; 5359typedef union cvmx_pciercx_cfg465 cvmx_pciercx_cfg465_t; 5360 5361/** 5362 * cvmx_pcierc#_cfg466 5363 * 5364 * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 1 config space 5365 * (VC0 Posted Receive Queue Control) 5366 */ 5367union cvmx_pciercx_cfg466 { 5368 uint32_t u32; 5369 struct cvmx_pciercx_cfg466_s { 5370#ifdef __BIG_ENDIAN_BITFIELD 5371 uint32_t rx_queue_order : 1; /**< VC Ordering for Receive Queues 5372 Determines the VC ordering rule for the receive queues, used 5373 only in the segmented-buffer configuration, 5374 writable through PEM(0..1)_CFG_WR: 5375 o 1: Strict ordering, higher numbered VCs have higher priority 5376 o 0: Round robin 5377 However, the application must not change this field. */ 5378 uint32_t type_ordering : 1; /**< TLP Type Ordering for VC0 5379 Determines the TLP type ordering rule for VC0 receive queues, 5380 used only in the segmented-buffer configuration, writable 5381 through PEM(0..1)_CFG_WR: 5382 o 1: Ordering of received TLPs follows the rules in 5383 PCI Express Base Specification 5384 o 0: Strict ordering for received TLPs: Posted, then 5385 Completion, then Non-Posted 5386 However, the application must not change this field. */ 5387 uint32_t reserved_24_29 : 6; 5388 uint32_t queue_mode : 3; /**< VC0 Posted TLP Queue Mode 5389 The operating mode of the Posted receive queue for VC0, used 5390 only in the segmented-buffer configuration, writable through 5391 PEM(0..1)_CFG_WR. 5392 However, the application must not change this field. 5393 Only one bit can be set at a time: 5394 o Bit 23: Bypass 5395 o Bit 22: Cut-through 5396 o Bit 21: Store-and-forward */ 5397 uint32_t reserved_20_20 : 1; 5398 uint32_t header_credits : 8; /**< VC0 Posted Header Credits 5399 The number of initial Posted header credits for VC0, used for 5400 all receive queue buffer configurations. 5401 This field is writable through PEM(0..1)_CFG_WR. 5402 However, the application must not change this field. */ 5403 uint32_t data_credits : 12; /**< VC0 Posted Data Credits 5404 The number of initial Posted data credits for VC0, used for all 5405 receive queue buffer configurations. 5406 This field is writable through PEM(0..1)_CFG_WR. 5407 However, the application must not change this field. */ 5408#else 5409 uint32_t data_credits : 12; 5410 uint32_t header_credits : 8; 5411 uint32_t reserved_20_20 : 1; 5412 uint32_t queue_mode : 3; 5413 uint32_t reserved_24_29 : 6; 5414 uint32_t type_ordering : 1; 5415 uint32_t rx_queue_order : 1; 5416#endif 5417 } s; 5418 struct cvmx_pciercx_cfg466_s cn52xx; 5419 struct cvmx_pciercx_cfg466_s cn52xxp1; 5420 struct cvmx_pciercx_cfg466_s cn56xx; 5421 struct cvmx_pciercx_cfg466_s cn56xxp1; 5422 struct cvmx_pciercx_cfg466_s cn61xx; 5423 struct cvmx_pciercx_cfg466_s cn63xx; 5424 struct cvmx_pciercx_cfg466_s cn63xxp1; 5425 struct cvmx_pciercx_cfg466_s cn66xx; 5426 struct cvmx_pciercx_cfg466_s cn68xx; 5427 struct cvmx_pciercx_cfg466_s cn68xxp1; 5428 struct cvmx_pciercx_cfg466_s cnf71xx; 5429}; 5430typedef union cvmx_pciercx_cfg466 cvmx_pciercx_cfg466_t; 5431 5432/** 5433 * cvmx_pcierc#_cfg467 5434 * 5435 * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 1 config space 5436 * (VC0 Non-Posted Receive Queue Control) 5437 */ 5438union cvmx_pciercx_cfg467 { 5439 uint32_t u32; 5440 struct cvmx_pciercx_cfg467_s { 5441#ifdef __BIG_ENDIAN_BITFIELD 5442 uint32_t reserved_24_31 : 8; 5443 uint32_t queue_mode : 3; /**< VC0 Non-Posted TLP Queue Mode 5444 The operating mode of the Non-Posted receive queue for VC0, 5445 used only in the segmented-buffer configuration, writable 5446 through PEM(0..1)_CFG_WR. 5447 Only one bit can be set at a time: 5448 o Bit 23: Bypass 5449 o Bit 22: Cut-through 5450 o Bit 21: Store-and-forward 5451 However, the application must not change this field. */ 5452 uint32_t reserved_20_20 : 1; 5453 uint32_t header_credits : 8; /**< VC0 Non-Posted Header Credits 5454 The number of initial Non-Posted header credits for VC0, used 5455 for all receive queue buffer configurations. 5456 This field is writable through PEM(0..1)_CFG_WR. 5457 However, the application must not change this field. */ 5458 uint32_t data_credits : 12; /**< VC0 Non-Posted Data Credits 5459 The number of initial Non-Posted data credits for VC0, used for 5460 all receive queue buffer configurations. 5461 This field is writable through PEM(0..1)_CFG_WR. 5462 However, the application must not change this field. */ 5463#else 5464 uint32_t data_credits : 12; 5465 uint32_t header_credits : 8; 5466 uint32_t reserved_20_20 : 1; 5467 uint32_t queue_mode : 3; 5468 uint32_t reserved_24_31 : 8; 5469#endif 5470 } s; 5471 struct cvmx_pciercx_cfg467_s cn52xx; 5472 struct cvmx_pciercx_cfg467_s cn52xxp1; 5473 struct cvmx_pciercx_cfg467_s cn56xx; 5474 struct cvmx_pciercx_cfg467_s cn56xxp1; 5475 struct cvmx_pciercx_cfg467_s cn61xx; 5476 struct cvmx_pciercx_cfg467_s cn63xx; 5477 struct cvmx_pciercx_cfg467_s cn63xxp1; 5478 struct cvmx_pciercx_cfg467_s cn66xx; 5479 struct cvmx_pciercx_cfg467_s cn68xx; 5480 struct cvmx_pciercx_cfg467_s cn68xxp1; 5481 struct cvmx_pciercx_cfg467_s cnf71xx; 5482}; 5483typedef union cvmx_pciercx_cfg467 cvmx_pciercx_cfg467_t; 5484 5485/** 5486 * cvmx_pcierc#_cfg468 5487 * 5488 * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 1 config space 5489 * (VC0 Completion Receive Queue Control) 5490 */ 5491union cvmx_pciercx_cfg468 { 5492 uint32_t u32; 5493 struct cvmx_pciercx_cfg468_s { 5494#ifdef __BIG_ENDIAN_BITFIELD 5495 uint32_t reserved_24_31 : 8; 5496 uint32_t queue_mode : 3; /**< VC0 Completion TLP Queue Mode 5497 The operating mode of the Completion receive queue for VC0, 5498 used only in the segmented-buffer configuration, writable 5499 through PEM(0..1)_CFG_WR. 5500 Only one bit can be set at a time: 5501 o Bit 23: Bypass 5502 o Bit 22: Cut-through 5503 o Bit 21: Store-and-forward 5504 However, the application must not change this field. */ 5505 uint32_t reserved_20_20 : 1; 5506 uint32_t header_credits : 8; /**< VC0 Completion Header Credits 5507 The number of initial Completion header credits for VC0, used 5508 for all receive queue buffer configurations. 5509 This field is writable through PEM(0..1)_CFG_WR. 5510 However, the application must not change this field. */ 5511 uint32_t data_credits : 12; /**< VC0 Completion Data Credits 5512 The number of initial Completion data credits for VC0, used for 5513 all receive queue buffer configurations. 5514 This field is writable through PEM(0..1)_CFG_WR. 5515 However, the application must not change this field. */ 5516#else 5517 uint32_t data_credits : 12; 5518 uint32_t header_credits : 8; 5519 uint32_t reserved_20_20 : 1; 5520 uint32_t queue_mode : 3; 5521 uint32_t reserved_24_31 : 8; 5522#endif 5523 } s; 5524 struct cvmx_pciercx_cfg468_s cn52xx; 5525 struct cvmx_pciercx_cfg468_s cn52xxp1; 5526 struct cvmx_pciercx_cfg468_s cn56xx; 5527 struct cvmx_pciercx_cfg468_s cn56xxp1; 5528 struct cvmx_pciercx_cfg468_s cn61xx; 5529 struct cvmx_pciercx_cfg468_s cn63xx; 5530 struct cvmx_pciercx_cfg468_s cn63xxp1; 5531 struct cvmx_pciercx_cfg468_s cn66xx; 5532 struct cvmx_pciercx_cfg468_s cn68xx; 5533 struct cvmx_pciercx_cfg468_s cn68xxp1; 5534 struct cvmx_pciercx_cfg468_s cnf71xx; 5535}; 5536typedef union cvmx_pciercx_cfg468 cvmx_pciercx_cfg468_t; 5537 5538/** 5539 * cvmx_pcierc#_cfg490 5540 * 5541 * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space 5542 * (VC0 Posted Buffer Depth) 5543 */ 5544union cvmx_pciercx_cfg490 { 5545 uint32_t u32; 5546 struct cvmx_pciercx_cfg490_s { 5547#ifdef __BIG_ENDIAN_BITFIELD 5548 uint32_t reserved_26_31 : 6; 5549 uint32_t header_depth : 10; /**< VC0 Posted Header Queue Depth 5550 Sets the number of entries in the Posted header queue for VC0 5551 when using the segmented-buffer configuration, writable through 5552 PEM(0..1)_CFG_WR. 5553 However, the application must not change this field. */ 5554 uint32_t reserved_14_15 : 2; 5555 uint32_t data_depth : 14; /**< VC0 Posted Data Queue Depth 5556 Sets the number of entries in the Posted data queue for VC0 5557 when using the segmented-buffer configuration, writable 5558 through PEM(0..1)_CFG_WR. 5559 However, the application must not change this field. */ 5560#else 5561 uint32_t data_depth : 14; 5562 uint32_t reserved_14_15 : 2; 5563 uint32_t header_depth : 10; 5564 uint32_t reserved_26_31 : 6; 5565#endif 5566 } s; 5567 struct cvmx_pciercx_cfg490_s cn52xx; 5568 struct cvmx_pciercx_cfg490_s cn52xxp1; 5569 struct cvmx_pciercx_cfg490_s cn56xx; 5570 struct cvmx_pciercx_cfg490_s cn56xxp1; 5571 struct cvmx_pciercx_cfg490_s cn61xx; 5572 struct cvmx_pciercx_cfg490_s cn63xx; 5573 struct cvmx_pciercx_cfg490_s cn63xxp1; 5574 struct cvmx_pciercx_cfg490_s cn66xx; 5575 struct cvmx_pciercx_cfg490_s cn68xx; 5576 struct cvmx_pciercx_cfg490_s cn68xxp1; 5577 struct cvmx_pciercx_cfg490_s cnf71xx; 5578}; 5579typedef union cvmx_pciercx_cfg490 cvmx_pciercx_cfg490_t; 5580 5581/** 5582 * cvmx_pcierc#_cfg491 5583 * 5584 * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space 5585 * (VC0 Non-Posted Buffer Depth) 5586 */ 5587union cvmx_pciercx_cfg491 { 5588 uint32_t u32; 5589 struct cvmx_pciercx_cfg491_s { 5590#ifdef __BIG_ENDIAN_BITFIELD 5591 uint32_t reserved_26_31 : 6; 5592 uint32_t header_depth : 10; /**< VC0 Non-Posted Header Queue Depth 5593 Sets the number of entries in the Non-Posted header queue for 5594 VC0 when using the segmented-buffer configuration, writable 5595 through PEM(0..1)_CFG_WR. 5596 However, the application must not change this field. */ 5597 uint32_t reserved_14_15 : 2; 5598 uint32_t data_depth : 14; /**< VC0 Non-Posted Data Queue Depth 5599 Sets the number of entries in the Non-Posted data queue for VC0 5600 when using the segmented-buffer configuration, writable 5601 through PEM(0..1)_CFG_WR. 5602 However, the application must not change this field. */ 5603#else 5604 uint32_t data_depth : 14; 5605 uint32_t reserved_14_15 : 2; 5606 uint32_t header_depth : 10; 5607 uint32_t reserved_26_31 : 6; 5608#endif 5609 } s; 5610 struct cvmx_pciercx_cfg491_s cn52xx; 5611 struct cvmx_pciercx_cfg491_s cn52xxp1; 5612 struct cvmx_pciercx_cfg491_s cn56xx; 5613 struct cvmx_pciercx_cfg491_s cn56xxp1; 5614 struct cvmx_pciercx_cfg491_s cn61xx; 5615 struct cvmx_pciercx_cfg491_s cn63xx; 5616 struct cvmx_pciercx_cfg491_s cn63xxp1; 5617 struct cvmx_pciercx_cfg491_s cn66xx; 5618 struct cvmx_pciercx_cfg491_s cn68xx; 5619 struct cvmx_pciercx_cfg491_s cn68xxp1; 5620 struct cvmx_pciercx_cfg491_s cnf71xx; 5621}; 5622typedef union cvmx_pciercx_cfg491 cvmx_pciercx_cfg491_t; 5623 5624/** 5625 * cvmx_pcierc#_cfg492 5626 * 5627 * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space 5628 * (VC0 Completion Buffer Depth) 5629 */ 5630union cvmx_pciercx_cfg492 { 5631 uint32_t u32; 5632 struct cvmx_pciercx_cfg492_s { 5633#ifdef __BIG_ENDIAN_BITFIELD 5634 uint32_t reserved_26_31 : 6; 5635 uint32_t header_depth : 10; /**< VC0 Completion Header Queue Depth 5636 Sets the number of entries in the Completion header queue for 5637 VC0 when using the segmented-buffer configuration, writable 5638 through PEM(0..1)_CFG_WR. 5639 However, the application must not change this field. */ 5640 uint32_t reserved_14_15 : 2; 5641 uint32_t data_depth : 14; /**< VC0 Completion Data Queue Depth 5642 Sets the number of entries in the Completion data queue for VC0 5643 when using the segmented-buffer configuration, writable 5644 through PEM(0..1)_CFG_WR. 5645 However, the application must not change this field. */ 5646#else 5647 uint32_t data_depth : 14; 5648 uint32_t reserved_14_15 : 2; 5649 uint32_t header_depth : 10; 5650 uint32_t reserved_26_31 : 6; 5651#endif 5652 } s; 5653 struct cvmx_pciercx_cfg492_s cn52xx; 5654 struct cvmx_pciercx_cfg492_s cn52xxp1; 5655 struct cvmx_pciercx_cfg492_s cn56xx; 5656 struct cvmx_pciercx_cfg492_s cn56xxp1; 5657 struct cvmx_pciercx_cfg492_s cn61xx; 5658 struct cvmx_pciercx_cfg492_s cn63xx; 5659 struct cvmx_pciercx_cfg492_s cn63xxp1; 5660 struct cvmx_pciercx_cfg492_s cn66xx; 5661 struct cvmx_pciercx_cfg492_s cn68xx; 5662 struct cvmx_pciercx_cfg492_s cn68xxp1; 5663 struct cvmx_pciercx_cfg492_s cnf71xx; 5664}; 5665typedef union cvmx_pciercx_cfg492 cvmx_pciercx_cfg492_t; 5666 5667/** 5668 * cvmx_pcierc#_cfg515 5669 * 5670 * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 1 config space 5671 * (Port Logic Register (Gen2)) 5672 */ 5673union cvmx_pciercx_cfg515 { 5674 uint32_t u32; 5675 struct cvmx_pciercx_cfg515_s { 5676#ifdef __BIG_ENDIAN_BITFIELD 5677 uint32_t reserved_21_31 : 11; 5678 uint32_t s_d_e : 1; /**< SEL_DE_EMPHASIS 5679 Used to set the de-emphasis level for upstream ports. */ 5680 uint32_t ctcrb : 1; /**< Config Tx Compliance Receive Bit 5681 When set to 1, signals LTSSM to transmit TS ordered sets 5682 with the compliance receive bit assert (equal to 1). */ 5683 uint32_t cpyts : 1; /**< Config PHY Tx Swing 5684 Indicates the voltage level the PHY should drive. When set to 5685 1, indicates Full Swing. When set to 0, indicates Low Swing */ 5686 uint32_t dsc : 1; /**< Directed Speed Change 5687 o a write of '1' will initiate a speed change 5688 o always reads a zero */ 5689 uint32_t le : 9; /**< Lane Enable 5690 Indicates the number of lanes to check for exit from electrical 5691 idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2, 5692 etc. Used to limit the maximum link width to ignore broken 5693 lanes that detect a receiver, but will not exit electrical 5694 idle and 5695 would otherwise prevent a valid link from being configured. */ 5696 uint32_t n_fts : 8; /**< N_FTS 5697 Sets the Number of Fast Training Sequences (N_FTS) that 5698 the core advertises as its N_FTS during GEN2 Link training. 5699 This value is used to inform the Link partner about the PHYs 5700 ability to recover synchronization after a low power state. 5701 Note: Do not set N_FTS to zero; doing so can cause the 5702 LTSSM to go into the recovery state when exiting from 5703 L0s. */ 5704#else 5705 uint32_t n_fts : 8; 5706 uint32_t le : 9; 5707 uint32_t dsc : 1; 5708 uint32_t cpyts : 1; 5709 uint32_t ctcrb : 1; 5710 uint32_t s_d_e : 1; 5711 uint32_t reserved_21_31 : 11; 5712#endif 5713 } s; 5714 struct cvmx_pciercx_cfg515_s cn61xx; 5715 struct cvmx_pciercx_cfg515_s cn63xx; 5716 struct cvmx_pciercx_cfg515_s cn63xxp1; 5717 struct cvmx_pciercx_cfg515_s cn66xx; 5718 struct cvmx_pciercx_cfg515_s cn68xx; 5719 struct cvmx_pciercx_cfg515_s cn68xxp1; 5720 struct cvmx_pciercx_cfg515_s cnf71xx; 5721}; 5722typedef union cvmx_pciercx_cfg515 cvmx_pciercx_cfg515_t; 5723 5724/** 5725 * cvmx_pcierc#_cfg516 5726 * 5727 * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 1 config space 5728 * (PHY Status Register) 5729 */ 5730union cvmx_pciercx_cfg516 { 5731 uint32_t u32; 5732 struct cvmx_pciercx_cfg516_s { 5733#ifdef __BIG_ENDIAN_BITFIELD 5734 uint32_t phy_stat : 32; /**< PHY Status */ 5735#else 5736 uint32_t phy_stat : 32; 5737#endif 5738 } s; 5739 struct cvmx_pciercx_cfg516_s cn52xx; 5740 struct cvmx_pciercx_cfg516_s cn52xxp1; 5741 struct cvmx_pciercx_cfg516_s cn56xx; 5742 struct cvmx_pciercx_cfg516_s cn56xxp1; 5743 struct cvmx_pciercx_cfg516_s cn61xx; 5744 struct cvmx_pciercx_cfg516_s cn63xx; 5745 struct cvmx_pciercx_cfg516_s cn63xxp1; 5746 struct cvmx_pciercx_cfg516_s cn66xx; 5747 struct cvmx_pciercx_cfg516_s cn68xx; 5748 struct cvmx_pciercx_cfg516_s cn68xxp1; 5749 struct cvmx_pciercx_cfg516_s cnf71xx; 5750}; 5751typedef union cvmx_pciercx_cfg516 cvmx_pciercx_cfg516_t; 5752 5753/** 5754 * cvmx_pcierc#_cfg517 5755 * 5756 * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 1 config space 5757 * (PHY Control Register) 5758 */ 5759union cvmx_pciercx_cfg517 { 5760 uint32_t u32; 5761 struct cvmx_pciercx_cfg517_s { 5762#ifdef __BIG_ENDIAN_BITFIELD 5763 uint32_t phy_ctrl : 32; /**< PHY Control */ 5764#else 5765 uint32_t phy_ctrl : 32; 5766#endif 5767 } s; 5768 struct cvmx_pciercx_cfg517_s cn52xx; 5769 struct cvmx_pciercx_cfg517_s cn52xxp1; 5770 struct cvmx_pciercx_cfg517_s cn56xx; 5771 struct cvmx_pciercx_cfg517_s cn56xxp1; 5772 struct cvmx_pciercx_cfg517_s cn61xx; 5773 struct cvmx_pciercx_cfg517_s cn63xx; 5774 struct cvmx_pciercx_cfg517_s cn63xxp1; 5775 struct cvmx_pciercx_cfg517_s cn66xx; 5776 struct cvmx_pciercx_cfg517_s cn68xx; 5777 struct cvmx_pciercx_cfg517_s cn68xxp1; 5778 struct cvmx_pciercx_cfg517_s cnf71xx; 5779}; 5780typedef union cvmx_pciercx_cfg517 cvmx_pciercx_cfg517_t; 5781 5782#endif 5783