1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-ipd-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon ipd. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_IPD_DEFS_H__ 53#define __CVMX_IPD_DEFS_H__ 54 55#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull)) 56#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) 57#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) 58#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) 59#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 60static inline uint64_t CVMX_IPD_BPIDX_MBUF_TH(unsigned long offset) 61{ 62 if (!( 63 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 64 cvmx_warn("CVMX_IPD_BPIDX_MBUF_TH(%lu) is invalid on this chip\n", offset); 65 return CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8; 66} 67#else 68#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8) 69#endif 70#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71static inline uint64_t CVMX_IPD_BPID_BP_COUNTERX(unsigned long offset) 72{ 73 if (!( 74 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 75 cvmx_warn("CVMX_IPD_BPID_BP_COUNTERX(%lu) is invalid on this chip\n", offset); 76 return CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8; 77} 78#else 79#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82#define CVMX_IPD_BP_PRT_RED_END CVMX_IPD_BP_PRT_RED_END_FUNC() 83static inline uint64_t CVMX_IPD_BP_PRT_RED_END_FUNC(void) 84{ 85 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 86 cvmx_warn("CVMX_IPD_BP_PRT_RED_END not supported on this chip\n"); 87 return CVMX_ADD_IO_SEG(0x00014F0000000328ull); 88} 89#else 90#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) 91#endif 92#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) 93#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 94#define CVMX_IPD_CREDITS CVMX_IPD_CREDITS_FUNC() 95static inline uint64_t CVMX_IPD_CREDITS_FUNC(void) 96{ 97 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 98 cvmx_warn("CVMX_IPD_CREDITS not supported on this chip\n"); 99 return CVMX_ADD_IO_SEG(0x00014F0000004410ull); 100} 101#else 102#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull)) 103#endif 104#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) 105#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 106#define CVMX_IPD_ECC_CTL CVMX_IPD_ECC_CTL_FUNC() 107static inline uint64_t CVMX_IPD_ECC_CTL_FUNC(void) 108{ 109 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 110 cvmx_warn("CVMX_IPD_ECC_CTL not supported on this chip\n"); 111 return CVMX_ADD_IO_SEG(0x00014F0000004408ull); 112} 113#else 114#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull)) 115#endif 116#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 117#define CVMX_IPD_FREE_PTR_FIFO_CTL CVMX_IPD_FREE_PTR_FIFO_CTL_FUNC() 118static inline uint64_t CVMX_IPD_FREE_PTR_FIFO_CTL_FUNC(void) 119{ 120 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 121 cvmx_warn("CVMX_IPD_FREE_PTR_FIFO_CTL not supported on this chip\n"); 122 return CVMX_ADD_IO_SEG(0x00014F0000000780ull); 123} 124#else 125#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull)) 126#endif 127#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128#define CVMX_IPD_FREE_PTR_VALUE CVMX_IPD_FREE_PTR_VALUE_FUNC() 129static inline uint64_t CVMX_IPD_FREE_PTR_VALUE_FUNC(void) 130{ 131 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 132 cvmx_warn("CVMX_IPD_FREE_PTR_VALUE not supported on this chip\n"); 133 return CVMX_ADD_IO_SEG(0x00014F0000000788ull); 134} 135#else 136#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull)) 137#endif 138#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 139#define CVMX_IPD_HOLD_PTR_FIFO_CTL CVMX_IPD_HOLD_PTR_FIFO_CTL_FUNC() 140static inline uint64_t CVMX_IPD_HOLD_PTR_FIFO_CTL_FUNC(void) 141{ 142 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 143 cvmx_warn("CVMX_IPD_HOLD_PTR_FIFO_CTL not supported on this chip\n"); 144 return CVMX_ADD_IO_SEG(0x00014F0000000790ull); 145} 146#else 147#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull)) 148#endif 149#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) 150#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) 151#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152#define CVMX_IPD_NEXT_PKT_PTR CVMX_IPD_NEXT_PKT_PTR_FUNC() 153static inline uint64_t CVMX_IPD_NEXT_PKT_PTR_FUNC(void) 154{ 155 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 156 cvmx_warn("CVMX_IPD_NEXT_PKT_PTR not supported on this chip\n"); 157 return CVMX_ADD_IO_SEG(0x00014F00000007A0ull); 158} 159#else 160#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull)) 161#endif 162#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 163#define CVMX_IPD_NEXT_WQE_PTR CVMX_IPD_NEXT_WQE_PTR_FUNC() 164static inline uint64_t CVMX_IPD_NEXT_WQE_PTR_FUNC(void) 165{ 166 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 167 cvmx_warn("CVMX_IPD_NEXT_WQE_PTR not supported on this chip\n"); 168 return CVMX_ADD_IO_SEG(0x00014F00000007A8ull); 169} 170#else 171#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull)) 172#endif 173#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) 174#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175static inline uint64_t CVMX_IPD_ON_BP_DROP_PKTX(unsigned long block_id) 176{ 177 if (!( 178 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))))) 179 cvmx_warn("CVMX_IPD_ON_BP_DROP_PKTX(%lu) is invalid on this chip\n", block_id); 180 return CVMX_ADD_IO_SEG(0x00014F0000004100ull); 181} 182#else 183#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull)) 184#endif 185#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) 186#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 187#define CVMX_IPD_PKT_ERR CVMX_IPD_PKT_ERR_FUNC() 188static inline uint64_t CVMX_IPD_PKT_ERR_FUNC(void) 189{ 190 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 191 cvmx_warn("CVMX_IPD_PKT_ERR not supported on this chip\n"); 192 return CVMX_ADD_IO_SEG(0x00014F00000003F0ull); 193} 194#else 195#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull)) 196#endif 197#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 198#define CVMX_IPD_PKT_PTR_VALID CVMX_IPD_PKT_PTR_VALID_FUNC() 199static inline uint64_t CVMX_IPD_PKT_PTR_VALID_FUNC(void) 200{ 201 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 202 cvmx_warn("CVMX_IPD_PKT_PTR_VALID not supported on this chip\n"); 203 return CVMX_ADD_IO_SEG(0x00014F0000000358ull); 204} 205#else 206#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) 207#endif 208#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 209static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset) 210{ 211 if (!( 212 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) || 213 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 214 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 215 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 216 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 217 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 218 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 219 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 220 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 221 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 222 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))))) 223 cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset); 224 return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8; 225} 226#else 227#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) 228#endif 229#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 230static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset) 231{ 232 if (!( 233 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) || 234 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) || 235 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 36) && (offset <= 39)))) || 236 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))) || 237 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 36) && (offset <= 39)))) || 238 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 36) && (offset <= 39)))))) 239 cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset); 240 return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36; 241} 242#else 243#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36) 244#endif 245#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 246static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT3(unsigned long offset) 247{ 248 if (!( 249 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 40) && (offset <= 47)))) || 250 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 251 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) || 252 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 40) && (offset <= 47)))))) 253 cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT3(%lu) is invalid on this chip\n", offset); 254 return CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40; 255} 256#else 257#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40) 258#endif 259#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset) 261{ 262 if (!( 263 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) || 264 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) || 265 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 36) && (offset <= 39)))) || 266 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))) || 267 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 36) && (offset <= 39)))) || 268 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 36) && (offset <= 39)))))) 269 cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset); 270 return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36; 271} 272#else 273#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(unsigned long offset) 277{ 278 if (!( 279 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 40) && (offset <= 43)))) || 280 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 281 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 43)))) || 282 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 40) && (offset <= 43)))))) 283 cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(%lu) is invalid on this chip\n", offset); 284 return CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40; 285} 286#else 287#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40) 288#endif 289#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 290static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(unsigned long offset) 291{ 292 if (!( 293 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 44) && (offset <= 47)))) || 294 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 44) && (offset <= 47)))) || 295 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 44) && (offset <= 47)))))) 296 cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(%lu) is invalid on this chip\n", offset); 297 return CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44; 298} 299#else 300#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44) 301#endif 302#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 303static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset) 304{ 305 if (!( 306 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) || 307 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 308 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 309 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 310 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 311 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 312 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 313 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 314 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 315 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 316 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))))) 317 cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset); 318 return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8; 319} 320#else 321#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) 322#endif 323#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324#define CVMX_IPD_PORT_PTR_FIFO_CTL CVMX_IPD_PORT_PTR_FIFO_CTL_FUNC() 325static inline uint64_t CVMX_IPD_PORT_PTR_FIFO_CTL_FUNC(void) 326{ 327 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 328 cvmx_warn("CVMX_IPD_PORT_PTR_FIFO_CTL not supported on this chip\n"); 329 return CVMX_ADD_IO_SEG(0x00014F0000000798ull); 330} 331#else 332#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull)) 333#endif 334#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 335static inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset) 336{ 337 if (!( 338 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) || 339 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) || 340 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) || 341 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))) || 342 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) || 343 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 344 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))))) 345 cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset); 346 return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8; 347} 348#else 349#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) 350#endif 351#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352static inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset) 353{ 354 if (!( 355 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) || 356 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) || 357 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) || 358 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))) || 359 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) || 360 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 361 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))))) 362 cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset); 363 return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8; 364} 365#else 366#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) 367#endif 368#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 369static inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset) 370{ 371 if (!( 372 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319)))) || 373 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) || 374 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 383)))) || 375 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 351)))) || 376 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 335)) || ((offset >= 352) && (offset <= 383)))) || 377 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 511))) || 378 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 383)))))) 379 cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset); 380 return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8; 381} 382#else 383#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386static inline uint64_t CVMX_IPD_PORT_SOPX(unsigned long block_id) 387{ 388 if (!( 389 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))))) 390 cvmx_warn("CVMX_IPD_PORT_SOPX(%lu) is invalid on this chip\n", block_id); 391 return CVMX_ADD_IO_SEG(0x00014F0000004400ull); 392} 393#else 394#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull)) 395#endif 396#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC() 398static inline uint64_t CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC(void) 399{ 400 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 401 cvmx_warn("CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL not supported on this chip\n"); 402 return CVMX_ADD_IO_SEG(0x00014F0000000348ull); 403} 404#else 405#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) 406#endif 407#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC() 409static inline uint64_t CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC(void) 410{ 411 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 412 cvmx_warn("CVMX_IPD_PRC_PORT_PTR_FIFO_CTL not supported on this chip\n"); 413 return CVMX_ADD_IO_SEG(0x00014F0000000350ull); 414} 415#else 416#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) 417#endif 418#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) 419#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 420#define CVMX_IPD_PWP_PTR_FIFO_CTL CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC() 421static inline uint64_t CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC(void) 422{ 423 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 424 cvmx_warn("CVMX_IPD_PWP_PTR_FIFO_CTL not supported on this chip\n"); 425 return CVMX_ADD_IO_SEG(0x00014F0000000340ull); 426} 427#else 428#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull)) 429#endif 430#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0) 431#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1) 432#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2) 433#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3) 434#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4) 435#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5) 436#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6) 437#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) 438#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 439static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset) 440{ 441 if (!( 442 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 443 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 444 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 445 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 446 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 447 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 448 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 449 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 450 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 451 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 452 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 453 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 454 cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset); 455 return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8; 456} 457#else 458#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) 459#endif 460#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) 461#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 462static inline uint64_t CVMX_IPD_RED_BPID_ENABLEX(unsigned long block_id) 463{ 464 if (!( 465 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))))) 466 cvmx_warn("CVMX_IPD_RED_BPID_ENABLEX(%lu) is invalid on this chip\n", block_id); 467 return CVMX_ADD_IO_SEG(0x00014F0000004200ull); 468} 469#else 470#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull)) 471#endif 472#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 473#define CVMX_IPD_RED_DELAY CVMX_IPD_RED_DELAY_FUNC() 474static inline uint64_t CVMX_IPD_RED_DELAY_FUNC(void) 475{ 476 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 477 cvmx_warn("CVMX_IPD_RED_DELAY not supported on this chip\n"); 478 return CVMX_ADD_IO_SEG(0x00014F0000004300ull); 479} 480#else 481#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull)) 482#endif 483#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 484#define CVMX_IPD_RED_PORT_ENABLE CVMX_IPD_RED_PORT_ENABLE_FUNC() 485static inline uint64_t CVMX_IPD_RED_PORT_ENABLE_FUNC(void) 486{ 487 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 488 cvmx_warn("CVMX_IPD_RED_PORT_ENABLE not supported on this chip\n"); 489 return CVMX_ADD_IO_SEG(0x00014F00000002D8ull); 490} 491#else 492#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) 493#endif 494#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 495#define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC() 496static inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void) 497{ 498 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 499 cvmx_warn("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n"); 500 return CVMX_ADD_IO_SEG(0x00014F00000003A8ull); 501} 502#else 503#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) 504#endif 505#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) 506#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1) 507#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2) 508#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3) 509#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4) 510#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5) 511#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) 512#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) 513#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 514static inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset) 515{ 516 if (!( 517 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 518 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 519 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 520 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 521 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 522 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 523 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 524 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 525 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 526 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 527 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 528 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 529 cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset); 530 return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8; 531} 532#else 533#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) 534#endif 535#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 536#define CVMX_IPD_REQ_WGT CVMX_IPD_REQ_WGT_FUNC() 537static inline uint64_t CVMX_IPD_REQ_WGT_FUNC(void) 538{ 539 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 540 cvmx_warn("CVMX_IPD_REQ_WGT not supported on this chip\n"); 541 return CVMX_ADD_IO_SEG(0x00014F0000004418ull); 542} 543#else 544#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull)) 545#endif 546#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) 547#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 548#define CVMX_IPD_SUB_PORT_FCS CVMX_IPD_SUB_PORT_FCS_FUNC() 549static inline uint64_t CVMX_IPD_SUB_PORT_FCS_FUNC(void) 550{ 551 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 552 cvmx_warn("CVMX_IPD_SUB_PORT_FCS not supported on this chip\n"); 553 return CVMX_ADD_IO_SEG(0x00014F0000000170ull); 554} 555#else 556#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) 557#endif 558#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 559#define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC() 560static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void) 561{ 562 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 563 cvmx_warn("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n"); 564 return CVMX_ADD_IO_SEG(0x00014F0000000800ull); 565} 566#else 567#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) 568#endif 569#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull)) 570#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 571#define CVMX_IPD_WQE_PTR_VALID CVMX_IPD_WQE_PTR_VALID_FUNC() 572static inline uint64_t CVMX_IPD_WQE_PTR_VALID_FUNC(void) 573{ 574 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 575 cvmx_warn("CVMX_IPD_WQE_PTR_VALID not supported on this chip\n"); 576 return CVMX_ADD_IO_SEG(0x00014F0000000360ull); 577} 578#else 579#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull)) 580#endif 581 582/** 583 * cvmx_ipd_1st_mbuff_skip 584 * 585 * IPD_1ST_MBUFF_SKIP = IPD First MBUFF Word Skip Size 586 * 587 * The number of words that the IPD will skip when writing the first MBUFF. 588 */ 589union cvmx_ipd_1st_mbuff_skip { 590 uint64_t u64; 591 struct cvmx_ipd_1st_mbuff_skip_s { 592#ifdef __BIG_ENDIAN_BITFIELD 593 uint64_t reserved_6_63 : 58; 594 uint64_t skip_sz : 6; /**< The number of 8-byte words from the top of the 595 1st MBUFF that the IPD will store the next-pointer. 596 Legal values are 0 to 32, where the MAX value 597 is also limited to: 598 IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 18. 599 Must be at least 16 when IPD_CTL_STATUS[NO_WPTR] 600 is set. */ 601#else 602 uint64_t skip_sz : 6; 603 uint64_t reserved_6_63 : 58; 604#endif 605 } s; 606 struct cvmx_ipd_1st_mbuff_skip_s cn30xx; 607 struct cvmx_ipd_1st_mbuff_skip_s cn31xx; 608 struct cvmx_ipd_1st_mbuff_skip_s cn38xx; 609 struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2; 610 struct cvmx_ipd_1st_mbuff_skip_s cn50xx; 611 struct cvmx_ipd_1st_mbuff_skip_s cn52xx; 612 struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1; 613 struct cvmx_ipd_1st_mbuff_skip_s cn56xx; 614 struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; 615 struct cvmx_ipd_1st_mbuff_skip_s cn58xx; 616 struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; 617 struct cvmx_ipd_1st_mbuff_skip_s cn61xx; 618 struct cvmx_ipd_1st_mbuff_skip_s cn63xx; 619 struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1; 620 struct cvmx_ipd_1st_mbuff_skip_s cn66xx; 621 struct cvmx_ipd_1st_mbuff_skip_s cn68xx; 622 struct cvmx_ipd_1st_mbuff_skip_s cn68xxp1; 623 struct cvmx_ipd_1st_mbuff_skip_s cnf71xx; 624}; 625typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_1st_mbuff_skip_t; 626 627/** 628 * cvmx_ipd_1st_next_ptr_back 629 * 630 * IPD_1st_NEXT_PTR_BACK = IPD First Next Pointer Back Values 631 * 632 * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF 633 */ 634union cvmx_ipd_1st_next_ptr_back { 635 uint64_t u64; 636 struct cvmx_ipd_1st_next_ptr_back_s { 637#ifdef __BIG_ENDIAN_BITFIELD 638 uint64_t reserved_4_63 : 60; 639 uint64_t back : 4; /**< Used to find head of buffer from the nxt-hdr-ptr. */ 640#else 641 uint64_t back : 4; 642 uint64_t reserved_4_63 : 60; 643#endif 644 } s; 645 struct cvmx_ipd_1st_next_ptr_back_s cn30xx; 646 struct cvmx_ipd_1st_next_ptr_back_s cn31xx; 647 struct cvmx_ipd_1st_next_ptr_back_s cn38xx; 648 struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2; 649 struct cvmx_ipd_1st_next_ptr_back_s cn50xx; 650 struct cvmx_ipd_1st_next_ptr_back_s cn52xx; 651 struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1; 652 struct cvmx_ipd_1st_next_ptr_back_s cn56xx; 653 struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; 654 struct cvmx_ipd_1st_next_ptr_back_s cn58xx; 655 struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; 656 struct cvmx_ipd_1st_next_ptr_back_s cn61xx; 657 struct cvmx_ipd_1st_next_ptr_back_s cn63xx; 658 struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1; 659 struct cvmx_ipd_1st_next_ptr_back_s cn66xx; 660 struct cvmx_ipd_1st_next_ptr_back_s cn68xx; 661 struct cvmx_ipd_1st_next_ptr_back_s cn68xxp1; 662 struct cvmx_ipd_1st_next_ptr_back_s cnf71xx; 663}; 664typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_1st_next_ptr_back_t; 665 666/** 667 * cvmx_ipd_2nd_next_ptr_back 668 * 669 * IPD_2nd_NEXT_PTR_BACK = IPD Second Next Pointer Back Value 670 * 671 * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF 672 */ 673union cvmx_ipd_2nd_next_ptr_back { 674 uint64_t u64; 675 struct cvmx_ipd_2nd_next_ptr_back_s { 676#ifdef __BIG_ENDIAN_BITFIELD 677 uint64_t reserved_4_63 : 60; 678 uint64_t back : 4; /**< Used to find head of buffer from the nxt-hdr-ptr. */ 679#else 680 uint64_t back : 4; 681 uint64_t reserved_4_63 : 60; 682#endif 683 } s; 684 struct cvmx_ipd_2nd_next_ptr_back_s cn30xx; 685 struct cvmx_ipd_2nd_next_ptr_back_s cn31xx; 686 struct cvmx_ipd_2nd_next_ptr_back_s cn38xx; 687 struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2; 688 struct cvmx_ipd_2nd_next_ptr_back_s cn50xx; 689 struct cvmx_ipd_2nd_next_ptr_back_s cn52xx; 690 struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1; 691 struct cvmx_ipd_2nd_next_ptr_back_s cn56xx; 692 struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; 693 struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; 694 struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; 695 struct cvmx_ipd_2nd_next_ptr_back_s cn61xx; 696 struct cvmx_ipd_2nd_next_ptr_back_s cn63xx; 697 struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1; 698 struct cvmx_ipd_2nd_next_ptr_back_s cn66xx; 699 struct cvmx_ipd_2nd_next_ptr_back_s cn68xx; 700 struct cvmx_ipd_2nd_next_ptr_back_s cn68xxp1; 701 struct cvmx_ipd_2nd_next_ptr_back_s cnf71xx; 702}; 703typedef union cvmx_ipd_2nd_next_ptr_back cvmx_ipd_2nd_next_ptr_back_t; 704 705/** 706 * cvmx_ipd_bist_status 707 * 708 * IPD_BIST_STATUS = IPD BIST STATUS 709 * 710 * BIST Status for IPD's Memories. 711 */ 712union cvmx_ipd_bist_status { 713 uint64_t u64; 714 struct cvmx_ipd_bist_status_s { 715#ifdef __BIG_ENDIAN_BITFIELD 716 uint64_t reserved_23_63 : 41; 717 uint64_t iiwo1 : 1; /**< IPD IOB WQE Dataout MEM1 Bist Status. */ 718 uint64_t iiwo0 : 1; /**< IPD IOB WQE Dataout MEM0 Bist Status. */ 719 uint64_t iio1 : 1; /**< IPD IOB Dataout MEM1 Bist Status. */ 720 uint64_t iio0 : 1; /**< IPD IOB Dataout MEM0 Bist Status. */ 721 uint64_t pbm4 : 1; /**< PBM4Memory Bist Status. */ 722 uint64_t csr_mem : 1; /**< CSR Register Memory Bist Status. */ 723 uint64_t csr_ncmd : 1; /**< CSR NCB Commands Memory Bist Status. */ 724 uint64_t pwq_wqed : 1; /**< PWQ PIP WQE DONE Memory Bist Status. */ 725 uint64_t pwq_wp1 : 1; /**< PWQ WQE PAGE1 PTR Memory Bist Status. */ 726 uint64_t pwq_pow : 1; /**< PWQ POW MEM Memory Bist Status. */ 727 uint64_t ipq_pbe1 : 1; /**< IPQ PBE1 Memory Bist Status. */ 728 uint64_t ipq_pbe0 : 1; /**< IPQ PBE0 Memory Bist Status. */ 729 uint64_t pbm3 : 1; /**< PBM3 Memory Bist Status. */ 730 uint64_t pbm2 : 1; /**< PBM2 Memory Bist Status. */ 731 uint64_t pbm1 : 1; /**< PBM1 Memory Bist Status. */ 732 uint64_t pbm0 : 1; /**< PBM0 Memory Bist Status. */ 733 uint64_t pbm_word : 1; /**< PBM_WORD Memory Bist Status. */ 734 uint64_t pwq1 : 1; /**< PWQ1 Memory Bist Status. */ 735 uint64_t pwq0 : 1; /**< PWQ0 Memory Bist Status. */ 736 uint64_t prc_off : 1; /**< PRC_OFF Memory Bist Status. */ 737 uint64_t ipd_old : 1; /**< IPD_OLD Memory Bist Status. */ 738 uint64_t ipd_new : 1; /**< IPD_NEW Memory Bist Status. */ 739 uint64_t pwp : 1; /**< PWP Memory Bist Status. */ 740#else 741 uint64_t pwp : 1; 742 uint64_t ipd_new : 1; 743 uint64_t ipd_old : 1; 744 uint64_t prc_off : 1; 745 uint64_t pwq0 : 1; 746 uint64_t pwq1 : 1; 747 uint64_t pbm_word : 1; 748 uint64_t pbm0 : 1; 749 uint64_t pbm1 : 1; 750 uint64_t pbm2 : 1; 751 uint64_t pbm3 : 1; 752 uint64_t ipq_pbe0 : 1; 753 uint64_t ipq_pbe1 : 1; 754 uint64_t pwq_pow : 1; 755 uint64_t pwq_wp1 : 1; 756 uint64_t pwq_wqed : 1; 757 uint64_t csr_ncmd : 1; 758 uint64_t csr_mem : 1; 759 uint64_t pbm4 : 1; 760 uint64_t iio0 : 1; 761 uint64_t iio1 : 1; 762 uint64_t iiwo0 : 1; 763 uint64_t iiwo1 : 1; 764 uint64_t reserved_23_63 : 41; 765#endif 766 } s; 767 struct cvmx_ipd_bist_status_cn30xx { 768#ifdef __BIG_ENDIAN_BITFIELD 769 uint64_t reserved_16_63 : 48; 770 uint64_t pwq_wqed : 1; /**< PWQ PIP WQE DONE Memory Bist Status. */ 771 uint64_t pwq_wp1 : 1; /**< PWQ WQE PAGE1 PTR Memory Bist Status. */ 772 uint64_t pwq_pow : 1; /**< PWQ POW MEM Memory Bist Status. */ 773 uint64_t ipq_pbe1 : 1; /**< IPQ PBE1 Memory Bist Status. */ 774 uint64_t ipq_pbe0 : 1; /**< IPQ PBE0 Memory Bist Status. */ 775 uint64_t pbm3 : 1; /**< PBM3 Memory Bist Status. */ 776 uint64_t pbm2 : 1; /**< PBM2 Memory Bist Status. */ 777 uint64_t pbm1 : 1; /**< PBM1 Memory Bist Status. */ 778 uint64_t pbm0 : 1; /**< PBM0 Memory Bist Status. */ 779 uint64_t pbm_word : 1; /**< PBM_WORD Memory Bist Status. */ 780 uint64_t pwq1 : 1; /**< PWQ1 Memory Bist Status. */ 781 uint64_t pwq0 : 1; /**< PWQ0 Memory Bist Status. */ 782 uint64_t prc_off : 1; /**< PRC_OFF Memory Bist Status. */ 783 uint64_t ipd_old : 1; /**< IPD_OLD Memory Bist Status. */ 784 uint64_t ipd_new : 1; /**< IPD_NEW Memory Bist Status. */ 785 uint64_t pwp : 1; /**< PWP Memory Bist Status. */ 786#else 787 uint64_t pwp : 1; 788 uint64_t ipd_new : 1; 789 uint64_t ipd_old : 1; 790 uint64_t prc_off : 1; 791 uint64_t pwq0 : 1; 792 uint64_t pwq1 : 1; 793 uint64_t pbm_word : 1; 794 uint64_t pbm0 : 1; 795 uint64_t pbm1 : 1; 796 uint64_t pbm2 : 1; 797 uint64_t pbm3 : 1; 798 uint64_t ipq_pbe0 : 1; 799 uint64_t ipq_pbe1 : 1; 800 uint64_t pwq_pow : 1; 801 uint64_t pwq_wp1 : 1; 802 uint64_t pwq_wqed : 1; 803 uint64_t reserved_16_63 : 48; 804#endif 805 } cn30xx; 806 struct cvmx_ipd_bist_status_cn30xx cn31xx; 807 struct cvmx_ipd_bist_status_cn30xx cn38xx; 808 struct cvmx_ipd_bist_status_cn30xx cn38xxp2; 809 struct cvmx_ipd_bist_status_cn30xx cn50xx; 810 struct cvmx_ipd_bist_status_cn52xx { 811#ifdef __BIG_ENDIAN_BITFIELD 812 uint64_t reserved_18_63 : 46; 813 uint64_t csr_mem : 1; /**< CSR Register Memory Bist Status. */ 814 uint64_t csr_ncmd : 1; /**< CSR NCB Commands Memory Bist Status. */ 815 uint64_t pwq_wqed : 1; /**< PWQ PIP WQE DONE Memory Bist Status. */ 816 uint64_t pwq_wp1 : 1; /**< PWQ WQE PAGE1 PTR Memory Bist Status. */ 817 uint64_t pwq_pow : 1; /**< PWQ POW MEM Memory Bist Status. */ 818 uint64_t ipq_pbe1 : 1; /**< IPQ PBE1 Memory Bist Status. */ 819 uint64_t ipq_pbe0 : 1; /**< IPQ PBE0 Memory Bist Status. */ 820 uint64_t pbm3 : 1; /**< PBM3 Memory Bist Status. */ 821 uint64_t pbm2 : 1; /**< PBM2 Memory Bist Status. */ 822 uint64_t pbm1 : 1; /**< PBM1 Memory Bist Status. */ 823 uint64_t pbm0 : 1; /**< PBM0 Memory Bist Status. */ 824 uint64_t pbm_word : 1; /**< PBM_WORD Memory Bist Status. */ 825 uint64_t pwq1 : 1; /**< PWQ1 Memory Bist Status. */ 826 uint64_t pwq0 : 1; /**< PWQ0 Memory Bist Status. */ 827 uint64_t prc_off : 1; /**< PRC_OFF Memory Bist Status. */ 828 uint64_t ipd_old : 1; /**< IPD_OLD Memory Bist Status. */ 829 uint64_t ipd_new : 1; /**< IPD_NEW Memory Bist Status. */ 830 uint64_t pwp : 1; /**< PWP Memory Bist Status. */ 831#else 832 uint64_t pwp : 1; 833 uint64_t ipd_new : 1; 834 uint64_t ipd_old : 1; 835 uint64_t prc_off : 1; 836 uint64_t pwq0 : 1; 837 uint64_t pwq1 : 1; 838 uint64_t pbm_word : 1; 839 uint64_t pbm0 : 1; 840 uint64_t pbm1 : 1; 841 uint64_t pbm2 : 1; 842 uint64_t pbm3 : 1; 843 uint64_t ipq_pbe0 : 1; 844 uint64_t ipq_pbe1 : 1; 845 uint64_t pwq_pow : 1; 846 uint64_t pwq_wp1 : 1; 847 uint64_t pwq_wqed : 1; 848 uint64_t csr_ncmd : 1; 849 uint64_t csr_mem : 1; 850 uint64_t reserved_18_63 : 46; 851#endif 852 } cn52xx; 853 struct cvmx_ipd_bist_status_cn52xx cn52xxp1; 854 struct cvmx_ipd_bist_status_cn52xx cn56xx; 855 struct cvmx_ipd_bist_status_cn52xx cn56xxp1; 856 struct cvmx_ipd_bist_status_cn30xx cn58xx; 857 struct cvmx_ipd_bist_status_cn30xx cn58xxp1; 858 struct cvmx_ipd_bist_status_cn52xx cn61xx; 859 struct cvmx_ipd_bist_status_cn52xx cn63xx; 860 struct cvmx_ipd_bist_status_cn52xx cn63xxp1; 861 struct cvmx_ipd_bist_status_cn52xx cn66xx; 862 struct cvmx_ipd_bist_status_s cn68xx; 863 struct cvmx_ipd_bist_status_s cn68xxp1; 864 struct cvmx_ipd_bist_status_cn52xx cnf71xx; 865}; 866typedef union cvmx_ipd_bist_status cvmx_ipd_bist_status_t; 867 868/** 869 * cvmx_ipd_bp_prt_red_end 870 * 871 * IPD_BP_PRT_RED_END = IPD Backpressure Port RED Enable 872 * 873 * When IPD applies backpressure to a PORT and the corresponding bit in this register is set, 874 * the RED Unit will drop packets for that port. 875 */ 876union cvmx_ipd_bp_prt_red_end { 877 uint64_t u64; 878 struct cvmx_ipd_bp_prt_red_end_s { 879#ifdef __BIG_ENDIAN_BITFIELD 880 uint64_t reserved_48_63 : 16; 881 uint64_t prt_enb : 48; /**< The port corresponding to the bit position in this 882 field will drop all NON-RAW packets to that port 883 when port level backpressure is applied to that 884 port. The applying of port-level backpressure for 885 this dropping does not take into consideration the 886 value of IPD_PORTX_BP_PAGE_CNT[BP_ENB], nor 887 IPD_RED_PORT_ENABLE[PRT_ENB]. */ 888#else 889 uint64_t prt_enb : 48; 890 uint64_t reserved_48_63 : 16; 891#endif 892 } s; 893 struct cvmx_ipd_bp_prt_red_end_cn30xx { 894#ifdef __BIG_ENDIAN_BITFIELD 895 uint64_t reserved_36_63 : 28; 896 uint64_t prt_enb : 36; /**< The port corresponding to the bit position in this 897 field, will allow RED to drop back when port level 898 backpressure is applied to the port. The applying 899 of port-level backpressure for this RED dropping 900 does not take into consideration the value of 901 IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */ 902#else 903 uint64_t prt_enb : 36; 904 uint64_t reserved_36_63 : 28; 905#endif 906 } cn30xx; 907 struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx; 908 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; 909 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; 910 struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; 911 struct cvmx_ipd_bp_prt_red_end_cn52xx { 912#ifdef __BIG_ENDIAN_BITFIELD 913 uint64_t reserved_40_63 : 24; 914 uint64_t prt_enb : 40; /**< The port corresponding to the bit position in this 915 field, will allow RED to drop back when port level 916 backpressure is applied to the port. The applying 917 of port-level backpressure for this RED dropping 918 does not take into consideration the value of 919 IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */ 920#else 921 uint64_t prt_enb : 40; 922 uint64_t reserved_40_63 : 24; 923#endif 924 } cn52xx; 925 struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1; 926 struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx; 927 struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1; 928 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; 929 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; 930 struct cvmx_ipd_bp_prt_red_end_s cn61xx; 931 struct cvmx_ipd_bp_prt_red_end_cn63xx { 932#ifdef __BIG_ENDIAN_BITFIELD 933 uint64_t reserved_44_63 : 20; 934 uint64_t prt_enb : 44; /**< The port corresponding to the bit position in this 935 field will drop all NON-RAW packets to that port 936 when port level backpressure is applied to that 937 port. The applying of port-level backpressure for 938 this dropping does not take into consideration the 939 value of IPD_PORTX_BP_PAGE_CNT[BP_ENB], nor 940 IPD_RED_PORT_ENABLE[PRT_ENB]. */ 941#else 942 uint64_t prt_enb : 44; 943 uint64_t reserved_44_63 : 20; 944#endif 945 } cn63xx; 946 struct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1; 947 struct cvmx_ipd_bp_prt_red_end_s cn66xx; 948 struct cvmx_ipd_bp_prt_red_end_s cnf71xx; 949}; 950typedef union cvmx_ipd_bp_prt_red_end cvmx_ipd_bp_prt_red_end_t; 951 952/** 953 * cvmx_ipd_bpid#_mbuf_th 954 * 955 * 0x2000 2FFF 956 * 957 * IPD_BPIDX_MBUF_TH = IPD BPID MBUFF Threshold 958 * 959 * The number of MBUFFs in use by the BPID, that when exceeded, backpressure will be applied to the BPID. 960 */ 961union cvmx_ipd_bpidx_mbuf_th { 962 uint64_t u64; 963 struct cvmx_ipd_bpidx_mbuf_th_s { 964#ifdef __BIG_ENDIAN_BITFIELD 965 uint64_t reserved_18_63 : 46; 966 uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 967 not be applied to bpid. */ 968 uint64_t page_cnt : 17; /**< The number of page pointers assigned to 969 the BPID, that when exceeded will cause 970 back-pressure to be applied to the BPID. 971 This value is in 256 page-pointer increments, 972 (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 973#else 974 uint64_t page_cnt : 17; 975 uint64_t bp_enb : 1; 976 uint64_t reserved_18_63 : 46; 977#endif 978 } s; 979 struct cvmx_ipd_bpidx_mbuf_th_s cn68xx; 980 struct cvmx_ipd_bpidx_mbuf_th_s cn68xxp1; 981}; 982typedef union cvmx_ipd_bpidx_mbuf_th cvmx_ipd_bpidx_mbuf_th_t; 983 984/** 985 * cvmx_ipd_bpid_bp_counter# 986 * 987 * RESERVE SPACE UPTO 0x2FFF 988 * 989 * 0x3000 0x3ffff 990 * 991 * IPD_BPID_BP_COUNTERX = MBUF BPID Counters used to generate Back Pressure Per BPID. 992 */ 993union cvmx_ipd_bpid_bp_counterx { 994 uint64_t u64; 995 struct cvmx_ipd_bpid_bp_counterx_s { 996#ifdef __BIG_ENDIAN_BITFIELD 997 uint64_t reserved_25_63 : 39; 998 uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this BPID. */ 999#else 1000 uint64_t cnt_val : 25; 1001 uint64_t reserved_25_63 : 39; 1002#endif 1003 } s; 1004 struct cvmx_ipd_bpid_bp_counterx_s cn68xx; 1005 struct cvmx_ipd_bpid_bp_counterx_s cn68xxp1; 1006}; 1007typedef union cvmx_ipd_bpid_bp_counterx cvmx_ipd_bpid_bp_counterx_t; 1008 1009/** 1010 * cvmx_ipd_clk_count 1011 * 1012 * IPD_CLK_COUNT = IPD Clock Count 1013 * 1014 * Counts the number of core clocks periods since the de-asserition of reset. 1015 */ 1016union cvmx_ipd_clk_count { 1017 uint64_t u64; 1018 struct cvmx_ipd_clk_count_s { 1019#ifdef __BIG_ENDIAN_BITFIELD 1020 uint64_t clk_cnt : 64; /**< This counter will be zeroed when reset is applied 1021 and will increment every rising edge of the 1022 core-clock. */ 1023#else 1024 uint64_t clk_cnt : 64; 1025#endif 1026 } s; 1027 struct cvmx_ipd_clk_count_s cn30xx; 1028 struct cvmx_ipd_clk_count_s cn31xx; 1029 struct cvmx_ipd_clk_count_s cn38xx; 1030 struct cvmx_ipd_clk_count_s cn38xxp2; 1031 struct cvmx_ipd_clk_count_s cn50xx; 1032 struct cvmx_ipd_clk_count_s cn52xx; 1033 struct cvmx_ipd_clk_count_s cn52xxp1; 1034 struct cvmx_ipd_clk_count_s cn56xx; 1035 struct cvmx_ipd_clk_count_s cn56xxp1; 1036 struct cvmx_ipd_clk_count_s cn58xx; 1037 struct cvmx_ipd_clk_count_s cn58xxp1; 1038 struct cvmx_ipd_clk_count_s cn61xx; 1039 struct cvmx_ipd_clk_count_s cn63xx; 1040 struct cvmx_ipd_clk_count_s cn63xxp1; 1041 struct cvmx_ipd_clk_count_s cn66xx; 1042 struct cvmx_ipd_clk_count_s cn68xx; 1043 struct cvmx_ipd_clk_count_s cn68xxp1; 1044 struct cvmx_ipd_clk_count_s cnf71xx; 1045}; 1046typedef union cvmx_ipd_clk_count cvmx_ipd_clk_count_t; 1047 1048/** 1049 * cvmx_ipd_credits 1050 * 1051 * IPD_CREDITS = IPD Credits 1052 * 1053 * The credits allowed for IPD. 1054 */ 1055union cvmx_ipd_credits { 1056 uint64_t u64; 1057 struct cvmx_ipd_credits_s { 1058#ifdef __BIG_ENDIAN_BITFIELD 1059 uint64_t reserved_16_63 : 48; 1060 uint64_t iob_wrc : 8; /**< The present number of credits available for 1061 stores to the IOB. */ 1062 uint64_t iob_wr : 8; /**< The number of command credits the IPD has to send 1063 stores to the IOB. Legal values for this field 1064 are 1-8 (a value of 0 will be treated as a 1 and 1065 a value greater than 8 will be treated as an 8. */ 1066#else 1067 uint64_t iob_wr : 8; 1068 uint64_t iob_wrc : 8; 1069 uint64_t reserved_16_63 : 48; 1070#endif 1071 } s; 1072 struct cvmx_ipd_credits_s cn68xx; 1073 struct cvmx_ipd_credits_s cn68xxp1; 1074}; 1075typedef union cvmx_ipd_credits cvmx_ipd_credits_t; 1076 1077/** 1078 * cvmx_ipd_ctl_status 1079 * 1080 * IPD_CTL_STATUS = IPD's Control Status Register 1081 * 1082 * The number of words in a MBUFF used for packet data store. 1083 */ 1084union cvmx_ipd_ctl_status { 1085 uint64_t u64; 1086 struct cvmx_ipd_ctl_status_s { 1087#ifdef __BIG_ENDIAN_BITFIELD 1088 uint64_t reserved_18_63 : 46; 1089 uint64_t use_sop : 1; /**< When '1' the SOP sent by the MAC will be used in 1090 place of the SOP generated by the IPD. */ 1091 uint64_t rst_done : 1; /**< When '0' IPD has finished reset. No access 1092 except the reading of this bit should occur to the 1093 IPD until this is asserted. Or a 1000 core clock 1094 cycles has passed after the de-assertion of reset. */ 1095 uint64_t clken : 1; /**< Controls the conditional clocking within IPD 1096 0=Allow HW to control the clocks 1097 1=Force the clocks to be always on */ 1098 uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 1099 the WQE will be located at the front of the packet. 1100 When set: 1101 - IPD_WQE_FPA_QUEUE[WQE_QUE] is not used 1102 - IPD_1ST_MBUFF_SKIP[SKIP_SZ] must be at least 16 1103 - If 16 <= IPD_1ST_MBUFF_SKIP[SKIP_SZ] <= 31 then 1104 the WQE will be written into the first 128B 1105 cache block in the first buffer that contains 1106 the packet. 1107 - If IPD_1ST_MBUFF_SKIP[SKIP_SZ] == 32 then 1108 the WQE will be written into the second 128B 1109 cache block in the first buffer that contains 1110 the packet. */ 1111 uint64_t pq_apkt : 1; /**< When set IPD_PORT_QOS_X_CNT WILL be incremented 1112 by one for every work queue entry that is sent to 1113 POW. */ 1114 uint64_t pq_nabuf : 1; /**< When set IPD_PORT_QOS_X_CNT WILL NOT be 1115 incremented when IPD allocates a buffer for a 1116 packet. */ 1117 uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1118 When set '1' the IPD drive the IPD_BUFF_FULL line to 1119 the IOB-arbiter, telling it to not give grants to 1120 NCB devices sending packet data. */ 1121 uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1122 buffering the received packet data. When set '1' 1123 the IPD will not buffer the received packet data. */ 1124 uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1125 data-length field in the header written to the 1126 POW and the top of a MBUFF. 1127 OCTEAN generates a length that includes the 1128 length of the data + 8 for the header-field. By 1129 setting this bit the 8 for the instr-field will 1130 not be included in the length field of the header. 1131 NOTE: IPD is compliant with the spec when this 1132 field is '1'. */ 1133 uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1134 RSL. */ 1135 uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1136 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1137 IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1138 IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1139 WILL be incremented by one for every work 1140 queue entry that is sent to POW. */ 1141 uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1142 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1143 IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1144 IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1145 WILL NOT be incremented when IPD allocates a 1146 buffer for a packet on the port. */ 1147 uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1148 uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1149 uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1150 the sending of port level backpressure to the 1151 Octane input-ports. The application should NOT 1152 de-assert this bit after asserting it. The 1153 receivers of this bit may have been put into 1154 backpressure mode and can only be released by 1155 IPD informing them that the backpressure has 1156 been released. 1157 GMXX_INF_MODE[EN] must be set to '1' for each 1158 packet interface which requires port back pressure 1159 prior to setting PBP_EN to '1'. */ 1160 cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1161 is written through to memory. 1162 1 ==> All packet data (and next buffer pointers) is 1163 written into the cache. 1164 2 ==> The first aligned cache block holding the 1165 packet data (and initial next buffer pointer) is 1166 written to the L2 cache, all remaining cache blocks 1167 are not written to the L2 cache. 1168 3 ==> The first two aligned cache blocks holding 1169 the packet data (and initial next buffer pointer) 1170 are written to the L2 cache, all remaining cache 1171 blocks are not written to the L2 cache. */ 1172 uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1173 When clear '0', the IPD will appear to the 1174 IOB-arbiter to be applying backpressure, this 1175 causes the IOB-Arbiter to not send grants to NCB 1176 devices requesting to send packet data to the IPD. */ 1177#else 1178 uint64_t ipd_en : 1; 1179 cvmx_ipd_mode_t opc_mode : 2; 1180 uint64_t pbp_en : 1; 1181 uint64_t wqe_lend : 1; 1182 uint64_t pkt_lend : 1; 1183 uint64_t naddbuf : 1; 1184 uint64_t addpkt : 1; 1185 uint64_t reset : 1; 1186 uint64_t len_m8 : 1; 1187 uint64_t pkt_off : 1; 1188 uint64_t ipd_full : 1; 1189 uint64_t pq_nabuf : 1; 1190 uint64_t pq_apkt : 1; 1191 uint64_t no_wptr : 1; 1192 uint64_t clken : 1; 1193 uint64_t rst_done : 1; 1194 uint64_t use_sop : 1; 1195 uint64_t reserved_18_63 : 46; 1196#endif 1197 } s; 1198 struct cvmx_ipd_ctl_status_cn30xx { 1199#ifdef __BIG_ENDIAN_BITFIELD 1200 uint64_t reserved_10_63 : 54; 1201 uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1202 data-length field in the header written wo the 1203 POW and the top of a MBUFF. 1204 OCTEAN generates a length that includes the 1205 length of the data + 8 for the header-field. By 1206 setting this bit the 8 for the instr-field will 1207 not be included in the length field of the header. 1208 NOTE: IPD is compliant with the spec when this 1209 field is '1'. */ 1210 uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1211 RSL. */ 1212 uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1213 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1214 WILL be incremented by one for every work 1215 queue entry that is sent to POW. */ 1216 uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1217 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1218 WILL NOT be incremented when IPD allocates a 1219 buffer for a packet on the port. */ 1220 uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1221 uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1222 uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1223 the sending of port level backpressure to the 1224 Octane input-ports. Once enabled the sending of 1225 port-level-backpressure can not be disabled by 1226 changing the value of this bit. 1227 GMXX_INF_MODE[EN] must be set to '1' for each 1228 packet interface which requires port back pressure 1229 prior to setting PBP_EN to '1'. */ 1230 cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1231 is written through to memory. 1232 1 ==> All packet data (and next buffer pointers) is 1233 written into the cache. 1234 2 ==> The first aligned cache block holding the 1235 packet data (and initial next buffer pointer) is 1236 written to the L2 cache, all remaining cache blocks 1237 are not written to the L2 cache. 1238 3 ==> The first two aligned cache blocks holding 1239 the packet data (and initial next buffer pointer) 1240 are written to the L2 cache, all remaining cache 1241 blocks are not written to the L2 cache. */ 1242 uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. */ 1243#else 1244 uint64_t ipd_en : 1; 1245 cvmx_ipd_mode_t opc_mode : 2; 1246 uint64_t pbp_en : 1; 1247 uint64_t wqe_lend : 1; 1248 uint64_t pkt_lend : 1; 1249 uint64_t naddbuf : 1; 1250 uint64_t addpkt : 1; 1251 uint64_t reset : 1; 1252 uint64_t len_m8 : 1; 1253 uint64_t reserved_10_63 : 54; 1254#endif 1255 } cn30xx; 1256 struct cvmx_ipd_ctl_status_cn30xx cn31xx; 1257 struct cvmx_ipd_ctl_status_cn30xx cn38xx; 1258 struct cvmx_ipd_ctl_status_cn38xxp2 { 1259#ifdef __BIG_ENDIAN_BITFIELD 1260 uint64_t reserved_9_63 : 55; 1261 uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1262 RSL. */ 1263 uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1264 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1265 WILL be incremented by one for every work 1266 queue entry that is sent to POW. 1267 PASS-2 Field. */ 1268 uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1269 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1270 WILL NOT be incremented when IPD allocates a 1271 buffer for a packet on the port. 1272 PASS-2 Field. */ 1273 uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1274 uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1275 uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1276 the sending of port level backpressure to the 1277 Octane input-ports. Once enabled the sending of 1278 port-level-backpressure can not be disabled by 1279 changing the value of this bit. */ 1280 cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1281 is written through to memory. 1282 1 ==> All packet data (and next buffer pointers) is 1283 written into the cache. 1284 2 ==> The first aligned cache block holding the 1285 packet data (and initial next buffer pointer) is 1286 written to the L2 cache, all remaining cache blocks 1287 are not written to the L2 cache. 1288 3 ==> The first two aligned cache blocks holding 1289 the packet data (and initial next buffer pointer) 1290 are written to the L2 cache, all remaining cache 1291 blocks are not written to the L2 cache. */ 1292 uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. */ 1293#else 1294 uint64_t ipd_en : 1; 1295 cvmx_ipd_mode_t opc_mode : 2; 1296 uint64_t pbp_en : 1; 1297 uint64_t wqe_lend : 1; 1298 uint64_t pkt_lend : 1; 1299 uint64_t naddbuf : 1; 1300 uint64_t addpkt : 1; 1301 uint64_t reset : 1; 1302 uint64_t reserved_9_63 : 55; 1303#endif 1304 } cn38xxp2; 1305 struct cvmx_ipd_ctl_status_cn50xx { 1306#ifdef __BIG_ENDIAN_BITFIELD 1307 uint64_t reserved_15_63 : 49; 1308 uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 1309 the WQE will be located at the front of the packet. */ 1310 uint64_t pq_apkt : 1; /**< Reserved. */ 1311 uint64_t pq_nabuf : 1; /**< Reserved. */ 1312 uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1313 When set '1' the IPD drive the IPD_BUFF_FULL line to 1314 the IOB-arbiter, telling it to not give grants to 1315 NCB devices sending packet data. */ 1316 uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1317 buffering the received packet data. When set '1' 1318 the IPD will not buffer the received packet data. */ 1319 uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1320 data-length field in the header written wo the 1321 POW and the top of a MBUFF. 1322 OCTEAN generates a length that includes the 1323 length of the data + 8 for the header-field. By 1324 setting this bit the 8 for the instr-field will 1325 not be included in the length field of the header. 1326 NOTE: IPD is compliant with the spec when this 1327 field is '1'. */ 1328 uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1329 RSL. */ 1330 uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1331 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1332 WILL be incremented by one for every work 1333 queue entry that is sent to POW. */ 1334 uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1335 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1336 WILL NOT be incremented when IPD allocates a 1337 buffer for a packet on the port. */ 1338 uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1339 uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1340 uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1341 the sending of port level backpressure to the 1342 Octane input-ports. Once enabled the sending of 1343 port-level-backpressure can not be disabled by 1344 changing the value of this bit. 1345 GMXX_INF_MODE[EN] must be set to '1' for each 1346 packet interface which requires port back pressure 1347 prior to setting PBP_EN to '1'. */ 1348 cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1349 is written through to memory. 1350 1 ==> All packet data (and next buffer pointers) is 1351 written into the cache. 1352 2 ==> The first aligned cache block holding the 1353 packet data (and initial next buffer pointer) is 1354 written to the L2 cache, all remaining cache blocks 1355 are not written to the L2 cache. 1356 3 ==> The first two aligned cache blocks holding 1357 the packet data (and initial next buffer pointer) 1358 are written to the L2 cache, all remaining cache 1359 blocks are not written to the L2 cache. */ 1360 uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1361 When clear '0', the IPD will appear to the 1362 IOB-arbiter to be applying backpressure, this 1363 causes the IOB-Arbiter to not send grants to NCB 1364 devices requesting to send packet data to the IPD. */ 1365#else 1366 uint64_t ipd_en : 1; 1367 cvmx_ipd_mode_t opc_mode : 2; 1368 uint64_t pbp_en : 1; 1369 uint64_t wqe_lend : 1; 1370 uint64_t pkt_lend : 1; 1371 uint64_t naddbuf : 1; 1372 uint64_t addpkt : 1; 1373 uint64_t reset : 1; 1374 uint64_t len_m8 : 1; 1375 uint64_t pkt_off : 1; 1376 uint64_t ipd_full : 1; 1377 uint64_t pq_nabuf : 1; 1378 uint64_t pq_apkt : 1; 1379 uint64_t no_wptr : 1; 1380 uint64_t reserved_15_63 : 49; 1381#endif 1382 } cn50xx; 1383 struct cvmx_ipd_ctl_status_cn50xx cn52xx; 1384 struct cvmx_ipd_ctl_status_cn50xx cn52xxp1; 1385 struct cvmx_ipd_ctl_status_cn50xx cn56xx; 1386 struct cvmx_ipd_ctl_status_cn50xx cn56xxp1; 1387 struct cvmx_ipd_ctl_status_cn58xx { 1388#ifdef __BIG_ENDIAN_BITFIELD 1389 uint64_t reserved_12_63 : 52; 1390 uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1391 When set '1' the IPD drive the IPD_BUFF_FULL line to 1392 the IOB-arbiter, telling it to not give grants to 1393 NCB devices sending packet data. */ 1394 uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1395 buffering the received packet data. When set '1' 1396 the IPD will not buffer the received packet data. */ 1397 uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1398 data-length field in the header written wo the 1399 POW and the top of a MBUFF. 1400 OCTEAN PASS2 generates a length that includes the 1401 length of the data + 8 for the header-field. By 1402 setting this bit the 8 for the instr-field will 1403 not be included in the length field of the header. 1404 NOTE: IPD is compliant with the spec when this 1405 field is '1'. */ 1406 uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1407 RSL. */ 1408 uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1409 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1410 WILL be incremented by one for every work 1411 queue entry that is sent to POW. 1412 PASS-2 Field. */ 1413 uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1414 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1415 WILL NOT be incremented when IPD allocates a 1416 buffer for a packet on the port. 1417 PASS-2 Field. */ 1418 uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1419 uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1420 uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1421 the sending of port level backpressure to the 1422 Octane input-ports. Once enabled the sending of 1423 port-level-backpressure can not be disabled by 1424 changing the value of this bit. */ 1425 cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1426 is written through to memory. 1427 1 ==> All packet data (and next buffer pointers) is 1428 written into the cache. 1429 2 ==> The first aligned cache block holding the 1430 packet data (and initial next buffer pointer) is 1431 written to the L2 cache, all remaining cache blocks 1432 are not written to the L2 cache. 1433 3 ==> The first two aligned cache blocks holding 1434 the packet data (and initial next buffer pointer) 1435 are written to the L2 cache, all remaining cache 1436 blocks are not written to the L2 cache. */ 1437 uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1438 When clear '0', the IPD will appear to the 1439 IOB-arbiter to be applying backpressure, this 1440 causes the IOB-Arbiter to not send grants to NCB 1441 devices requesting to send packet data to the IPD. */ 1442#else 1443 uint64_t ipd_en : 1; 1444 cvmx_ipd_mode_t opc_mode : 2; 1445 uint64_t pbp_en : 1; 1446 uint64_t wqe_lend : 1; 1447 uint64_t pkt_lend : 1; 1448 uint64_t naddbuf : 1; 1449 uint64_t addpkt : 1; 1450 uint64_t reset : 1; 1451 uint64_t len_m8 : 1; 1452 uint64_t pkt_off : 1; 1453 uint64_t ipd_full : 1; 1454 uint64_t reserved_12_63 : 52; 1455#endif 1456 } cn58xx; 1457 struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; 1458 struct cvmx_ipd_ctl_status_s cn61xx; 1459 struct cvmx_ipd_ctl_status_s cn63xx; 1460 struct cvmx_ipd_ctl_status_cn63xxp1 { 1461#ifdef __BIG_ENDIAN_BITFIELD 1462 uint64_t reserved_16_63 : 48; 1463 uint64_t clken : 1; /**< Controls the conditional clocking within IPD 1464 0=Allow HW to control the clocks 1465 1=Force the clocks to be always on */ 1466 uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 1467 the WQE will be located at the front of the packet. 1468 When set: 1469 - IPD_WQE_FPA_QUEUE[WQE_QUE] is not used 1470 - IPD_1ST_MBUFF_SKIP[SKIP_SZ] must be at least 16 1471 - If 16 <= IPD_1ST_MBUFF_SKIP[SKIP_SZ] <= 31 then 1472 the WQE will be written into the first 128B 1473 cache block in the first buffer that contains 1474 the packet. 1475 - If IPD_1ST_MBUFF_SKIP[SKIP_SZ] == 32 then 1476 the WQE will be written into the second 128B 1477 cache block in the first buffer that contains 1478 the packet. */ 1479 uint64_t pq_apkt : 1; /**< When set IPD_PORT_QOS_X_CNT WILL be incremented 1480 by one for every work queue entry that is sent to 1481 POW. */ 1482 uint64_t pq_nabuf : 1; /**< When set IPD_PORT_QOS_X_CNT WILL NOT be 1483 incremented when IPD allocates a buffer for a 1484 packet. */ 1485 uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1486 When set '1' the IPD drive the IPD_BUFF_FULL line to 1487 the IOB-arbiter, telling it to not give grants to 1488 NCB devices sending packet data. */ 1489 uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1490 buffering the received packet data. When set '1' 1491 the IPD will not buffer the received packet data. */ 1492 uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1493 data-length field in the header written to the 1494 POW and the top of a MBUFF. 1495 OCTEAN generates a length that includes the 1496 length of the data + 8 for the header-field. By 1497 setting this bit the 8 for the instr-field will 1498 not be included in the length field of the header. 1499 NOTE: IPD is compliant with the spec when this 1500 field is '1'. */ 1501 uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1502 RSL. */ 1503 uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1504 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1505 IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1506 IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1507 WILL be incremented by one for every work 1508 queue entry that is sent to POW. */ 1509 uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1510 IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1511 IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1512 IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1513 WILL NOT be incremented when IPD allocates a 1514 buffer for a packet on the port. */ 1515 uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1516 uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1517 uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1518 the sending of port level backpressure to the 1519 Octane input-ports. The application should NOT 1520 de-assert this bit after asserting it. The 1521 receivers of this bit may have been put into 1522 backpressure mode and can only be released by 1523 IPD informing them that the backpressure has 1524 been released. 1525 GMXX_INF_MODE[EN] must be set to '1' for each 1526 packet interface which requires port back pressure 1527 prior to setting PBP_EN to '1'. */ 1528 cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1529 is written through to memory. 1530 1 ==> All packet data (and next buffer pointers) is 1531 written into the cache. 1532 2 ==> The first aligned cache block holding the 1533 packet data (and initial next buffer pointer) is 1534 written to the L2 cache, all remaining cache blocks 1535 are not written to the L2 cache. 1536 3 ==> The first two aligned cache blocks holding 1537 the packet data (and initial next buffer pointer) 1538 are written to the L2 cache, all remaining cache 1539 blocks are not written to the L2 cache. */ 1540 uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1541 When clear '0', the IPD will appear to the 1542 IOB-arbiter to be applying backpressure, this 1543 causes the IOB-Arbiter to not send grants to NCB 1544 devices requesting to send packet data to the IPD. */ 1545#else 1546 uint64_t ipd_en : 1; 1547 cvmx_ipd_mode_t opc_mode : 2; 1548 uint64_t pbp_en : 1; 1549 uint64_t wqe_lend : 1; 1550 uint64_t pkt_lend : 1; 1551 uint64_t naddbuf : 1; 1552 uint64_t addpkt : 1; 1553 uint64_t reset : 1; 1554 uint64_t len_m8 : 1; 1555 uint64_t pkt_off : 1; 1556 uint64_t ipd_full : 1; 1557 uint64_t pq_nabuf : 1; 1558 uint64_t pq_apkt : 1; 1559 uint64_t no_wptr : 1; 1560 uint64_t clken : 1; 1561 uint64_t reserved_16_63 : 48; 1562#endif 1563 } cn63xxp1; 1564 struct cvmx_ipd_ctl_status_s cn66xx; 1565 struct cvmx_ipd_ctl_status_s cn68xx; 1566 struct cvmx_ipd_ctl_status_s cn68xxp1; 1567 struct cvmx_ipd_ctl_status_s cnf71xx; 1568}; 1569typedef union cvmx_ipd_ctl_status cvmx_ipd_ctl_status_t; 1570 1571/** 1572 * cvmx_ipd_ecc_ctl 1573 * 1574 * IPD_ECC_CTL = IPD ECC Control 1575 * 1576 * Allows inserting ECC errors for testing. 1577 */ 1578union cvmx_ipd_ecc_ctl { 1579 uint64_t u64; 1580 struct cvmx_ipd_ecc_ctl_s { 1581#ifdef __BIG_ENDIAN_BITFIELD 1582 uint64_t reserved_8_63 : 56; 1583 uint64_t pm3_syn : 2; /**< Flip the syndrom to generate 1-bit/2-bits error 1584 for testing of Packet Memory 3. 1585 2'b00 : No Error Generation 1586 2'b10, 2'b01: Flip 1 bit 1587 2'b11 : Flip 2 bits */ 1588 uint64_t pm2_syn : 2; /**< Flip the syndrom to generate 1-bit/2-bits error 1589 for testing of Packet Memory 2. 1590 2'b00 : No Error Generation 1591 2'b10, 2'b01: Flip 1 bit 1592 2'b11 : Flip 2 bits */ 1593 uint64_t pm1_syn : 2; /**< Flip the syndrom to generate 1-bit/2-bits error 1594 for testing of Packet Memory 1. 1595 2'b00 : No Error Generation 1596 2'b10, 2'b01: Flip 1 bit 1597 2'b11 : Flip 2 bits */ 1598 uint64_t pm0_syn : 2; /**< Flip the syndrom to generate 1-bit/2-bits error 1599 for testing of Packet Memory 0. 1600 2'b00 : No Error Generation 1601 2'b10, 2'b01: Flip 1 bit 1602 2'b11 : Flip 2 bits */ 1603#else 1604 uint64_t pm0_syn : 2; 1605 uint64_t pm1_syn : 2; 1606 uint64_t pm2_syn : 2; 1607 uint64_t pm3_syn : 2; 1608 uint64_t reserved_8_63 : 56; 1609#endif 1610 } s; 1611 struct cvmx_ipd_ecc_ctl_s cn68xx; 1612 struct cvmx_ipd_ecc_ctl_s cn68xxp1; 1613}; 1614typedef union cvmx_ipd_ecc_ctl cvmx_ipd_ecc_ctl_t; 1615 1616/** 1617 * cvmx_ipd_free_ptr_fifo_ctl 1618 * 1619 * IPD_FREE_PTR_FIFO_CTL = IPD's FREE Pointer FIFO Control 1620 * 1621 * Allows reading of the Page-Pointers stored in the IPD's FREE Fifo. 1622 * See also the IPD_FREE_PTR_VALUE 1623 */ 1624union cvmx_ipd_free_ptr_fifo_ctl { 1625 uint64_t u64; 1626 struct cvmx_ipd_free_ptr_fifo_ctl_s { 1627#ifdef __BIG_ENDIAN_BITFIELD 1628 uint64_t reserved_32_63 : 32; 1629 uint64_t max_cnts : 7; /**< Maximum number of Packet-Pointers or WQE-Pointers 1630 that COULD be in the FIFO. 1631 When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 1632 only represents the Max number of Packet-Pointers, 1633 WQE-Pointers are not used in this mode. */ 1634 uint64_t wraddr : 8; /**< Present FIFO WQE Read address. */ 1635 uint64_t praddr : 8; /**< Present FIFO Packet Read address. */ 1636 uint64_t cena : 1; /**< Active low Chip Enable to the read the 1637 pwp_fifo. This bit also controls the MUX-select 1638 that steers [RADDR] to the pwp_fifo. 1639 *WARNING - Setting this field to '0' will allow 1640 reading of the memories thorugh the PTR field, 1641 but will cause unpredictable operation of the IPD 1642 under normal operation. */ 1643 uint64_t raddr : 8; /**< Sets the address to read from in the pwp_fifo. 1644 Addresses 0 through 63 contain Packet-Pointers and 1645 addresses 64 through 127 contain WQE-Pointers. 1646 When IPD_CTL_STATUS[NO_WPTR] is set '1' addresses 1647 64 through 127 are not valid. */ 1648#else 1649 uint64_t raddr : 8; 1650 uint64_t cena : 1; 1651 uint64_t praddr : 8; 1652 uint64_t wraddr : 8; 1653 uint64_t max_cnts : 7; 1654 uint64_t reserved_32_63 : 32; 1655#endif 1656 } s; 1657 struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xx; 1658 struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xxp1; 1659}; 1660typedef union cvmx_ipd_free_ptr_fifo_ctl cvmx_ipd_free_ptr_fifo_ctl_t; 1661 1662/** 1663 * cvmx_ipd_free_ptr_value 1664 * 1665 * IPD_FREE_PTR_VALUE = IPD's FREE Pointer Value 1666 * 1667 * The value of the pointer selected through the IPD_FREE_PTR_FIFO_CTL 1668 */ 1669union cvmx_ipd_free_ptr_value { 1670 uint64_t u64; 1671 struct cvmx_ipd_free_ptr_value_s { 1672#ifdef __BIG_ENDIAN_BITFIELD 1673 uint64_t reserved_33_63 : 31; 1674 uint64_t ptr : 33; /**< The output of the pwp_fifo. */ 1675#else 1676 uint64_t ptr : 33; 1677 uint64_t reserved_33_63 : 31; 1678#endif 1679 } s; 1680 struct cvmx_ipd_free_ptr_value_s cn68xx; 1681 struct cvmx_ipd_free_ptr_value_s cn68xxp1; 1682}; 1683typedef union cvmx_ipd_free_ptr_value cvmx_ipd_free_ptr_value_t; 1684 1685/** 1686 * cvmx_ipd_hold_ptr_fifo_ctl 1687 * 1688 * IPD_HOLD_PTR_FIFO_CTL = IPD's Holding Pointer FIFO Control 1689 * 1690 * Allows reading of the Page-Pointers stored in the IPD's Holding Fifo. 1691 */ 1692union cvmx_ipd_hold_ptr_fifo_ctl { 1693 uint64_t u64; 1694 struct cvmx_ipd_hold_ptr_fifo_ctl_s { 1695#ifdef __BIG_ENDIAN_BITFIELD 1696 uint64_t reserved_43_63 : 21; 1697 uint64_t ptr : 33; /**< The output of the holding-fifo. */ 1698 uint64_t max_pkt : 3; /**< Maximum number of Packet-Pointers that COULD be 1699 in the FIFO. */ 1700 uint64_t praddr : 3; /**< Present Packet-Pointer read address. */ 1701 uint64_t cena : 1; /**< Active low Chip Enable that controls the 1702 MUX-select that steers [RADDR] to the fifo. 1703 *WARNING - Setting this field to '0' will allow 1704 reading of the memories thorugh the PTR field, 1705 but will cause unpredictable operation of the IPD 1706 under normal operation. */ 1707 uint64_t raddr : 3; /**< Sets the address to read from in the holding. 1708 fifo in the IPD. This FIFO holds Packet-Pointers 1709 to be used for packet data storage. */ 1710#else 1711 uint64_t raddr : 3; 1712 uint64_t cena : 1; 1713 uint64_t praddr : 3; 1714 uint64_t max_pkt : 3; 1715 uint64_t ptr : 33; 1716 uint64_t reserved_43_63 : 21; 1717#endif 1718 } s; 1719 struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xx; 1720 struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xxp1; 1721}; 1722typedef union cvmx_ipd_hold_ptr_fifo_ctl cvmx_ipd_hold_ptr_fifo_ctl_t; 1723 1724/** 1725 * cvmx_ipd_int_enb 1726 * 1727 * IPD_INTERRUPT_ENB = IPD Interrupt Enable Register 1728 * 1729 * Used to enable the various interrupting conditions of IPD 1730 */ 1731union cvmx_ipd_int_enb { 1732 uint64_t u64; 1733 struct cvmx_ipd_int_enb_s { 1734#ifdef __BIG_ENDIAN_BITFIELD 1735 uint64_t reserved_23_63 : 41; 1736 uint64_t pw3_dbe : 1; /**< Allows an interrupt to be sent when the 1737 corresponding bit in the IPD_INT_SUM is set. */ 1738 uint64_t pw3_sbe : 1; /**< Allows an interrupt to be sent when the 1739 corresponding bit in the IPD_INT_SUM is set. */ 1740 uint64_t pw2_dbe : 1; /**< Allows an interrupt to be sent when the 1741 corresponding bit in the IPD_INT_SUM is set. */ 1742 uint64_t pw2_sbe : 1; /**< Allows an interrupt to be sent when the 1743 corresponding bit in the IPD_INT_SUM is set. */ 1744 uint64_t pw1_dbe : 1; /**< Allows an interrupt to be sent when the 1745 corresponding bit in the IPD_INT_SUM is set. */ 1746 uint64_t pw1_sbe : 1; /**< Allows an interrupt to be sent when the 1747 corresponding bit in the IPD_INT_SUM is set. */ 1748 uint64_t pw0_dbe : 1; /**< Allows an interrupt to be sent when the 1749 corresponding bit in the IPD_INT_SUM is set. */ 1750 uint64_t pw0_sbe : 1; /**< Allows an interrupt to be sent when the 1751 corresponding bit in the IPD_INT_SUM is set. */ 1752 uint64_t dat : 1; /**< Allows an interrupt to be sent when the 1753 corresponding bit in the IPD_INT_SUM is set. */ 1754 uint64_t eop : 1; /**< Allows an interrupt to be sent when the 1755 corresponding bit in the IPD_INT_SUM is set. */ 1756 uint64_t sop : 1; /**< Allows an interrupt to be sent when the 1757 corresponding bit in the IPD_INT_SUM is set. */ 1758 uint64_t pq_sub : 1; /**< Allows an interrupt to be sent when the 1759 corresponding bit in the IPD_INT_SUM is set. */ 1760 uint64_t pq_add : 1; /**< Allows an interrupt to be sent when the 1761 corresponding bit in the IPD_INT_SUM is set. */ 1762 uint64_t bc_ovr : 1; /**< Allows an interrupt to be sent when the 1763 corresponding bit in the IPD_INT_SUM is set. */ 1764 uint64_t d_coll : 1; /**< Allows an interrupt to be sent when the 1765 corresponding bit in the IPD_INT_SUM is set. */ 1766 uint64_t c_coll : 1; /**< Allows an interrupt to be sent when the 1767 corresponding bit in the IPD_INT_SUM is set. */ 1768 uint64_t cc_ovr : 1; /**< Allows an interrupt to be sent when the 1769 corresponding bit in the IPD_INT_SUM is set. */ 1770 uint64_t dc_ovr : 1; /**< Allows an interrupt to be sent when the 1771 corresponding bit in the IPD_INT_SUM is set. */ 1772 uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1773 has an illegal value. */ 1774 uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1775 [127:96] of the PBM memory. */ 1776 uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1777 [95:64] of the PBM memory. */ 1778 uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1779 [63:32] of the PBM memory. */ 1780 uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1781 [31:0] of the PBM memory. */ 1782#else 1783 uint64_t prc_par0 : 1; 1784 uint64_t prc_par1 : 1; 1785 uint64_t prc_par2 : 1; 1786 uint64_t prc_par3 : 1; 1787 uint64_t bp_sub : 1; 1788 uint64_t dc_ovr : 1; 1789 uint64_t cc_ovr : 1; 1790 uint64_t c_coll : 1; 1791 uint64_t d_coll : 1; 1792 uint64_t bc_ovr : 1; 1793 uint64_t pq_add : 1; 1794 uint64_t pq_sub : 1; 1795 uint64_t sop : 1; 1796 uint64_t eop : 1; 1797 uint64_t dat : 1; 1798 uint64_t pw0_sbe : 1; 1799 uint64_t pw0_dbe : 1; 1800 uint64_t pw1_sbe : 1; 1801 uint64_t pw1_dbe : 1; 1802 uint64_t pw2_sbe : 1; 1803 uint64_t pw2_dbe : 1; 1804 uint64_t pw3_sbe : 1; 1805 uint64_t pw3_dbe : 1; 1806 uint64_t reserved_23_63 : 41; 1807#endif 1808 } s; 1809 struct cvmx_ipd_int_enb_cn30xx { 1810#ifdef __BIG_ENDIAN_BITFIELD 1811 uint64_t reserved_5_63 : 59; 1812 uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1813 has an illegal value. */ 1814 uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1815 [127:96] of the PBM memory. */ 1816 uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1817 [95:64] of the PBM memory. */ 1818 uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1819 [63:32] of the PBM memory. */ 1820 uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1821 [31:0] of the PBM memory. */ 1822#else 1823 uint64_t prc_par0 : 1; 1824 uint64_t prc_par1 : 1; 1825 uint64_t prc_par2 : 1; 1826 uint64_t prc_par3 : 1; 1827 uint64_t bp_sub : 1; 1828 uint64_t reserved_5_63 : 59; 1829#endif 1830 } cn30xx; 1831 struct cvmx_ipd_int_enb_cn30xx cn31xx; 1832 struct cvmx_ipd_int_enb_cn38xx { 1833#ifdef __BIG_ENDIAN_BITFIELD 1834 uint64_t reserved_10_63 : 54; 1835 uint64_t bc_ovr : 1; /**< Allows an interrupt to be sent when the 1836 corresponding bit in the IPD_INT_SUM is set. 1837 This is a PASS-3 Field. */ 1838 uint64_t d_coll : 1; /**< Allows an interrupt to be sent when the 1839 corresponding bit in the IPD_INT_SUM is set. 1840 This is a PASS-3 Field. */ 1841 uint64_t c_coll : 1; /**< Allows an interrupt to be sent when the 1842 corresponding bit in the IPD_INT_SUM is set. 1843 This is a PASS-3 Field. */ 1844 uint64_t cc_ovr : 1; /**< Allows an interrupt to be sent when the 1845 corresponding bit in the IPD_INT_SUM is set. 1846 This is a PASS-3 Field. */ 1847 uint64_t dc_ovr : 1; /**< Allows an interrupt to be sent when the 1848 corresponding bit in the IPD_INT_SUM is set. 1849 This is a PASS-3 Field. */ 1850 uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1851 has an illegal value. */ 1852 uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1853 [127:96] of the PBM memory. */ 1854 uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1855 [95:64] of the PBM memory. */ 1856 uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1857 [63:32] of the PBM memory. */ 1858 uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1859 [31:0] of the PBM memory. */ 1860#else 1861 uint64_t prc_par0 : 1; 1862 uint64_t prc_par1 : 1; 1863 uint64_t prc_par2 : 1; 1864 uint64_t prc_par3 : 1; 1865 uint64_t bp_sub : 1; 1866 uint64_t dc_ovr : 1; 1867 uint64_t cc_ovr : 1; 1868 uint64_t c_coll : 1; 1869 uint64_t d_coll : 1; 1870 uint64_t bc_ovr : 1; 1871 uint64_t reserved_10_63 : 54; 1872#endif 1873 } cn38xx; 1874 struct cvmx_ipd_int_enb_cn30xx cn38xxp2; 1875 struct cvmx_ipd_int_enb_cn38xx cn50xx; 1876 struct cvmx_ipd_int_enb_cn52xx { 1877#ifdef __BIG_ENDIAN_BITFIELD 1878 uint64_t reserved_12_63 : 52; 1879 uint64_t pq_sub : 1; /**< Allows an interrupt to be sent when the 1880 corresponding bit in the IPD_INT_SUM is set. */ 1881 uint64_t pq_add : 1; /**< Allows an interrupt to be sent when the 1882 corresponding bit in the IPD_INT_SUM is set. */ 1883 uint64_t bc_ovr : 1; /**< Allows an interrupt to be sent when the 1884 corresponding bit in the IPD_INT_SUM is set. */ 1885 uint64_t d_coll : 1; /**< Allows an interrupt to be sent when the 1886 corresponding bit in the IPD_INT_SUM is set. */ 1887 uint64_t c_coll : 1; /**< Allows an interrupt to be sent when the 1888 corresponding bit in the IPD_INT_SUM is set. */ 1889 uint64_t cc_ovr : 1; /**< Allows an interrupt to be sent when the 1890 corresponding bit in the IPD_INT_SUM is set. */ 1891 uint64_t dc_ovr : 1; /**< Allows an interrupt to be sent when the 1892 corresponding bit in the IPD_INT_SUM is set. */ 1893 uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1894 has an illegal value. */ 1895 uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1896 [127:96] of the PBM memory. */ 1897 uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1898 [95:64] of the PBM memory. */ 1899 uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1900 [63:32] of the PBM memory. */ 1901 uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1902 [31:0] of the PBM memory. */ 1903#else 1904 uint64_t prc_par0 : 1; 1905 uint64_t prc_par1 : 1; 1906 uint64_t prc_par2 : 1; 1907 uint64_t prc_par3 : 1; 1908 uint64_t bp_sub : 1; 1909 uint64_t dc_ovr : 1; 1910 uint64_t cc_ovr : 1; 1911 uint64_t c_coll : 1; 1912 uint64_t d_coll : 1; 1913 uint64_t bc_ovr : 1; 1914 uint64_t pq_add : 1; 1915 uint64_t pq_sub : 1; 1916 uint64_t reserved_12_63 : 52; 1917#endif 1918 } cn52xx; 1919 struct cvmx_ipd_int_enb_cn52xx cn52xxp1; 1920 struct cvmx_ipd_int_enb_cn52xx cn56xx; 1921 struct cvmx_ipd_int_enb_cn52xx cn56xxp1; 1922 struct cvmx_ipd_int_enb_cn38xx cn58xx; 1923 struct cvmx_ipd_int_enb_cn38xx cn58xxp1; 1924 struct cvmx_ipd_int_enb_cn52xx cn61xx; 1925 struct cvmx_ipd_int_enb_cn52xx cn63xx; 1926 struct cvmx_ipd_int_enb_cn52xx cn63xxp1; 1927 struct cvmx_ipd_int_enb_cn52xx cn66xx; 1928 struct cvmx_ipd_int_enb_s cn68xx; 1929 struct cvmx_ipd_int_enb_s cn68xxp1; 1930 struct cvmx_ipd_int_enb_cn52xx cnf71xx; 1931}; 1932typedef union cvmx_ipd_int_enb cvmx_ipd_int_enb_t; 1933 1934/** 1935 * cvmx_ipd_int_sum 1936 * 1937 * IPD_INTERRUPT_SUM = IPD Interrupt Summary Register 1938 * 1939 * Set when an interrupt condition occurs, write '1' to clear. 1940 */ 1941union cvmx_ipd_int_sum { 1942 uint64_t u64; 1943 struct cvmx_ipd_int_sum_s { 1944#ifdef __BIG_ENDIAN_BITFIELD 1945 uint64_t reserved_23_63 : 41; 1946 uint64_t pw3_dbe : 1; /**< Packet memory 3 had ECC DBE. */ 1947 uint64_t pw3_sbe : 1; /**< Packet memory 3 had ECC SBE. */ 1948 uint64_t pw2_dbe : 1; /**< Packet memory 2 had ECC DBE. */ 1949 uint64_t pw2_sbe : 1; /**< Packet memory 2 had ECC SBE. */ 1950 uint64_t pw1_dbe : 1; /**< Packet memory 1 had ECC DBE. */ 1951 uint64_t pw1_sbe : 1; /**< Packet memory 1 had ECC SBE. */ 1952 uint64_t pw0_dbe : 1; /**< Packet memory 0 had ECC DBE. */ 1953 uint64_t pw0_sbe : 1; /**< Packet memory 0 had ECC SBE. */ 1954 uint64_t dat : 1; /**< Set when a data arrives before a SOP for the same 1955 reasm-id for a packet. 1956 The first detected error associated with bits [14:12] 1957 of this register will only be set here. A new bit 1958 can be set when the previous reported bit is cleared. 1959 Also see IPD_PKT_ERR. */ 1960 uint64_t eop : 1; /**< Set when a EOP is followed by an EOP for the same 1961 reasm-id for a packet. 1962 The first detected error associated with bits [14:12] 1963 of this register will only be set here. A new bit 1964 can be set when the previous reported bit is cleared. 1965 Also see IPD_PKT_ERR. */ 1966 uint64_t sop : 1; /**< Set when a SOP is followed by an SOP for the same 1967 reasm-id for a packet. 1968 The first detected error associated with bits [14:12] 1969 of this register will only be set here. A new bit 1970 can be set when the previous reported bit is cleared. 1971 Also see IPD_PKT_ERR. */ 1972 uint64_t pq_sub : 1; /**< Set when a port-qos does an sub to the count 1973 that causes the counter to wrap. */ 1974 uint64_t pq_add : 1; /**< Set when a port-qos does an add to the count 1975 that causes the counter to wrap. */ 1976 uint64_t bc_ovr : 1; /**< Set when the byte-count to send to IOB overflows. */ 1977 uint64_t d_coll : 1; /**< Set when the packet/WQE data to be sent to IOB 1978 collides. */ 1979 uint64_t c_coll : 1; /**< Set when the packet/WQE commands to be sent to IOB 1980 collides. */ 1981 uint64_t cc_ovr : 1; /**< Set when the command credits to the IOB overflow. */ 1982 uint64_t dc_ovr : 1; /**< Set when the data credits to the IOB overflow. */ 1983 uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 1984 supplied illegal value. */ 1985 uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 1986 [127:96] of the PBM memory. */ 1987 uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 1988 [95:64] of the PBM memory. */ 1989 uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 1990 [63:32] of the PBM memory. */ 1991 uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 1992 [31:0] of the PBM memory. */ 1993#else 1994 uint64_t prc_par0 : 1; 1995 uint64_t prc_par1 : 1; 1996 uint64_t prc_par2 : 1; 1997 uint64_t prc_par3 : 1; 1998 uint64_t bp_sub : 1; 1999 uint64_t dc_ovr : 1; 2000 uint64_t cc_ovr : 1; 2001 uint64_t c_coll : 1; 2002 uint64_t d_coll : 1; 2003 uint64_t bc_ovr : 1; 2004 uint64_t pq_add : 1; 2005 uint64_t pq_sub : 1; 2006 uint64_t sop : 1; 2007 uint64_t eop : 1; 2008 uint64_t dat : 1; 2009 uint64_t pw0_sbe : 1; 2010 uint64_t pw0_dbe : 1; 2011 uint64_t pw1_sbe : 1; 2012 uint64_t pw1_dbe : 1; 2013 uint64_t pw2_sbe : 1; 2014 uint64_t pw2_dbe : 1; 2015 uint64_t pw3_sbe : 1; 2016 uint64_t pw3_dbe : 1; 2017 uint64_t reserved_23_63 : 41; 2018#endif 2019 } s; 2020 struct cvmx_ipd_int_sum_cn30xx { 2021#ifdef __BIG_ENDIAN_BITFIELD 2022 uint64_t reserved_5_63 : 59; 2023 uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 2024 supplied illegal value. */ 2025 uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 2026 [127:96] of the PBM memory. */ 2027 uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 2028 [95:64] of the PBM memory. */ 2029 uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 2030 [63:32] of the PBM memory. */ 2031 uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 2032 [31:0] of the PBM memory. */ 2033#else 2034 uint64_t prc_par0 : 1; 2035 uint64_t prc_par1 : 1; 2036 uint64_t prc_par2 : 1; 2037 uint64_t prc_par3 : 1; 2038 uint64_t bp_sub : 1; 2039 uint64_t reserved_5_63 : 59; 2040#endif 2041 } cn30xx; 2042 struct cvmx_ipd_int_sum_cn30xx cn31xx; 2043 struct cvmx_ipd_int_sum_cn38xx { 2044#ifdef __BIG_ENDIAN_BITFIELD 2045 uint64_t reserved_10_63 : 54; 2046 uint64_t bc_ovr : 1; /**< Set when the byte-count to send to IOB overflows. 2047 This is a PASS-3 Field. */ 2048 uint64_t d_coll : 1; /**< Set when the packet/WQE data to be sent to IOB 2049 collides. 2050 This is a PASS-3 Field. */ 2051 uint64_t c_coll : 1; /**< Set when the packet/WQE commands to be sent to IOB 2052 collides. 2053 This is a PASS-3 Field. */ 2054 uint64_t cc_ovr : 1; /**< Set when the command credits to the IOB overflow. 2055 This is a PASS-3 Field. */ 2056 uint64_t dc_ovr : 1; /**< Set when the data credits to the IOB overflow. 2057 This is a PASS-3 Field. */ 2058 uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 2059 supplied illegal value. */ 2060 uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 2061 [127:96] of the PBM memory. */ 2062 uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 2063 [95:64] of the PBM memory. */ 2064 uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 2065 [63:32] of the PBM memory. */ 2066 uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 2067 [31:0] of the PBM memory. */ 2068#else 2069 uint64_t prc_par0 : 1; 2070 uint64_t prc_par1 : 1; 2071 uint64_t prc_par2 : 1; 2072 uint64_t prc_par3 : 1; 2073 uint64_t bp_sub : 1; 2074 uint64_t dc_ovr : 1; 2075 uint64_t cc_ovr : 1; 2076 uint64_t c_coll : 1; 2077 uint64_t d_coll : 1; 2078 uint64_t bc_ovr : 1; 2079 uint64_t reserved_10_63 : 54; 2080#endif 2081 } cn38xx; 2082 struct cvmx_ipd_int_sum_cn30xx cn38xxp2; 2083 struct cvmx_ipd_int_sum_cn38xx cn50xx; 2084 struct cvmx_ipd_int_sum_cn52xx { 2085#ifdef __BIG_ENDIAN_BITFIELD 2086 uint64_t reserved_12_63 : 52; 2087 uint64_t pq_sub : 1; /**< Set when a port-qos does an sub to the count 2088 that causes the counter to wrap. */ 2089 uint64_t pq_add : 1; /**< Set when a port-qos does an add to the count 2090 that causes the counter to wrap. */ 2091 uint64_t bc_ovr : 1; /**< Set when the byte-count to send to IOB overflows. */ 2092 uint64_t d_coll : 1; /**< Set when the packet/WQE data to be sent to IOB 2093 collides. */ 2094 uint64_t c_coll : 1; /**< Set when the packet/WQE commands to be sent to IOB 2095 collides. */ 2096 uint64_t cc_ovr : 1; /**< Set when the command credits to the IOB overflow. */ 2097 uint64_t dc_ovr : 1; /**< Set when the data credits to the IOB overflow. */ 2098 uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 2099 supplied illegal value. */ 2100 uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 2101 [127:96] of the PBM memory. */ 2102 uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 2103 [95:64] of the PBM memory. */ 2104 uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 2105 [63:32] of the PBM memory. */ 2106 uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 2107 [31:0] of the PBM memory. */ 2108#else 2109 uint64_t prc_par0 : 1; 2110 uint64_t prc_par1 : 1; 2111 uint64_t prc_par2 : 1; 2112 uint64_t prc_par3 : 1; 2113 uint64_t bp_sub : 1; 2114 uint64_t dc_ovr : 1; 2115 uint64_t cc_ovr : 1; 2116 uint64_t c_coll : 1; 2117 uint64_t d_coll : 1; 2118 uint64_t bc_ovr : 1; 2119 uint64_t pq_add : 1; 2120 uint64_t pq_sub : 1; 2121 uint64_t reserved_12_63 : 52; 2122#endif 2123 } cn52xx; 2124 struct cvmx_ipd_int_sum_cn52xx cn52xxp1; 2125 struct cvmx_ipd_int_sum_cn52xx cn56xx; 2126 struct cvmx_ipd_int_sum_cn52xx cn56xxp1; 2127 struct cvmx_ipd_int_sum_cn38xx cn58xx; 2128 struct cvmx_ipd_int_sum_cn38xx cn58xxp1; 2129 struct cvmx_ipd_int_sum_cn52xx cn61xx; 2130 struct cvmx_ipd_int_sum_cn52xx cn63xx; 2131 struct cvmx_ipd_int_sum_cn52xx cn63xxp1; 2132 struct cvmx_ipd_int_sum_cn52xx cn66xx; 2133 struct cvmx_ipd_int_sum_s cn68xx; 2134 struct cvmx_ipd_int_sum_s cn68xxp1; 2135 struct cvmx_ipd_int_sum_cn52xx cnf71xx; 2136}; 2137typedef union cvmx_ipd_int_sum cvmx_ipd_int_sum_t; 2138 2139/** 2140 * cvmx_ipd_next_pkt_ptr 2141 * 2142 * IPD_NEXT_PKT_PTR = IPD's Next Packet Pointer 2143 * 2144 * The value of the packet-pointer fetched and in the valid register. 2145 */ 2146union cvmx_ipd_next_pkt_ptr { 2147 uint64_t u64; 2148 struct cvmx_ipd_next_pkt_ptr_s { 2149#ifdef __BIG_ENDIAN_BITFIELD 2150 uint64_t reserved_33_63 : 31; 2151 uint64_t ptr : 33; /**< Pointer value. */ 2152#else 2153 uint64_t ptr : 33; 2154 uint64_t reserved_33_63 : 31; 2155#endif 2156 } s; 2157 struct cvmx_ipd_next_pkt_ptr_s cn68xx; 2158 struct cvmx_ipd_next_pkt_ptr_s cn68xxp1; 2159}; 2160typedef union cvmx_ipd_next_pkt_ptr cvmx_ipd_next_pkt_ptr_t; 2161 2162/** 2163 * cvmx_ipd_next_wqe_ptr 2164 * 2165 * IPD_NEXT_WQE_PTR = IPD's NEXT_WQE Pointer 2166 * 2167 * The value of the WQE-pointer fetched and in the valid register. 2168 */ 2169union cvmx_ipd_next_wqe_ptr { 2170 uint64_t u64; 2171 struct cvmx_ipd_next_wqe_ptr_s { 2172#ifdef __BIG_ENDIAN_BITFIELD 2173 uint64_t reserved_33_63 : 31; 2174 uint64_t ptr : 33; /**< Pointer value. 2175 When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 2176 represents a Packet-Pointer NOT a WQE pointer. */ 2177#else 2178 uint64_t ptr : 33; 2179 uint64_t reserved_33_63 : 31; 2180#endif 2181 } s; 2182 struct cvmx_ipd_next_wqe_ptr_s cn68xx; 2183 struct cvmx_ipd_next_wqe_ptr_s cn68xxp1; 2184}; 2185typedef union cvmx_ipd_next_wqe_ptr cvmx_ipd_next_wqe_ptr_t; 2186 2187/** 2188 * cvmx_ipd_not_1st_mbuff_skip 2189 * 2190 * IPD_NOT_1ST_MBUFF_SKIP = IPD Not First MBUFF Word Skip Size 2191 * 2192 * The number of words that the IPD will skip when writing any MBUFF that is not the first. 2193 */ 2194union cvmx_ipd_not_1st_mbuff_skip { 2195 uint64_t u64; 2196 struct cvmx_ipd_not_1st_mbuff_skip_s { 2197#ifdef __BIG_ENDIAN_BITFIELD 2198 uint64_t reserved_6_63 : 58; 2199 uint64_t skip_sz : 6; /**< The number of 8-byte words from the top of any 2200 MBUFF, that is not the 1st MBUFF, that the IPD 2201 will write the next-pointer. 2202 Legal values are 0 to 32, where the MAX value 2203 is also limited to: 2204 IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 16. */ 2205#else 2206 uint64_t skip_sz : 6; 2207 uint64_t reserved_6_63 : 58; 2208#endif 2209 } s; 2210 struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx; 2211 struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx; 2212 struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx; 2213 struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2; 2214 struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx; 2215 struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx; 2216 struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1; 2217 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx; 2218 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; 2219 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; 2220 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; 2221 struct cvmx_ipd_not_1st_mbuff_skip_s cn61xx; 2222 struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx; 2223 struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1; 2224 struct cvmx_ipd_not_1st_mbuff_skip_s cn66xx; 2225 struct cvmx_ipd_not_1st_mbuff_skip_s cn68xx; 2226 struct cvmx_ipd_not_1st_mbuff_skip_s cn68xxp1; 2227 struct cvmx_ipd_not_1st_mbuff_skip_s cnf71xx; 2228}; 2229typedef union cvmx_ipd_not_1st_mbuff_skip cvmx_ipd_not_1st_mbuff_skip_t; 2230 2231/** 2232 * cvmx_ipd_on_bp_drop_pkt# 2233 * 2234 * RESERVE SPACE UPTO 0x3FFF 2235 * 2236 * 2237 * RESERVED FOR FORMER IPD_SUB_PKIND_FCS - MOVED TO PIP 2238 * 2239 * RESERVE 4008 - 40FF 2240 * 2241 * 2242 * IPD_ON_BP_DROP_PKT = IPD On Backpressure Drop Packet 2243 * 2244 * When IPD applies backpressure to a BPID and the corresponding bit in this register is set, 2245 * then previously received packets will be dropped when processed. 2246 */ 2247union cvmx_ipd_on_bp_drop_pktx { 2248 uint64_t u64; 2249 struct cvmx_ipd_on_bp_drop_pktx_s { 2250#ifdef __BIG_ENDIAN_BITFIELD 2251 uint64_t prt_enb : 64; /**< The BPID corresponding to the bit position in this 2252 field will drop all NON-RAW packets to that BPID 2253 when BPID level backpressure is applied to that 2254 BPID. The applying of BPID-level backpressure for 2255 this dropping does not take into consideration the 2256 value of IPD_BPIDX_MBUF_TH[BP_ENB], nor 2257 IPD_RED_BPID_ENABLE[PRT_ENB]. */ 2258#else 2259 uint64_t prt_enb : 64; 2260#endif 2261 } s; 2262 struct cvmx_ipd_on_bp_drop_pktx_s cn68xx; 2263 struct cvmx_ipd_on_bp_drop_pktx_s cn68xxp1; 2264}; 2265typedef union cvmx_ipd_on_bp_drop_pktx cvmx_ipd_on_bp_drop_pktx_t; 2266 2267/** 2268 * cvmx_ipd_packet_mbuff_size 2269 * 2270 * IPD_PACKET_MBUFF_SIZE = IPD's PACKET MUBUF Size In Words 2271 * 2272 * The number of words in a MBUFF used for packet data store. 2273 */ 2274union cvmx_ipd_packet_mbuff_size { 2275 uint64_t u64; 2276 struct cvmx_ipd_packet_mbuff_size_s { 2277#ifdef __BIG_ENDIAN_BITFIELD 2278 uint64_t reserved_12_63 : 52; 2279 uint64_t mb_size : 12; /**< The number of 8-byte words in a MBUF. 2280 This must be a number in the range of 32 to 2281 2048. 2282 This is also the size of the FPA's 2283 Queue-0 Free-Page. */ 2284#else 2285 uint64_t mb_size : 12; 2286 uint64_t reserved_12_63 : 52; 2287#endif 2288 } s; 2289 struct cvmx_ipd_packet_mbuff_size_s cn30xx; 2290 struct cvmx_ipd_packet_mbuff_size_s cn31xx; 2291 struct cvmx_ipd_packet_mbuff_size_s cn38xx; 2292 struct cvmx_ipd_packet_mbuff_size_s cn38xxp2; 2293 struct cvmx_ipd_packet_mbuff_size_s cn50xx; 2294 struct cvmx_ipd_packet_mbuff_size_s cn52xx; 2295 struct cvmx_ipd_packet_mbuff_size_s cn52xxp1; 2296 struct cvmx_ipd_packet_mbuff_size_s cn56xx; 2297 struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; 2298 struct cvmx_ipd_packet_mbuff_size_s cn58xx; 2299 struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; 2300 struct cvmx_ipd_packet_mbuff_size_s cn61xx; 2301 struct cvmx_ipd_packet_mbuff_size_s cn63xx; 2302 struct cvmx_ipd_packet_mbuff_size_s cn63xxp1; 2303 struct cvmx_ipd_packet_mbuff_size_s cn66xx; 2304 struct cvmx_ipd_packet_mbuff_size_s cn68xx; 2305 struct cvmx_ipd_packet_mbuff_size_s cn68xxp1; 2306 struct cvmx_ipd_packet_mbuff_size_s cnf71xx; 2307}; 2308typedef union cvmx_ipd_packet_mbuff_size cvmx_ipd_packet_mbuff_size_t; 2309 2310/** 2311 * cvmx_ipd_pkt_err 2312 * 2313 * IPD_PKT_ERR = IPD Packet Error Register 2314 * 2315 * Provides status about the failing packet recevie error. 2316 */ 2317union cvmx_ipd_pkt_err { 2318 uint64_t u64; 2319 struct cvmx_ipd_pkt_err_s { 2320#ifdef __BIG_ENDIAN_BITFIELD 2321 uint64_t reserved_6_63 : 58; 2322 uint64_t reasm : 6; /**< When IPD_INT_SUM[14:12] bit is set, this field 2323 latches the failing reasm number associated with 2324 the IPD_INT_SUM[14:12] bit set. 2325 Values 0-62 can be seen here, reasm-id 63 is not 2326 used. */ 2327#else 2328 uint64_t reasm : 6; 2329 uint64_t reserved_6_63 : 58; 2330#endif 2331 } s; 2332 struct cvmx_ipd_pkt_err_s cn68xx; 2333 struct cvmx_ipd_pkt_err_s cn68xxp1; 2334}; 2335typedef union cvmx_ipd_pkt_err cvmx_ipd_pkt_err_t; 2336 2337/** 2338 * cvmx_ipd_pkt_ptr_valid 2339 * 2340 * IPD_PKT_PTR_VALID = IPD's Packet Pointer Valid 2341 * 2342 * The value of the packet-pointer fetched and in the valid register. 2343 */ 2344union cvmx_ipd_pkt_ptr_valid { 2345 uint64_t u64; 2346 struct cvmx_ipd_pkt_ptr_valid_s { 2347#ifdef __BIG_ENDIAN_BITFIELD 2348 uint64_t reserved_29_63 : 35; 2349 uint64_t ptr : 29; /**< Pointer value. */ 2350#else 2351 uint64_t ptr : 29; 2352 uint64_t reserved_29_63 : 35; 2353#endif 2354 } s; 2355 struct cvmx_ipd_pkt_ptr_valid_s cn30xx; 2356 struct cvmx_ipd_pkt_ptr_valid_s cn31xx; 2357 struct cvmx_ipd_pkt_ptr_valid_s cn38xx; 2358 struct cvmx_ipd_pkt_ptr_valid_s cn50xx; 2359 struct cvmx_ipd_pkt_ptr_valid_s cn52xx; 2360 struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1; 2361 struct cvmx_ipd_pkt_ptr_valid_s cn56xx; 2362 struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; 2363 struct cvmx_ipd_pkt_ptr_valid_s cn58xx; 2364 struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; 2365 struct cvmx_ipd_pkt_ptr_valid_s cn61xx; 2366 struct cvmx_ipd_pkt_ptr_valid_s cn63xx; 2367 struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1; 2368 struct cvmx_ipd_pkt_ptr_valid_s cn66xx; 2369 struct cvmx_ipd_pkt_ptr_valid_s cnf71xx; 2370}; 2371typedef union cvmx_ipd_pkt_ptr_valid cvmx_ipd_pkt_ptr_valid_t; 2372 2373/** 2374 * cvmx_ipd_port#_bp_page_cnt 2375 * 2376 * IPD_PORTX_BP_PAGE_CNT = IPD Port Backpressure Page Count 2377 * 2378 * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 2379 * See also IPD_PORTX_BP_PAGE_CNT2 2380 * See also IPD_PORTX_BP_PAGE_CNT3 2381 */ 2382union cvmx_ipd_portx_bp_page_cnt { 2383 uint64_t u64; 2384 struct cvmx_ipd_portx_bp_page_cnt_s { 2385#ifdef __BIG_ENDIAN_BITFIELD 2386 uint64_t reserved_18_63 : 46; 2387 uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 2388 not be applied to port. */ 2389 uint64_t page_cnt : 17; /**< The number of page pointers assigned to 2390 the port, that when exceeded will cause 2391 back-pressure to be applied to the port. 2392 This value is in 256 page-pointer increments, 2393 (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 2394#else 2395 uint64_t page_cnt : 17; 2396 uint64_t bp_enb : 1; 2397 uint64_t reserved_18_63 : 46; 2398#endif 2399 } s; 2400 struct cvmx_ipd_portx_bp_page_cnt_s cn30xx; 2401 struct cvmx_ipd_portx_bp_page_cnt_s cn31xx; 2402 struct cvmx_ipd_portx_bp_page_cnt_s cn38xx; 2403 struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2; 2404 struct cvmx_ipd_portx_bp_page_cnt_s cn50xx; 2405 struct cvmx_ipd_portx_bp_page_cnt_s cn52xx; 2406 struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1; 2407 struct cvmx_ipd_portx_bp_page_cnt_s cn56xx; 2408 struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; 2409 struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; 2410 struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; 2411 struct cvmx_ipd_portx_bp_page_cnt_s cn61xx; 2412 struct cvmx_ipd_portx_bp_page_cnt_s cn63xx; 2413 struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1; 2414 struct cvmx_ipd_portx_bp_page_cnt_s cn66xx; 2415 struct cvmx_ipd_portx_bp_page_cnt_s cnf71xx; 2416}; 2417typedef union cvmx_ipd_portx_bp_page_cnt cvmx_ipd_portx_bp_page_cnt_t; 2418 2419/** 2420 * cvmx_ipd_port#_bp_page_cnt2 2421 * 2422 * IPD_PORTX_BP_PAGE_CNT2 = IPD Port Backpressure Page Count 2423 * 2424 * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 2425 * See also IPD_PORTX_BP_PAGE_CNT 2426 * See also IPD_PORTX_BP_PAGE_CNT3 2427 * 0x368-0x380 2428 */ 2429union cvmx_ipd_portx_bp_page_cnt2 { 2430 uint64_t u64; 2431 struct cvmx_ipd_portx_bp_page_cnt2_s { 2432#ifdef __BIG_ENDIAN_BITFIELD 2433 uint64_t reserved_18_63 : 46; 2434 uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 2435 not be applied to port. */ 2436 uint64_t page_cnt : 17; /**< The number of page pointers assigned to 2437 the port, that when exceeded will cause 2438 back-pressure to be applied to the port. 2439 This value is in 256 page-pointer increments, 2440 (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 2441#else 2442 uint64_t page_cnt : 17; 2443 uint64_t bp_enb : 1; 2444 uint64_t reserved_18_63 : 46; 2445#endif 2446 } s; 2447 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx; 2448 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; 2449 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; 2450 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; 2451 struct cvmx_ipd_portx_bp_page_cnt2_s cn61xx; 2452 struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx; 2453 struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1; 2454 struct cvmx_ipd_portx_bp_page_cnt2_s cn66xx; 2455 struct cvmx_ipd_portx_bp_page_cnt2_s cnf71xx; 2456}; 2457typedef union cvmx_ipd_portx_bp_page_cnt2 cvmx_ipd_portx_bp_page_cnt2_t; 2458 2459/** 2460 * cvmx_ipd_port#_bp_page_cnt3 2461 * 2462 * IPD_PORTX_BP_PAGE_CNT3 = IPD Port Backpressure Page Count 2463 * 2464 * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 2465 * See also IPD_PORTX_BP_PAGE_CNT 2466 * See also IPD_PORTX_BP_PAGE_CNT2 2467 * 0x3d0-408 2468 */ 2469union cvmx_ipd_portx_bp_page_cnt3 { 2470 uint64_t u64; 2471 struct cvmx_ipd_portx_bp_page_cnt3_s { 2472#ifdef __BIG_ENDIAN_BITFIELD 2473 uint64_t reserved_18_63 : 46; 2474 uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 2475 not be applied to port. */ 2476 uint64_t page_cnt : 17; /**< The number of page pointers assigned to 2477 the port, that when exceeded will cause 2478 back-pressure to be applied to the port. 2479 This value is in 256 page-pointer increments, 2480 (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 2481#else 2482 uint64_t page_cnt : 17; 2483 uint64_t bp_enb : 1; 2484 uint64_t reserved_18_63 : 46; 2485#endif 2486 } s; 2487 struct cvmx_ipd_portx_bp_page_cnt3_s cn61xx; 2488 struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx; 2489 struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1; 2490 struct cvmx_ipd_portx_bp_page_cnt3_s cn66xx; 2491 struct cvmx_ipd_portx_bp_page_cnt3_s cnf71xx; 2492}; 2493typedef union cvmx_ipd_portx_bp_page_cnt3 cvmx_ipd_portx_bp_page_cnt3_t; 2494 2495/** 2496 * cvmx_ipd_port_bp_counters2_pair# 2497 * 2498 * IPD_PORT_BP_COUNTERS2_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 2499 * See also IPD_PORT_BP_COUNTERS_PAIRX 2500 * See also IPD_PORT_BP_COUNTERS3_PAIRX 2501 * 0x388-0x3a0 2502 */ 2503union cvmx_ipd_port_bp_counters2_pairx { 2504 uint64_t u64; 2505 struct cvmx_ipd_port_bp_counters2_pairx_s { 2506#ifdef __BIG_ENDIAN_BITFIELD 2507 uint64_t reserved_25_63 : 39; 2508 uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 2509#else 2510 uint64_t cnt_val : 25; 2511 uint64_t reserved_25_63 : 39; 2512#endif 2513 } s; 2514 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx; 2515 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; 2516 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; 2517 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; 2518 struct cvmx_ipd_port_bp_counters2_pairx_s cn61xx; 2519 struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx; 2520 struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1; 2521 struct cvmx_ipd_port_bp_counters2_pairx_s cn66xx; 2522 struct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx; 2523}; 2524typedef union cvmx_ipd_port_bp_counters2_pairx cvmx_ipd_port_bp_counters2_pairx_t; 2525 2526/** 2527 * cvmx_ipd_port_bp_counters3_pair# 2528 * 2529 * IPD_PORT_BP_COUNTERS3_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 2530 * See also IPD_PORT_BP_COUNTERS_PAIRX 2531 * See also IPD_PORT_BP_COUNTERS2_PAIRX 2532 * 0x3b0-0x3c8 2533 */ 2534union cvmx_ipd_port_bp_counters3_pairx { 2535 uint64_t u64; 2536 struct cvmx_ipd_port_bp_counters3_pairx_s { 2537#ifdef __BIG_ENDIAN_BITFIELD 2538 uint64_t reserved_25_63 : 39; 2539 uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 2540#else 2541 uint64_t cnt_val : 25; 2542 uint64_t reserved_25_63 : 39; 2543#endif 2544 } s; 2545 struct cvmx_ipd_port_bp_counters3_pairx_s cn61xx; 2546 struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx; 2547 struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1; 2548 struct cvmx_ipd_port_bp_counters3_pairx_s cn66xx; 2549 struct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx; 2550}; 2551typedef union cvmx_ipd_port_bp_counters3_pairx cvmx_ipd_port_bp_counters3_pairx_t; 2552 2553/** 2554 * cvmx_ipd_port_bp_counters4_pair# 2555 * 2556 * IPD_PORT_BP_COUNTERS4_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 2557 * See also IPD_PORT_BP_COUNTERS_PAIRX 2558 * See also IPD_PORT_BP_COUNTERS2_PAIRX 2559 * 0x410-0x3c8 2560 */ 2561union cvmx_ipd_port_bp_counters4_pairx { 2562 uint64_t u64; 2563 struct cvmx_ipd_port_bp_counters4_pairx_s { 2564#ifdef __BIG_ENDIAN_BITFIELD 2565 uint64_t reserved_25_63 : 39; 2566 uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 2567#else 2568 uint64_t cnt_val : 25; 2569 uint64_t reserved_25_63 : 39; 2570#endif 2571 } s; 2572 struct cvmx_ipd_port_bp_counters4_pairx_s cn61xx; 2573 struct cvmx_ipd_port_bp_counters4_pairx_s cn66xx; 2574 struct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx; 2575}; 2576typedef union cvmx_ipd_port_bp_counters4_pairx cvmx_ipd_port_bp_counters4_pairx_t; 2577 2578/** 2579 * cvmx_ipd_port_bp_counters_pair# 2580 * 2581 * IPD_PORT_BP_COUNTERS_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 2582 * See also IPD_PORT_BP_COUNTERS2_PAIRX 2583 * See also IPD_PORT_BP_COUNTERS3_PAIRX 2584 * 0x1b8-0x2d0 2585 */ 2586union cvmx_ipd_port_bp_counters_pairx { 2587 uint64_t u64; 2588 struct cvmx_ipd_port_bp_counters_pairx_s { 2589#ifdef __BIG_ENDIAN_BITFIELD 2590 uint64_t reserved_25_63 : 39; 2591 uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 2592#else 2593 uint64_t cnt_val : 25; 2594 uint64_t reserved_25_63 : 39; 2595#endif 2596 } s; 2597 struct cvmx_ipd_port_bp_counters_pairx_s cn30xx; 2598 struct cvmx_ipd_port_bp_counters_pairx_s cn31xx; 2599 struct cvmx_ipd_port_bp_counters_pairx_s cn38xx; 2600 struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2; 2601 struct cvmx_ipd_port_bp_counters_pairx_s cn50xx; 2602 struct cvmx_ipd_port_bp_counters_pairx_s cn52xx; 2603 struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1; 2604 struct cvmx_ipd_port_bp_counters_pairx_s cn56xx; 2605 struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; 2606 struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; 2607 struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; 2608 struct cvmx_ipd_port_bp_counters_pairx_s cn61xx; 2609 struct cvmx_ipd_port_bp_counters_pairx_s cn63xx; 2610 struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1; 2611 struct cvmx_ipd_port_bp_counters_pairx_s cn66xx; 2612 struct cvmx_ipd_port_bp_counters_pairx_s cnf71xx; 2613}; 2614typedef union cvmx_ipd_port_bp_counters_pairx cvmx_ipd_port_bp_counters_pairx_t; 2615 2616/** 2617 * cvmx_ipd_port_ptr_fifo_ctl 2618 * 2619 * IPD_PORT_PTR_FIFO_CTL = IPD's Reasm-Id Pointer FIFO Control 2620 * 2621 * Allows reading of the Page-Pointers stored in the IPD's Reasm-Id Fifo. 2622 */ 2623union cvmx_ipd_port_ptr_fifo_ctl { 2624 uint64_t u64; 2625 struct cvmx_ipd_port_ptr_fifo_ctl_s { 2626#ifdef __BIG_ENDIAN_BITFIELD 2627 uint64_t reserved_48_63 : 16; 2628 uint64_t ptr : 33; /**< The output of the reasm-id-ptr-fifo. */ 2629 uint64_t max_pkt : 7; /**< Maximum number of Packet-Pointers that are in 2630 in the FIFO. */ 2631 uint64_t cena : 1; /**< Active low Chip Enable to the read the 2632 pwp_fifo. This bit also controls the MUX-select 2633 that steers [RADDR] to the pwp_fifo. 2634 *WARNING - Setting this field to '0' will allow 2635 reading of the memories thorugh the PTR field, 2636 but will cause unpredictable operation of the IPD 2637 under normal operation. */ 2638 uint64_t raddr : 7; /**< Sets the address to read from in the reasm-id 2639 fifo in the IPD. This FIFO holds Packet-Pointers 2640 to be used for packet data storage. */ 2641#else 2642 uint64_t raddr : 7; 2643 uint64_t cena : 1; 2644 uint64_t max_pkt : 7; 2645 uint64_t ptr : 33; 2646 uint64_t reserved_48_63 : 16; 2647#endif 2648 } s; 2649 struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xx; 2650 struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xxp1; 2651}; 2652typedef union cvmx_ipd_port_ptr_fifo_ctl cvmx_ipd_port_ptr_fifo_ctl_t; 2653 2654/** 2655 * cvmx_ipd_port_qos_#_cnt 2656 * 2657 * IPD_PORT_QOS_X_CNT = IPD PortX QOS-0 Count 2658 * 2659 * A counter per port/qos. Counter are originzed in sequence where the first 8 counter (0-7) belong to Port-0 2660 * QOS 0-7 respectively followed by port 1 at (8-15), etc 2661 * Ports 0-3, 32-43 2662 */ 2663union cvmx_ipd_port_qos_x_cnt { 2664 uint64_t u64; 2665 struct cvmx_ipd_port_qos_x_cnt_s { 2666#ifdef __BIG_ENDIAN_BITFIELD 2667 uint64_t wmark : 32; /**< When the field CNT after being modified is equal to 2668 or crosses this value (i.e. value was greater than 2669 then becomes less then, or value was less than and 2670 becomes greater than) the corresponding bit in 2671 IPD_PORT_QOS_INTX is set. */ 2672 uint64_t cnt : 32; /**< The packet related count that is incremented as 2673 specified by IPD_SUB_PORT_QOS_CNT. */ 2674#else 2675 uint64_t cnt : 32; 2676 uint64_t wmark : 32; 2677#endif 2678 } s; 2679 struct cvmx_ipd_port_qos_x_cnt_s cn52xx; 2680 struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; 2681 struct cvmx_ipd_port_qos_x_cnt_s cn56xx; 2682 struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; 2683 struct cvmx_ipd_port_qos_x_cnt_s cn61xx; 2684 struct cvmx_ipd_port_qos_x_cnt_s cn63xx; 2685 struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1; 2686 struct cvmx_ipd_port_qos_x_cnt_s cn66xx; 2687 struct cvmx_ipd_port_qos_x_cnt_s cn68xx; 2688 struct cvmx_ipd_port_qos_x_cnt_s cn68xxp1; 2689 struct cvmx_ipd_port_qos_x_cnt_s cnf71xx; 2690}; 2691typedef union cvmx_ipd_port_qos_x_cnt cvmx_ipd_port_qos_x_cnt_t; 2692 2693/** 2694 * cvmx_ipd_port_qos_int# 2695 * 2696 * IPD_PORT_QOS_INTX = IPD PORT-QOS Interrupt 2697 * 2698 * See the description for IPD_PORT_QOS_X_CNT 2699 * 2700 * 0=P0-7; 1=P8-15; 2=P16-23; 3=P24-31; 4=P32-39; 5=P40-47; 6=P48-55; 7=P56-63 2701 * 2702 * Only ports used are: P0-3, P32-39, and P40-47. Therefore only IPD_PORT_QOS_INT0, IPD_PORT_QOS_INT4, 2703 * and IPD_PORT_QOS_INT5 exist and, furthermore: <63:32> of IPD_PORT_QOS_INT0, 2704 * are reserved. 2705 */ 2706union cvmx_ipd_port_qos_intx { 2707 uint64_t u64; 2708 struct cvmx_ipd_port_qos_intx_s { 2709#ifdef __BIG_ENDIAN_BITFIELD 2710 uint64_t intr : 64; /**< Interrupt bits. */ 2711#else 2712 uint64_t intr : 64; 2713#endif 2714 } s; 2715 struct cvmx_ipd_port_qos_intx_s cn52xx; 2716 struct cvmx_ipd_port_qos_intx_s cn52xxp1; 2717 struct cvmx_ipd_port_qos_intx_s cn56xx; 2718 struct cvmx_ipd_port_qos_intx_s cn56xxp1; 2719 struct cvmx_ipd_port_qos_intx_s cn61xx; 2720 struct cvmx_ipd_port_qos_intx_s cn63xx; 2721 struct cvmx_ipd_port_qos_intx_s cn63xxp1; 2722 struct cvmx_ipd_port_qos_intx_s cn66xx; 2723 struct cvmx_ipd_port_qos_intx_s cn68xx; 2724 struct cvmx_ipd_port_qos_intx_s cn68xxp1; 2725 struct cvmx_ipd_port_qos_intx_s cnf71xx; 2726}; 2727typedef union cvmx_ipd_port_qos_intx cvmx_ipd_port_qos_intx_t; 2728 2729/** 2730 * cvmx_ipd_port_qos_int_enb# 2731 * 2732 * IPD_PORT_QOS_INT_ENBX = IPD PORT-QOS Interrupt Enable 2733 * 2734 * When the IPD_PORT_QOS_INTX[\#] is '1' and IPD_PORT_QOS_INT_ENBX[\#] is '1' a interrupt will be generated. 2735 */ 2736union cvmx_ipd_port_qos_int_enbx { 2737 uint64_t u64; 2738 struct cvmx_ipd_port_qos_int_enbx_s { 2739#ifdef __BIG_ENDIAN_BITFIELD 2740 uint64_t enb : 64; /**< Enable bits. */ 2741#else 2742 uint64_t enb : 64; 2743#endif 2744 } s; 2745 struct cvmx_ipd_port_qos_int_enbx_s cn52xx; 2746 struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; 2747 struct cvmx_ipd_port_qos_int_enbx_s cn56xx; 2748 struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; 2749 struct cvmx_ipd_port_qos_int_enbx_s cn61xx; 2750 struct cvmx_ipd_port_qos_int_enbx_s cn63xx; 2751 struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1; 2752 struct cvmx_ipd_port_qos_int_enbx_s cn66xx; 2753 struct cvmx_ipd_port_qos_int_enbx_s cn68xx; 2754 struct cvmx_ipd_port_qos_int_enbx_s cn68xxp1; 2755 struct cvmx_ipd_port_qos_int_enbx_s cnf71xx; 2756}; 2757typedef union cvmx_ipd_port_qos_int_enbx cvmx_ipd_port_qos_int_enbx_t; 2758 2759/** 2760 * cvmx_ipd_port_sop# 2761 * 2762 * IPD_PORT_SOP = IPD Reasm-Id SOP 2763 * 2764 * Set when a SOP is detected on a reasm-num. Where the reasm-num value set the bit vector of this register. 2765 */ 2766union cvmx_ipd_port_sopx { 2767 uint64_t u64; 2768 struct cvmx_ipd_port_sopx_s { 2769#ifdef __BIG_ENDIAN_BITFIELD 2770 uint64_t sop : 64; /**< When set '1' a SOP was detected on a reasm-num, 2771 When clear '0' no SOP was yet received or an EOP 2772 was received on the reasm-num. 2773 IPD only supports 63 reasm-nums, so bit [63] 2774 should never be set. */ 2775#else 2776 uint64_t sop : 64; 2777#endif 2778 } s; 2779 struct cvmx_ipd_port_sopx_s cn68xx; 2780 struct cvmx_ipd_port_sopx_s cn68xxp1; 2781}; 2782typedef union cvmx_ipd_port_sopx cvmx_ipd_port_sopx_t; 2783 2784/** 2785 * cvmx_ipd_prc_hold_ptr_fifo_ctl 2786 * 2787 * IPD_PRC_HOLD_PTR_FIFO_CTL = IPD's PRC Holding Pointer FIFO Control 2788 * 2789 * Allows reading of the Page-Pointers stored in the IPD's PRC Holding Fifo. 2790 */ 2791union cvmx_ipd_prc_hold_ptr_fifo_ctl { 2792 uint64_t u64; 2793 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { 2794#ifdef __BIG_ENDIAN_BITFIELD 2795 uint64_t reserved_39_63 : 25; 2796 uint64_t max_pkt : 3; /**< Maximum number of Packet-Pointers that COULD be 2797 in the FIFO. */ 2798 uint64_t praddr : 3; /**< Present Packet-Pointer read address. */ 2799 uint64_t ptr : 29; /**< The output of the prc-holding-fifo. */ 2800 uint64_t cena : 1; /**< Active low Chip Enable that controls the 2801 MUX-select that steers [RADDR] to the fifo. 2802 *WARNING - Setting this field to '0' will allow 2803 reading of the memories thorugh the PTR field, 2804 but will cause unpredictable operation of the IPD 2805 under normal operation. */ 2806 uint64_t raddr : 3; /**< Sets the address to read from in the holding. 2807 fifo in the PRC. This FIFO holds Packet-Pointers 2808 to be used for packet data storage. */ 2809#else 2810 uint64_t raddr : 3; 2811 uint64_t cena : 1; 2812 uint64_t ptr : 29; 2813 uint64_t praddr : 3; 2814 uint64_t max_pkt : 3; 2815 uint64_t reserved_39_63 : 25; 2816#endif 2817 } s; 2818 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx; 2819 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx; 2820 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx; 2821 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx; 2822 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx; 2823 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1; 2824 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx; 2825 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; 2826 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; 2827 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; 2828 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx; 2829 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx; 2830 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1; 2831 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx; 2832 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx; 2833}; 2834typedef union cvmx_ipd_prc_hold_ptr_fifo_ctl cvmx_ipd_prc_hold_ptr_fifo_ctl_t; 2835 2836/** 2837 * cvmx_ipd_prc_port_ptr_fifo_ctl 2838 * 2839 * IPD_PRC_PORT_PTR_FIFO_CTL = IPD's PRC PORT Pointer FIFO Control 2840 * 2841 * Allows reading of the Page-Pointers stored in the IPD's PRC PORT Fifo. 2842 */ 2843union cvmx_ipd_prc_port_ptr_fifo_ctl { 2844 uint64_t u64; 2845 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { 2846#ifdef __BIG_ENDIAN_BITFIELD 2847 uint64_t reserved_44_63 : 20; 2848 uint64_t max_pkt : 7; /**< Maximum number of Packet-Pointers that are in 2849 in the FIFO. */ 2850 uint64_t ptr : 29; /**< The output of the prc-port-ptr-fifo. */ 2851 uint64_t cena : 1; /**< Active low Chip Enable to the read port of the 2852 pwp_fifo. This bit also controls the MUX-select 2853 that steers [RADDR] to the pwp_fifo. 2854 *WARNING - Setting this field to '0' will allow 2855 reading of the memories thorugh the PTR field, 2856 but will cause unpredictable operation of the IPD 2857 under normal operation. */ 2858 uint64_t raddr : 7; /**< Sets the address to read from in the port 2859 fifo in the PRC. This FIFO holds Packet-Pointers 2860 to be used for packet data storage. */ 2861#else 2862 uint64_t raddr : 7; 2863 uint64_t cena : 1; 2864 uint64_t ptr : 29; 2865 uint64_t max_pkt : 7; 2866 uint64_t reserved_44_63 : 20; 2867#endif 2868 } s; 2869 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx; 2870 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx; 2871 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx; 2872 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx; 2873 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx; 2874 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1; 2875 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx; 2876 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; 2877 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; 2878 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; 2879 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx; 2880 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx; 2881 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1; 2882 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx; 2883 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx; 2884}; 2885typedef union cvmx_ipd_prc_port_ptr_fifo_ctl cvmx_ipd_prc_port_ptr_fifo_ctl_t; 2886 2887/** 2888 * cvmx_ipd_ptr_count 2889 * 2890 * IPD_PTR_COUNT = IPD Page Pointer Count 2891 * 2892 * Shows the number of WQE and Packet Page Pointers stored in the IPD. 2893 */ 2894union cvmx_ipd_ptr_count { 2895 uint64_t u64; 2896 struct cvmx_ipd_ptr_count_s { 2897#ifdef __BIG_ENDIAN_BITFIELD 2898 uint64_t reserved_19_63 : 45; 2899 uint64_t pktv_cnt : 1; /**< PKT Ptr Valid. */ 2900 uint64_t wqev_cnt : 1; /**< WQE Ptr Valid. This value is '1' when a WQE 2901 is being for use by the IPD. The value of this 2902 field should be added to tha value of the 2903 WQE_PCNT field, of this register, for a total 2904 count of the WQE Page Pointers being held by IPD. 2905 When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 2906 represents a Packet-Pointer NOT a WQE pointer. */ 2907 uint64_t pfif_cnt : 3; /**< See PKT_PCNT. */ 2908 uint64_t pkt_pcnt : 7; /**< This value plus PFIF_CNT plus 2909 IPD_PRC_PORT_PTR_FIFO_CTL[MAX_PKT] is the number 2910 of PKT Page Pointers in IPD. */ 2911 uint64_t wqe_pcnt : 7; /**< Number of page pointers for WQE storage that are 2912 buffered in the IPD. The total count is the value 2913 of this buffer plus the field [WQEV_CNT]. For 2914 PASS-1 (which does not have the WQEV_CNT field) 2915 when the value of this register is '0' there still 2916 may be 1 pointer being held by IPD. */ 2917#else 2918 uint64_t wqe_pcnt : 7; 2919 uint64_t pkt_pcnt : 7; 2920 uint64_t pfif_cnt : 3; 2921 uint64_t wqev_cnt : 1; 2922 uint64_t pktv_cnt : 1; 2923 uint64_t reserved_19_63 : 45; 2924#endif 2925 } s; 2926 struct cvmx_ipd_ptr_count_s cn30xx; 2927 struct cvmx_ipd_ptr_count_s cn31xx; 2928 struct cvmx_ipd_ptr_count_s cn38xx; 2929 struct cvmx_ipd_ptr_count_s cn38xxp2; 2930 struct cvmx_ipd_ptr_count_s cn50xx; 2931 struct cvmx_ipd_ptr_count_s cn52xx; 2932 struct cvmx_ipd_ptr_count_s cn52xxp1; 2933 struct cvmx_ipd_ptr_count_s cn56xx; 2934 struct cvmx_ipd_ptr_count_s cn56xxp1; 2935 struct cvmx_ipd_ptr_count_s cn58xx; 2936 struct cvmx_ipd_ptr_count_s cn58xxp1; 2937 struct cvmx_ipd_ptr_count_s cn61xx; 2938 struct cvmx_ipd_ptr_count_s cn63xx; 2939 struct cvmx_ipd_ptr_count_s cn63xxp1; 2940 struct cvmx_ipd_ptr_count_s cn66xx; 2941 struct cvmx_ipd_ptr_count_s cn68xx; 2942 struct cvmx_ipd_ptr_count_s cn68xxp1; 2943 struct cvmx_ipd_ptr_count_s cnf71xx; 2944}; 2945typedef union cvmx_ipd_ptr_count cvmx_ipd_ptr_count_t; 2946 2947/** 2948 * cvmx_ipd_pwp_ptr_fifo_ctl 2949 * 2950 * IPD_PWP_PTR_FIFO_CTL = IPD's PWP Pointer FIFO Control 2951 * 2952 * Allows reading of the Page-Pointers stored in the IPD's PWP Fifo. 2953 */ 2954union cvmx_ipd_pwp_ptr_fifo_ctl { 2955 uint64_t u64; 2956 struct cvmx_ipd_pwp_ptr_fifo_ctl_s { 2957#ifdef __BIG_ENDIAN_BITFIELD 2958 uint64_t reserved_61_63 : 3; 2959 uint64_t max_cnts : 7; /**< Maximum number of Packet-Pointers or WQE-Pointers 2960 that COULD be in the FIFO. 2961 When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 2962 only represents the Max number of Packet-Pointers, 2963 WQE-Pointers are not used in this mode. */ 2964 uint64_t wraddr : 8; /**< Present FIFO WQE Read address. */ 2965 uint64_t praddr : 8; /**< Present FIFO Packet Read address. */ 2966 uint64_t ptr : 29; /**< The output of the pwp_fifo. */ 2967 uint64_t cena : 1; /**< Active low Chip Enable to the read port of the 2968 pwp_fifo. This bit also controls the MUX-select 2969 that steers [RADDR] to the pwp_fifo. 2970 *WARNING - Setting this field to '0' will allow 2971 reading of the memories thorugh the PTR field, 2972 but will cause unpredictable operation of the IPD 2973 under normal operation. */ 2974 uint64_t raddr : 8; /**< Sets the address to read from in the pwp_fifo. 2975 Addresses 0 through 63 contain Packet-Pointers and 2976 addresses 64 through 127 contain WQE-Pointers. 2977 When IPD_CTL_STATUS[NO_WPTR] is set '1' addresses 2978 64 through 127 are not valid. */ 2979#else 2980 uint64_t raddr : 8; 2981 uint64_t cena : 1; 2982 uint64_t ptr : 29; 2983 uint64_t praddr : 8; 2984 uint64_t wraddr : 8; 2985 uint64_t max_cnts : 7; 2986 uint64_t reserved_61_63 : 3; 2987#endif 2988 } s; 2989 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx; 2990 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx; 2991 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx; 2992 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx; 2993 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx; 2994 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1; 2995 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx; 2996 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; 2997 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; 2998 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; 2999 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn61xx; 3000 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx; 3001 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1; 3002 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn66xx; 3003 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cnf71xx; 3004}; 3005typedef union cvmx_ipd_pwp_ptr_fifo_ctl cvmx_ipd_pwp_ptr_fifo_ctl_t; 3006 3007/** 3008 * cvmx_ipd_qos#_red_marks 3009 * 3010 * IPD_QOS0_RED_MARKS = IPD QOS 0 Marks Red High Low 3011 * 3012 * Set the pass-drop marks for qos level. 3013 */ 3014union cvmx_ipd_qosx_red_marks { 3015 uint64_t u64; 3016 struct cvmx_ipd_qosx_red_marks_s { 3017#ifdef __BIG_ENDIAN_BITFIELD 3018 uint64_t drop : 32; /**< Packets will be dropped when the average value of 3019 IPD_QUE0_FREE_PAGE_CNT is equal to or less than 3020 this value. */ 3021 uint64_t pass : 32; /**< Packets will be passed when the average value of 3022 IPD_QUE0_FREE_PAGE_CNT is larger than this value. */ 3023#else 3024 uint64_t pass : 32; 3025 uint64_t drop : 32; 3026#endif 3027 } s; 3028 struct cvmx_ipd_qosx_red_marks_s cn30xx; 3029 struct cvmx_ipd_qosx_red_marks_s cn31xx; 3030 struct cvmx_ipd_qosx_red_marks_s cn38xx; 3031 struct cvmx_ipd_qosx_red_marks_s cn38xxp2; 3032 struct cvmx_ipd_qosx_red_marks_s cn50xx; 3033 struct cvmx_ipd_qosx_red_marks_s cn52xx; 3034 struct cvmx_ipd_qosx_red_marks_s cn52xxp1; 3035 struct cvmx_ipd_qosx_red_marks_s cn56xx; 3036 struct cvmx_ipd_qosx_red_marks_s cn56xxp1; 3037 struct cvmx_ipd_qosx_red_marks_s cn58xx; 3038 struct cvmx_ipd_qosx_red_marks_s cn58xxp1; 3039 struct cvmx_ipd_qosx_red_marks_s cn61xx; 3040 struct cvmx_ipd_qosx_red_marks_s cn63xx; 3041 struct cvmx_ipd_qosx_red_marks_s cn63xxp1; 3042 struct cvmx_ipd_qosx_red_marks_s cn66xx; 3043 struct cvmx_ipd_qosx_red_marks_s cn68xx; 3044 struct cvmx_ipd_qosx_red_marks_s cn68xxp1; 3045 struct cvmx_ipd_qosx_red_marks_s cnf71xx; 3046}; 3047typedef union cvmx_ipd_qosx_red_marks cvmx_ipd_qosx_red_marks_t; 3048 3049/** 3050 * cvmx_ipd_que0_free_page_cnt 3051 * 3052 * IPD_QUE0_FREE_PAGE_CNT = IPD Queue0 Free Page Count 3053 * 3054 * Number of Free-Page Pointer that are available for use in the FPA for Queue-0. 3055 */ 3056union cvmx_ipd_que0_free_page_cnt { 3057 uint64_t u64; 3058 struct cvmx_ipd_que0_free_page_cnt_s { 3059#ifdef __BIG_ENDIAN_BITFIELD 3060 uint64_t reserved_32_63 : 32; 3061 uint64_t q0_pcnt : 32; /**< Number of Queue-0 Page Pointers Available. */ 3062#else 3063 uint64_t q0_pcnt : 32; 3064 uint64_t reserved_32_63 : 32; 3065#endif 3066 } s; 3067 struct cvmx_ipd_que0_free_page_cnt_s cn30xx; 3068 struct cvmx_ipd_que0_free_page_cnt_s cn31xx; 3069 struct cvmx_ipd_que0_free_page_cnt_s cn38xx; 3070 struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2; 3071 struct cvmx_ipd_que0_free_page_cnt_s cn50xx; 3072 struct cvmx_ipd_que0_free_page_cnt_s cn52xx; 3073 struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1; 3074 struct cvmx_ipd_que0_free_page_cnt_s cn56xx; 3075 struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; 3076 struct cvmx_ipd_que0_free_page_cnt_s cn58xx; 3077 struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; 3078 struct cvmx_ipd_que0_free_page_cnt_s cn61xx; 3079 struct cvmx_ipd_que0_free_page_cnt_s cn63xx; 3080 struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1; 3081 struct cvmx_ipd_que0_free_page_cnt_s cn66xx; 3082 struct cvmx_ipd_que0_free_page_cnt_s cn68xx; 3083 struct cvmx_ipd_que0_free_page_cnt_s cn68xxp1; 3084 struct cvmx_ipd_que0_free_page_cnt_s cnf71xx; 3085}; 3086typedef union cvmx_ipd_que0_free_page_cnt cvmx_ipd_que0_free_page_cnt_t; 3087 3088/** 3089 * cvmx_ipd_red_bpid_enable# 3090 * 3091 * IPD_RED_BPID_ENABLE = IPD RED BPID Enable 3092 * 3093 * Set the pass-drop marks for qos level. 3094 */ 3095union cvmx_ipd_red_bpid_enablex { 3096 uint64_t u64; 3097 struct cvmx_ipd_red_bpid_enablex_s { 3098#ifdef __BIG_ENDIAN_BITFIELD 3099 uint64_t prt_enb : 64; /**< The bit position will enable the corresponding 3100 BPIDs ability to have packets dropped by RED 3101 probability. */ 3102#else 3103 uint64_t prt_enb : 64; 3104#endif 3105 } s; 3106 struct cvmx_ipd_red_bpid_enablex_s cn68xx; 3107 struct cvmx_ipd_red_bpid_enablex_s cn68xxp1; 3108}; 3109typedef union cvmx_ipd_red_bpid_enablex cvmx_ipd_red_bpid_enablex_t; 3110 3111/** 3112 * cvmx_ipd_red_delay 3113 * 3114 * IPD_RED_DELAY = IPD RED BPID Enable 3115 * 3116 * Set the pass-drop marks for qos level. 3117 */ 3118union cvmx_ipd_red_delay { 3119 uint64_t u64; 3120 struct cvmx_ipd_red_delay_s { 3121#ifdef __BIG_ENDIAN_BITFIELD 3122 uint64_t reserved_28_63 : 36; 3123 uint64_t prb_dly : 14; /**< Number (core clocks periods + 68) * 8 to wait 3124 before calculating the new packet drop 3125 probability for each QOS level. */ 3126 uint64_t avg_dly : 14; /**< Number (core clocks periods + 10) * 8 to wait 3127 before calculating the moving average for each 3128 QOS level. 3129 Larger AVG_DLY values cause the moving averages 3130 of ALL QOS levels to track changes in the actual 3131 free space more slowly. Smaller NEW_CON (and 3132 larger AVG_CON) values can have a similar effect, 3133 but only affect an individual QOS level, rather 3134 than all. */ 3135#else 3136 uint64_t avg_dly : 14; 3137 uint64_t prb_dly : 14; 3138 uint64_t reserved_28_63 : 36; 3139#endif 3140 } s; 3141 struct cvmx_ipd_red_delay_s cn68xx; 3142 struct cvmx_ipd_red_delay_s cn68xxp1; 3143}; 3144typedef union cvmx_ipd_red_delay cvmx_ipd_red_delay_t; 3145 3146/** 3147 * cvmx_ipd_red_port_enable 3148 * 3149 * IPD_RED_PORT_ENABLE = IPD RED Port Enable 3150 * 3151 * Set the pass-drop marks for qos level. 3152 */ 3153union cvmx_ipd_red_port_enable { 3154 uint64_t u64; 3155 struct cvmx_ipd_red_port_enable_s { 3156#ifdef __BIG_ENDIAN_BITFIELD 3157 uint64_t prb_dly : 14; /**< Number (core clocks periods + 68) * 8 to wait 3158 before calculating the new packet drop 3159 probability for each QOS level. */ 3160 uint64_t avg_dly : 14; /**< Number (core clocks periods + 10) * 8 to wait 3161 before calculating the moving average for each 3162 QOS level. 3163 Larger AVG_DLY values cause the moving averages 3164 of ALL QOS levels to track changes in the actual 3165 free space more slowly. Smaller NEW_CON (and 3166 larger AVG_CON) values can have a similar effect, 3167 but only affect an individual QOS level, rather 3168 than all. */ 3169 uint64_t prt_enb : 36; /**< The bit position will enable the corresponding 3170 Ports ability to have packets dropped by RED 3171 probability. */ 3172#else 3173 uint64_t prt_enb : 36; 3174 uint64_t avg_dly : 14; 3175 uint64_t prb_dly : 14; 3176#endif 3177 } s; 3178 struct cvmx_ipd_red_port_enable_s cn30xx; 3179 struct cvmx_ipd_red_port_enable_s cn31xx; 3180 struct cvmx_ipd_red_port_enable_s cn38xx; 3181 struct cvmx_ipd_red_port_enable_s cn38xxp2; 3182 struct cvmx_ipd_red_port_enable_s cn50xx; 3183 struct cvmx_ipd_red_port_enable_s cn52xx; 3184 struct cvmx_ipd_red_port_enable_s cn52xxp1; 3185 struct cvmx_ipd_red_port_enable_s cn56xx; 3186 struct cvmx_ipd_red_port_enable_s cn56xxp1; 3187 struct cvmx_ipd_red_port_enable_s cn58xx; 3188 struct cvmx_ipd_red_port_enable_s cn58xxp1; 3189 struct cvmx_ipd_red_port_enable_s cn61xx; 3190 struct cvmx_ipd_red_port_enable_s cn63xx; 3191 struct cvmx_ipd_red_port_enable_s cn63xxp1; 3192 struct cvmx_ipd_red_port_enable_s cn66xx; 3193 struct cvmx_ipd_red_port_enable_s cnf71xx; 3194}; 3195typedef union cvmx_ipd_red_port_enable cvmx_ipd_red_port_enable_t; 3196 3197/** 3198 * cvmx_ipd_red_port_enable2 3199 * 3200 * IPD_RED_PORT_ENABLE2 = IPD RED Port Enable2 3201 * 3202 * Set the pass-drop marks for qos level. 3203 */ 3204union cvmx_ipd_red_port_enable2 { 3205 uint64_t u64; 3206 struct cvmx_ipd_red_port_enable2_s { 3207#ifdef __BIG_ENDIAN_BITFIELD 3208 uint64_t reserved_12_63 : 52; 3209 uint64_t prt_enb : 12; /**< Bits 11-0 corresponds to ports 47-36. These bits 3210 have the same meaning as the PRT_ENB field of 3211 IPD_RED_PORT_ENABLE. */ 3212#else 3213 uint64_t prt_enb : 12; 3214 uint64_t reserved_12_63 : 52; 3215#endif 3216 } s; 3217 struct cvmx_ipd_red_port_enable2_cn52xx { 3218#ifdef __BIG_ENDIAN_BITFIELD 3219 uint64_t reserved_4_63 : 60; 3220 uint64_t prt_enb : 4; /**< Bits 3-0 cooresponds to ports 39-36. These bits 3221 have the same meaning as the PRT_ENB field of 3222 IPD_RED_PORT_ENABLE. */ 3223#else 3224 uint64_t prt_enb : 4; 3225 uint64_t reserved_4_63 : 60; 3226#endif 3227 } cn52xx; 3228 struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1; 3229 struct cvmx_ipd_red_port_enable2_cn52xx cn56xx; 3230 struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1; 3231 struct cvmx_ipd_red_port_enable2_s cn61xx; 3232 struct cvmx_ipd_red_port_enable2_cn63xx { 3233#ifdef __BIG_ENDIAN_BITFIELD 3234 uint64_t reserved_8_63 : 56; 3235 uint64_t prt_enb : 8; /**< Bits 7-0 corresponds to ports 43-36. These bits 3236 have the same meaning as the PRT_ENB field of 3237 IPD_RED_PORT_ENABLE. */ 3238#else 3239 uint64_t prt_enb : 8; 3240 uint64_t reserved_8_63 : 56; 3241#endif 3242 } cn63xx; 3243 struct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1; 3244 struct cvmx_ipd_red_port_enable2_s cn66xx; 3245 struct cvmx_ipd_red_port_enable2_s cnf71xx; 3246}; 3247typedef union cvmx_ipd_red_port_enable2 cvmx_ipd_red_port_enable2_t; 3248 3249/** 3250 * cvmx_ipd_red_que#_param 3251 * 3252 * IPD_RED_QUE0_PARAM = IPD RED Queue-0 Parameters 3253 * 3254 * Value control the Passing and Dropping of packets by the red engine for QOS Level-0. 3255 */ 3256union cvmx_ipd_red_quex_param { 3257 uint64_t u64; 3258 struct cvmx_ipd_red_quex_param_s { 3259#ifdef __BIG_ENDIAN_BITFIELD 3260 uint64_t reserved_49_63 : 15; 3261 uint64_t use_pcnt : 1; /**< When set '1' red will use the actual Packet-Page 3262 Count in place of the Average for RED calculations. */ 3263 uint64_t new_con : 8; /**< This value is used control how much of the present 3264 Actual Queue Size is used to calculate the new 3265 Average Queue Size. The value is a number from 0 3266 256, which represents NEW_CON/256 of the Actual 3267 Queue Size that will be used in the calculation. 3268 The number in this field plus the value of 3269 AVG_CON must be equal to 256. 3270 Larger AVG_DLY values cause the moving averages 3271 of ALL QOS levels to track changes in the actual 3272 free space more slowly. Smaller NEW_CON (and 3273 larger AVG_CON) values can have a similar effect, 3274 but only affect an individual QOS level, rather 3275 than all. */ 3276 uint64_t avg_con : 8; /**< This value is used control how much of the present 3277 Average Queue Size is used to calculate the new 3278 Average Queue Size. The value is a number from 0 3279 256, which represents AVG_CON/256 of the Average 3280 Queue Size that will be used in the calculation. 3281 The number in this field plus the value of 3282 NEW_CON must be equal to 256. 3283 Larger AVG_DLY values cause the moving averages 3284 of ALL QOS levels to track changes in the actual 3285 free space more slowly. Smaller NEW_CON (and 3286 larger AVG_CON) values can have a similar effect, 3287 but only affect an individual QOS level, rather 3288 than all. */ 3289 uint64_t prb_con : 32; /**< Used in computing the probability of a packet being 3290 passed or drop by the WRED engine. The field is 3291 calculated to be (255 * 2^24)/(PASS-DROP). Where 3292 PASS and DROP are the field from the 3293 IPD_QOS0_RED_MARKS CSR. */ 3294#else 3295 uint64_t prb_con : 32; 3296 uint64_t avg_con : 8; 3297 uint64_t new_con : 8; 3298 uint64_t use_pcnt : 1; 3299 uint64_t reserved_49_63 : 15; 3300#endif 3301 } s; 3302 struct cvmx_ipd_red_quex_param_s cn30xx; 3303 struct cvmx_ipd_red_quex_param_s cn31xx; 3304 struct cvmx_ipd_red_quex_param_s cn38xx; 3305 struct cvmx_ipd_red_quex_param_s cn38xxp2; 3306 struct cvmx_ipd_red_quex_param_s cn50xx; 3307 struct cvmx_ipd_red_quex_param_s cn52xx; 3308 struct cvmx_ipd_red_quex_param_s cn52xxp1; 3309 struct cvmx_ipd_red_quex_param_s cn56xx; 3310 struct cvmx_ipd_red_quex_param_s cn56xxp1; 3311 struct cvmx_ipd_red_quex_param_s cn58xx; 3312 struct cvmx_ipd_red_quex_param_s cn58xxp1; 3313 struct cvmx_ipd_red_quex_param_s cn61xx; 3314 struct cvmx_ipd_red_quex_param_s cn63xx; 3315 struct cvmx_ipd_red_quex_param_s cn63xxp1; 3316 struct cvmx_ipd_red_quex_param_s cn66xx; 3317 struct cvmx_ipd_red_quex_param_s cn68xx; 3318 struct cvmx_ipd_red_quex_param_s cn68xxp1; 3319 struct cvmx_ipd_red_quex_param_s cnf71xx; 3320}; 3321typedef union cvmx_ipd_red_quex_param cvmx_ipd_red_quex_param_t; 3322 3323/** 3324 * cvmx_ipd_req_wgt 3325 * 3326 * IPD_REQ_WGT = IPD REQ weights 3327 * 3328 * There are 8 devices that can request to send packet traffic to the IPD. These weights are used for the Weighted Round Robin 3329 * grant generated by the IPD to requestors. 3330 */ 3331union cvmx_ipd_req_wgt { 3332 uint64_t u64; 3333 struct cvmx_ipd_req_wgt_s { 3334#ifdef __BIG_ENDIAN_BITFIELD 3335 uint64_t wgt7 : 8; /**< Weight for ILK REQ */ 3336 uint64_t wgt6 : 8; /**< Weight for PKO REQ */ 3337 uint64_t wgt5 : 8; /**< Weight for DPI REQ */ 3338 uint64_t wgt4 : 8; /**< Weight for AGX4 REQ */ 3339 uint64_t wgt3 : 8; /**< Weight for AGX3 REQ */ 3340 uint64_t wgt2 : 8; /**< Weight for AGX2 REQ */ 3341 uint64_t wgt1 : 8; /**< Weight for AGX1 REQ */ 3342 uint64_t wgt0 : 8; /**< Weight for AGX0 REQ */ 3343#else 3344 uint64_t wgt0 : 8; 3345 uint64_t wgt1 : 8; 3346 uint64_t wgt2 : 8; 3347 uint64_t wgt3 : 8; 3348 uint64_t wgt4 : 8; 3349 uint64_t wgt5 : 8; 3350 uint64_t wgt6 : 8; 3351 uint64_t wgt7 : 8; 3352#endif 3353 } s; 3354 struct cvmx_ipd_req_wgt_s cn68xx; 3355}; 3356typedef union cvmx_ipd_req_wgt cvmx_ipd_req_wgt_t; 3357 3358/** 3359 * cvmx_ipd_sub_port_bp_page_cnt 3360 * 3361 * IPD_SUB_PORT_BP_PAGE_CNT = IPD Subtract Port Backpressure Page Count 3362 * 3363 * Will add the value to the indicated port count register, the number of pages supplied. The value added should 3364 * be the 2's complement of the value that needs to be subtracted. Users add 2's complement values to the 3365 * port-mbuf-count register to return (lower the count) mbufs to the counter in order to avoid port-level 3366 * backpressure being applied to the port. Backpressure is applied when the MBUF used count of a port exceeds the 3367 * value in the IPD_PORTX_BP_PAGE_CNT, IPD_PORTX_BP_PAGE_CNT2, and IPD_PORTX_BP_PAGE_CNT3. 3368 * 3369 * This register can't be written from the PCI via a window write. 3370 */ 3371union cvmx_ipd_sub_port_bp_page_cnt { 3372 uint64_t u64; 3373 struct cvmx_ipd_sub_port_bp_page_cnt_s { 3374#ifdef __BIG_ENDIAN_BITFIELD 3375 uint64_t reserved_31_63 : 33; 3376 uint64_t port : 6; /**< The port to add the PAGE_CNT field to. */ 3377 uint64_t page_cnt : 25; /**< The number of page pointers to add to 3378 the port counter pointed to by the 3379 PORT Field. */ 3380#else 3381 uint64_t page_cnt : 25; 3382 uint64_t port : 6; 3383 uint64_t reserved_31_63 : 33; 3384#endif 3385 } s; 3386 struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx; 3387 struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx; 3388 struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx; 3389 struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2; 3390 struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx; 3391 struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx; 3392 struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1; 3393 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx; 3394 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; 3395 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; 3396 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; 3397 struct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx; 3398 struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx; 3399 struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1; 3400 struct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx; 3401 struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx; 3402 struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1; 3403 struct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx; 3404}; 3405typedef union cvmx_ipd_sub_port_bp_page_cnt cvmx_ipd_sub_port_bp_page_cnt_t; 3406 3407/** 3408 * cvmx_ipd_sub_port_fcs 3409 * 3410 * IPD_SUB_PORT_FCS = IPD Subtract Ports FCS Register 3411 * 3412 * When set '1' the port corresponding to the bit set will subtract 4 bytes from the end of 3413 * the packet. 3414 */ 3415union cvmx_ipd_sub_port_fcs { 3416 uint64_t u64; 3417 struct cvmx_ipd_sub_port_fcs_s { 3418#ifdef __BIG_ENDIAN_BITFIELD 3419 uint64_t reserved_40_63 : 24; 3420 uint64_t port_bit2 : 4; /**< When set '1', the port corresponding to the bit 3421 position set, will subtract the FCS for packets 3422 on that port. */ 3423 uint64_t reserved_32_35 : 4; 3424 uint64_t port_bit : 32; /**< When set '1', the port corresponding to the bit 3425 position set, will subtract the FCS for packets 3426 on that port. */ 3427#else 3428 uint64_t port_bit : 32; 3429 uint64_t reserved_32_35 : 4; 3430 uint64_t port_bit2 : 4; 3431 uint64_t reserved_40_63 : 24; 3432#endif 3433 } s; 3434 struct cvmx_ipd_sub_port_fcs_cn30xx { 3435#ifdef __BIG_ENDIAN_BITFIELD 3436 uint64_t reserved_3_63 : 61; 3437 uint64_t port_bit : 3; /**< When set '1', the port corresponding to the bit 3438 position set, will subtract the FCS for packets 3439 on that port. */ 3440#else 3441 uint64_t port_bit : 3; 3442 uint64_t reserved_3_63 : 61; 3443#endif 3444 } cn30xx; 3445 struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx; 3446 struct cvmx_ipd_sub_port_fcs_cn38xx { 3447#ifdef __BIG_ENDIAN_BITFIELD 3448 uint64_t reserved_32_63 : 32; 3449 uint64_t port_bit : 32; /**< When set '1', the port corresponding to the bit 3450 position set, will subtract the FCS for packets 3451 on that port. */ 3452#else 3453 uint64_t port_bit : 32; 3454 uint64_t reserved_32_63 : 32; 3455#endif 3456 } cn38xx; 3457 struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2; 3458 struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx; 3459 struct cvmx_ipd_sub_port_fcs_s cn52xx; 3460 struct cvmx_ipd_sub_port_fcs_s cn52xxp1; 3461 struct cvmx_ipd_sub_port_fcs_s cn56xx; 3462 struct cvmx_ipd_sub_port_fcs_s cn56xxp1; 3463 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; 3464 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; 3465 struct cvmx_ipd_sub_port_fcs_s cn61xx; 3466 struct cvmx_ipd_sub_port_fcs_s cn63xx; 3467 struct cvmx_ipd_sub_port_fcs_s cn63xxp1; 3468 struct cvmx_ipd_sub_port_fcs_s cn66xx; 3469 struct cvmx_ipd_sub_port_fcs_s cnf71xx; 3470}; 3471typedef union cvmx_ipd_sub_port_fcs cvmx_ipd_sub_port_fcs_t; 3472 3473/** 3474 * cvmx_ipd_sub_port_qos_cnt 3475 * 3476 * IPD_SUB_PORT_QOS_CNT = IPD Subtract Port QOS Count 3477 * 3478 * Will add the value (CNT) to the indicated Port-QOS register (PORT_QOS). The value added must be 3479 * be the 2's complement of the value that needs to be subtracted. 3480 */ 3481union cvmx_ipd_sub_port_qos_cnt { 3482 uint64_t u64; 3483 struct cvmx_ipd_sub_port_qos_cnt_s { 3484#ifdef __BIG_ENDIAN_BITFIELD 3485 uint64_t reserved_41_63 : 23; 3486 uint64_t port_qos : 9; /**< The port to add the CNT field to. */ 3487 uint64_t cnt : 32; /**< The value to be added to the register selected 3488 in the PORT_QOS field. */ 3489#else 3490 uint64_t cnt : 32; 3491 uint64_t port_qos : 9; 3492 uint64_t reserved_41_63 : 23; 3493#endif 3494 } s; 3495 struct cvmx_ipd_sub_port_qos_cnt_s cn52xx; 3496 struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; 3497 struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; 3498 struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; 3499 struct cvmx_ipd_sub_port_qos_cnt_s cn61xx; 3500 struct cvmx_ipd_sub_port_qos_cnt_s cn63xx; 3501 struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1; 3502 struct cvmx_ipd_sub_port_qos_cnt_s cn66xx; 3503 struct cvmx_ipd_sub_port_qos_cnt_s cn68xx; 3504 struct cvmx_ipd_sub_port_qos_cnt_s cn68xxp1; 3505 struct cvmx_ipd_sub_port_qos_cnt_s cnf71xx; 3506}; 3507typedef union cvmx_ipd_sub_port_qos_cnt cvmx_ipd_sub_port_qos_cnt_t; 3508 3509/** 3510 * cvmx_ipd_wqe_fpa_queue 3511 * 3512 * IPD_WQE_FPA_QUEUE = IPD Work-Queue-Entry FPA Page Size 3513 * 3514 * Which FPA Queue (0-7) to fetch page-pointers from for WQE's 3515 */ 3516union cvmx_ipd_wqe_fpa_queue { 3517 uint64_t u64; 3518 struct cvmx_ipd_wqe_fpa_queue_s { 3519#ifdef __BIG_ENDIAN_BITFIELD 3520 uint64_t reserved_3_63 : 61; 3521 uint64_t wqe_pool : 3; /**< Which FPA Queue to fetch page-pointers 3522 from for WQE's. 3523 Not used when IPD_CTL_STATUS[NO_WPTR] is set. */ 3524#else 3525 uint64_t wqe_pool : 3; 3526 uint64_t reserved_3_63 : 61; 3527#endif 3528 } s; 3529 struct cvmx_ipd_wqe_fpa_queue_s cn30xx; 3530 struct cvmx_ipd_wqe_fpa_queue_s cn31xx; 3531 struct cvmx_ipd_wqe_fpa_queue_s cn38xx; 3532 struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2; 3533 struct cvmx_ipd_wqe_fpa_queue_s cn50xx; 3534 struct cvmx_ipd_wqe_fpa_queue_s cn52xx; 3535 struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1; 3536 struct cvmx_ipd_wqe_fpa_queue_s cn56xx; 3537 struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; 3538 struct cvmx_ipd_wqe_fpa_queue_s cn58xx; 3539 struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; 3540 struct cvmx_ipd_wqe_fpa_queue_s cn61xx; 3541 struct cvmx_ipd_wqe_fpa_queue_s cn63xx; 3542 struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1; 3543 struct cvmx_ipd_wqe_fpa_queue_s cn66xx; 3544 struct cvmx_ipd_wqe_fpa_queue_s cn68xx; 3545 struct cvmx_ipd_wqe_fpa_queue_s cn68xxp1; 3546 struct cvmx_ipd_wqe_fpa_queue_s cnf71xx; 3547}; 3548typedef union cvmx_ipd_wqe_fpa_queue cvmx_ipd_wqe_fpa_queue_t; 3549 3550/** 3551 * cvmx_ipd_wqe_ptr_valid 3552 * 3553 * IPD_WQE_PTR_VALID = IPD's WQE Pointer Valid 3554 * 3555 * The value of the WQE-pointer fetched and in the valid register. 3556 */ 3557union cvmx_ipd_wqe_ptr_valid { 3558 uint64_t u64; 3559 struct cvmx_ipd_wqe_ptr_valid_s { 3560#ifdef __BIG_ENDIAN_BITFIELD 3561 uint64_t reserved_29_63 : 35; 3562 uint64_t ptr : 29; /**< Pointer value. 3563 When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 3564 represents a Packet-Pointer NOT a WQE pointer. */ 3565#else 3566 uint64_t ptr : 29; 3567 uint64_t reserved_29_63 : 35; 3568#endif 3569 } s; 3570 struct cvmx_ipd_wqe_ptr_valid_s cn30xx; 3571 struct cvmx_ipd_wqe_ptr_valid_s cn31xx; 3572 struct cvmx_ipd_wqe_ptr_valid_s cn38xx; 3573 struct cvmx_ipd_wqe_ptr_valid_s cn50xx; 3574 struct cvmx_ipd_wqe_ptr_valid_s cn52xx; 3575 struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1; 3576 struct cvmx_ipd_wqe_ptr_valid_s cn56xx; 3577 struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; 3578 struct cvmx_ipd_wqe_ptr_valid_s cn58xx; 3579 struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; 3580 struct cvmx_ipd_wqe_ptr_valid_s cn61xx; 3581 struct cvmx_ipd_wqe_ptr_valid_s cn63xx; 3582 struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1; 3583 struct cvmx_ipd_wqe_ptr_valid_s cn66xx; 3584 struct cvmx_ipd_wqe_ptr_valid_s cnf71xx; 3585}; 3586typedef union cvmx_ipd_wqe_ptr_valid cvmx_ipd_wqe_ptr_valid_t; 3587 3588#endif 3589